From: Yuantian Tang Date: Thu, 19 Mar 2020 08:48:25 +0000 (+0800) Subject: armv8: ls1028aqds: add lpuart dts support X-Git-Tag: v2020.07-rc2~25^2~15 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=e88cfb07ebbcc0f185e80ee4ab0783dfe32794c9;p=oweals%2Fu-boot.git armv8: ls1028aqds: add lpuart dts support Rename fsl-ls1028a-qds.dts to fsl-ls1028a-qds.dtsi so that it can be used as common device tree for lpuart and duart. Add lpuart device tree and duart device tree respectively for qds which are used with duart and lpuart console. Signed-off-by: Vabhav Sharma Signed-off-by: Yuantian Tang Reviewed-by: Priyanka Jain --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index af7d804b66..29dc6150ef 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -377,7 +377,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls1088a-rdb.dtb \ fsl-ls1088a-qds.dtb \ fsl-ls1028a-rdb.dtb \ - fsl-ls1028a-qds.dtb \ + fsl-ls1028a-qds-duart.dtb \ + fsl-ls1028a-qds-lpuart.dtb \ fsl-lx2160a-rdb.dtb \ fsl-lx2160a-qds.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ diff --git a/arch/arm/dts/fsl-ls1028a-qds-duart.dts b/arch/arm/dts/fsl-ls1028a-qds-duart.dts new file mode 100644 index 0000000000..83264e0f54 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-duart.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Freescale Layerscape-1028AQDS family SoC. + * + * Copyright 2020 NXP + */ + +/dts-v1/; +#include "fsl-ls1028a-qds.dtsi" + +/ { + chosen { + stdout-path = &serial0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts new file mode 100644 index 0000000000..063857b2f2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-lpuart.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Freescale Layerscape-1028AQDS family SoC. + * + * Copyright 2020 NXP + */ + +/dts-v1/; +#include "fsl-ls1028a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dts b/arch/arm/dts/fsl-ls1028a-qds.dts deleted file mode 100644 index 029a8e386b..0000000000 --- a/arch/arm/dts/fsl-ls1028a-qds.dts +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * NXP ls1028AQDS device tree source - * - * Copyright 2019 NXP - * - */ - -/dts-v1/; - -#include "fsl-ls1028a.dtsi" - -/ { - model = "NXP Layerscape 1028a QDS Board"; - compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; - aliases { - spi0 = &fspi; - }; - -}; - -&dspi0 { - status = "okay"; -}; - -&dspi1 { - status = "okay"; -}; - -&dspi2 { - status = "okay"; -}; - -&esdhc0 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; - -}; - -&fspi { - status = "okay"; - - mt35xu02g0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <1>; - }; -}; - -&i2c0 { - status = "okay"; - u-boot,dm-pre-reloc; - - fpga@66 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-mfd"; - reg = <0x66>; - - mux-mdio@54 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "mdio-mux-i2creg"; - reg = <0x54>; - #mux-control-cells = <1>; - mux-reg-masks = <0x54 0xf0>; - mdio-parent-bus = <&mdio0>; - - /* on-board MDIO with a single RGMII PHY */ - mdio@00 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - - qds_phy0: phy@5 { - reg = <5>; - }; - }; - /* slot 1 */ - slot1: mdio@40 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40>; - }; - /* slot 2 */ - slot2: mdio@50 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x50>; - }; - /* slot 3 */ - slot3: mdio@60 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x60>; - }; - /* slot 4 */ - slot4: mdio@70 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - }; - }; - }; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&i2c1 { - status = "okay"; - - rtc@51 { - compatible = "pcf2127-rtc"; - reg = <0x51>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&enetc1 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&qds_phy0>; -}; - -&mdio0 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi new file mode 100644 index 0000000000..4f56f40bd3 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1028AQDS device tree source + * + * Copyright 2019 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1028a.dtsi" + +/ { + model = "NXP Layerscape 1028a QDS Board"; + compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; + aliases { + spi0 = &fspi; + }; + +}; + +&dspi0 { + status = "okay"; +}; + +&dspi1 { + status = "okay"; +}; + +&dspi2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; + +}; + +&fspi { + status = "okay"; + + mt35xu02g0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; + }; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf0>; + mdio-parent-bus = <&mdio0>; + + /* on-board MDIO with a single RGMII PHY */ + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + qds_phy0: phy@5 { + reg = <5>; + }; + }; + /* slot 1 */ + slot1: mdio@40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40>; + }; + /* slot 2 */ + slot2: mdio@50 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x50>; + }; + /* slot 3 */ + slot3: mdio@60 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60>; + }; + /* slot 4 */ + slot4: mdio@70 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&i2c1 { + status = "okay"; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&lpuart0 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&enetc1 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&qds_phy0>; +}; + +&mdio0 { + status = "okay"; +}; diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 92b944f426..e9db27a368 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_DM=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 66d3ee1761..a7597957d8 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds" +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds-duart" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000