From: Simon Glass Date: Thu, 2 May 2019 16:52:21 +0000 (-0600) Subject: x86: Fix device-tree indentation X-Git-Tag: v2019.07-rc2~14^2~8 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=e766d9f1835e6ad6a2a3080c4abb2e5175b156e8;p=oweals%2Fu-boot.git x86: Fix device-tree indentation With the use of a phandle we can outdent the device tree nodes a little. Fix this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 6b176339ae..daeb168b65 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -23,42 +23,41 @@ #ifdef CONFIG_ROM_SIZE &rom { - filename = "u-boot.rom"; - end-at-4gb; - sort-by-offset; - pad-byte = <0xff>; - size = ; + filename = "u-boot.rom"; + end-at-4gb; + sort-by-offset; + pad-byte = <0xff>; + size = ; #ifdef CONFIG_HAVE_INTEL_ME - intel-descriptor { - filename = CONFIG_FLASH_DESCRIPTOR_FILE; - }; - intel-me { - filename = CONFIG_INTEL_ME_FILE; - }; + intel-descriptor { + filename = CONFIG_FLASH_DESCRIPTOR_FILE; + }; + intel-me { + filename = CONFIG_INTEL_ME_FILE; + }; #endif #ifdef CONFIG_TPL - u-boot-tpl-with-ucode-ptr { - offset = ; - }; - u-boot-tpl-dtb { - }; - u-boot-spl { - offset = ; - }; - u-boot-spl-dtb { - }; - u-boot { - offset = ; - }; + u-boot-tpl-with-ucode-ptr { + offset = ; + }; + u-boot-tpl-dtb { + }; + u-boot-spl { + offset = ; + }; + u-boot-spl-dtb { + }; + u-boot { + offset = ; + }; #elif defined(CONFIG_SPL) - u-boot-spl-with-ucode-ptr { - offset = ; - }; - - u-boot-dtb-with-ucode2 { - type = "u-boot-dtb-with-ucode"; - }; - u-boot { + u-boot-spl-with-ucode-ptr { + offset = ; + }; + u-boot-dtb-with-ucode2 { + type = "u-boot-dtb-with-ucode"; + }; + u-boot { /* * TODO(sjg@chromium.org): * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But @@ -68,67 +67,67 @@ * We need a better solution, perhaps a separate Kconfig. */ #if CONFIG_SYS_TEXT_BASE == 0x1110000 - offset = <0xfff00000>; + offset = <0xfff00000>; #else - offset = ; + offset = ; #endif - }; + }; #else - u-boot-with-ucode-ptr { - offset = ; - }; + u-boot-with-ucode-ptr { + offset = ; + }; #endif - u-boot-dtb-with-ucode { - }; - u-boot-ucode { - align = <16>; - }; + u-boot-dtb-with-ucode { + }; + u-boot-ucode { + align = <16>; + }; #ifdef CONFIG_HAVE_MRC - intel-mrc { - offset = ; - }; + intel-mrc { + offset = ; + }; #endif #ifdef CONFIG_HAVE_FSP - intel-fsp { - filename = CONFIG_FSP_FILE; - offset = ; - }; + intel-fsp { + filename = CONFIG_FSP_FILE; + offset = ; + }; #endif #ifdef CONFIG_HAVE_CMC - intel-cmc { - filename = CONFIG_CMC_FILE; - offset = ; - }; + intel-cmc { + filename = CONFIG_CMC_FILE; + offset = ; + }; #endif #ifdef CONFIG_HAVE_VGA_BIOS - intel-vga { - filename = CONFIG_VGA_BIOS_FILE; - offset = ; - }; + intel-vga { + filename = CONFIG_VGA_BIOS_FILE; + offset = ; + }; #endif #ifdef CONFIG_HAVE_VBT - intel-vbt { - filename = CONFIG_VBT_FILE; - offset = ; - }; + intel-vbt { + filename = CONFIG_VBT_FILE; + offset = ; + }; #endif #ifdef CONFIG_HAVE_REFCODE - intel-refcode { - offset = ; - }; + intel-refcode { + offset = ; + }; #endif #ifdef CONFIG_TPL - x86-start16-tpl { - offset = ; - }; + x86-start16-tpl { + offset = ; + }; #elif defined(CONFIG_SPL) - x86-start16-spl { - offset = ; - }; + x86-start16-spl { + offset = ; + }; #else - x86-start16 { - offset = ; - }; + x86-start16 { + offset = ; + }; #endif }; #endif