From: Aneesh V <aneesh@ti.com>
Date: Mon, 21 Nov 2011 23:34:01 +0000 (+0000)
Subject: start.S: remove omap3 specific code from start.S
X-Git-Tag: v2011.12-rc1~60^2~73
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=e4fce34e7a5f484de2ca557fd43a198fd14894b7;p=oweals%2Fu-boot.git

start.S: remove omap3 specific code from start.S

Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Aneesh V <aneesh@ti.com>
Acked-by: Tom Rini <trini@ti.com>
---

diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index a308ebdb6a..2f6930b22d 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -216,6 +216,14 @@ lowlevel_init:
 	ldr	sp, SRAM_STACK
 	str	ip, [sp]	/* stash old link register */
 	mov	ip, lr		/* save link reg across call */
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
+/*
+ * No need to copy/exec the clock code - DPLL adjust already done
+ * in NAND/oneNAND Boot.
+ */
+	ldr	r1, =SRAM_CLK_CODE
+	bl	cpy_clk_code
+#endif /* NAND Boot */
 	bl	s_init		/* go setup pll, mux, memory */
 	ldr	ip, [sp]	/* restore save ip */
 	mov	lr, ip		/* restore link reg */
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f17763f2a1..d23dc9d719 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -160,29 +160,6 @@ reset:
 	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
 #endif
 
-#if defined(CONFIG_OMAP34XX)
-	/* Copy vectors to mask ROM indirect addr */
-	adr	r0, _start		@ r0 <- current position of code
-	add	r0, r0, #4		@ skip reset vector
-	mov	r2, #64			@ r2 <- size to copy
-	add	r2, r0, r2		@ r2 <- source end address
-	mov	r1, #SRAM_OFFSET0	@ build vect addr
-	mov	r3, #SRAM_OFFSET1
-	add	r1, r1, r3
-	mov	r3, #SRAM_OFFSET2
-	add	r1, r1, r3
-next:
-	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
-	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
-	cmp	r0, r2			@ until source end address [r2]
-	bne	next			@ loop until equal */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
-	/* No need to copy/exec the clock code - DPLL adjust already done
-	 * in NAND/oneNAND Boot.
-	 */
-	bl	cpy_clk_code		@ put dpll adjust code behind vectors
-#endif /* NAND Boot */
-#endif
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 02eb865dc1..2b5e9aeae1 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -153,6 +153,7 @@ struct gpio {
 #define SRAM_OFFSET2			0x0000F800
 #define SRAM_VECT_CODE			(SRAM_OFFSET0 | SRAM_OFFSET1 | \
 					 SRAM_OFFSET2)
+#define SRAM_CLK_CODE			(SRAM_VECT_CODE + 64)
 
 #define OMAP3_PUBLIC_SRAM_BASE		0x40208000 /* Works for GP & EMU */
 #define OMAP3_PUBLIC_SRAM_END		0x40210000