From: Patrick Delaunay <patrick.delaunay@st.com>
Date: Mon, 4 Feb 2019 10:26:18 +0000 (+0100)
Subject: stpmic1: update register names
X-Git-Tag: v2019.07-rc1~27^2~15
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=db4ff0df656f8ca8d363df64cddc7b5f835a7ecc;p=oweals%2Fu-boot.git

stpmic1: update register names

Alignment with  STPMIC1 datasheet
  s/MAIN_CONTROL_REG/MAIN_CR/g
  s/MASK_RESET_BUCK/BUCKS_MRST_CR/g
  s/MASK_RESET_LDOS/LDOS_MRST_CR/g
  s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g
  s/VREF_CTRL_REG/REFDDR_MAIN_CR/g
  s/LDOX_CTRL_REG/LDOX_MAIN_CR/g
  s/USB_CTRL_REG/BST_SW_CR/g
  s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g
  s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g
and update all the associated defines.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---

diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c
index 2a94f10155..5c1acca20d 100644
--- a/board/st/stm32mp1/board.c
+++ b/board/st/stm32mp1/board.c
@@ -50,39 +50,39 @@ int board_ddr_power_init(void)
 		return 0;
 
 	/* VTT = Set LDO3 to sync mode */
-	ret = pmic_reg_read(dev, STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3));
+	ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
 	if (ret < 0)
 		return ret;
 
 	ret &= ~STPMIC1_LDO3_MODE;
-	ret &= ~STPMIC1_LDO12356_OUTPUT_MASK;
-	ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_OUTPUT_SHIFT;
+	ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+	ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
 
-	ret = pmic_reg_write(dev, STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3),
+	ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 			     ret);
 	if (ret < 0)
 		return ret;
 
 	/* VDD_DDR = Set BUCK2 to 1.35V */
 	ret = pmic_clrsetbits(dev,
-			      STPMIC1_BUCKX_CTRL_REG(STPMIC1_BUCK2),
-			      STPMIC1_BUCK_OUTPUT_MASK,
+			      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+			      STPMIC1_BUCK_VOUT_MASK,
 			      STPMIC1_BUCK2_1350000V);
 	if (ret < 0)
 		return ret;
 
 	/* Enable VDD_DDR = BUCK2 */
 	ret = pmic_clrsetbits(dev,
-			      STPMIC1_BUCKX_CTRL_REG(STPMIC1_BUCK2),
-			      STPMIC1_BUCK_EN, STPMIC1_BUCK_EN);
+			      STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
+			      STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
 	if (ret < 0)
 		return ret;
 
 	mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 
 	/* Enable VREF */
-	ret = pmic_clrsetbits(dev, STPMIC1_VREF_CTRL_REG,
-			      STPMIC1_VREF_EN, STPMIC1_VREF_EN);
+	ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
+			      STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
 	if (ret < 0)
 		return ret;
 
@@ -90,8 +90,8 @@ int board_ddr_power_init(void)
 
 	/* Enable LDO3 */
 	ret = pmic_clrsetbits(dev,
-			      STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3),
-			      STPMIC1_LDO_EN, STPMIC1_LDO_EN);
+			      STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
+			      STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
 	if (ret < 0)
 		return ret;
 
diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c
index 546a92325c..a7844f244b 100644
--- a/board/st/stm32mp1/spl.c
+++ b/board/st/stm32mp1/spl.c
@@ -25,8 +25,8 @@ void spl_board_init(void)
 					  DM_GET_DRIVER(pmic_stpmic1), &dev);
 	if (!ret)
 		pmic_clrsetbits(dev,
-				STPMIC1_MASK_RESET_BUCK,
-				STPMIC1_MASK_RESET_BUCK3,
-				STPMIC1_MASK_RESET_BUCK3);
+				STPMIC1_BUCKS_MRST_CR,
+				STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
+				STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
 #endif
 }
diff --git a/drivers/power/regulator/stpmic1.c b/drivers/power/regulator/stpmic1.c
index 860258388e..50ef2a21d1 100644
--- a/drivers/power/regulator/stpmic1.c
+++ b/drivers/power/regulator/stpmic1.c
@@ -132,20 +132,20 @@ static const struct stpmic1_output buck_voltage_range[] = {
 
 /* BUCK modes */
 static const struct dm_regulator_mode buck_modes[] = {
-	STPMIC1_MODE(STPMIC1_BUCK_MODE_HP, STPMIC1_BUCK_MODE_HP, "HP"),
-	STPMIC1_MODE(STPMIC1_BUCK_MODE_LP, STPMIC1_BUCK_MODE_LP, "LP"),
+	STPMIC1_MODE(STPMIC1_PREG_MODE_HP, STPMIC1_PREG_MODE_HP, "HP"),
+	STPMIC1_MODE(STPMIC1_PREG_MODE_LP, STPMIC1_PREG_MODE_LP, "LP"),
 };
 
 static int stpmic1_buck_get_uv(struct udevice *dev, int buck)
 {
 	int sel;
 
-	sel = pmic_reg_read(dev, STPMIC1_BUCKX_CTRL_REG(buck));
+	sel = pmic_reg_read(dev, STPMIC1_BUCKX_MAIN_CR(buck));
 	if (sel < 0)
 		return sel;
 
-	sel &= STPMIC1_BUCK_OUTPUT_MASK;
-	sel >>= STPMIC1_BUCK_OUTPUT_SHIFT;
+	sel &= STPMIC1_BUCK_VOUT_MASK;
+	sel >>= STPMIC1_BUCK_VOUT_SHIFT;
 
 	return stpmic1_output_find_uv(sel, &buck_voltage_range[buck]);
 }
@@ -164,9 +164,9 @@ static int stpmic1_buck_set_value(struct udevice *dev, int uv)
 		return sel;
 
 	return pmic_clrsetbits(dev->parent,
-			       STPMIC1_BUCKX_CTRL_REG(buck),
-			       STPMIC1_BUCK_OUTPUT_MASK,
-			       sel << STPMIC1_BUCK_OUTPUT_SHIFT);
+			       STPMIC1_BUCKX_MAIN_CR(buck),
+			       STPMIC1_BUCK_VOUT_MASK,
+			       sel << STPMIC1_BUCK_VOUT_SHIFT);
 }
 
 static int stpmic1_buck_get_enable(struct udevice *dev)
@@ -174,11 +174,11 @@ static int stpmic1_buck_get_enable(struct udevice *dev)
 	int ret;
 
 	ret = pmic_reg_read(dev->parent,
-			    STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1));
+			    STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1));
 	if (ret < 0)
 		return false;
 
-	return ret & STPMIC1_BUCK_EN ? true : false;
+	return ret & STPMIC1_BUCK_ENA ? true : false;
 }
 
 static int stpmic1_buck_set_enable(struct udevice *dev, bool enable)
@@ -200,8 +200,8 @@ static int stpmic1_buck_set_enable(struct udevice *dev, bool enable)
 	}
 
 	ret = pmic_clrsetbits(dev->parent,
-			      STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1),
-			      STPMIC1_BUCK_EN, enable ? STPMIC1_BUCK_EN : 0);
+			      STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1),
+			      STPMIC1_BUCK_ENA, enable ? STPMIC1_BUCK_ENA : 0);
 	mdelay(delay);
 
 	return ret;
@@ -212,20 +212,20 @@ static int stpmic1_buck_get_mode(struct udevice *dev)
 	int ret;
 
 	ret = pmic_reg_read(dev->parent,
-			    STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1));
+			    STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1));
 	if (ret < 0)
 		return ret;
 
-	return ret & STPMIC1_BUCK_MODE ? STPMIC1_BUCK_MODE_LP :
-					 STPMIC1_BUCK_MODE_HP;
+	return ret & STPMIC1_BUCK_PREG_MODE ? STPMIC1_PREG_MODE_LP :
+					      STPMIC1_PREG_MODE_HP;
 }
 
 static int stpmic1_buck_set_mode(struct udevice *dev, int mode)
 {
 	return pmic_clrsetbits(dev->parent,
-			       STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1),
-			       STPMIC1_BUCK_MODE,
-			       mode ? STPMIC1_BUCK_MODE : 0);
+			       STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1),
+			       STPMIC1_BUCK_PREG_MODE,
+			       mode ? STPMIC1_BUCK_PREG_MODE : 0);
 }
 
 static int stpmic1_buck_probe(struct udevice *dev)
@@ -312,7 +312,7 @@ static int stpmic1_ldo_get_value(struct udevice *dev)
 {
 	int sel, ldo = dev->driver_data - 1;
 
-	sel = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
+	sel = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
 	if (sel < 0)
 		return sel;
 
@@ -320,8 +320,8 @@ static int stpmic1_ldo_get_value(struct udevice *dev)
 	if (ldo == STPMIC1_LDO4)
 		return STPMIC1_LDO4_UV;
 
-	sel &= STPMIC1_LDO12356_OUTPUT_MASK;
-	sel >>= STPMIC1_LDO12356_OUTPUT_SHIFT;
+	sel &= STPMIC1_LDO12356_VOUT_MASK;
+	sel >>= STPMIC1_LDO12356_VOUT_SHIFT;
 
 	/* ldo3, sel = 31 => BUCK2/2 */
 	if (ldo == STPMIC1_LDO3 && sel == STPMIC1_LDO3_DDR_SEL)
@@ -343,9 +343,9 @@ static int stpmic1_ldo_set_value(struct udevice *dev, int uv)
 		return sel;
 
 	return pmic_clrsetbits(dev->parent,
-			       STPMIC1_LDOX_CTRL_REG(ldo),
-			       STPMIC1_LDO12356_OUTPUT_MASK,
-			       sel << STPMIC1_LDO12356_OUTPUT_SHIFT);
+			       STPMIC1_LDOX_MAIN_CR(ldo),
+			       STPMIC1_LDO12356_VOUT_MASK,
+			       sel << STPMIC1_LDO12356_VOUT_SHIFT);
 }
 
 static int stpmic1_ldo_get_enable(struct udevice *dev)
@@ -353,11 +353,11 @@ static int stpmic1_ldo_get_enable(struct udevice *dev)
 	int ret;
 
 	ret = pmic_reg_read(dev->parent,
-			    STPMIC1_LDOX_CTRL_REG(dev->driver_data - 1));
+			    STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1));
 	if (ret < 0)
 		return false;
 
-	return ret & STPMIC1_LDO_EN ? true : false;
+	return ret & STPMIC1_LDO_ENA ? true : false;
 }
 
 static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable)
@@ -379,8 +379,8 @@ static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable)
 	}
 
 	ret = pmic_clrsetbits(dev->parent,
-			      STPMIC1_LDOX_CTRL_REG(dev->driver_data - 1),
-			      STPMIC1_LDO_EN, enable ? STPMIC1_LDO_EN : 0);
+			      STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1),
+			      STPMIC1_LDO_ENA, enable ? STPMIC1_LDO_ENA : 0);
 	mdelay(delay);
 
 	return ret;
@@ -393,15 +393,15 @@ static int stpmic1_ldo_get_mode(struct udevice *dev)
 	if (ldo != STPMIC1_LDO3)
 		return -EINVAL;
 
-	ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
+	ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
 	if (ret < 0)
 		return ret;
 
 	if (ret & STPMIC1_LDO3_MODE)
 		return STPMIC1_LDO_MODE_BYPASS;
 
-	ret &= STPMIC1_LDO12356_OUTPUT_MASK;
-	ret >>= STPMIC1_LDO12356_OUTPUT_SHIFT;
+	ret &= STPMIC1_LDO12356_VOUT_MASK;
+	ret >>= STPMIC1_LDO12356_VOUT_SHIFT;
 
 	return ret == STPMIC1_LDO3_DDR_SEL ? STPMIC1_LDO_MODE_SINK_SOURCE :
 					     STPMIC1_LDO_MODE_NORMAL;
@@ -414,14 +414,14 @@ static int stpmic1_ldo_set_mode(struct udevice *dev, int mode)
 	if (ldo != STPMIC1_LDO3)
 		return -EINVAL;
 
-	ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
+	ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
 	if (ret < 0)
 		return ret;
 
 	switch (mode) {
 	case STPMIC1_LDO_MODE_SINK_SOURCE:
-		ret &= ~STPMIC1_LDO12356_OUTPUT_MASK;
-		ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_OUTPUT_SHIFT;
+		ret &= ~STPMIC1_LDO12356_VOUT_MASK;
+		ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_VOUT_SHIFT;
 	case STPMIC1_LDO_MODE_NORMAL:
 		ret &= ~STPMIC1_LDO3_MODE;
 		break;
@@ -430,7 +430,7 @@ static int stpmic1_ldo_set_mode(struct udevice *dev, int mode)
 		break;
 	}
 
-	return pmic_reg_write(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo), ret);
+	return pmic_reg_write(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo), ret);
 }
 
 static int stpmic1_ldo_probe(struct udevice *dev)
@@ -483,11 +483,11 @@ static int stpmic1_vref_ddr_get_enable(struct udevice *dev)
 {
 	int ret;
 
-	ret = pmic_reg_read(dev->parent, STPMIC1_VREF_CTRL_REG);
+	ret = pmic_reg_read(dev->parent, STPMIC1_REFDDR_MAIN_CR);
 	if (ret < 0)
 		return false;
 
-	return ret & STPMIC1_VREF_EN ? true : false;
+	return ret & STPMIC1_VREF_ENA ? true : false;
 }
 
 static int stpmic1_vref_ddr_set_enable(struct udevice *dev, bool enable)
@@ -500,8 +500,8 @@ static int stpmic1_vref_ddr_set_enable(struct udevice *dev, bool enable)
 	if (stpmic1_vref_ddr_get_enable(dev) == enable)
 		return 0;
 
-	ret = pmic_clrsetbits(dev->parent, STPMIC1_VREF_CTRL_REG,
-			      STPMIC1_VREF_EN, enable ? STPMIC1_VREF_EN : 0);
+	ret = pmic_clrsetbits(dev->parent, STPMIC1_REFDDR_MAIN_CR,
+			      STPMIC1_VREF_ENA, enable ? STPMIC1_VREF_ENA : 0);
 	mdelay(delay);
 
 	return ret;
@@ -540,31 +540,31 @@ static int stpmic1_boost_get_enable(struct udevice *dev)
 {
 	int ret;
 
-	ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
+	ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
 	if (ret < 0)
 		return false;
 
-	return ret & STPMIC1_USB_BOOST_EN ? true : false;
+	return ret & STPMIC1_BST_ON ? true : false;
 }
 
 static int stpmic1_boost_set_enable(struct udevice *dev, bool enable)
 {
 	int ret;
 
-	ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
+	ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
 	if (ret < 0)
 		return ret;
 
-	if (!enable && ret & STPMIC1_USB_PWR_SW_EN)
+	if (!enable && ret & STPMIC1_PWR_SW_ON)
 		return -EINVAL;
 
 	/* if regulator is already in the wanted state, nothing to do */
-	if (!!(ret & STPMIC1_USB_BOOST_EN) == enable)
+	if (!!(ret & STPMIC1_BST_ON) == enable)
 		return 0;
 
-	ret = pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
-			      STPMIC1_USB_BOOST_EN,
-			      enable ? STPMIC1_USB_BOOST_EN : 0);
+	ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
+			      STPMIC1_BST_ON,
+			      enable ? STPMIC1_BST_ON : 0);
 	if (enable)
 		mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS);
 
@@ -604,7 +604,7 @@ static int stpmic1_pwr_sw_get_enable(struct udevice *dev)
 	uint mask = 1 << dev->driver_data;
 	int ret;
 
-	ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
+	ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
 	if (ret < 0)
 		return false;
 
@@ -618,7 +618,7 @@ static int stpmic1_pwr_sw_set_enable(struct udevice *dev, bool enable)
 			     STPMIC1_DEFAULT_STOP_DELAY_MS;
 	int ret;
 
-	ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
+	ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
 	if (ret < 0)
 		return ret;
 
@@ -627,17 +627,17 @@ static int stpmic1_pwr_sw_set_enable(struct udevice *dev, bool enable)
 		return 0;
 
 	/* Boost management */
-	if (enable && !(ret & STPMIC1_USB_BOOST_EN)) {
-		pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
-				STPMIC1_USB_BOOST_EN, STPMIC1_USB_BOOST_EN);
+	if (enable && !(ret & STPMIC1_BST_ON)) {
+		pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
+				STPMIC1_BST_ON, STPMIC1_BST_ON);
 		mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS);
-	} else if (!enable && ret & STPMIC1_USB_BOOST_EN &&
-		   (ret & STPMIC1_USB_PWR_SW_EN) != STPMIC1_USB_PWR_SW_EN) {
-		pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
-				STPMIC1_USB_BOOST_EN, 0);
+	} else if (!enable && ret & STPMIC1_BST_ON &&
+		   (ret & STPMIC1_PWR_SW_ON) != STPMIC1_PWR_SW_ON) {
+		pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
+				STPMIC1_BST_ON, 0);
 	}
 
-	ret = pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
+	ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
 			      mask, enable ? mask : 0);
 	mdelay(delay);
 
diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h
index 5ed67d29cf..ea91b75cfd 100644
--- a/include/power/stpmic1.h
+++ b/include/power/stpmic1.h
@@ -6,51 +6,69 @@
 #ifndef __PMIC_STPMIC1_H_
 #define __PMIC_STPMIC1_H_
 
-#define STPMIC1_MAIN_CONTROL_REG	0x10
-#define STPMIC1_MASK_RESET_BUCK		0x18
-#define STPMIC1_MASK_RESET_LDOS		0x1a
-#define STPMIC1_BUCKX_CTRL_REG(buck)	(0x20 + (buck))
-#define STPMIC1_VREF_CTRL_REG		0x24
-#define STPMIC1_LDOX_CTRL_REG(ldo)	(0x25 + (ldo))
-#define STPMIC1_USB_CTRL_REG		0x40
-#define STPMIC1_NVM_USER_STATUS_REG	0xb8
-#define STPMIC1_NVM_USER_CONTROL_REG	0xb9
-
-/* Main PMIC Control Register (MAIN_CONTROL_REG) */
-#define STPMIC1_CTRL_SWITCH_OFF		BIT(0)
-#define STPMIC1_CTRL_RESTART		BIT(1)
-
-#define STPMIC1_MASK_RESET_BUCK3	BIT(2)
-#define STPMIC1_MASK_RESET_BUCK_DBG	GENMASK(3, 0)
-#define STPMIC1_MASK_RESET_LDOS_DBG	0x6F
-
-#define STPMIC1_BUCK_EN			BIT(0)
-#define STPMIC1_BUCK_MODE		BIT(1)
-#define STPMIC1_BUCK_OUTPUT_MASK	GENMASK(7, 2)
-#define STPMIC1_BUCK_OUTPUT_SHIFT	2
-#define STPMIC1_BUCK2_1200000V		(24 << STPMIC1_BUCK_OUTPUT_SHIFT)
-#define STPMIC1_BUCK2_1350000V		(30 << STPMIC1_BUCK_OUTPUT_SHIFT)
-#define STPMIC1_BUCK3_1800000V		(39 << STPMIC1_BUCK_OUTPUT_SHIFT)
-
-#define STPMIC1_VREF_EN			BIT(0)
-
-#define STPMIC1_LDO_EN			BIT(0)
-#define STPMIC1_LDO12356_OUTPUT_MASK	GENMASK(6, 2)
-#define STPMIC1_LDO12356_OUTPUT_SHIFT	2
+#define STPMIC1_MAIN_CR			0x10
+#define STPMIC1_BUCKS_MRST_CR		0x18
+#define STPMIC1_LDOS_MRST_CR		0x1a
+#define STPMIC1_BUCKX_MAIN_CR(buck)	(0x20 + (buck))
+#define STPMIC1_REFDDR_MAIN_CR		0x24
+#define STPMIC1_LDOX_MAIN_CR(ldo)	(0x25 + (ldo))
+#define STPMIC1_BST_SW_CR		0x40
+#define STPMIC1_NVM_SR			0xb8
+#define STPMIC1_NVM_CR			0xb9
+
+/* Main PMIC Control Register (MAIN_CR) */
+#define STPMIC1_SWOFF			BIT(0)
+#define STPMIC1_RREQ_EN			BIT(1)
+
+/* BUCKS_MRST_CR */
+#define STPMIC1_MRST_BUCK(buck)		BIT(buck)
+#define STPMIC1_MRST_BUCK_ALL		GENMASK(3, 0)
+
+/* LDOS_MRST_CR */
+#define STPMIC1_MRST_LDO(ldo)		BIT(ldo)
+#define STPMIC1_MRST_LDO_ALL		GENMASK(6, 0)
+
+/* BUCKx_MAIN_CR (x=1...4) */
+#define STPMIC1_BUCK_ENA		BIT(0)
+#define STPMIC1_BUCK_PREG_MODE		BIT(1)
+#define STPMIC1_BUCK_VOUT_MASK		GENMASK(7, 2)
+#define STPMIC1_BUCK_VOUT_SHIFT		2
+#define STPMIC1_BUCK_VOUT(sel)		(sel << STPMIC1_BUCK_VOUT_SHIFT)
+
+#define STPMIC1_BUCK2_1200000V		STPMIC1_BUCK_VOUT(24)
+#define STPMIC1_BUCK2_1350000V		STPMIC1_BUCK_VOUT(30)
+
+#define STPMIC1_BUCK3_1800000V		STPMIC1_BUCK_VOUT(39)
+
+/* REFDDR_MAIN_CR */
+#define STPMIC1_VREF_ENA		BIT(0)
+
+/* LDOX_MAIN_CR */
+#define STPMIC1_LDO_ENA			BIT(0)
+#define STPMIC1_LDO12356_VOUT_MASK	GENMASK(6, 2)
+#define STPMIC1_LDO12356_VOUT_SHIFT	2
+#define STPMIC1_LDO_VOUT(sel)		(sel << STPMIC1_LDO12356_VOUT_SHIFT)
+
 #define STPMIC1_LDO3_MODE		BIT(7)
 #define STPMIC1_LDO3_DDR_SEL		31
-#define STPMIC1_LDO3_1800000		(9 << STPMIC1_LDO12356_OUTPUT_SHIFT)
+#define STPMIC1_LDO3_1800000		STPMIC1_LDO_VOUT(9)
+
 #define STPMIC1_LDO4_UV			3300000
 
-#define STPMIC1_USB_BOOST_EN		BIT(0)
-#define STPMIC1_USB_PWR_SW_EN		GENMASK(2, 1)
+/* BST_SW_CR */
+#define STPMIC1_BST_ON			BIT(0)
+#define STPMIC1_VBUSOTG_ON		BIT(1)
+#define STPMIC1_SWOUT_ON		BIT(2)
+#define STPMIC1_PWR_SW_ON		(STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
 
-#define STPMIC1_NVM_USER_CONTROL_PROGRAM	BIT(0)
-#define STPMIC1_NVM_USER_CONTROL_READ		BIT(1)
+/* NVM_SR */
+#define STPMIC1_NVM_BUSY		BIT(0)
 
-#define STPMIC1_NVM_USER_STATUS_BUSY		BIT(0)
-#define STPMIC1_NVM_USER_STATUS_ERROR		BIT(1)
+/* NVM_CR */
+#define STPMIC1_NVM_CMD_PROGRAM		1
+#define STPMIC1_NVM_CMD_READ		2
 
+/* Timeout */
 #define STPMIC1_DEFAULT_START_UP_DELAY_MS	1
 #define STPMIC1_DEFAULT_STOP_DELAY_MS		5
 #define STPMIC1_USB_BOOST_START_UP_DELAY_MS	10
@@ -64,8 +82,8 @@ enum {
 };
 
 enum {
-	STPMIC1_BUCK_MODE_HP,
-	STPMIC1_BUCK_MODE_LP,
+	STPMIC1_PREG_MODE_HP,
+	STPMIC1_PREG_MODE_LP,
 };
 
 enum {