From: Piotr Dymacz Date: Sun, 20 Mar 2016 16:05:51 +0000 (+0100) Subject: Use BIT() macro in common QC/A header X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=d80572d53b993c0faf88a000a707e07fde35f417;p=oweals%2Fu-boot_mod.git Use BIT() macro in common QC/A header --- diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h index fc4f14a..53879d1 100644 --- a/u-boot/include/soc/qca_soc_common.h +++ b/u-boot/include/soc/qca_soc_common.h @@ -137,21 +137,21 @@ #define QCA_DDR_CFG_CAS_3LSB_SHIFT 27 #define QCA_DDR_CFG_CAS_3LSB_MASK BITS(QCA_DDR_CFG_CAS_3LSB_SHIFT, 3) #define QCA_DDR_CFG_PAGE_CLOSE_SHIFT 30 -#define QCA_DDR_CFG_PAGE_CLOSE_MASK (1 << QCA_DDR_CFG_PAGE_CLOSE_SHIFT) +#define QCA_DDR_CFG_PAGE_CLOSE_MASK BIT(QCA_DDR_CFG_PAGE_CLOSE_SHIFT) #define QCA_DDR_CFG_CAS_MSB_SHIFT 31 -#define QCA_DDR_CFG_CAS_MSB_MASK (1 << QCA_DDR_CFG_CAS_MSB_SHIFT) +#define QCA_DDR_CFG_CAS_MSB_MASK BIT(QCA_DDR_CFG_CAS_MSB_SHIFT) /* DDR_CONFIG2 register (DDR DRAM configuration 2) */ #define QCA_DDR_CFG2_BURST_LEN_SHIFT 0 #define QCA_DDR_CFG2_BURST_LEN_MASK BITS(QCA_DDR_CFG2_BURST_LEN_SHIFT, 4) #define QCA_DDR_CFG2_BURST_TYPE_SHIFT 4 -#define QCA_DDR_CFG2_BURST_TYPE_MASK (1 << QCA_DDR_CFG2_BURST_TYPE_SHIFT) +#define QCA_DDR_CFG2_BURST_TYPE_MASK BIT(QCA_DDR_CFG2_BURST_TYPE_SHIFT) #define QCA_DDR_CFG2_CTRL_OE_EN_SHIFT 5 -#define QCA_DDR_CFG2_CTRL_OE_EN_MASK (1 << QCA_DDR_CFG2_CTRL_OE_EN_SHIFT) +#define QCA_DDR_CFG2_CTRL_OE_EN_MASK BIT(QCA_DDR_CFG2_CTRL_OE_EN_SHIFT) #define QCA_DDR_CFG2_PHASE_SEL_SHIFT 6 -#define QCA_DDR_CFG2_PHASE_SEL_MASK (1 << QCA_DDR_CFG2_PHASE_SEL_SHIFT) +#define QCA_DDR_CFG2_PHASE_SEL_MASK BIT(QCA_DDR_CFG2_PHASE_SEL_SHIFT) #define QCA_DDR_CFG2_CKE_SHIFT 7 -#define QCA_DDR_CFG2_CKE_MASK (1 << QCA_DDR_CFG2_CKE_SHIFT) +#define QCA_DDR_CFG2_CKE_MASK BIT(QCA_DDR_CFG2_CKE_SHIFT) #define QCA_DDR_CFG2_TWR_SHIFT 8 #define QCA_DDR_CFG2_TWR_MASK BITS(QCA_DDR_CFG2_TWR_SHIFT, 4) #define QCA_DDR_CFG2_TRTW_SHIFT 12 @@ -163,9 +163,9 @@ #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT 26 #define QCA_DDR_CFG2_GATE_OPEN_LATENCY_MASK BITS(QCA_DDR_CFG2_GATE_OPEN_LATENCY_SHIFT, 4) #define QCA_DDR_CFG2_SWAP_A26_A27_SHIFT 30 -#define QCA_DDR_CFG2_SWAP_A26_A27_MASK (1 << QCA_DDR_CFG2_SWAP_A26_A27_SHIFT) +#define QCA_DDR_CFG2_SWAP_A26_A27_MASK BIT(QCA_DDR_CFG2_SWAP_A26_A27_SHIFT) #define QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT 31 -#define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK (1 << QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT) +#define QCA_DDR_CFG2_HALF_WIDTH_LOW_MASK BIT(QCA_DDR_CFG2_HALF_WIDTH_LOW_SHIFT) /* DDR_MODE register (DDR mode register value) */ #define QCA_DDR_MR_VALUE_SHIFT 0 @@ -177,23 +177,23 @@ /* DDR_CONTROL register (DDR control) */ #define QCA_DDR_CTRL_FORCE_MRS_SHIFT 0 -#define QCA_DDR_CTRL_FORCE_MRS_MASK (1 << QCA_DDR_CTRL_FORCE_MRS_SHIFT) +#define QCA_DDR_CTRL_FORCE_MRS_MASK BIT(QCA_DDR_CTRL_FORCE_MRS_SHIFT) #define QCA_DDR_CTRL_FORCE_EMRS_SHIFT 1 -#define QCA_DDR_CTRL_FORCE_EMRS_MASK (1 << QCA_DDR_CTRL_FORCE_EMRS_SHIFT) +#define QCA_DDR_CTRL_FORCE_EMRS_MASK BIT(QCA_DDR_CTRL_FORCE_EMRS_SHIFT) #define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT 2 -#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK (1 << QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT) +#define QCA_DDR_CTRL_FORCE_AUTO_REFRESH_MASK BIT(QCA_DDR_CTRL_FORCE_AUTO_REFRESH_SHIFT) #define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT 3 -#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK (1 << QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT) +#define QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_MASK BIT(QCA_DDR_CTRL_FORCE_PRECHARGE_ALL_SHIFT) #define QCA_DDR_CTRL_FORCE_EMR2S_SHIFT 4 -#define QCA_DDR_CTRL_FORCE_EMR2S_MASK (1 << QCA_DDR_CTRL_FORCE_EMR2S_SHIFT) +#define QCA_DDR_CTRL_FORCE_EMR2S_MASK BIT(QCA_DDR_CTRL_FORCE_EMR2S_SHIFT) #define QCA_DDR_CTRL_FORCE_EMR3S_SHIFT 5 -#define QCA_DDR_CTRL_FORCE_EMR3S_MASK (1 << QCA_DDR_CTRL_FORCE_EMR3S_SHIFT) +#define QCA_DDR_CTRL_FORCE_EMR3S_MASK BIT(QCA_DDR_CTRL_FORCE_EMR3S_SHIFT) /* DDR_REFRESH register (DDR refresh control and configuration) */ #define QCA_DDR_REFRESH_PERIOD_SHIFT 0 #define QCA_DDR_REFRESH_PERIOD_MASK BITS(QCA_DDR_REFRESH_PERIOD_SHIFT, 14) #define QCA_DDR_REFRESH_EN_SHIFT 14 -#define QCA_DDR_REFRESH_EN_MASK (1 << QCA_DDR_REFRESH_EN_SHIFT) +#define QCA_DDR_REFRESH_EN_MASK BIT(QCA_DDR_REFRESH_EN_SHIFT) /* DDR_RD_DATA_THIS_CYCLE register (DDR read data capture bit mask) */ #define QCA_DDR_RD_DATA_THIS_CYCLE_VEC_SHIFT 0 @@ -207,7 +207,7 @@ #define QCA_DDR_TAP_CTRL_TAP_H_SHIFT 8 #define QCA_DDR_TAP_CTRL_TAP_H_MASK BITS(QCA_DDR_TAP_CTRL_TAP_H_SHIFT, 5) #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT 16 - #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_MASK (1 << QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT) + #define QCA_DDR_TAP_CTRL_TAP_H_BYPASS_MASK BIT(QCA_DDR_TAP_CTRL_TAP_H_BYPASS_SHIFT) #else #define QCA_DDR_TAP_CTRL_TAP_SHIFT 0 #define QCA_DDR_TAP_CTRL_TAP_MASK BITS(QCA_DDR_TAP_CTRL_TAP_SHIFT, 6) @@ -215,7 +215,7 @@ /* DDR_DDR2_CONFIG register (DDR2 configuration) */ #define QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT 0 -#define QCA_DDR_DDR2_CFG_DDR2_EN_MASK (1 << QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT) +#define QCA_DDR_DDR2_CFG_DDR2_EN_MASK BIT(QCA_DDR_DDR2_CFG_DDR2_EN_SHIFT) #define QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT 2 #define QCA_DDR_DDR2_CFG_DDR2_TFAW_MASK BITS(QCA_DDR_DDR2_CFG_DDR2_TFAW_SHIFT, 6) #if (SOC_TYPE & QCA_AR933X_SOC) @@ -244,9 +244,9 @@ #define QCA_DDR_BURST_RWP_MASK_EN_SHIFT 28 #define QCA_DDR_BURST_RWP_MASK_EN_MASK BITS(QCA_DDR_BURST_RWP_MASK_EN_SHIFT, 2) #define QCA_DDR_BURST_CPU_PRIO_BE_SHIFT 30 -#define QCA_DDR_BURST_CPU_PRIO_BE_MASK (1 << QCA_DDR_BURST_CPU_PRIO_BE_SHIFT) +#define QCA_DDR_BURST_CPU_PRIO_BE_MASK BIT(QCA_DDR_BURST_CPU_PRIO_BE_SHIFT) #define QCA_DDR_BURST_CPU_PRIO_SHIFT 31 -#define QCA_DDR_BURST_CPU_PRIO_MASK (1 << QCA_DDR_BURST_CPU_PRIO_SHIFT) +#define QCA_DDR_BURST_CPU_PRIO_MASK BIT(QCA_DDR_BURST_CPU_PRIO_SHIFT) /* DDR_BURST2 (DDR bank arbiter per client burst size 2) */ #define QCA_DDR_BURST2_WMAC_MAX_BL_SHIFT 0 @@ -258,33 +258,33 @@ /* DDR_CTRL_CFG (DDR controller configuration) */ #define QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT 0 -#define QCA_DDR_CTRL_CFG_SDRAM_EN_MASK (1 << QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT) +#define QCA_DDR_CTRL_CFG_SDRAM_EN_MASK BIT(QCA_DDR_CTRL_CFG_SDRAM_EN_SHIFT) #define QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT 1 -#define QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK (1 << QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT) +#define QCA_DDR_CTRL_CFG_HALF_WIDTH_MASK BIT(QCA_DDR_CTRL_CFG_HALF_WIDTH_SHIFT) #define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT 2 -#define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK (1 << QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT) +#define QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_MASK BIT(QCA_DDR_CTRL_CFG_CPU_DDR_SYNC_SHIFT) #define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT 3 -#define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_MASK (1 << QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT) +#define QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_MASK BIT(QCA_DDR_CTRL_CFG_SRAM_REQ_ACK_SHIFT) #define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT 4 -#define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_MASK (1 << QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT) +#define QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_MASK BIT(QCA_DDR_CTRL_CFG_SRAM_GATE_CLK_SHIFT) #define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT 6 -#define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK (1 << QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT) +#define QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK BIT(QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_SHIFT) /* DDR_CONFIG3 register (DDR DRAM configuration 3) */ #define QCA_DDR_CFG3_TRFC_LSB_SHIFT 0 #define QCA_DDR_CFG3_TRFC_LSB_MASK BITS(QCA_DDR_CFG3_TRFC_LSB_SHIFT, 2) #define QCA_DDR_CFG3_TRAS_MSB_SHIFT 2 -#define QCA_DDR_CFG3_TRAS_MSB_MASK (1 << QCA_DDR_CFG3_TRAS_MSB_SHIFT) +#define QCA_DDR_CFG3_TRAS_MSB_MASK BIT(QCA_DDR_CFG3_TRAS_MSB_SHIFT) #define QCA_DDR_CFG3_TWR_MSB_SHIFT 3 -#define QCA_DDR_CFG3_TWR_MSB_MASK (1 << QCA_DDR_CFG3_TWR_MSB_SHIFT) +#define QCA_DDR_CFG3_TWR_MSB_MASK BIT(QCA_DDR_CFG3_TWR_MSB_SHIFT) /* DDR_BIST (unknown, not described in datasheet, based on code only) */ #define QCA_DDR_BIST_TEST_EN_SHIFT 0 -#define QCA_DDR_BIST_TEST_EN_MASK (1 << QCA_DDR_BIST_TEST_EN_SHIFT) +#define QCA_DDR_BIST_TEST_EN_MASK BIT(QCA_DDR_BIST_TEST_EN_SHIFT) /* DDR_BIST_STATUS (unknown, not described in datasheet, based on code only) */ #define QCA_DDR_BIST_STATUS_DONE_SHIFT 0 -#define QCA_DDR_BIST_STATUS_DONE_MASK (1 << QCA_DDR_BIST_STATUS_DONE_SHIFT) +#define QCA_DDR_BIST_STATUS_DONE_MASK BIT(QCA_DDR_BIST_STATUS_DONE_SHIFT) #define QCA_DDR_BIST_STATUS_PASS_CNT_SHIFT 1 #define QCA_DDR_BIST_STATUS_PASS_CNT_MASK BITS(QCA_DDR_BIST_STATUS_PASS_CNT_SHIFT, 8) #define QCA_DDR_BIST_STATUS_FAIL_CNT_SHIFT 9 @@ -331,13 +331,13 @@ /* IER register (Interrupt enable) */ #define QCA_LSUART_IER_ERBFI_SHIFT 0 -#define QCA_LSUART_IER_ERBFI_MASK (1 << QCA_LSUART_IER_ERBFI_SHIFT) +#define QCA_LSUART_IER_ERBFI_MASK BIT(QCA_LSUART_IER_ERBFI_SHIFT) #define QCA_LSUART_IER_ETBEI_SHIFT 1 -#define QCA_LSUART_IER_ETBEI_MASK (1 << QCA_LSUART_IER_ETBEI_SHIFT) +#define QCA_LSUART_IER_ETBEI_MASK BIT(QCA_LSUART_IER_ETBEI_SHIFT) #define QCA_LSUART_IER_ELSI_SHIFT 2 -#define QCA_LSUART_IER_ELSI_MASK (1 << QCA_LSUART_IER_ELSI_SHIFT) +#define QCA_LSUART_IER_ELSI_MASK BIT(QCA_LSUART_IER_ELSI_SHIFT) #define QCA_LSUART_IER_EDDSI_SHIFT 3 -#define QCA_LSUART_IER_EDDSI_MASK (1 << QCA_LSUART_IER_EDDSI_SHIFT) +#define QCA_LSUART_IER_EDDSI_MASK BIT(QCA_LSUART_IER_EDDSI_SHIFT) /* IIR register (Interrupt identity) */ #define QCA_LSUART_IIR_IID_SHIFT 0 @@ -347,13 +347,13 @@ /* FCR register (FIFO control) */ #define QCA_LSUART_FCR_FIFO_EN_SHIFT 0 -#define QCA_LSUART_FCR_EDDSI_MASK (1 << QCA_LSUART_FCR_FIFO_EN_SHIFT) +#define QCA_LSUART_FCR_EDDSI_MASK BIT(QCA_LSUART_FCR_FIFO_EN_SHIFT) #define QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT 1 -#define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK (1 << QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT) +#define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK BIT(QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT) #define QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT 2 -#define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK (1 << QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT) +#define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK BIT(QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT) #define QCA_LSUART_FCR_DMA_MODE_SHIFT 3 -#define QCA_LSUART_FCR_DMA_MODE_MASK (1 << QCA_LSUART_FCR_DMA_MODE_SHIFT) +#define QCA_LSUART_FCR_DMA_MODE_MASK BIT(QCA_LSUART_FCR_DMA_MODE_SHIFT) #define QCA_LSUART_FCR_RCVR_TRIG_SHIFT 6 #define QCA_LSUART_FCR_RCVR_TRIG_MASK BITS(QCA_LSUART_FCR_RCVR_TRIG_SHIFT, 2) @@ -365,63 +365,63 @@ #define QCA_LSUART_LCR_CLS_7BIT_VAL 0x2 #define QCA_LSUART_LCR_CLS_8BIT_VAL 0x3 #define QCA_LSUART_LCR_STOP_SHIFT 2 -#define QCA_LSUART_LCR_STOP_MASK (1 << QCA_LSUART_LCR_STOP_SHIFT) +#define QCA_LSUART_LCR_STOP_MASK BIT(QCA_LSUART_LCR_STOP_SHIFT) #define QCA_LSUART_LCR_PEN_SHIFT 3 -#define QCA_LSUART_LCR_PEN_MASK (1 << QCA_LSUART_LCR_PEN_SHIFT) +#define QCA_LSUART_LCR_PEN_MASK BIT(QCA_LSUART_LCR_PEN_SHIFT) #define QCA_LSUART_LCR_EPS_SHIFT 4 -#define QCA_LSUART_LCR_EPS_MASK (1 << QCA_LSUART_LCR_EPS_SHIFT) +#define QCA_LSUART_LCR_EPS_MASK BIT(QCA_LSUART_LCR_EPS_SHIFT) #define QCA_LSUART_LCR_BREAK_SHIFT 6 -#define QCA_LSUART_LCR_BREAK_MASK (1 << QCA_LSUART_LCR_BREAK_SHIFT) +#define QCA_LSUART_LCR_BREAK_MASK BIT(QCA_LSUART_LCR_BREAK_SHIFT) #define QCA_LSUART_LCR_DLAB_SHIFT 7 -#define QCA_LSUART_LCR_DLAB_MASK (1 << QCA_LSUART_LCR_DLAB_SHIFT) +#define QCA_LSUART_LCR_DLAB_MASK BIT(QCA_LSUART_LCR_DLAB_SHIFT) /* MCR register (Modem control) */ #define QCA_LSUART_MCR_DTR_SHIFT 0 -#define QCA_LSUART_MCR_DTR_MASK (1 << QCA_LSUART_MCR_DTR_SHIFT) +#define QCA_LSUART_MCR_DTR_MASK BIT(QCA_LSUART_MCR_DTR_SHIFT) #define QCA_LSUART_MCR_RTS_SHIFT 1 -#define QCA_LSUART_MCR_RTS_MASK (1 << QCA_LSUART_MCR_RTS_SHIFT) +#define QCA_LSUART_MCR_RTS_MASK BIT(QCA_LSUART_MCR_RTS_SHIFT) #define QCA_LSUART_MCR_OUT1_SHIFT 2 -#define QCA_LSUART_MCR_OUT1_MASK (1 << QCA_LSUART_MCR_OUT1_SHIFT) +#define QCA_LSUART_MCR_OUT1_MASK BIT(QCA_LSUART_MCR_OUT1_SHIFT) #define QCA_LSUART_MCR_OUT2_SHIFT 3 -#define QCA_LSUART_MCR_OUT2_MASK (1 << QCA_LSUART_MCR_OUT2_SHIFT) +#define QCA_LSUART_MCR_OUT2_MASK BIT(QCA_LSUART_MCR_OUT2_SHIFT) #define QCA_LSUART_MCR_LOOPBACK_SHIFT 5 -#define QCA_LSUART_MCR_LOOPBACK_MASK (1 << QCA_LSUART_MCR_LOOPBACK_SHIFT) +#define QCA_LSUART_MCR_LOOPBACK_MASK BIT(QCA_LSUART_MCR_LOOPBACK_SHIFT) /* LSR register (Line status) */ #define QCA_LSUART_LSR_DR_SHIFT 0 -#define QCA_LSUART_LSR_DR_MASK (1 << QCA_LSUART_LSR_DR_SHIFT) +#define QCA_LSUART_LSR_DR_MASK BIT(QCA_LSUART_LSR_DR_SHIFT) #define QCA_LSUART_LSR_OE_SHIFT 1 -#define QCA_LSUART_LSR_OE_MASK (1 << QCA_LSUART_LSR_OE_SHIFT) +#define QCA_LSUART_LSR_OE_MASK BIT(QCA_LSUART_LSR_OE_SHIFT) #define QCA_LSUART_LSR_PE_SHIFT 2 -#define QCA_LSUART_LSR_PE_MASK (1 << QCA_LSUART_LSR_PE_SHIFT) +#define QCA_LSUART_LSR_PE_MASK BIT(QCA_LSUART_LSR_PE_SHIFT) #define QCA_LSUART_LSR_FE_SHIFT 3 -#define QCA_LSUART_LSR_FE_MASK (1 << QCA_LSUART_LSR_FE_SHIFT) +#define QCA_LSUART_LSR_FE_MASK BIT(QCA_LSUART_LSR_FE_SHIFT) #define QCA_LSUART_LSR_BI_SHIFT 4 -#define QCA_LSUART_LSR_BI_MASK (1 << QCA_LSUART_LSR_BI_SHIFT) +#define QCA_LSUART_LSR_BI_MASK BIT(QCA_LSUART_LSR_BI_SHIFT) #define QCA_LSUART_LSR_THRE_SHIFT 5 -#define QCA_LSUART_LSR_THRE_MASK (1 << QCA_LSUART_LSR_THRE_SHIFT) +#define QCA_LSUART_LSR_THRE_MASK BIT(QCA_LSUART_LSR_THRE_SHIFT) #define QCA_LSUART_LSR_TEMT_SHIFT 6 -#define QCA_LSUART_LSR_TEMT_MASK (1 << QCA_LSUART_LSR_TEMT_SHIFT) +#define QCA_LSUART_LSR_TEMT_MASK BIT(QCA_LSUART_LSR_TEMT_SHIFT) #define QCA_LSUART_LSR_FERR_SHIFT 7 -#define QCA_LSUART_LSR_FERR_MASK (1 << QCA_LSUART_LSR_FERR_SHIFT) +#define QCA_LSUART_LSR_FERR_MASK BIT(QCA_LSUART_LSR_FERR_SHIFT) /* MCR register (Modem status) */ #define QCA_LSUART_MCR_DCTS_SHIFT 0 -#define QCA_LSUART_MCR_DCTS_MASK (1 << QCA_LSUART_MCR_DCTS_SHIFT) +#define QCA_LSUART_MCR_DCTS_MASK BIT(QCA_LSUART_MCR_DCTS_SHIFT) #define QCA_LSUART_MCR_DDSR_SHIFT 1 -#define QCA_LSUART_MCR_DDSR_MASK (1 << QCA_LSUART_MCR_DDSR_SHIFT) +#define QCA_LSUART_MCR_DDSR_MASK BIT(QCA_LSUART_MCR_DDSR_SHIFT) #define QCA_LSUART_MCR_TERI_SHIFT 2 -#define QCA_LSUART_MCR_TERI_MASK (1 << QCA_LSUART_MCR_TERI_SHIFT) +#define QCA_LSUART_MCR_TERI_MASK BIT(QCA_LSUART_MCR_TERI_SHIFT) #define QCA_LSUART_MCR_DDCD_SHIFT 3 -#define QCA_LSUART_MCR_DDCD_MASK (1 << QCA_LSUART_MCR_DDCD_SHIFT) +#define QCA_LSUART_MCR_DDCD_MASK BIT(QCA_LSUART_MCR_DDCD_SHIFT) #define QCA_LSUART_MCR_CTS_SHIFT 4 -#define QCA_LSUART_MCR_CTS_MASK (1 << QCA_LSUART_MCR_CTS_SHIFT) +#define QCA_LSUART_MCR_CTS_MASK BIT(QCA_LSUART_MCR_CTS_SHIFT) #define QCA_LSUART_MCR_DSR_SHIFT 5 -#define QCA_LSUART_MCR_DSR_MASK (1 << QCA_LSUART_MCR_DSR_SHIFT) +#define QCA_LSUART_MCR_DSR_MASK BIT(QCA_LSUART_MCR_DSR_SHIFT) #define QCA_LSUART_MCR_RI_SHIFT 6 -#define QCA_LSUART_MCR_RI_MASK (1 << QCA_LSUART_MCR_RI_SHIFT) +#define QCA_LSUART_MCR_RI_MASK BIT(QCA_LSUART_MCR_RI_SHIFT) #define QCA_LSUART_MCR_DCD_SHIFT 7 -#define QCA_LSUART_MCR_DCD_MASK (1 << QCA_LSUART_MCR_DCD_SHIFT) +#define QCA_LSUART_MCR_DCD_MASK BIT(QCA_LSUART_MCR_DCD_SHIFT) /* * High-Speed UART registers @@ -440,9 +440,9 @@ #define QCA_HSUART_DATA_TX_RX_DATA_SHIFT 0 #define QCA_HSUART_DATA_TX_RX_DATA_MASK BITS(QCA_HSUART_DATA_TX_RX_DATA_SHIFT, 8) #define QCA_HSUART_DATA_RX_CSR_SHIFT 8 -#define QCA_HSUART_DATA_RX_CSR_MASK (1 << QCA_HSUART_DATA_RX_CSR_SHIFT) +#define QCA_HSUART_DATA_RX_CSR_MASK BIT(QCA_HSUART_DATA_RX_CSR_SHIFT) #define QCA_HSUART_DATA_TX_CSR_SHIFT 9 -#define QCA_HSUART_DATA_TX_CSR_MASK (1 << QCA_HSUART_DATA_TX_CSR_SHIFT) +#define QCA_HSUART_DATA_TX_CSR_MASK BIT(QCA_HSUART_DATA_TX_CSR_SHIFT) /* UART_CS register (UART configuration and status) */ #define QCA_HSUART_CS_PAR_MODE_SHIFT 0 @@ -461,25 +461,25 @@ #define QCA_HSUART_CS_FLOW_MODE_HW_VAL 0x2 #define QCA_HSUART_CS_FLOW_MODE_INV_VAL 0x3 #define QCA_HSUART_CS_DMA_EN_SHIFT 6 -#define QCA_HSUART_CS_DMA_EN_MASK (1 << QCA_HSUART_CS_DMA_EN_SHIFT) +#define QCA_HSUART_CS_DMA_EN_MASK BIT(QCA_HSUART_CS_DMA_EN_SHIFT) #define QCA_HSUART_CS_RX_READY_ORIDE_SHIFT 7 -#define QCA_HSUART_CS_RX_READY_ORIDE_MASK (1 << QCA_HSUART_CS_RX_READY_ORIDE_SHIFT) +#define QCA_HSUART_CS_RX_READY_ORIDE_MASK BIT(QCA_HSUART_CS_RX_READY_ORIDE_SHIFT) #define QCA_HSUART_CS_TX_READY_ORIDE_SHIFT 8 -#define QCA_HSUART_CS_TX_READY_ORIDE_MASK (1 << QCA_HSUART_CS_TX_READY_ORIDE_SHIFT) +#define QCA_HSUART_CS_TX_READY_ORIDE_MASK BIT(QCA_HSUART_CS_TX_READY_ORIDE_SHIFT) #define QCA_HSUART_CS_TX_READY_SHIFT 9 -#define QCA_HSUART_CS_TX_READY_MASK (1 << QCA_HSUART_CS_TX_READY_SHIFT) +#define QCA_HSUART_CS_TX_READY_MASK BIT(QCA_HSUART_CS_TX_READY_SHIFT) #define QCA_HSUART_CS_RX_BREAK_SHIFT 10 -#define QCA_HSUART_CS_RX_BREAK_MASK (1 << QCA_HSUART_CS_RX_BREAK_SHIFT) +#define QCA_HSUART_CS_RX_BREAK_MASK BIT(QCA_HSUART_CS_RX_BREAK_SHIFT) #define QCA_HSUART_CS_TX_BREAK_SHIFT 11 -#define QCA_HSUART_CS_TX_BREAK_MASK (1 << QCA_HSUART_CS_TX_BREAK_SHIFT) +#define QCA_HSUART_CS_TX_BREAK_MASK BIT(QCA_HSUART_CS_TX_BREAK_SHIFT) #define QCA_HSUART_CS_HOST_INT_SHIFT 12 -#define QCA_HSUART_CS_HOST_INT_MASK (1 << QCA_HSUART_CS_HOST_INT_SHIFT) +#define QCA_HSUART_CS_HOST_INT_MASK BIT(QCA_HSUART_CS_HOST_INT_SHIFT) #define QCA_HSUART_CS_HOST_INT_EN_SHIFT 13 -#define QCA_HSUART_CS_HOST_INT_EN_MASK (1 << QCA_HSUART_CS_HOST_INT_EN_SHIFT) +#define QCA_HSUART_CS_HOST_INT_EN_MASK BIT(QCA_HSUART_CS_HOST_INT_EN_SHIFT) #define QCA_HSUART_CS_TX_BUSY_SHIFT 14 -#define QCA_HSUART_CS_TX_BUSY_MASK (1 << QCA_HSUART_CS_TX_BUSY_SHIFT) +#define QCA_HSUART_CS_TX_BUSY_MASK BIT(QCA_HSUART_CS_TX_BUSY_SHIFT) #define QCA_HSUART_CS_RX_BUSY_SHIFT 15 -#define QCA_HSUART_CS_RX_BUSY_MASK (1 << QCA_HSUART_CS_RX_BUSY_SHIFT) +#define QCA_HSUART_CS_RX_BUSY_MASK BIT(QCA_HSUART_CS_RX_BUSY_SHIFT) /* UART_CLOCK register (UART clock) */ #define QCA_HSUART_CLK_STEP_SHIFT 0 @@ -491,47 +491,47 @@ /* UART_INT register (UART interrupt/control status) */ #define QCA_HSUART_INT_RX_VALID_SHIFT 0 -#define QCA_HSUART_INT_RX_VALID_MASK (1 << QCA_HSUART_INT_RX_VALID_SHIFT) +#define QCA_HSUART_INT_RX_VALID_MASK BIT(QCA_HSUART_INT_RX_VALID_SHIFT) #define QCA_HSUART_INT_TX_READY_SHIFT 1 -#define QCA_HSUART_INT_TX_READY_MASK (1 << QCA_HSUART_INT_TX_READY_SHIFT) +#define QCA_HSUART_INT_TX_READY_MASK BIT(QCA_HSUART_INT_TX_READY_SHIFT) #define QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT 2 -#define QCA_HSUART_INT_RX_FRAMING_ERR_MASK (1 << QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT) +#define QCA_HSUART_INT_RX_FRAMING_ERR_MASK BIT(QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT) #define QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT 3 -#define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT) +#define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT) #define QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT 4 -#define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT) +#define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT) #define QCA_HSUART_INT_RX_PARITY_ERR_SHIFT 5 -#define QCA_HSUART_INT_RX_PARITY_ERR_MASK (1 << QCA_HSUART_INT_RX_PARITY_ERR_SHIFT) +#define QCA_HSUART_INT_RX_PARITY_ERR_MASK BIT(QCA_HSUART_INT_RX_PARITY_ERR_SHIFT) #define QCA_HSUART_INT_RX_BREAK_ON_SHIFT 6 -#define QCA_HSUART_INT_RX_BREAK_ON_MASK (1 << QCA_HSUART_INT_RX_BREAK_ON_SHIFT) +#define QCA_HSUART_INT_RX_BREAK_ON_MASK BIT(QCA_HSUART_INT_RX_BREAK_ON_SHIFT) #define QCA_HSUART_INT_RX_BREAK_OFF_SHIFT 7 -#define QCA_HSUART_INT_RX_BREAK_OFF_MASK (1 << QCA_HSUART_INT_RX_BREAK_OFF_SHIFT) +#define QCA_HSUART_INT_RX_BREAK_OFF_MASK BIT(QCA_HSUART_INT_RX_BREAK_OFF_SHIFT) #define QCA_HSUART_INT_RX_FULL_SHIFT 8 -#define QCA_HSUART_INT_RX_FULL_MASK (1 << QCA_HSUART_INT_RX_FULL_SHIFT) +#define QCA_HSUART_INT_RX_FULL_MASK BIT(QCA_HSUART_INT_RX_FULL_SHIFT) #define QCA_HSUART_INT_TX_EMPTY_SHIFT 9 -#define QCA_HSUART_INT_TX_EMPTY_MASK (1 << QCA_HSUART_INT_TX_EMPTY_SHIFT) +#define QCA_HSUART_INT_TX_EMPTY_MASK BIT(QCA_HSUART_INT_TX_EMPTY_SHIFT) /* UART_INT_EN register (UART interrupt enable) */ #define QCA_HSUART_INT_EN_RX_VALID_SHIFT 0 -#define QCA_HSUART_INT_EN_RX_VALID_MASK (1 << QCA_HSUART_INT_EN_RX_VALID_SHIFT) +#define QCA_HSUART_INT_EN_RX_VALID_MASK BIT(QCA_HSUART_INT_EN_RX_VALID_SHIFT) #define QCA_HSUART_INT_EN_TX_READY_SHIFT 1 -#define QCA_HSUART_INT_EN_TX_READY_MASK (1 << QCA_HSUART_INT_EN_TX_READY_SHIFT) +#define QCA_HSUART_INT_EN_TX_READY_MASK BIT(QCA_HSUART_INT_EN_TX_READY_SHIFT) #define QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT 2 -#define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT) +#define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT) #define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT 3 -#define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT) +#define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT) #define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT 4 -#define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT) +#define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK BIT(QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT) #define QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT 5 -#define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT) +#define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK BIT(QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT) #define QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT 6 -#define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK (1 << QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT) +#define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK BIT(QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT) #define QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT 7 -#define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK (1 << QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT) +#define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK BIT(QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT) #define QCA_HSUART_INT_EN_RX_FULL_SHIFT 8 -#define QCA_HSUART_INT_EN_RX_FULL_MASK (1 << QCA_HSUART_INT_EN_RX_FULL_SHIFT) +#define QCA_HSUART_INT_EN_RX_FULL_MASK BIT(QCA_HSUART_INT_EN_RX_FULL_SHIFT) #define QCA_HSUART_INT_EN_TX_EMPTY_SHIFT 9 -#define QCA_HSUART_INT_EN_TX_EMPTY_MASK (1 << QCA_HSUART_INT_EN_TX_EMPTY_SHIFT) +#define QCA_HSUART_INT_EN_TX_EMPTY_MASK BIT(QCA_HSUART_INT_EN_TX_EMPTY_SHIFT) /* @@ -595,72 +595,72 @@ /* GPIO_FUNCTION_1/2 register (GPIO function) */ #if (SOC_TYPE & QCA_AR933X_SOC) #define QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT 0 - #define QCA_GPIO_FUNC_1_JTAG_DIS_MASK (1 << QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT) + #define QCA_GPIO_FUNC_1_JTAG_DIS_MASK BIT(QCA_GPIO_FUNC_1_JTAG_DIS_SHIFT) #define QCA_GPIO_FUNC_1_UART_EN_SHIFT 1 - #define QCA_GPIO_FUNC_1_UART_EN_MASK (1 << QCA_GPIO_FUNC_1_UART_EN_SHIFT) + #define QCA_GPIO_FUNC_1_UART_EN_MASK BIT(QCA_GPIO_FUNC_1_UART_EN_SHIFT) #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT 2 - #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK (1 << QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT) + #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK BIT(QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT) #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT 3 - #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT) #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT 4 - #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT) #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT 5 - #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED2_EN_SHIFT) #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT 6 - #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED3_EN_SHIFT) #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT 7 - #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED4_EN_SHIFT) #define QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT 13 - #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK (1 << QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT) + #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK BIT(QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT) #define QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT 14 - #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK (1 << QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT) + #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK BIT(QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT) #define QCA_GPIO_FUNC_1_SPI_EN_SHIFT 18 - #define QCA_GPIO_FUNC_1_SPI_EN_MASK (1 << QCA_GPIO_FUNC_1_SPI_EN_SHIFT) + #define QCA_GPIO_FUNC_1_SPI_EN_MASK BIT(QCA_GPIO_FUNC_1_SPI_EN_SHIFT) #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT 23 - #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT) #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT 24 - #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT) #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT 25 - #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK BIT(QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT) #define QCA_GPIO_FUNC_1_I2S_EN_SHIFT 26 - #define QCA_GPIO_FUNC_1_I2S_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_EN_SHIFT) + #define QCA_GPIO_FUNC_1_I2S_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_EN_SHIFT) #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT 27 - #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT) + #define QCA_GPIO_FUNC_1_I2S_MCLK_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_MCLK_EN_SHIFT) #define QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT 29 - #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT) + #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK BIT(QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT) #define QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT 30 - #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK (1 << QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT) + #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK BIT(QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT) #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT 31 - #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK (1 << QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT) + #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK BIT(QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT) #define QCA_GPIO_FUNC_2_MIC_DIS_SHIFT 0 - #define QCA_GPIO_FUNC_2_MIC_DIS_MASK (1 << QCA_GPIO_FUNC_2_MIC_DIS_SHIFT) + #define QCA_GPIO_FUNC_2_MIC_DIS_MASK BIT(QCA_GPIO_FUNC_2_MIC_DIS_SHIFT) #define QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT 1 - #define QCA_GPIO_FUNC_2_I2S_ON_LED_MASK (1 << QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT) + #define QCA_GPIO_FUNC_2_I2S_ON_LED_MASK BIT(QCA_GPIO_FUNC_2_I2S_ON_LED_SHIFT) #define QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT 2 - #define QCA_GPIO_FUNC_2_SPDIF_ON23_MASK (1 << QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT) + #define QCA_GPIO_FUNC_2_SPDIF_ON23_MASK BIT(QCA_GPIO_FUNC_2_SPDIF_ON23_SHIFT) #define QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT 3 - #define QCA_GPIO_FUNC_2_I2SCK_ON1_MASK (1 << QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT) + #define QCA_GPIO_FUNC_2_I2SCK_ON1_MASK BIT(QCA_GPIO_FUNC_2_I2SCK_ON1_SHIFT) #define QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT 4 - #define QCA_GPIO_FUNC_2_I2SWS_ON0_MASK (1 << QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT) + #define QCA_GPIO_FUNC_2_I2SWS_ON0_MASK BIT(QCA_GPIO_FUNC_2_I2SWS_ON0_SHIFT) #define QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT 5 - #define QCA_GPIO_FUNC_2_I2SSD_ON12_MASK (1 << QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT) + #define QCA_GPIO_FUNC_2_I2SSD_ON12_MASK BIT(QCA_GPIO_FUNC_2_I2SSD_ON12_SHIFT) #define QCA_GPIO_FUNC_2_WPS_DIS_SHIFT 8 - #define QCA_GPIO_FUNC_2_WPS_DIS_MASK (1 << QCA_GPIO_FUNC_2_WPS_DIS_SHIFT) + #define QCA_GPIO_FUNC_2_WPS_DIS_MASK BIT(QCA_GPIO_FUNC_2_WPS_DIS_SHIFT) #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT 9 - #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK (1 << QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT) + #define QCA_GPIO_FUNC_2_JUMPSTART_DIS_MASK BIT(QCA_GPIO_FUNC_2_JUMPSTART_DIS_SHIFT) #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT 10 - #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_MASK (1 << QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT) + #define QCA_GPIO_FUNC_2_WLAN_LED_ON0_MASK BIT(QCA_GPIO_FUNC_2_WLAN_LED_ON0_SHIFT) #define QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT 11 - #define QCA_GPIO_FUNC_2_USB_LED_ON1_MASK (1 << QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT) + #define QCA_GPIO_FUNC_2_USB_LED_ON1_MASK BIT(QCA_GPIO_FUNC_2_USB_LED_ON1_SHIFT) #define QCA_GPIO_FUNC_2_LNA_ON28_SHIFT 12 - #define QCA_GPIO_FUNC_2_LNA_ON28_MASK (1 << QCA_GPIO_FUNC_2_LNA_ON28_SHIFT) + #define QCA_GPIO_FUNC_2_LNA_ON28_MASK BIT(QCA_GPIO_FUNC_2_LNA_ON28_SHIFT) #define QCA_GPIO_FUNC_2_SLIC_EN_SHIFT 13 - #define QCA_GPIO_FUNC_2_SLIC_EN_MASK (1 << QCA_GPIO_FUNC_2_SLIC_EN_SHIFT) + #define QCA_GPIO_FUNC_2_SLIC_EN_MASK BIT(QCA_GPIO_FUNC_2_SLIC_EN_SHIFT) #define QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT 14 - #define QCA_GPIO_FUNC_2_SLIC_ON18_22_MASK (1 << QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT) + #define QCA_GPIO_FUNC_2_SLIC_ON18_22_MASK BIT(QCA_GPIO_FUNC_2_SLIC_ON18_22_SHIFT) #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT 15 - #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK (1 << QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT) + #define QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_MASK BIT(QCA_GPIO_FUNC_2_SLIC_DIO_MUX_EN_SHIFT) #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT 16 #define QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_MASK BITS(QCA_GPIO_FUNC_2_MDIO_SLAVE_ADDR_SHIFT, 3) #endif @@ -901,25 +901,25 @@ /* GPIO_FUNCTION register (GPIO function) */ #define QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT 0 -#define QCA_GPIO_FUNC_GPIO_SRIF_EN_MASK (1 << QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT) +#define QCA_GPIO_FUNC_GPIO_SRIF_EN_MASK BIT(QCA_GPIO_FUNC_GPIO_SRIF_EN_SHIFT) #define QCA_GPIO_FUNC_JTAG_DIS_SHIFT 1 -#define QCA_GPIO_FUNC_JTAG_DIS_MASK (1 << QCA_GPIO_FUNC_JTAG_DIS_SHIFT) +#define QCA_GPIO_FUNC_JTAG_DIS_MASK BIT(QCA_GPIO_FUNC_JTAG_DIS_SHIFT) #define QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT 2 -#define QCA_GPIO_FUNC_CLK_OBS0_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT) +#define QCA_GPIO_FUNC_CLK_OBS0_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS0_EN_SHIFT) #define QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT 3 -#define QCA_GPIO_FUNC_CLK_OBS1_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT) +#define QCA_GPIO_FUNC_CLK_OBS1_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS1_EN_SHIFT) #define QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT 4 -#define QCA_GPIO_FUNC_CLK_OBS2_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT) +#define QCA_GPIO_FUNC_CLK_OBS2_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS2_EN_SHIFT) #define QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT 5 -#define QCA_GPIO_FUNC_CLK_OBS3_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT) +#define QCA_GPIO_FUNC_CLK_OBS3_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS3_EN_SHIFT) #define QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT 6 -#define QCA_GPIO_FUNC_CLK_OBS4_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT) +#define QCA_GPIO_FUNC_CLK_OBS4_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS4_EN_SHIFT) #define QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT 7 -#define QCA_GPIO_FUNC_CLK_OBS5_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT) +#define QCA_GPIO_FUNC_CLK_OBS5_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS5_EN_SHIFT) #define QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT 8 -#define QCA_GPIO_FUNC_CLK_OBS6_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT) +#define QCA_GPIO_FUNC_CLK_OBS6_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS6_EN_SHIFT) #define QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT 9 -#define QCA_GPIO_FUNC_CLK_OBS7_EN_MASK (1 << QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT) +#define QCA_GPIO_FUNC_CLK_OBS7_EN_MASK BIT(QCA_GPIO_FUNC_CLK_OBS7_EN_SHIFT) /* * PLL control registers @@ -996,7 +996,7 @@ #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 16 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5) #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 21 - #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK (1 << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT) + #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BIT(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT) #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 23 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3) #else @@ -1013,9 +1013,9 @@ #endif #define QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT 30 -#define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK (1 << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT) +#define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT) #define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT 31 -#define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK (1 << QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT) +#define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT) /* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */ #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT 0 @@ -1023,7 +1023,7 @@ /* CPU_CLOCK_CONTROL register (CPU clock control, AR933x only) */ #define QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT 2 -#define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK (1 << QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT) +#define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK BIT(QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT) #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT 5 #define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT, 2) #define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT 10 @@ -1033,9 +1033,9 @@ /* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */ #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT 3 -#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT) +#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK BIT(QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT) #define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT 4 -#define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT) +#define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK BIT(QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT) /* ETH_XMII_CONTROL register (Ethernet XMII control) */ #define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT 0 @@ -1045,43 +1045,43 @@ #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT 16 #define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT, 8) #define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT 24 -#define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK (1 << QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT) +#define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK BIT(QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT) #define QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT 25 -#define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT) +#define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK BIT(QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT) #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT 26 #define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT, 2) #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT 28 #define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT, 2) #define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT 30 -#define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT) +#define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK BIT(QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT) #define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT 31 -#define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK (1 << QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT) +#define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK BIT(QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT) /* SUSPEND register (USB suspend, AR933x only) */ #define QCA_PLL_USB_SUSPEND_EN_SHIFT 0 -#define QCA_PLL_USB_SUSPEND_EN_MASK (1 << QCA_PLL_USB_SUSPEND_EN_SHIFT) +#define QCA_PLL_USB_SUSPEND_EN_MASK BIT(QCA_PLL_USB_SUSPEND_EN_SHIFT) #define QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT 8 #define QCA_PLL_USB_SUSPEND_RESTART_TIME_MASK BITS(QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT, 20) /* WLAN_CLOCK_CONTROL register (WLAN clock control, AR933x only) */ #define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT 0 -#define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT) #define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT 1 -#define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT) #define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT 2 -#define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT) #define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT 3 -#define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_PLLPWD_CTL_SHIFT) #define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT 4 -#define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT) #define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT 8 -#define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT) #define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT 9 -#define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT) #define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT 10 -#define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT) #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT 12 -#define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT) /* DDR_PLL_CONFIG register (DDR PLL configuration) */ #define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0 @@ -1095,19 +1095,19 @@ #define QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT 23 #define QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT, 3) #define QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT 30 -#define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK (1 << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT) +#define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT) #define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT 31 -#define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK (1 << QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT) +#define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT) /* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */ #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT 1 -#define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT 2 -#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT 3 -#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT 4 -#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT, 5) #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 @@ -1115,15 +1115,15 @@ #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5) #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20 -#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21 -#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT 22 -#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT 23 -#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24 -#define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) /* DDR_PLL_DITHER register (DDR PLL dither parameter) */ #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0 @@ -1135,7 +1135,7 @@ #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT 27 #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT, 4) #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT 31 -#define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT) +#define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT) #if (SOC_TYPE & QCA_AR933X_SOC) /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */ @@ -1150,7 +1150,7 @@ #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14) #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31 - #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) + #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) #else /* CPU_PLL_DITHER register (CPU PLL dither parameter) */ #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0 @@ -1162,7 +1162,7 @@ #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6) #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31 - #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) + #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) #endif /* @@ -1196,9 +1196,9 @@ /* DPLL2 (common for CPU, AUD, DDR and PCIE) */ #if (SOC_TYPE & QCA_QCA953X_SOC) #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT 0 - #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK (1 << QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT) + #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK BIT(QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT) #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT 1 - #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK (1 << QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT) + #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT) #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT 2 #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 10) #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT 12 @@ -1206,30 +1206,30 @@ #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 19 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 3) #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 22 - #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT) + #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT) #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT 23 - #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK (1 << QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT) + #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT) #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT 24 - #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK (1 << QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT) + #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK BIT(QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT) #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 25 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4) #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 29 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 2) #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 31 - #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT) + #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT) #else #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 13 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2) #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 16 - #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT) + #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT) #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 19 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7) #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 26 #define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KI_SHIFT, 4) #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 30 - #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT) + #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT) #define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT 31 - #define QCA_PLL_SRIF_DPLL2_RANGE_MASK (1 << QCA_PLL_SRIF_DPLL2_RANGE_SHIFT) + #define QCA_PLL_SRIF_DPLL2_RANGE_MASK BIT(QCA_PLL_SRIF_DPLL2_RANGE_SHIFT) #endif /* DPLL3 (common for CPU, AUD, DDR and PCIE) */ @@ -1271,23 +1271,23 @@ #else #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 4 #endif -#define QCA_RST_BOOTSTRAP_REF_CLK_MASK (1 << QCA_RST_BOOTSTRAP_REF_CLK_SHIFT) +#define QCA_RST_BOOTSTRAP_REF_CLK_MASK BIT(QCA_RST_BOOTSTRAP_REF_CLK_SHIFT) #define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL 0x0 #define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL 0x1 #if (SOC_TYPE & QCA_AR933X_SOC) #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 3 - #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK (1 << QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT) + #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK BIT(QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT) #define QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT 4 - #define QCA_RST_BOOTSTRAP_EEPBUSY_MASK (1 << QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT) + #define QCA_RST_BOOTSTRAP_EEPBUSY_MASK BIT(QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT) #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 12 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2) #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT 16 - #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK (1 << QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT) + #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK BIT(QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT) #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT 17 - #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT) + #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK BIT(QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT) #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT 18 - #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT) + #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK BIT(QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT) #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 @@ -1299,17 +1299,17 @@ #if (SOC_TYPE & QCA_QCA953X_SOC) #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2) #else - #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK (1 << QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT) + #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BIT(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT) #endif #define QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT 2 - #define QCA_RST_BOOTSTRAP_BOOT_SEL_MASK (1 << QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT) + #define QCA_RST_BOOTSTRAP_BOOT_SEL_MASK BIT(QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT) #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT 3 - #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK (1 << QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT) + #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK BIT(QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT) #define QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT 5 - #define QCA_RST_BOOTSTRAP_JTAG_MODE_MASK (1 << QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT) + #define QCA_RST_BOOTSTRAP_JTAG_MODE_MASK BIT(QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT) #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 7 - #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK (1 << QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT) + #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK BIT(QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT) #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 @@ -1318,110 +1318,110 @@ /* RST_RESET */ #define QCA_RST_RESET_I2C_RST_SHIFT 0 -#define QCA_RST_RESET_I2C_RST_MASK (1 << QCA_RST_RESET_I2C_RST_SHIFT) +#define QCA_RST_RESET_I2C_RST_MASK BIT(QCA_RST_RESET_I2C_RST_SHIFT) #define QCA_RST_RESET_MBOX_RST_SHIFT 1 -#define QCA_RST_RESET_MBOX_RST_MASK (1 << QCA_RST_RESET_MBOX_RST_SHIFT) +#define QCA_RST_RESET_MBOX_RST_MASK BIT(QCA_RST_RESET_MBOX_RST_SHIFT) #define QCA_RST_RESET_LUT_RST_SHIFT 2 -#define QCA_RST_RESET_LUT_RST_MASK (1 << QCA_RST_RESET_LUT_RST_SHIFT) +#define QCA_RST_RESET_LUT_RST_MASK BIT(QCA_RST_RESET_LUT_RST_SHIFT) #define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT 3 -#define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK (1 << QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT) +#define QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_MASK BIT(QCA_RST_RESET_USB_PHY_SUSPEND_ORIDE_SHIFT) #define QCA_RST_RESET_USB_PHY_RST_SHIFT 4 -#define QCA_RST_RESET_USB_PHY_RST_MASK (1 << QCA_RST_RESET_USB_PHY_RST_SHIFT) +#define QCA_RST_RESET_USB_PHY_RST_MASK BIT(QCA_RST_RESET_USB_PHY_RST_SHIFT) #define QCA_RST_RESET_USB_HOST_RST_SHIFT 5 -#define QCA_RST_RESET_USB_HOST_RST_MASK (1 << QCA_RST_RESET_USB_HOST_RST_SHIFT) +#define QCA_RST_RESET_USB_HOST_RST_MASK BIT(QCA_RST_RESET_USB_HOST_RST_SHIFT) #if (SOC_TYPE & QCA_AR933X_SOC) #define QCA_RST_RESET_SLIC_RST_SHIFT 6 - #define QCA_RST_RESET_SLIC_RST_MASK (1 << QCA_RST_RESET_SLIC_RST_SHIFT) + #define QCA_RST_RESET_SLIC_RST_MASK BIT(QCA_RST_RESET_SLIC_RST_SHIFT) #else #define QCA_RST_RESET_PCIE_RST_SHIFT 6 - #define QCA_RST_RESET_PCIE_RST_MASK (1 << QCA_RST_RESET_PCIE_RST_SHIFT) + #define QCA_RST_RESET_PCIE_RST_MASK BIT(QCA_RST_RESET_PCIE_RST_SHIFT) #define QCA_RST_RESET_SLIC_RST_SHIFT 30 - #define QCA_RST_RESET_SLIC_RST_MASK (1 << QCA_RST_RESET_SLIC_RST_SHIFT) + #define QCA_RST_RESET_SLIC_RST_MASK BIT(QCA_RST_RESET_SLIC_RST_SHIFT) #endif #define QCA_RST_RESET_PCIE_PHY_RST_SHIFT 7 -#define QCA_RST_RESET_PCIE_PHY_RST_MASK (1 << QCA_RST_RESET_PCIE_PHY_RST_SHIFT) +#define QCA_RST_RESET_PCIE_PHY_RST_MASK BIT(QCA_RST_RESET_PCIE_PHY_RST_SHIFT) #if (SOC_TYPE & QCA_QCA955X_SOC) #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT 8 - #define QCA_RST_RESET_ETH_SGMII_RST_MASK (1 << QCA_RST_RESET_ETH_SGMII_RST_SHIFT) + #define QCA_RST_RESET_ETH_SGMII_RST_MASK BIT(QCA_RST_RESET_ETH_SGMII_RST_SHIFT) #else #define QCA_RST_RESET_ETH_SWITCH_RST_SHIFT 8 - #define QCA_RST_RESET_ETH_SWITCH_RST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_RST_SHIFT) + #define QCA_RST_RESET_ETH_SWITCH_RST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_RST_SHIFT) #endif #define QCA_RST_RESET_GE0_MAC_RST_SHIFT 9 -#define QCA_RST_RESET_GE0_MAC_RST_MASK (1 << QCA_RST_RESET_GE0_MAC_RST_SHIFT) +#define QCA_RST_RESET_GE0_MAC_RST_MASK BIT(QCA_RST_RESET_GE0_MAC_RST_SHIFT) #define QCA_RST_RESET_HOST_DMA_INT_SHIFT 10 -#define QCA_RST_RESET_HOST_DMA_INT_MASK (1 << QCA_RST_RESET_HOST_DMA_INT_SHIFT) +#define QCA_RST_RESET_HOST_DMA_INT_MASK BIT(QCA_RST_RESET_HOST_DMA_INT_SHIFT) #if (SOC_TYPE & QCA_AR933X_SOC) #define QCA_RST_RESET_WLAN_RST_SHIFT 11 - #define QCA_RST_RESET_WLAN_RST_MASK (1 << QCA_RST_RESET_WLAN_RST_SHIFT) + #define QCA_RST_RESET_WLAN_RST_MASK BIT(QCA_RST_RESET_WLAN_RST_SHIFT) #else #define QCA_RST_RESET_USB_PHY_ARST_SHIFT 11 - #define QCA_RST_RESET_USB_PHY_ARST_MASK (1 << QCA_RST_RESET_USB_PHY_ARST_SHIFT) + #define QCA_RST_RESET_USB_PHY_ARST_MASK BIT(QCA_RST_RESET_USB_PHY_ARST_SHIFT) #endif #if (SOC_TYPE & QCA_AR933X_SOC) #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 14 - #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT) + #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT) #else #if (SOC_TYPE & QCA_QCA955X_SOC) #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT 12 - #define QCA_RST_RESET_ETH_SGMII_ARST_MASK (1 << QCA_RST_RESET_ETH_SGMII_ARST_SHIFT) + #define QCA_RST_RESET_ETH_SGMII_ARST_MASK BIT(QCA_RST_RESET_ETH_SGMII_ARST_SHIFT) #else #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT 12 - #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT) + #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK BIT(QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT) #endif #define QCA_RST_RESET_NANDF_RST_SHIFT 14 - #define QCA_RST_RESET_NANDF_RST_MASK (1 << QCA_RST_RESET_NANDF_RST_SHIFT) + #define QCA_RST_RESET_NANDF_RST_MASK BIT(QCA_RST_RESET_NANDF_RST_SHIFT) #endif #define QCA_RST_RESET_GE1_MAC_RST_SHIFT 13 -#define QCA_RST_RESET_GE1_MAC_RST_MASK (1 << QCA_RST_RESET_GE1_MAC_RST_SHIFT) +#define QCA_RST_RESET_GE1_MAC_RST_MASK BIT(QCA_RST_RESET_GE1_MAC_RST_SHIFT) #define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT 15 -#define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK (1 << QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT) +#define QCA_RST_RESET_USB_PHY_PLLPWD_EXT_MASK BIT(QCA_RST_RESET_USB_PHY_PLLPWD_EXT_SHIFT) #define QCA_RST_RESET_DDR_RST_SHIFT 16 -#define QCA_RST_RESET_DDR_RST_MASK (1 << QCA_RST_RESET_DDR_RST_SHIFT) +#define QCA_RST_RESET_DDR_RST_MASK BIT(QCA_RST_RESET_DDR_RST_SHIFT) #define QCA_RST_RESET_HSUART_RST_SHIFT 17 -#define QCA_RST_RESET_HSUART_RST_MASK (1 << QCA_RST_RESET_HSUART_RST_SHIFT) +#define QCA_RST_RESET_HSUART_RST_MASK BIT(QCA_RST_RESET_HSUART_RST_SHIFT) #define QCA_RST_RESET_PCIEEP_RST_SHIFT 18 -#define QCA_RST_RESET_PCIEEP_RST_MASK (1 << QCA_RST_RESET_PCIEEP_RST_SHIFT) +#define QCA_RST_RESET_PCIEEP_RST_MASK BIT(QCA_RST_RESET_PCIEEP_RST_SHIFT) #define QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT 19 -#define QCA_RST_RESET_HOST_DMA_RST_INT_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT) +#define QCA_RST_RESET_HOST_DMA_RST_INT_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_INT_SHIFT) #define QCA_RST_RESET_CPU_COLD_RST_SHIFT 20 -#define QCA_RST_RESET_CPU_COLD_RST_MASK (1 << QCA_RST_RESET_CPU_COLD_RST_SHIFT) +#define QCA_RST_RESET_CPU_COLD_RST_MASK BIT(QCA_RST_RESET_CPU_COLD_RST_SHIFT) #define QCA_RST_RESET_CPU_NMI_SHIFT 21 -#define QCA_RST_RESET_CPU_NMI_MASK (1 << QCA_RST_RESET_CPU_NMI_SHIFT) +#define QCA_RST_RESET_CPU_NMI_MASK BIT(QCA_RST_RESET_CPU_NMI_SHIFT) #define QCA_RST_RESET_GE0_MDIO_RST_SHIFT 22 -#define QCA_RST_RESET_GE0_MDIO_RST_MASK (1 << QCA_RST_RESET_GE0_MDIO_RST_SHIFT) +#define QCA_RST_RESET_GE0_MDIO_RST_MASK BIT(QCA_RST_RESET_GE0_MDIO_RST_SHIFT) #define QCA_RST_RESET_GE1_MDIO_RST_SHIFT 23 -#define QCA_RST_RESET_GE1_MDIO_RST_MASK (1 << QCA_RST_RESET_GE1_MDIO_RST_SHIFT) +#define QCA_RST_RESET_GE1_MDIO_RST_MASK BIT(QCA_RST_RESET_GE1_MDIO_RST_SHIFT) #define QCA_RST_RESET_FULL_CHIP_RST_SHIFT 24 -#define QCA_RST_RESET_FULL_CHIP_RST_MASK (1 << QCA_RST_RESET_FULL_CHIP_RST_SHIFT) +#define QCA_RST_RESET_FULL_CHIP_RST_MASK BIT(QCA_RST_RESET_FULL_CHIP_RST_SHIFT) #define QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT 25 -#define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK (1 << QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT) +#define QCA_RST_RESET_CHECKSUM_ACC_RST_MASK BIT(QCA_RST_RESET_CHECKSUM_ACC_RST_SHIFT) #define QCA_RST_RESET_PCIEEP_RST_INT_SHIFT 26 -#define QCA_RST_RESET_PCIEEP_RST_INT_MASK (1 << QCA_RST_RESET_PCIEEP_RST_INT_SHIFT) +#define QCA_RST_RESET_PCIEEP_RST_INT_MASK BIT(QCA_RST_RESET_PCIEEP_RST_INT_SHIFT) #define QCA_RST_RESET_RTC_RST_SHIFT 27 -#define QCA_RST_RESET_RTC_RST_MASK (1 << QCA_RST_RESET_RTC_RST_SHIFT) +#define QCA_RST_RESET_RTC_RST_MASK BIT(QCA_RST_RESET_RTC_RST_SHIFT) #define QCA_RST_RESET_EXT_RST_SHIFT 28 -#define QCA_RST_RESET_EXT_RST_MASK (1 << QCA_RST_RESET_EXT_RST_SHIFT) +#define QCA_RST_RESET_EXT_RST_MASK BIT(QCA_RST_RESET_EXT_RST_SHIFT) #if (SOC_TYPE & QCA_AR934X_SOC) |\ (SOC_TYPE & QCA_QCA955X_SOC) #define QCA_RST_RESET_HOST_DMA_RST_SHIFT 29 - #define QCA_RST_RESET_HOST_DMA_RST_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_SHIFT) + #define QCA_RST_RESET_HOST_DMA_RST_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_SHIFT) #else #define QCA_RST_RESET_USB_EXT_PWR_SHIFT 29 - #define QCA_RST_RESET_USB_EXT_PWR_MASK (1 << QCA_RST_RESET_USB_EXT_PWR_SHIFT) + #define QCA_RST_RESET_USB_EXT_PWR_MASK BIT(QCA_RST_RESET_USB_EXT_PWR_SHIFT) #endif #define QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT 31 -#define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK (1 << QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT) +#define QCA_RST_RESET_HOST_DMA_RST_STATUS_MASK BIT(QCA_RST_RESET_HOST_DMA_RST_STATUS_SHIFT) /* RST_REVISION_ID (Chip revision ID) */ #define QCA_RST_REVISION_ID_MAJOR_SHIFT 4 @@ -1471,13 +1471,13 @@ /* RESET_CONTROL register (RTC reset control) */ #define QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT 0 -#define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK (1 << QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT) +#define QCA_RTC_RST_CTRL_MAC_WARM_RST_MASK BIT(QCA_RTC_RST_CTRL_MAC_WARM_RST_SHIFT) #define QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT 1 -#define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK (1 << QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT) +#define QCA_RTC_RST_CTRL_MAC_COLD_RST_MASK BIT(QCA_RTC_RST_CTRL_MAC_COLD_RST_SHIFT) #define QCA_RTC_RST_CTRL_WARM_RST_SHIFT 2 -#define QCA_RTC_RST_CTRL_WARM_RST_MASK (1 << QCA_RTC_RST_CTRL_WARM_RST_SHIFT) +#define QCA_RTC_RST_CTRL_WARM_RST_MASK BIT(QCA_RTC_RST_CTRL_WARM_RST_SHIFT) #define QCA_RTC_RST_CTRL_COLD_RST_SHIFT 3 -#define QCA_RTC_RST_CTRL_COLD_RST_MASK (1 << QCA_RTC_RST_CTRL_COLD_RST_SHIFT) +#define QCA_RTC_RST_CTRL_COLD_RST_MASK BIT(QCA_RTC_RST_CTRL_COLD_RST_SHIFT) /* RESET_CAUSE register (Reset cause) */ #define QCA_RTC_RST_CAUSE_LAST_SHIFT 0 @@ -1489,27 +1489,27 @@ /* RTC_SYNC_REGISTER register (RTC reset, force sleep and force wakeup) */ #define QCA_RTC_SYNC_RST_RESET_SHIFT 0 -#define QCA_RTC_SYNC_RST_RESET_MASK (1 << QCA_RTC_SYNC_RST_RESET_SHIFT) +#define QCA_RTC_SYNC_RST_RESET_MASK BIT(QCA_RTC_SYNC_RST_RESET_SHIFT) /* RTC_SYNC_STATUS register (RTC sync/sleep status) */ #define QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT 0 -#define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK (1 << QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT) +#define QCA_RTC_SYNC_STATUS_SHUTDOWN_MASK BIT(QCA_RTC_SYNC_STATUS_SHUTDOWN_SHIFT) #define QCA_RTC_SYNC_STATUS_ON_SHIFT 1 -#define QCA_RTC_SYNC_STATUS_ON_MASK (1 << QCA_RTC_SYNC_STATUS_ON_SHIFT) +#define QCA_RTC_SYNC_STATUS_ON_MASK BIT(QCA_RTC_SYNC_STATUS_ON_SHIFT) #define QCA_RTC_SYNC_STATUS_SLEEP_SHIFT 2 -#define QCA_RTC_SYNC_STATUS_SLEEP_MASK (1 << QCA_RTC_SYNC_STATUS_SLEEP_SHIFT) +#define QCA_RTC_SYNC_STATUS_SLEEP_MASK BIT(QCA_RTC_SYNC_STATUS_SLEEP_SHIFT) #define QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT 3 -#define QCA_RTC_SYNC_STATUS_WAKEUP_MASK (1 << QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT) +#define QCA_RTC_SYNC_STATUS_WAKEUP_MASK BIT(QCA_RTC_SYNC_STATUS_WAKEUP_SHIFT) #define QCA_RTC_SYNC_STATUS_WRESET_SHIFT 4 -#define QCA_RTC_SYNC_STATUS_WRESET_MASK (1 << QCA_RTC_SYNC_STATUS_WRESET_SHIFT) +#define QCA_RTC_SYNC_STATUS_WRESET_MASK BIT(QCA_RTC_SYNC_STATUS_WRESET_SHIFT) #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT 5 -#define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK (1 << QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT) +#define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK BIT(QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT) /* RTC_SYNC_FORCE_WAKE register (RTC force wake) */ #define QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT 0 -#define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK (1 << QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT) +#define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK BIT(QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT) #define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT 1 -#define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK (1 << QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT) +#define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK BIT(QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT) /* * SPI serial flash registers @@ -1528,45 +1528,45 @@ /* SPI_FUNC_SELECT register (SPI function select) */ #define QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT 0 -#define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK (1 << QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT) +#define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK BIT(QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT) /* SPI_CONTROL register (SPI control) */ #define QCA_SPI_CTRL_CLK_DIV_SHIFT 0 #define QCA_SPI_CTRL_CLK_DIV_MASK BITS(QCA_SPI_CTRL_CLK_DIV_SHIFT, 6) #define QCA_SPI_CTRL_REMAP_DIS_SHIFT 6 -#define QCA_SPI_CTRL_REMAP_DIS_MASK (1 << QCA_SPI_CTRL_REMAP_DIS_SHIFT) +#define QCA_SPI_CTRL_REMAP_DIS_MASK BIT(QCA_SPI_CTRL_REMAP_DIS_SHIFT) #define QCA_SPI_CTRL_SPI_RELOCATE_SHIFT 7 -#define QCA_SPI_CTRL_SPI_RELOCATE_MASK (1 << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) +#define QCA_SPI_CTRL_SPI_RELOCATE_MASK BIT(QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) #define QCA_SPI_CTRL_TSHSL_CNT_SHIFT 8 #define QCA_SPI_CTRL_TSHSL_CNT_MASK BITS(QCA_SPI_CTRL_TSHSL_CNT_SHIFT, 6) /* SPI_IO_CONTROL register (SPI I/O control) */ #define QCA_SPI_IO_CTRL_IO_DO_SHIFT 0 -#define QCA_SPI_IO_CTRL_IO_DO_MASK (1 << QCA_SPI_IO_CTRL_IO_DO_SHIFT) +#define QCA_SPI_IO_CTRL_IO_DO_MASK BIT(QCA_SPI_IO_CTRL_IO_DO_SHIFT) #define QCA_SPI_IO_CTRL_IO_CLK_SHIFT 8 -#define QCA_SPI_IO_CTRL_IO_CLK_MASK (1 << QCA_SPI_IO_CTRL_IO_CLK_SHIFT) +#define QCA_SPI_IO_CTRL_IO_CLK_MASK BIT(QCA_SPI_IO_CTRL_IO_CLK_SHIFT) #define QCA_SPI_IO_CTRL_IO_CS0_SHIFT 16 -#define QCA_SPI_IO_CTRL_IO_CS0_MASK (1 << QCA_SPI_IO_CTRL_IO_CS0_SHIFT) +#define QCA_SPI_IO_CTRL_IO_CS0_MASK BIT(QCA_SPI_IO_CTRL_IO_CS0_SHIFT) #define QCA_SPI_IO_CTRL_IO_CS1_SHIFT 17 -#define QCA_SPI_IO_CTRL_IO_CS1_MASK (1 << QCA_SPI_IO_CTRL_IO_CS1_SHIFT) +#define QCA_SPI_IO_CTRL_IO_CS1_MASK BIT(QCA_SPI_IO_CTRL_IO_CS1_SHIFT) #define QCA_SPI_IO_CTRL_IO_CS2_SHIFT 18 -#define QCA_SPI_IO_CTRL_IO_CS2_MASK (1 << QCA_SPI_IO_CTRL_IO_CS2_SHIFT) +#define QCA_SPI_IO_CTRL_IO_CS2_MASK BIT(QCA_SPI_IO_CTRL_IO_CS2_SHIFT) /* SPI_SHIFT_CNT_ADDR register (SPI content to shift out or in) */ #define QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT 0 #define QCA_SPI_SHIFT_CNT_BITS_CNT_MASK BITS(QCA_SPI_SHIFT_CNT_BITS_CNT_SHIFT, 7) #define QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT 26 -#define QCA_SPI_SHIFT_CNT_TERMINATE_MASK (1 << QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT) +#define QCA_SPI_SHIFT_CNT_TERMINATE_MASK BIT(QCA_SPI_SHIFT_CNT_TERMINATE_SHIFT) #define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT 27 -#define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_MASK (1 << QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT) +#define QCA_SPI_SHIFT_CNT_CLKOUT_INIT_MASK BIT(QCA_SPI_SHIFT_CNT_CLKOUT_INIT_SHIFT) #define QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT 28 -#define QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT) +#define QCA_SPI_SHIFT_CNT_CHNL_CS0_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS0_SHIFT) #define QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT 29 -#define QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT) +#define QCA_SPI_SHIFT_CNT_CHNL_CS1_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS1_SHIFT) #define QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT 30 -#define QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK (1 << QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT) +#define QCA_SPI_SHIFT_CNT_CHNL_CS2_MASK BIT(QCA_SPI_SHIFT_CNT_CHNL_CS2_SHIFT) #define QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT 31 -#define QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK (1 << QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT) +#define QCA_SPI_SHIFT_CNT_SHIFT_EN_MASK BIT(QCA_SPI_SHIFT_CNT_SHIFT_EN_SHIFT) /* * Other useful defines