From: Piotr Dymacz Date: Sun, 21 Feb 2016 09:40:44 +0000 (+0100) Subject: Add new setclk/clearclk custom commands for QC/A X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=d43e268fa553e43b897156072f3b920632ae698b;p=oweals%2Fu-boot_mod.git Add new setclk/clearclk custom commands for QC/A New code is universal, supports not only AR933x, but also new QCA95xx and AR934x WiSoCs. --- diff --git a/u-boot/common/cmd_qcaclk.c b/u-boot/common/cmd_qcaclk.c new file mode 100755 index 0000000..df2ea7b --- /dev/null +++ b/u-boot/common/cmd_qcaclk.c @@ -0,0 +1,314 @@ +/* + * Commands related with PLL/clocks settings + * for Qualcomm/Atheros WiSoCs + * + * Copyright (C) 2016 Piotr Dymacz + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + +static void print_reg_values(const clk_cfg_flash *cfg) +{ + puts("Target values:\n"); + +#if (SOC_TYPE & QCA_AR933X_SOC) + printf(" SPI_CTRL: 0x%08lX\n", cfg->spi_ctrl); + printf(" CPU_PLL_CFG: 0x%08lX\n", cfg->regs.cpu_pll_cfg); + printf("CPU_CLOCK_CONTROL: 0x%08lX\n", cfg->regs.cpu_clk_ctrl); + puts("\n"); + printf("NFRAC_MIN in PLL_DITHER_FRAC: %d\n", cfg->regs.cpu_pll_dit); +#else + printf(" SPI_CTRL: 0x%08lX\n", cfg->spi_ctrl); + printf(" CPU_PLL_CFG: 0x%08lX\n", cfg->regs.cpu_pll_cfg); + printf(" DDR_PLL_CFG: 0x%08lX\n", cfg->regs.ddr_pll_cfg); + printf("CPU_DDR_CLK_CTRL: 0x%08lX\n", cfg->regs.cpu_ddr_clk_ctrl); + puts("\n"); + printf("NFRAC_MIN in CPU_PLL_DITHER: %d\n", cfg->regs.cpu_pll_dit); + printf("NFRAC_MIN in DDR_PLL_DITHER: %d\n", cfg->regs.ddr_pll_dit); +#endif /* SOC_TYPE & QCA_AR933X_SOC */ + + puts("\n"); +} + +static u32 compare_pll_regs(const pll_regs *from_flash, + const pll_regs *to_compare) +{ +#if (SOC_TYPE & QCA_AR933X_SOC) + if (from_flash->cpu_pll_cfg == to_compare->cpu_pll_cfg && + from_flash->cpu_pll_dit == to_compare->cpu_pll_dit && + from_flash->cpu_clk_ctrl == to_compare->cpu_clk_ctrl) + return 1; +#else + if (from_flash->cpu_pll_cfg == to_compare->cpu_pll_cfg && + from_flash->ddr_pll_cfg == to_compare->ddr_pll_cfg && + from_flash->cpu_pll_dit == to_compare->cpu_pll_dit && + from_flash->ddr_pll_dit == to_compare->ddr_pll_dit && + from_flash->cpu_ddr_clk_ctrl == to_compare->cpu_ddr_clk_ctrl) + return 1; +#endif /* SOC_TYPE & QCA_AR933X_SOC */ + + return 0; +} + +/* Set and store PLL configuration in FLASH */ +int do_set_clk(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u32 ahb_clk, cpu_clk, ddr_clk, ref_clk, reg, spi_clk; + clk_cfg_flash from_flash, to_flash; + const pll_regs *pll_registers; + char buf[128]; + int i; + u8 *c; + + /* Read current clocks and make MHz from Hz */ + qca_sys_clocks(&cpu_clk, &ddr_clk, &ahb_clk, &spi_clk, &ref_clk); + + cpu_clk /= 1000000; + ddr_clk /= 1000000; + ahb_clk /= 1000000; + spi_clk /= 1000000; + ref_clk /= 1000000; + + /* Print all available profiles and current settings */ + if (argc == 1) { + printf("Current configuration:\n"); + printf("- CPU: %3d MHz\n", cpu_clk); + printf("- RAM: %3d MHz\n", ddr_clk); + printf("- AHB: %3d MHz\n", ahb_clk); + printf("- SPI: %3d MHz\n", spi_clk); + printf("- REF: %3d MHz\n", ref_clk); + puts("\n"); + + /* If we have PLL_MAGIC in FLASH, copy configuration from FLASH */ + reg = qca_soc_reg_read(CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET); + + /* PLL configuration starts _after_ PLL_MAGIC value */ + if (reg == QCA_PLL_IN_FLASH_MAGIC) { + c = (u8 *)(CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + 4); + memcpy(&from_flash, (void *)c, sizeof(clk_cfg_flash)); + } + + puts("Clocks in MHz, run 'setclk #' to select\n"); + puts("one configuration from the below table:\n\n"); + puts(" # | CPU | RAM | AHB | SPI | [ ]\n" + " ----------------------------------\n"); + + for (i = 0; i < clk_profiles_cnt; i++) { + printf("%5d |%4d |%4d |%4d |%4d | ", + i + 1, + clk_profiles[i].cpu_clk, + clk_profiles[i].ddr_clk, + clk_profiles[i].ahb_clk, + clk_profiles[i].spi_clk); + + if (reg == QCA_PLL_IN_FLASH_MAGIC) { + if (ref_clk == 25) { + pll_registers = &(clk_profiles[i].xtal_25mhz); + } else { + pll_registers = &(clk_profiles[i].xtal_40mhz); + } + + if (from_flash.spi_ctrl == clk_profiles[i].spi_ctrl && + compare_pll_regs(&(from_flash.regs), pll_registers)) { + puts("[*]\n"); + } else { + puts("[ ]\n"); + } + } else { + puts("[ ]\n"); + } + } + + puts("\n[*] profile currently stored in FLASH\n\n"); + + /* Show some additional information */ + puts("** Notice:\n"); + printf(" configuration is stored in FLASH at: 0x%08lX\n", + CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET); + + printf(" magic value is: 0x%08lX, block size is: %2d B\n", + QCA_PLL_IN_FLASH_MAGIC, sizeof(clk_cfg_flash)); + + puts("\n"); + + puts("** Notice:\n"); + puts(" you should always make a backup of your devices\n"); + puts(" entire FLASH content, before making any changes\n"); + +#ifndef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + puts("\n"); + puts("** Warning:"); + puts(" your device does not support O/C revovery mode!\n"); +#endif + + puts("\n"); + } else { + /* Configuration selected by user */ + i = simple_strtoul(argv[1], NULL, 10); + + if (i > clk_profiles_cnt || i < 1) { + printf("## Error: selected profile should be in range 1..%d!\n", + clk_profiles_cnt); + return 1; + } + + /* Array is zero-based indexed */ + printf("Selected profile %d:\n", i); + i--; + + /* Copy target values */ + to_flash.spi_ctrl = clk_profiles[i].spi_ctrl; + + if (ref_clk == 25) { + to_flash.regs = clk_profiles[i].xtal_25mhz; + } else { + to_flash.regs = clk_profiles[i].xtal_40mhz; + } + + printf("- CPU: %3d MHz\n", clk_profiles[i].cpu_clk); + printf("- RAM: %3d MHz\n", clk_profiles[i].ddr_clk); + printf("- AHB: %3d MHz\n", clk_profiles[i].ahb_clk); + printf("- SPI: %3d MHz\n", clk_profiles[i].spi_clk); + puts("\n"); + + print_reg_values(&to_flash); + + /* First, backup in RAM entire block where we store PLL config */ + sprintf(buf, "cp.b 0x%lX 0x%lX 0x%lX", + CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET, + CONFIG_LOADADDR, + CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE); + + if (run_command(buf, 0) < 0) { + puts("## Error: could not make data backup in RAM!\n"); + return 1; + } + + /* Overwrite PLL configuration block in RAM */ + c = (u8 *)(CONFIG_LOADADDR + + (CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + - CFG_FLASH_BASE + - CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)); + + reg = QCA_PLL_IN_FLASH_MAGIC; + memcpy((void *)c, ®, sizeof(reg)); + + c += 4; + + if (ref_clk == 25) { + memcpy((void *)c, &to_flash, sizeof(clk_cfg_flash)); + } else { + memcpy((void *)c, &to_flash, sizeof(clk_cfg_flash)); + } + + /* Erase FLASH and copy modified data back */ + sprintf(buf, + "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", + CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET, + CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE, + CONFIG_LOADADDR, + CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET, + CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE); + + if (run_command(buf, 0) < 0) { + puts("## Error: could not erase FLASH and copy data back from RAM!\n"); + return 1; + } + + puts("** Notice:\n"); + puts(" selected clocks configuration saved in FLASH,\n" + " you can restart the device with 'res' command\n"); + +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + puts("\n"); + puts(" If the device does not start, use recovery mode\n"); + #ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW + printf(" with button connected to GPIO%d (active in low)\n", + CONFIG_QCA_GPIO_OC_RECOVERY_BTN); + #else + printf(" with button connected to GPIO%d (active in high)\n", + CONFIG_QCA_GPIO_OC_RECOVERY_BTN); + #endif +#else + puts("\n"); + puts("** Warning:"); + puts(" your device does not support O/C revovery mode!\n"); +#endif /* CONFIG_QCA_GPIO_OC_RECOVERY_BTN */ + + puts("\n"); + } + + return 0; +} + +/* Remove clock configuration from FLASH */ +int do_clear_clk(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char buf[128]; + u32 reg; + u8 *c; + + /* Do we have PLL_MAGIC in FLASH? */ + reg = qca_soc_reg_read(CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET); + + if (reg == QCA_PLL_IN_FLASH_MAGIC) { + /* First, backup in RAM entire block where we store PLL config */ + sprintf(buf, "cp.b 0x%lX 0x%lX 0x%lX", + CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET, + CONFIG_LOADADDR, + CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE); + + if (run_command(buf, 0) < 0) { + puts("## Error: could not make data backup in RAM!\n\n"); + return 1; + } + + /* Clear magic value and whole configuration */ + c = (u8 *)(CONFIG_LOADADDR + + (CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + - CFG_FLASH_BASE + - CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)); + + memset((void *)c, 0xFF, sizeof(clk_cfg_flash) + 4); + + /* Erase FLASH and copy modified data back */ + sprintf(buf, + "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", + CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET, + CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE, + CONFIG_LOADADDR, + CFG_FLASH_BASE + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET, + CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE); + + if (run_command(buf, 0) < 0) { + puts("## Error: could not erase FLASH and copy data back from RAM!\n\n"); + return 1; + } + } else { + puts("** Warning: clock configuration is not stored in FLASH!\n\n"); + return 1; + } + + return 0; +} + +U_BOOT_CMD(setclk, 2, 0, do_set_clk, + "select clocks configuration from predefined list\n", + "index\n" + "\t- save 'index' configuration in FLASH\n" + "setclk\n" + "\t- prints available clocks configurations and current settings\n"); + +U_BOOT_CMD(clearclk, 1, 0, do_clear_clk, + "remove PLL and clocks configuration from FLASH\n", NULL); + +#endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */ diff --git a/u-boot/include/cmd_qcaclk.h b/u-boot/include/cmd_qcaclk.h new file mode 100755 index 0000000..da9c92a --- /dev/null +++ b/u-boot/include/cmd_qcaclk.h @@ -0,0 +1,2212 @@ +/* + * Commands related with PLL/clocks settings + * for Qualcomm/Atheros WiSoCs + * + * Copyright (C) 2016 Piotr Dymacz + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _CMD_QCACLK_H_ +#define _CMD_QCACLK_H_ + +#include +#if (SOC_TYPE & QCA_AR933X_SOC) + #include +#else + #include +#endif + +#ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + + #ifndef CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + #error "Missing definition for CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET" + #endif + + #ifndef CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE + #error "Missing definition for CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE" + #endif + + #if (SOC_TYPE & QCA_AR933X_SOC) +typedef struct { + u32 cpu_pll_cfg; + u32 cpu_clk_ctrl; + u32 cpu_pll_dit; +} pll_regs; + #else +typedef struct { + u32 cpu_pll_cfg; + u32 ddr_pll_cfg; + u32 cpu_ddr_clk_ctrl; + u32 cpu_pll_dit; + u32 ddr_pll_dit; +} pll_regs; + #endif /* SOC_TYPE & QCA_AR933X_SOC */ + +typedef struct { + u32 spi_ctrl; + pll_regs regs; +} clk_cfg_flash; + +/* + * Contains: + * 1. CPU, RAM, AHB and SPI clocks [MHz] + * 2. Target SPI_CONTROL register value + * 3. Target PLL related register values, + * for 25 and 40 MHz XTAL types + */ +typedef struct { + u16 cpu_clk; + u16 ddr_clk; + u16 ahb_clk; + u8 spi_clk; + + u32 spi_ctrl; + + pll_regs xtal_25mhz; + pll_regs xtal_40mhz; +} clk_profile; + +static const clk_profile clk_profiles[] = { + #if (SOC_TYPE & QCA_AR933X_SOC) + { + 100, 100, 50, 12, + _ar933x_spi_ctrl_addr_reg_val(4, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + { + 100, 100, 100, 16, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + { + 150, 150, 150, 18, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(7, 1, 1, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1), + _ar933x_cpu_pll_dither_frac_reg_val(512) + }, + }, + { + 160, 160, 80, 13, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(820) + }, { + _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + { + 200, 200, 100, 16, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + { + 200, 200, 200, 25, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + { + 300, 300, 150, 15, + _ar933x_spi_ctrl_addr_reg_val(10, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + { + 350, 350, 175, 17, + _ar933x_spi_ctrl_addr_reg_val(10, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(512) + }, + }, + { + 400, 400, 200, 25, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + { + 500, 500, 250, 25, + _ar933x_spi_ctrl_addr_reg_val(10, 1, 0), + { + _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, { + _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + #else + { + 25, 25, 12, 1, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 8, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 25, 25, 25, 3, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 50, 50, 25, 3, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 50, 50, 50, 6, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 75, 75, 25, 3, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 75, 75, 50, 6, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 75, 75, 75, 9, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 100, 100, 25, 3, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 100, 100, 50, 6, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 100, 100, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 50, 25, 3, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 50, 50, 6, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 62, 25, 3, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 5, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 10, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 62, 50, 6, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 2, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 62, 62, 7, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 100, 25, 3, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 100, 50, 6, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 100, 62, 7, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 125, 100, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 150, 150, 75, 9, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 150, 150, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 150, 150, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 160, 160, 80, 10, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 170, 170, 85, 10, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 5, 10, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(17, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 180, 180, 90, 11, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 200, 200, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + } + }, { + 200, 200, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + } + }, { + 200, 200, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + } + }, { + 300, 200, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + } + }, { + 300, 200, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + } + }, { + 300, 200, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + } + }, { + 300, 300, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + } + }, { + 300, 300, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 300, 300, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 350, 350, 175, 21, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(35, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 360, 360, 180, 22, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 380, 380, 190, 23, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(46, 3, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(46, 3, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 200, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 200, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 200, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 300, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 300, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 300, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 300, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 400, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 400, 400, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 200, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 200, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 200, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 300, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 300, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 300, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 300, 250, 25, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 300, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 400, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 400, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 400, 250, 25, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 500, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 500, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 500, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 500, 250, 25, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 500, 500, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 200, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 200, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 200, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 300, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 300, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 300, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 300, 275, 27, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 300, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 375, 250, 25, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 550, 400, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 560, 450, 225, 28, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(26), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 200, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 200, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 200, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 300, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 300, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 300, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 300, 250, 25, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 300, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 400, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 400, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 400, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 400, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 450, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 450, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 450, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 450, 225, 28, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 450, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 500, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 500, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 500, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 500, 250, 25, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 500, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 550, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 550, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 550, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 550, 275, 27, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 550, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 600, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 600, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 600, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 600, 250, 25, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 600, 600, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 200, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 200, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 200, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 300, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 300, 150, 18, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 300, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 300, 300, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 400, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 400, 155, 19, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 400, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 400, 310, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 500, 100, 12, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 500, 155, 19, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 500, 166, 20, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 500, 206, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 500, 250, 25, + _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 620, 500, 310, 25, + _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(52), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 650, 400, 200, 25, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(16), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 650, 420, 210, 26, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(820) + }, { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(42, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(16), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, { + 650, 450, 225, 28, + _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + { + _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_ddr_pll_dither_reg_val(0) + }, { + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(16), + _qca95xx_ddr_pll_dither_reg_val(0) + }, + }, + #endif /* SOC_TYPE & QCA_AR933X_SOC */ +}; + +/* Number of all profiles */ +static u32 clk_profiles_cnt = sizeof(clk_profiles) / sizeof(clk_profile); + +#endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */ + +#endif /* _CMD_QCACLK_H_ */