From: Ofer Heifetz <oferh@marvell.com>
Date: Wed, 29 Aug 2018 08:56:04 +0000 (+0300)
Subject: mtd: nand: pxa3xx-nand: fix random command timeouts
X-Git-Tag: v2018.11-rc1~114^2~17
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=cd11b2b457bb8aa5e0e72c4d90df1c7995c738b4;p=oweals%2Fu-boot.git

mtd: nand: pxa3xx-nand: fix random command timeouts

When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase

This patch is taken from Linux:
'commit 21fc0ef9652f'
("mtd: nand: pxa3xx-nand: fix random command timeouts")

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 7b1dcb24ee..98bb4c643e 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -623,8 +623,14 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
 		is_ready = 1;
 	}
 
+	/*
+	 * Clear all status bit before issuing the next command, which
+	 * can and will alter the status bits and will deserve a new
+	 * interrupt on its own. This lets the controller exit the IRQ
+	 */
+	nand_writel(info, NDSR, status);
+
 	if (status & NDSR_WRCMDREQ) {
-		nand_writel(info, NDSR, NDSR_WRCMDREQ);
 		status &= ~NDSR_WRCMDREQ;
 		info->state = STATE_CMD_HANDLE;
 
@@ -645,8 +651,6 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
 			nand_writel(info, NDCB0, info->ndcb3);
 	}
 
-	/* clear NDSR to let the controller exit the IRQ */
-	nand_writel(info, NDSR, status);
 	if (is_completed)
 		info->cmd_complete = 1;
 	if (is_ready)