From: Andy Polyakov <appro@openssl.org>
Date: Sun, 5 Mar 2017 19:38:36 +0000 (+0100)
Subject: crypto/x86_64cpuid.pl: move extended feature detection upwards.
X-Git-Tag: OpenSSL_1_1_0f~174
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=c6e4fdbf8b44010ba12b72d519e437bbd2da71e6;p=oweals%2Fopenssl.git

crypto/x86_64cpuid.pl: move extended feature detection upwards.

Exteneded feature flags were not pulled on AMD processors, as result a
number of extensions were effectively masked on Ryzen. It should have
been reported for Excavator since it implements AVX2 extension, but
apparently nobody noticed or cared...

Reviewed-by: Rich Salz <rsalz@openssl.org>
(cherry picked from commit f8418d87e191e46b81e1b9548326ab2876fa0907)
---

diff --git a/crypto/x86_64cpuid.pl b/crypto/x86_64cpuid.pl
index 6cb152148b..21d48ee6f9 100644
--- a/crypto/x86_64cpuid.pl
+++ b/crypto/x86_64cpuid.pl
@@ -70,6 +70,16 @@ OPENSSL_ia32_cpuid:
 	cpuid
 	mov	%eax,%r11d		# max value for standard query level
 
+	cmp	\$7,%eax
+	jb	.Lno_extended_info
+
+	mov	\$7,%eax
+	xor	%ecx,%ecx
+	cpuid
+	mov	%ebx,8(%rdi)
+
+.Lno_extended_info:
+
 	xor	%eax,%eax
 	cmp	\$0x756e6547,%ebx	# "Genu"
 	setne	%al
@@ -134,14 +144,6 @@ OPENSSL_ia32_cpuid:
 	shr	\$14,%r10d
 	and	\$0xfff,%r10d		# number of cores -1 per L1D
 
-	cmp	\$7,%r11d
-	jb	.Lnocacheinfo
-
-	mov	\$7,%eax
-	xor	%ecx,%ecx
-	cpuid
-	mov	%ebx,8(%rdi)
-
 .Lnocacheinfo:
 	mov	\$1,%eax
 	cpuid