From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Date: Fri, 1 Mar 2019 19:12:36 +0000 (+0100)
Subject: arm: socfpga: implement proper peripheral reset
X-Git-Tag: v2019.07-rc1~14^2~8
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=c5de2b7eae68ac27da78c32cdf0845126a0d1a77;p=oweals%2Fu-boot.git

arm: socfpga: implement proper peripheral reset

This commit removes ad-hoc reset handling for peripheral resets from SPL
for socfpga gen5.

This is done because as U-Boot drivers support reset handling by now.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---

diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 6e11ba6cb2..9865f5b5b1 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -201,16 +201,6 @@ int arch_early_init_r(void)
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add(&altera_fpga[0]);
 
-#ifdef CONFIG_DESIGNWARE_SPI
-	/* Get Designware SPI controller out of reset */
-	socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
-	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
-#endif
-
-#ifdef CONFIG_NAND_DENALI
-	socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
-#endif
-
 	return 0;
 }
 
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index c5399bb697..9dd0afb4bc 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -39,16 +39,12 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_RAM;
 	case 0x2:	/* NAND Flash (1.8V) */
 	case 0x3:	/* NAND Flash (3.0V) */
-		socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 		return BOOT_DEVICE_NAND;
 	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
 	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
-		socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
-		socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
 		return BOOT_DEVICE_MMC1;
 	case 0x6:	/* QSPI Flash (1.8V) */
 	case 0x7:	/* QSPI Flash (3.0V) */
-		socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
 		return BOOT_DEVICE_SPI;
 	default:
 		printf("Invalid boot device (bsel=%08x)!\n", bsel);
@@ -157,9 +153,7 @@ void board_init_f(ulong dummy)
 		socfpga_bridges_reset(1);
 	}
 
-	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-
 	timer_init();
 
 	debug("Reconfigure Clock Manager\n");
@@ -181,8 +175,7 @@ void board_init_f(ulong dummy)
 	sysmgr_pinmux_init();
 	sysmgr_config_warmrstcfgio(0);
 
-	/* De-assert reset for peripherals and bridges based on handoff */
-	reset_deassert_peripherals_handoff();
+	/* De-assert reset for bridges based on handoff */
 	socfpga_bridges_reset(0);
 
 	debug("Unfreezing/Thaw all I/O banks\n");