From: Rafał Miłecki Date: Sat, 28 Jan 2017 15:50:06 +0000 (+0100) Subject: kernel: backport BCM54210E PHY support X-Git-Tag: v18.06.0-rc1~3900 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=c437df09c98799236c34bb32c2235ec8feb15045;p=oweals%2Fopenwrt.git kernel: backport BCM54210E PHY support Signed-off-by: Rafał Miłecki --- diff --git a/target/linux/generic/patches-4.4/078-0004-net-phy-pick-Broadcom-drivers-updates-from-net-next-.patch b/target/linux/generic/patches-4.4/078-0004-net-phy-pick-Broadcom-drivers-updates-from-net-next-.patch index d0842dfa97..dad44930d9 100644 --- a/target/linux/generic/patches-4.4/078-0004-net-phy-pick-Broadcom-drivers-updates-from-net-next-.patch +++ b/target/linux/generic/patches-4.4/078-0004-net-phy-pick-Broadcom-drivers-updates-from-net-next-.patch @@ -82,7 +82,43 @@ Signed-off-by: Rafał Miłecki { PHY_ID_BCM7346, 0xfffffff0, }, --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c -@@ -395,12 +395,10 @@ static int bcm54612e_config_aneg(struct +@@ -30,6 +30,22 @@ MODULE_DESCRIPTION("Broadcom PHY driver" + MODULE_AUTHOR("Maciej W. Rozycki"); + MODULE_LICENSE("GPL"); + ++static int bcm54210e_config_init(struct phy_device *phydev) ++{ ++ int val; ++ ++ val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); ++ val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; ++ val |= MII_BCM54XX_AUXCTL_MISC_WREN; ++ bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val); ++ ++ val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); ++ val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; ++ bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); ++ ++ return 0; ++} ++ + static int bcm54810_config(struct phy_device *phydev) + { + int rc, val; +@@ -230,7 +246,11 @@ static int bcm54xx_config_init(struct ph + (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) + bcm54xx_adjust_rxrefclk(phydev); + +- if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) { ++ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) { ++ err = bcm54210e_config_init(phydev); ++ if (err) ++ return err; ++ } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) { + err = bcm54810_config(phydev); + if (err) + return err; +@@ -395,12 +415,10 @@ static int bcm54612e_config_aneg(struct (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) { u16 reg; @@ -98,9 +134,43 @@ Signed-off-by: Rafał Miłecki /* Clear shadow selector field */ reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK; bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, +@@ -548,6 +566,17 @@ static struct phy_driver broadcom_driver + .config_intr = bcm_phy_config_intr, + .driver = { .owner = THIS_MODULE }, + }, { ++ .phy_id = PHY_ID_BCM54210E, ++ .phy_id_mask = 0xfffffff0, ++ .name = "Broadcom BCM54210E", ++ .features = PHY_GBIT_FEATURES, ++ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, ++ .config_init = bcm54xx_config_init, ++ .config_aneg = genphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = bcm_phy_ack_intr, ++ .config_intr = bcm_phy_config_intr, ++}, { + .phy_id = PHY_ID_BCM5461, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM5461", +@@ -708,6 +737,7 @@ module_phy_driver(broadcom_drivers); + static struct mdio_device_id __maybe_unused broadcom_tbl[] = { + { PHY_ID_BCM5411, 0xfffffff0 }, + { PHY_ID_BCM5421, 0xfffffff0 }, ++ { PHY_ID_BCM54210E, 0xfffffff0 }, + { PHY_ID_BCM5461, 0xfffffff0 }, + { PHY_ID_BCM54612E, 0xfffffff0 }, + { PHY_ID_BCM54616S, 0xfffffff0 }, --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h -@@ -24,6 +24,7 @@ +@@ -17,6 +17,7 @@ + #define PHY_ID_BCM5482 0x0143bcb0 + #define PHY_ID_BCM5411 0x00206070 + #define PHY_ID_BCM5421 0x002060e0 ++#define PHY_ID_BCM54210E 0x600d84a0 + #define PHY_ID_BCM5464 0x002060b0 + #define PHY_ID_BCM5461 0x002060c0 + #define PHY_ID_BCM54612E 0x03625e60 +@@ -24,6 +25,7 @@ #define PHY_ID_BCM57780 0x03625d90 #define PHY_ID_BCM7250 0xae025280 @@ -108,7 +178,7 @@ Signed-off-by: Rafał Miłecki #define PHY_ID_BCM7364 0xae025260 #define PHY_ID_BCM7366 0x600d8490 #define PHY_ID_BCM7346 0x600d8650 -@@ -103,18 +104,17 @@ +@@ -103,18 +105,17 @@ /* * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) */