From: Nitin Garg Date: Wed, 2 Apr 2014 13:55:02 +0000 (-0500) Subject: ARM: Add workaround for Cortex-A9 errata 761320 X-Git-Tag: v2014.04~18^2~1 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=b7588e3bdcdb2ee073a6a66a4c882b23feaaa0e6;p=oweals%2Fu-boot.git ARM: Add workaround for Cortex-A9 errata 761320 Full cache line writes to the same memory region from at least two processors might deadlock the processor. Exists on r1, r2, r3 revisions. Signed-off-by: Nitin Garg Acked-by: Fabio Estevam --- diff --git a/README b/README index 00127a75ef..da85c8995c 100644 --- a/README +++ b/README @@ -567,6 +567,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f3830c8471..27be451a89 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15)