From: Bo Shen <voice.shen@atmel.com>
Date: Mon, 15 Dec 2014 05:24:36 +0000 (+0800)
Subject: ARM: atmel: sama5d4: can access DDR in interleave mode
X-Git-Tag: v2015.04-rc2~33^2~15
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=b54dd1b3adad4613bb8aa471b12f88bede699775;p=oweals%2Fu-boot.git

ARM: atmel: sama5d4: can access DDR in interleave mode

The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
---

diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c
index 44798e612c..beec13db8c 100644
--- a/arch/arm/cpu/at91-common/mpddrc.c
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
 
 static int ddr2_decodtype_is_seq(u32 cr)
 {
-#if defined(CONFIG_SAMA5D3)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
 	if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
 		return 0;
 #endif