From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Date: Fri, 18 Oct 2019 09:01:56 +0000 (+0000)
Subject: armv8: ls1028a: add erratum A-050382 workaround
X-Git-Tag: v2020.01-rc2~6^2~8
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=b4a59115e2cad84a47352948570c02cce34591b1;p=oweals%2Fu-boot.git

armv8: ls1028a: add erratum A-050382 workaround

Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 24c606a232..046dcf539e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -45,6 +45,7 @@ config ARCH_LS1028A
 	select SYS_FSL_ERRATUM_A008514 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+	select SYS_FSL_ERRATUM_A050382
 	imply PANIC_HANG
 
 config ARCH_LS1043A
@@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660
 config SYS_FSL_ERRATUM_A009929
 	bool
 
+config SYS_FSL_ERRATUM_A050382
+	bool
 
 config SYS_FSL_HAS_RGMII
 	bool
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
index 0b36416ad3..94ea99a349 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -105,7 +105,22 @@
 #define FSL_SEC_JR4_STREAM_ID		68
 
 #define FSL_SDMMC2_STREAM_ID		69
+
+/*
+ * Erratum A-050382 workaround
+ *
+ * Description:
+ *   The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not
+ *   correctly forwarded to the SMMU.
+ * Workaround:
+ *   Program eDMA ICID in the eDMA_AMQR register in DCFG to 40.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A050382
+#define FSL_EDMA_STREAM_ID		40
+#else
 #define FSL_EDMA_STREAM_ID		70
+#endif
+
 #define FSL_GPU_STREAM_ID		71
 #define FSL_DISPLAY_STREAM_ID		72
 #define FSL_SATA3_STREAM_ID		73