From: MengDongyang Date: Wed, 24 Aug 2016 04:02:17 +0000 (+0800) Subject: usb: xhci-rockchip: add rockchip dwc3 controller driver X-Git-Tag: v2016.11-rc1~109^2~11 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=b44566c4ce5ca95264860f78a6ba1d26a5edb5ea;p=oweals%2Fu-boot.git usb: xhci-rockchip: add rockchip dwc3 controller driver This patch add support for rockchip dwc3 controller, which corresponding to the two type-C port on rk3399 evb. Only support usb2.0 currently for we have not enable the usb3.0 phy driver and PD(fusb302) driver. Signed-off-by: MengDongyang Signed-off-by: Kever Yang Reviewed-by: Marek Vasut Reviewed-by: Simon Glass --- diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 55190bb667..de253284fb 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c new file mode 100644 index 0000000000..561bf86702 --- /dev/null +++ b/drivers/usb/host/xhci-rockchip.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2016 Rockchip, Inc. + * Authors: Daniel Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xhci.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct rockchip_xhci_platdata { + fdt_addr_t hcd_base; + fdt_addr_t phy_base; + struct gpio_desc vbus_gpio; +}; + +/* + * Contains pointers to register base addresses + * for the usb controller. + */ +struct rockchip_xhci { + struct usb_platdata usb_plat; + struct xhci_ctrl ctrl; + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +static int xhci_usb_ofdata_to_platdata(struct udevice *dev) +{ + struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); + struct udevice *child; + int ret = 0; + + /* + * Get the base address for XHCI controller from the device node + */ + plat->hcd_base = dev_get_addr(dev); + if (plat->hcd_base == FDT_ADDR_T_NONE) { + debug("Can't get the XHCI register base address\n"); + return -ENXIO; + } + + /* Get the base address for usbphy from the device node */ + for (device_find_first_child(dev, &child); child; + device_find_next_child(&child)) { + if (!of_device_is_compatible(child, "rockchip,rk3399-usb3-phy")) + continue; + plat->phy_base = dev_get_addr(child); + break; + } + + if (plat->phy_base == FDT_ADDR_T_NONE) { + debug("Can't get the usbphy register address\n"); + return -ENXIO; + } + + /* Vbus gpio */ + ret = gpio_request_by_name(dev, "rockchip,vbus-gpio", 0, + &plat->vbus_gpio, GPIOD_IS_OUT); + if (ret) + debug("rockchip,vbus-gpio node missing!"); + + return 0; +} + +/* + * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core + * @dwc: Pointer to our controller context structure + * @dev: Pointer to ulcass device + */ +static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, + struct udevice *dev) +{ + u32 reg; + const void *blob = gd->fdt_blob; + u32 utmi_bits; + + /* Set dwc3 usb2 phy config */ + reg = readl(&dwc3_reg->g_usb2phycfg[0]); + + if (fdtdec_get_bool(blob, dev->of_offset, + "snps,dis-enblslpm-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + + utmi_bits = fdtdec_get_int(blob, dev->of_offset, + "snps,phyif-utmi-bits", -1); + if (utmi_bits == 16) { + reg |= DWC3_GUSB2PHYCFG_PHYIF; + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + } else if (utmi_bits == 8) { + reg &= ~DWC3_GUSB2PHYCFG_PHYIF; + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; + } + + if (fdtdec_get_bool(blob, dev->of_offset, + "snps,dis-u2-freeclk-exists-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + + if (fdtdec_get_bool(blob, dev->of_offset, + "snps,dis-u2-susphy-quirk")) + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; + + writel(reg, &dwc3_reg->g_usb2phycfg[0]); +} + +static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, + struct udevice *dev) +{ + int ret; + + ret = dwc3_core_init(rkxhci->dwc3_reg); + if (ret) { + debug("failed to initialize core\n"); + return ret; + } + + rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return 0; +} + +static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) +{ + return 0; +} + +static int xhci_usb_probe(struct udevice *dev) +{ + struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); + struct rockchip_xhci *ctx = dev_get_priv(dev); + struct xhci_hcor *hcor; + int ret; + + ctx->hcd = (struct xhci_hccr *)plat->hcd_base; + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + + HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); + + /* setup the Vbus gpio here */ + if (dm_gpio_is_valid(&plat->vbus_gpio)) + dm_gpio_set_value(&plat->vbus_gpio, 1); + + ret = rockchip_xhci_core_init(ctx, dev); + if (ret) { + debug("XHCI: failed to initialize controller\n"); + return ret; + } + + return xhci_register(dev, ctx->hcd, hcor); +} + +static int xhci_usb_remove(struct udevice *dev) +{ + struct rockchip_xhci *ctx = dev_get_priv(dev); + int ret; + + ret = xhci_deregister(dev); + if (ret) + return ret; + ret = rockchip_xhci_core_exit(ctx); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id xhci_usb_ids[] = { + { .compatible = "rockchip,rk3399-xhci" }, + { } +}; + +U_BOOT_DRIVER(usb_xhci) = { + .name = "xhci_rockchip", + .id = UCLASS_USB, + .of_match = xhci_usb_ids, + .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, + .probe = xhci_usb_probe, + .remove = xhci_usb_remove, + .ops = &xhci_usb_ops, + .bind = dm_scan_fdt_dev, + .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), + .priv_auto_alloc_size = sizeof(struct rockchip_xhci), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static const struct udevice_id usb_phy_ids[] = { + { .compatible = "rockchip,rk3399-usb3-phy" }, + { } +}; + +U_BOOT_DRIVER(usb_phy) = { + .name = "usb_phy_rockchip", + .of_match = usb_phy_ids, +}; diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index 6d1e36505d..a0274461cc 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -180,7 +180,21 @@ struct dwc3 { /* offset: 0xC100 */ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) +#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3) + +/* Global USB2 PHY Configuration Mask */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) + +/* Global USB2 PHY Configuration Offset */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10 + +#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)