From: Piotr Dymacz Date: Mon, 24 Apr 2017 19:11:52 +0000 (+0200) Subject: Restore workaround for AR9331 hang on soft reset X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=aba8e6f81d6b84592a487526bddc33d916940bba;p=oweals%2Fu-boot_mod.git Restore workaround for AR9331 hang on soft reset This workaround was already included in ff7a030 and then removed in d9ba54f. As it turned out, it's critical and required. Tests showed that on some devices with AR9331, CPU PLL doesn't lock after a soft reset with AHB clock divider lower than 4. In original code from Qualcomm Atheros SDK, AHB clock divider is set to 4 before CPU PLL is powered up. Then, when PLL update is done, divider is set to target value. Tests were made on multiple devices, with DDR1, DDR2 and different AR9331 chip revisions: -AL1A, -AL2A and -AL3A. Unfortunately, the problem exists in every configuration type, isn't related with chip revision and is reproductible. Without this workaround, some devices hangs at waiting for CPU PLL update process to finish and can be recovered from this state only with a hard reset. --- diff --git a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S index 442f957..2ddbf88 100644 --- a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S +++ b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S @@ -296,11 +296,14 @@ xtal_is_40mhz_recovery: /* * Load target value into CPU_CLOCK_CONTROL register, but for now keep bypass * enabled (by default, after reset, it should be bypassed, do it just in case) + * and AHB_POST_DIV equal to 4 */ cpu_clock_control: li t8, QCA_PLL_CPU_CLK_CTRL_REG move t9, reg_cpu_clk_ctrl or t9, t9, QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK + and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK + or t9, t9, (3 << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) sw t9, 0(t8) /* @@ -338,10 +341,10 @@ cpu_pll_wait: /* Disable bypassing all clocks, use target AHB_POST_DIV value */ pll_bypass_disable: - li t8, QCA_PLL_CPU_CLK_CTRL_REG - lw t9, 0(t8) - and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK - sw t9, 0(t8) + li t8, QCA_PLL_CPU_CLK_CTRL_REG + move t9, reg_cpu_clk_ctrl + and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK + sw t9, 0(t8) /* Setup SPI (clock and other settings) */ spi_setup: