From: Marian Balakowicz <m8@semihalf.com>
Date: Tue, 14 Mar 2006 15:01:25 +0000 (+0100)
Subject: Correct shift offsets in icache_status and dcache_status for MPC83xx.
X-Git-Tag: LABEL_2006_04_18_1106~7^2~2^2~9
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=a7c66ad2e52b49a7cf5efb9665dd0527db96ea29;p=oweals%2Fu-boot.git

Correct shift offsets in icache_status and dcache_status for MPC83xx.
---

diff --git a/CHANGELOG b/CHANGELOG
index 77f1a254d2..e40ba053e9 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Correct shift offsets in icache_status and dcache_status for MPC83xx.
+
 * Add support for DS1374 RTC chip.
 
 * Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 46c748f790..324f6c36fe 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -796,7 +796,7 @@ icache_disable:
 	.globl	icache_status
 icache_status:
 	mfspr	r3, HID0
-	rlwinm	r3, r3, HID0_ICE_SHIFT, 31, 31
+	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
 	blr
 
 	.globl	dcache_enable
@@ -828,7 +828,7 @@ dcache_disable:
 	.globl	dcache_status
 dcache_status:
 	mfspr	r3, HID0
-	rlwinm	r3, r3, HID0_DCE_SHIFT, 31, 31
+	rlwinm	r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
 	blr
 
 	.globl get_pvr