From: Nick Xie Date: Tue, 30 Jul 2019 03:51:16 +0000 (+0800) Subject: arm64: dts: rockchip: Add support for Khadas Edge-Captain X-Git-Tag: v2019.10-rc2~12^2~9 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=a5f1249bd303e49f35d1bc3b665aad62dd90b9c9;p=oweals%2Fu-boot.git arm64: dts: rockchip: Add support for Khadas Edge-Captain Add devicetree support for Khadas Edge-Captain. Khadas Captain is the carrier board for Khadas Edge. Specification - Rockchip RK3399 - Dual-Channel 2GB/4GB LPDDR4 - SD card slot - Onboard 16GB/32GB/128GB eMMC - RTL8211FD 1Gbps - AP6356S/AP6398S WiFI/BT - HDMI Out, DP, MIPI DSI/CSI, eDP - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - Full 4 Lane M.2 Socket - 16MB SPI Flash - IR - Programmable MCU Commit details of rk3399-khadas-edge-*.dts sync from Linux 5.3-rc2: "arm64: dts: rockchip: Add support for Khadas Edge/Edge-V/Captain boards" (sha1: c2aacceedc86af87428d998e23a1aca24fd8aa2e) Signed-off-by: Nick Xie Tested-by: Chris Webb Reviewed-by: Kever Yang --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e00860ee3b..77c47d0a4f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ rk3399-khadas-edge.dtb \ + rk3399-khadas-edge-captain.dtb \ rk3399-khadas-edge-v.dtb \ rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ diff --git a/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi b/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi new file mode 100644 index 0000000000..ca1bbffb50 --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Nick Xie + */ + +#include "rk3399-khadas-edge-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-khadas-edge-captain.dts b/arch/arm/dts/rk3399-khadas-edge-captain.dts new file mode 100644 index 0000000000..8302e51def --- /dev/null +++ b/arch/arm/dts/rk3399-khadas-edge-captain.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge-Captain"; + compatible = "khadas,edge-captain", "rockchip,rk3399"; +}; + +&gmac { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index c5b5018ae0..d9711ab227 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -12,6 +12,12 @@ S: Maintained F: configs/khadas-edge-rk3399_defconfig F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +KHADAS-EDGE-CAPTAIN +M: Nick Xie +S: Maintained +F: configs/khadas-edge-captain-rk3399_defconfig +F: arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi + KHADAS-EDGE-V M: Nick Xie S: Maintained diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig new file mode 100644 index 0000000000..11ec2dab13 --- /dev/null +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -0,0 +1,60 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_SYS_PROMPT="kedge# " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y