From: Lokesh Vutla Date: Mon, 4 Feb 2013 04:21:59 +0000 (+0000) Subject: ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register X-Git-Tag: v2013.04-rc2~24^2~28 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=9ca8bfea80f38e3b423e339499c861ddc24b830c;p=oweals%2Fu-boot.git ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index b1fd277d6d..1f95fba8cd 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -36,6 +36,7 @@ #include #include #include +#include #ifndef CONFIG_SPL_BUILD /* @@ -299,7 +300,7 @@ static void setup_dplls(void) * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - if (omap_revision() != OMAP5432_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, "core"); else diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 88253cf8ce..8864abc16e 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -66,6 +66,19 @@ inline u32 emif_num(u32 base) return 0; } +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +u32 emif_sdram_type() +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { @@ -1079,7 +1092,7 @@ static void do_sdram_init(u32 base) * OPP to another) */ if (!(in_sdram || warm_reset())) { - if (omap_revision() != OMAP5432_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) lpddr2_init(base, regs); else ddr3_init(base, regs); @@ -1264,7 +1277,7 @@ void dmm_init(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; - u32 omap_rev = omap_revision(); + u32 sdram_type = emif_sdram_type(); debug(">>sdram_init()\n"); @@ -1275,7 +1288,7 @@ void sdram_init(void) debug("in_sdram = %d\n", in_sdram); if (!(in_sdram || warm_reset())) { - if (omap_rev != OMAP5432_ES1_0) + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) bypass_dpll(&prcm->cm_clkmode_dpll_core); else writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); @@ -1298,7 +1311,7 @@ void sdram_init(void) } /* for the shadow registers to take effect */ - if (omap_rev != OMAP5432_ES1_0) + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) freq_update_core(); /* Do some testing after the init */ diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index eecfbade35..1f3369268d 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -36,6 +36,7 @@ #include #include #include +#include #ifndef CONFIG_SPL_BUILD /* @@ -279,7 +280,7 @@ void scale_vcores(void) do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); - if (omap_revision() == OMAP5432_ES1_0) { + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ writel(2, &prcm->prm_sldo_core_setup); writel(2, &prcm->prm_sldo_mpu_setup); diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d0c3ff7021..4def422df1 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -191,7 +191,7 @@ void do_io_settings(void) (sc_fast << 17) | (sc_fast << 14); writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); - if (omap_revision() <= OMAP5430_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) io_settings_lpddr2(); else io_settings_ddr3(); diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index ed251ec8ec..0824a80d06 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1027,6 +1027,11 @@ extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define MR8_IO_WIDTH_SHIFT 0x6 #define MR8_IO_WIDTH_MASK (0x3 << 0x6) +/* SDRAM TYPE */ +#define EMIF_SDRAM_TYPE_DDR2 0x2 +#define EMIF_SDRAM_TYPE_DDR3 0x3 +#define EMIF_SDRAM_TYPE_LPDDR2 0x4 + struct lpddr2_addressing { u8 num_banks; u8 t_REFI_us_x10; @@ -1156,4 +1161,5 @@ extern u32 *const emif_sizes; #endif void config_data_eye_leveling_samples(u32 emif_base); +u32 emif_sdram_type(void); #endif