From: Simon Glass Date: Thu, 2 May 2019 16:52:19 +0000 (-0600) Subject: x86: Update device tree for TPL X-Git-Tag: v2019.07-rc2~14^2~10 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=93c76075802dba9bed40d20cfe1e4351c7bed4e5;p=oweals%2Fu-boot.git x86: Update device tree for TPL Add TPL binaries to the device x86 binman desciption. When enabled, TPL will start first, doing the 16-bit init, then jump to SPL and finally U-Boot proper. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 1050236330..9cf733806a 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -22,7 +22,21 @@ filename = CONFIG_INTEL_ME_FILE; }; #endif -#ifdef CONFIG_SPL +#ifdef CONFIG_TPL + u-boot-tpl-with-ucode-ptr { + offset = ; + }; + u-boot-tpl-dtb { + }; + u-boot-spl { + offset = ; + }; + u-boot-spl-dtb { + }; + u-boot { + offset = ; + }; +#elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { offset = ; }; @@ -31,7 +45,19 @@ type = "u-boot-dtb-with-ucode"; }; u-boot { + /* + * TODO(sjg@chromium.org): + * Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But + * for boards with textbase in SDRAM we cannot do this. Just use + * an assumed-valid value (1MB before the end of flash) here so + * that we can actually build an image for coreboot, etc. + * We need a better solution, perhaps a separate Kconfig. + */ +#if CONFIG_SYS_TEXT_BASE == 0x1110000 offset = <0xfff00000>; +#else + offset = ; +#endif }; #else u-boot-with-ucode-ptr { @@ -77,7 +103,11 @@ offset = ; }; #endif -#ifdef CONFIG_SPL +#ifdef CONFIG_TPL + x86-start16-tpl { + offset = ; + }; +#elif defined(CONFIG_SPL) x86-start16-spl { offset = ; };