From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 17 Dec 2014 07:50:42 +0000 (+0800)
Subject: x86: Use consistent name XXX_ADDR for binary blob flash address
X-Git-Tag: v2015.01-rc4~16^2~8
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=8c5224c9f5c8a24ff5153f018e10a3ac4da5783a;p=oweals%2Fu-boot.git

x86: Use consistent name XXX_ADDR for binary blob flash address

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

diff --git a/Makefile b/Makefile
index bda8222af4..d962576c34 100644
--- a/Makefile
+++ b/Makefile
@@ -958,7 +958,7 @@ IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
 endif
 
 ifneq ($(CONFIG_HAVE_MRC),)
-IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin
+IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
 endif
 
 ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index df2b9901fc..b95e781bbf 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -177,7 +177,7 @@ int sdram_initialise(struct pei_data *pei_data)
 
 	debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
 
-	data = (char *)CONFIG_X86_MRC_START;
+	data = (char *)CONFIG_X86_MRC_ADDR;
 	if (data) {
 		int rv;
 		int (*func)(struct pei_data *);
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 56fe85ccad..f6b52010c3 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -29,7 +29,7 @@ config FSP_FILE
 	  The filename of the file to use as Firmware Support Package binary
 	  in the board directory.
 
-config FSP_LOCATION
+config FSP_ADDR
 	hex "Firmware Support Package binary location"
 	depends on HAVE_FSP
 	default 0xfffc0000
@@ -65,7 +65,7 @@ config CMC_FILE
 	  The filename of the file to use as Chipset Micro Code state machine
 	  binary in the board directory.
 
-config CMC_LOCATION
+config CMC_ADDR
 	hex "Chipset Micro Code state machine binary location"
 	depends on HAVE_CMC
 	default 0xfffb0000
diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c
index df3bbd07c9..f830eeb33d 100644
--- a/arch/x86/cpu/queensbay/fsp_support.c
+++ b/arch/x86/cpu/queensbay/fsp_support.c
@@ -64,7 +64,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
 	volatile register u8 *fsp asm("eax");
 
 	/* Initalize the FSP base */
-	fsp = (u8 *)CONFIG_FSP_LOCATION;
+	fsp = (u8 *)CONFIG_FSP_ADDR;
 
 	/* Check the FV signature, _FVH */
 	if (((struct fv_header_t *)fsp)->sign == 0x4856465F) {
diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S
index 2e9139eb8c..5e09568b85 100644
--- a/arch/x86/cpu/queensbay/tnc_car.S
+++ b/arch/x86/cpu/queensbay/tnc_car.S
@@ -29,7 +29,7 @@ find_fsp_header_ret:
 	mov	%eax, %ebp
 
 	/* sanity test */
-	cmp	$CONFIG_FSP_LOCATION, %eax
+	cmp	$CONFIG_FSP_ADDR, %eax
 	jb	die
 
 	/* calculate TempRamInitEntry address */
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 645b31c2e2..c9d84e4f06 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -25,7 +25,7 @@
 
 #define CONFIG_X86_RESET_VECTOR
 #define CONFIG_NR_DRAM_BANKS			8
-#define CONFIG_X86_MRC_START			0xfffa0000
+#define CONFIG_X86_MRC_ADDR			0xfffa0000
 #define CONFIG_CACHE_MRC_SIZE_KB		512
 
 #define CONFIG_COREBOOT_SERIAL