From: Igor Opaniuk <igor.opaniuk@toradex.com>
Date: Thu, 28 Nov 2019 13:56:20 +0000 (+0200)
Subject: mach-imx: bootaux: add dcache flushing before enabling M4
X-Git-Tag: v2020.04-rc1~37^2~41
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=89038264bb242787826fa4621dca80f7f9594a7f;p=oweals%2Fu-boot.git

mach-imx: bootaux: add dcache flushing before enabling M4

This patch fixes the issue with broken bootaux command,
when M4 binary is loaded and data cache isn't flushed
before M4 core is enabled.

Reproducing:
> tftpboot ${loadaddr} ${board_name}/hello_world.bin
> cp.b ${loadaddr} 0x7F8000 $filesize
> bootaux 0x7F8000

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
---

diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index ee786f7d06..7c8195e715 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -9,6 +9,7 @@
 #include <command.h>
 #include <imx_sip.h>
 #include <linux/compiler.h>
+#include <cpu_func.h>
 
 int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 {
@@ -27,6 +28,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 	writel(stack, M4_BOOTROM_BASE_ADDR);
 	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
 
+	flush_dcache_all();
+
 	/* Enable M4 */
 #ifdef CONFIG_IMX8M
 	call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0);