From: Piotr Dymacz <pepe2k@gmail.com>
Date: Mon, 21 Mar 2016 20:43:08 +0000 (+0100)
Subject: Don't use CPU/DDR sync mode with fractional multipliers in PLL/clocks config
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=878acc1d1c034832597045840c732c1fcff88044;p=oweals%2Fu-boot_mod.git

Don't use CPU/DDR sync mode with fractional multipliers in PLL/clocks config
---

diff --git a/u-boot/cpu/mips/ar7240/qca_dram.c b/u-boot/cpu/mips/ar7240/qca_dram.c
index cc07897..8b10802 100644
--- a/u-boot/cpu/mips/ar7240/qca_dram.c
+++ b/u-boot/cpu/mips/ar7240/qca_dram.c
@@ -772,7 +772,7 @@ static inline void qca_dram_set_en_refresh(void)
 void qca_dram_init(void)
 {
 	u32 ahb_clk, cpu_clk, ddr_clk, mem_type, tmp_clk;
-	u32 cas_lat, ddr_width, wr_recovery;
+	u32 cas_lat, ddr_width, reg, tmp, wr_recovery;
 
 	mem_type = qca_dram_type();
 
@@ -832,8 +832,36 @@ void qca_dram_init(void)
 		qca_soc_reg_write(QCA_DDR_FSM_WAIT_CTRL_REG, 0xA24);
 #endif
 
-	/* CPU/DDR sync mode */
-	if (cpu_clk == ddr_clk) {
+	/*
+	 * CPU/DDR sync mode only when we don't use
+	 * fractional multipliers in PLL/clocks config
+	 */
+	tmp = 0;
+
+#if (SOC_TYPE & QCA_AR933X_SOC)
+	reg = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_FRAC_REG);
+	reg = (reg & QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK)
+		  >> QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT;
+
+	if (reg)
+		tmp = 1;
+#else
+	reg = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_REG);
+	reg = (reg & QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK)
+		  >> QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT;
+
+	if (reg)
+		tmp = 1;
+
+	reg = qca_soc_reg_read(QCA_PLL_DDR_PLL_DITHER_REG);
+	reg = (reg & QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK)
+		  >> QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT;
+
+	if (reg)
+		tmp = 1;
+#endif
+
+	if (!tmp && (cpu_clk == ddr_clk)) {
 #if (SOC_TYPE & QCA_AR933X_SOC)
 		qca_soc_reg_read_set(QCA_DDR_TAP_CTRL_3_REG, (1 << 8));
 #else