From: Marek Vasut <marex@denx.de>
Date: Tue, 19 Feb 2019 00:43:51 +0000 (+0100)
Subject: ARM: cache: Fix incorrect bitwise operation
X-Git-Tag: v2019.04-rc3~8^2~7
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=86dc480d73776e6628ea39a5429f160ffdc2ec85;p=oweals%2Fu-boot.git

ARM: cache: Fix incorrect bitwise operation

The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Tom Rini <trini@konsulko.com>
Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot")
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
---

diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
index 1296ba6efd..bbaaaa4157 100644
--- a/arch/arm/lib/cache-pl310.c
+++ b/arch/arm/lib/cache-pl310.c
@@ -33,7 +33,7 @@ static void pl310_background_op_all_ways(u32 *op_reg)
 	/* Invalidate all ways */
 	writel(way_mask, op_reg);
 	/* Wait for all ways to be invalidated */
-	while (readl(op_reg) && way_mask)
+	while (readl(op_reg) & way_mask)
 		;
 	pl310_cache_sync();
 }