From: Andre Przywara Date: Thu, 16 Feb 2017 01:20:21 +0000 (+0000) Subject: sunxi: simplify ACTLR.SMP bit set #ifdef X-Git-Tag: v2017.05-rc2~81^2~8 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=85db5831ad4b62719775ff0fd0918a944755b967;p=oweals%2Fu-boot.git sunxi: simplify ACTLR.SMP bit set #ifdef Instead of enumerating all SoC families that need that bit set, let's just express this more clearly: The SMP bits needs to be set on SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the other way round, so we use ! CPU_IS_UP and ! ARM64. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e644ee3e18..7b20750662 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -214,6 +214,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK ARM_SOC_BOOT0_HOOK which contains the required assembler preprocessor code. +config ARM_CORTEX_CPU_IS_UP + bool + default n + config USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy" default y diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 58fbacb774..fdcf68e93b 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -180,10 +180,7 @@ void s_init(void) /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ #endif -#if defined CONFIG_MACH_SUN6I || \ - defined CONFIG_MACH_SUN7I || \ - defined CONFIG_MACH_SUN8I || \ - defined CONFIG_MACH_SUN9I +#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 37b42521a4..ea0d6586fa 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -50,12 +50,14 @@ choice config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7 + select ARM_CORTEX_CPU_IS_UP select SUNXI_GEN_SUN4I select SUPPORT_SPL config MACH_SUN5I bool "sun5i (Allwinner A13)" select CPU_V7 + select ARM_CORTEX_CPU_IS_UP select SUNXI_GEN_SUN4I select SUPPORT_SPL