From: Luís Marques <luismarques@lowrisc.org>
Date: Wed, 15 Jan 2020 13:24:41 +0000 (+0000)
Subject: fix riscv64 a_cas inline asm operand sign extension
X-Git-Tag: v1.2.0~16
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=83350eb17b9cb355e3f08b0340c4f1e8c437fac9;p=oweals%2Fmusl.git

fix riscv64 a_cas inline asm operand sign extension

This patch adds an explicit cast to the int arguments passed to the
inline asm used in the RISC-V's implementation of `a_cas`, to ensure
that they are properly sign extended to 64 bits. They aren't
automatically sign extended by Clang, and GCC technically also doesn't
guarantee that they will be sign extended.
---

diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
index 41ad4d04..0c382588 100644
--- a/arch/riscv64/atomic_arch.h
+++ b/arch/riscv64/atomic_arch.h
@@ -15,7 +15,7 @@ static inline int a_cas(volatile int *p, int t, int s)
 		"	bnez %1, 1b\n"
 		"1:"
 		: "=&r"(old), "=&r"(tmp)
-		: "r"(p), "r"(t), "r"(s)
+		: "r"(p), "r"((long)t), "r"((long)s)
 		: "memory");
 	return old;
 }