From: Icenowy Zheng <icenowy@aosc.io>
Date: Thu, 25 Oct 2018 09:23:05 +0000 (+0800)
Subject: sunxi: map DRAM part with 3G size
X-Git-Tag: v2018.11-rc3~1^2~2
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=7009134c99512bd8a9a09cf14f35450f32a8602c;p=oweals%2Fu-boot.git

sunxi: map DRAM part with 3G size

All Allwinner 64-bit SoCs now are known to be able to access 3GiB of
external DRAM, however the size of DRAM part in the MMU translation
table is still 2GiB.

Change the size of DRAM part in MMU table to 3GiB.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
---

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index d22a84ea6b..b74eaf2a0e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -52,7 +52,7 @@ static struct mm_region sunxi_mem_map[] = {
 		/* RAM */
 		.virt = 0x40000000UL,
 		.phys = 0x40000000UL,
-		.size = 0x80000000UL,
+		.size = 0xC0000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_INNER_SHARE
 	}, {