From: Piotr Dymacz <pepe2k@gmail.com>
Date: Sun, 25 Sep 2016 20:48:18 +0000 (+0200)
Subject: Fix DDR2 setup on AR934x and QCA95xx
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=6bcd876a2b13dc9c6db90e15f91754e6c3c2d6d9;p=oweals%2Fu-boot_mod.git

Fix DDR2 setup on AR934x and QCA95xx

Instead of set/unset a SEL_18 bit field in DDR_CTL_CONFIG register,
without touching values of rest of the fields, the code was writing
value 0x40 (bit 6 set) into register (and clearing other fields).

This bug was causing problems with DDR2 initialization at least on
AR934{1,2} with DDR2 memory type.
---

diff --git a/u-boot/cpu/mips/ar7240/qca_dram.c b/u-boot/cpu/mips/ar7240/qca_dram.c
index d5384b3..ad173ce 100644
--- a/u-boot/cpu/mips/ar7240/qca_dram.c
+++ b/u-boot/cpu/mips/ar7240/qca_dram.c
@@ -891,17 +891,20 @@ void qca_dram_init(void)
 	}
 
 	/* Enable DDR2 */
-	if (mem_type == RAM_MEMORY_TYPE_DDR2) {
 #if (SOC_TYPE & QCA_AR933X_SOC)
+	if (mem_type == RAM_MEMORY_TYPE_DDR2)
 		qca_dram_set_ddr2_cfg(cas_lat, tmp_clk);
 #else
-		qca_soc_reg_write(QCA_DDR_CTRL_CFG_REG,
-				  QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK);
+	if (mem_type == RAM_MEMORY_TYPE_DDR2) {
+		qca_soc_reg_read_set(QCA_DDR_CTRL_CFG_REG,
+				     QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK);
 
 		qca_dram_set_ddr2_cfg(cas_lat, tmp_clk);
-#endif
-
+	} else {
+		qca_soc_reg_read_clear(QCA_DDR_CTRL_CFG_REG,
+				       QCA_DDR_CTRL_CFG_PAD_DDR2_SEL_MASK);
 	}
+#endif
 
 	/* Setup DDR timing related registers */
 	qca_dram_set_ddr_cfg(cas_lat, tmp_clk, mem_type);