From: Piotr Dymacz Date: Mon, 21 Mar 2016 22:32:28 +0000 (+0100) Subject: Make use of new PLL/clock profiles, remove some not really useful, fix profiles for... X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=6b84b99a37dd8bd3ddc5e86fe1493ac602c305fb;p=oweals%2Fu-boot_mod.git Make use of new PLL/clock profiles, remove some not really useful, fix profiles for QCA95xx and mark tested --- diff --git a/u-boot/include/cmd_qcaclk.h b/u-boot/include/cmd_qcaclk.h index 26dd05d..57f4738 100755 --- a/u-boot/include/cmd_qcaclk.h +++ b/u-boot/include/cmd_qcaclk.h @@ -197,372 +197,327 @@ static const clk_profile clk_profiles[] = { }, { /* Tested! */ - 500, 500, 250, 25, - _ar933x_spi_ctrl_addr_reg_val(10, 1, 0), + 410, 410, 205, 25, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1), + _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1), _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), - _ar933x_cpu_pll_dither_frac_reg_val(0) + _ar933x_cpu_pll_dither_frac_reg_val(820) }, { - _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1), + _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1), _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), - _ar933x_cpu_pll_dither_frac_reg_val(0) + _ar933x_cpu_pll_dither_frac_reg_val(512) }, }, - #else { - 25, 25, 12, 1, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), - { - _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) - }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 8, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) - }, - }, { - 25, 25, 25, 3, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + /* Tested! */ + 420, 420, 210, 26, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(33, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(615) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 50, 50, 25, 3, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 430, 430, 215, 26, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(34, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(410) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(21, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(512) }, - }, { - 50, 50, 50, 6, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 440, 440, 220, 27, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(35, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(205) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(22, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 75, 75, 25, 3, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 450, 450, 225, 28, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(45, 2, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 75, 75, 50, 6, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 460, 460, 230, 28, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(36, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(820) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 75, 75, 75, 9, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 470, 470, 235, 29, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(37, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(615) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(23, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(512) }, - }, { - 100, 100, 25, 3, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 480, 480, 240, 30, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(38, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(410) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 100, 100, 50, 6, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 490, 490, 245, 30, + _ar933x_spi_ctrl_addr_reg_val(8, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(39, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(205) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(512) }, - }, { - 100, 100, 100, 12, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 500, 500, 250, 25, + _ar933x_spi_ctrl_addr_reg_val(10, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 125, 50, 25, 3, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 510, 510, 255, 25, + _ar933x_spi_ctrl_addr_reg_val(10, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(820) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(512) }, - }, { - 125, 50, 50, 6, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 520, 520, 260, 26, + _ar933x_spi_ctrl_addr_reg_val(10, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(41, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(615) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 125, 62, 25, 3, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 530, 265, 132, 22, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 5, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(42, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(410) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 10, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(26, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(512) }, - }, { - 125, 62, 50, 6, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 540, 270, 135, 22, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(43, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(205) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 2, 1, 0, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 125, 62, 62, 7, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 550, 275, 137, 22, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(27, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(512) }, - }, { - 125, 100, 25, 3, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 560, 280, 140, 23, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(44, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(820) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(0) }, - }, { - 125, 100, 50, 6, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 570, 285, 142, 23, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(45, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(615) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(512) }, - }, { - 125, 100, 62, 7, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + }, + { + /* Tested! */ + 580, 290, 145, 24, + _ar933x_spi_ctrl_addr_reg_val(6, 1, 0), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _ar933x_cpu_pll_cfg_reg_val(46, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(410) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 0), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) - }, - }, { - 125, 100, 100, 12, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + _ar933x_cpu_pll_cfg_reg_val(29, 1, 0, 1), + _ar933x_cpu_clk_ctrl_reg_val(1, 2, 4), + _ar933x_cpu_pll_dither_frac_reg_val(0) + }, + }, + #else + { + /* Tested! */ + 100, 100, 100, 25, + _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(28, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(35, 2, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { - 150, 150, 75, 9, - _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), + /* Tested! */ + 125, 100, 100, 25, + _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(25, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1), + _qca95xx_cpu_pll_dither_reg_val(16), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 150, 150, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { - 150, 150, 150, 18, + /* Tested! */ + 150, 150, 150, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 160, 160, 80, 10, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -572,13 +527,14 @@ static const clk_profile clk_profiles[] = { _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 1, 0), - _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0), + _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 0, 1, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 170, 170, 85, 10, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -595,6 +551,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 180, 180, 90, 11, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -611,150 +568,160 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 200, 200, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) - } + }, }, { + /* Tested! */ 200, 200, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) - } + }, }, { + /* Tested! */ 200, 200, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) - } + }, }, { + /* Tested! */ 300, 200, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) - } + }, }, { + /* Tested! */ 300, 200, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) - } + }, }, { + /* Tested! */ 300, 200, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) - } + }, }, { + /* Tested! */ 300, 300, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) - } + }, }, { + /* Tested! */ 300, 300, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 300, 300, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 350, 350, 175, 21, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -771,6 +738,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 360, 360, 180, 22, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -787,14 +755,15 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 380, 380, 190, 23, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(46, 3, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(46, 3, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), - _qca95xx_cpu_pll_dither_reg_val(0), - _qca95xx_ddr_pll_dither_reg_val(0) + _qca95xx_cpu_pll_dither_reg_val(13), + _qca95xx_ddr_pll_dither_reg_val(205) }, { _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0), _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0), @@ -803,54 +772,58 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 200, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 200, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1), + _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 200, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 300, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -867,6 +840,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 300, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -883,6 +857,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 300, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -899,6 +874,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 300, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -915,6 +891,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 400, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -931,6 +908,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 400, 400, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -947,22 +925,24 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 200, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 200, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -979,22 +959,24 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 200, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 300, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1011,6 +993,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 300, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1027,6 +1010,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 300, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1043,6 +1027,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 300, 250, 25, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1059,6 +1044,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 300, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -1075,6 +1061,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 400, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1091,6 +1078,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 400, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1107,6 +1095,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 400, 250, 25, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1123,6 +1112,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 500, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1139,6 +1129,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 500, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1155,22 +1146,24 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 500, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 500, 250, 25, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1187,6 +1180,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 500, 500, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -1203,6 +1197,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 200, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1219,6 +1214,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 200, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1235,22 +1231,24 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 200, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 300, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1267,6 +1265,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 300, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1283,6 +1282,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 300, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1299,6 +1299,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 300, 275, 27, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1315,6 +1316,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 300, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -1331,6 +1333,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 375, 250, 25, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1347,6 +1350,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 550, 400, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1363,6 +1367,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 560, 450, 225, 28, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1379,70 +1384,75 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 200, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 200, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 200, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 300, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 300, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1459,22 +1469,24 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 300, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 300, 250, 25, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1491,6 +1503,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 300, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -1507,6 +1520,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 400, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1523,6 +1537,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 400, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1539,6 +1554,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 400, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1555,6 +1571,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 400, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -1571,6 +1588,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 450, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1587,6 +1605,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 450, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1603,6 +1622,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 450, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1619,6 +1639,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 450, 225, 28, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1635,6 +1656,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 450, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -1651,6 +1673,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 500, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1667,6 +1690,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 500, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1683,6 +1707,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 500, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1699,6 +1724,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 500, 250, 25, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1715,22 +1741,24 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 500, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 550, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1747,6 +1775,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 550, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1763,6 +1792,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 550, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1779,6 +1809,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 550, 275, 27, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1795,6 +1826,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 550, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -1811,6 +1843,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 600, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1827,6 +1860,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 600, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1843,6 +1877,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 600, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1859,6 +1894,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 600, 250, 25, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { @@ -1875,6 +1911,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 600, 600, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -1891,22 +1928,24 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 200, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(52), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 200, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1923,22 +1962,24 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 200, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(52), _qca95xx_ddr_pll_dither_reg_val(0) }, { _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), - _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0), - _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1), + _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0), + _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 300, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1955,6 +1996,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 300, 150, 18, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1971,6 +2013,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 300, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -1987,6 +2030,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 300, 300, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -2003,6 +2047,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 400, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -2019,6 +2064,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 400, 155, 19, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -2035,6 +2081,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 400, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -2051,6 +2098,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 400, 310, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { @@ -2067,102 +2115,109 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 500, 100, 12, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(52), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 500, 155, 19, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(52), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 500, 166, 20, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(52), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 500, 206, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(52), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 500, 250, 25, _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(52), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 620, 500, 310, 25, _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2), { - _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(52), _qca95xx_ddr_pll_dither_reg_val(0) }, { - _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0), + _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0), _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0), _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0), _qca95xx_cpu_pll_dither_reg_val(0), _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 650, 400, 200, 25, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -2179,6 +2234,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 650, 420, 210, 26, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { @@ -2195,6 +2251,7 @@ static const clk_profile clk_profiles[] = { _qca95xx_ddr_pll_dither_reg_val(0) }, }, { + /* Tested! */ 650, 450, 225, 28, _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2), { diff --git a/u-boot/include/soc/qca95xx_pll_init.h b/u-boot/include/soc/qca95xx_pll_init.h old mode 100644 new mode 100755 index b8ea1e5..87c82ec --- a/u-boot/include/soc/qca95xx_pll_init.h +++ b/u-boot/include/soc/qca95xx_pll_init.h @@ -85,227 +85,52 @@ * PLL configuration preset list * ============================= */ -#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_25_25_12) +#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 8, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(28, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_25_25_25) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(35, 2, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(7, 7, 7, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 4, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_50_50_25) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_50_50_50) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_100) /* Tested! */ -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_25) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(25, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(28, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 2, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 7, 7, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1) + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(4, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_50) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_100) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_75) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 1, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_25) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_50_25) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_50_50) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_25) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 5, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 10, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_50) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 2, 1, 0, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_62) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 4, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_25) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_50) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_62) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 0) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_100) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 1, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_75) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_100) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) - -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) - - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 1, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0) @@ -315,7 +140,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_170_170_85) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_170_170_85) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0) @@ -325,7 +150,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_180_180_90) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_180_180_90) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0) @@ -335,97 +160,97 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 6, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_150) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(3, 3, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_100) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 6, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_150) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_200) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 3, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_100) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_200) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0) @@ -435,7 +260,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_360_360_180) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_360_360_180) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0) @@ -445,27 +270,29 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_380_380_190) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_380_380_190) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(46, 3, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(46, 3, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(13) + #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_ddr_pll_dither_reg_val(205) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) @@ -475,17 +302,17 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -495,7 +322,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -505,7 +332,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -515,7 +342,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -527,7 +354,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -537,7 +364,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -549,17 +376,17 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -569,17 +396,17 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -589,7 +416,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -599,7 +426,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -609,7 +436,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_250) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_250) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -621,7 +448,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -633,7 +460,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -643,7 +470,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -653,7 +480,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_250) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_250) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -665,7 +492,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) @@ -675,7 +502,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -685,17 +512,17 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) @@ -707,7 +534,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -719,7 +546,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -729,7 +556,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -739,17 +566,17 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -759,7 +586,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -769,7 +596,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -779,7 +606,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_275) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_275) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -791,7 +618,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -803,7 +630,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_375_250) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_375_250) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0) @@ -815,7 +642,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_400_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_400_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -825,7 +652,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_450_225) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_450_225) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) @@ -836,47 +663,47 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 0, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -886,17 +713,17 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_250) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_250) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) @@ -908,7 +735,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -920,7 +747,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -930,7 +757,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -940,7 +767,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -950,7 +777,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -962,7 +789,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) @@ -972,7 +799,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) @@ -982,7 +809,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) @@ -992,7 +819,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_225) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_225) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) @@ -1002,7 +829,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) @@ -1014,7 +841,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) @@ -1024,7 +851,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) @@ -1034,7 +861,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) @@ -1044,7 +871,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_250) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_250) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) @@ -1056,7 +883,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) @@ -1068,7 +895,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) @@ -1078,7 +905,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) @@ -1088,7 +915,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) @@ -1098,7 +925,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_275) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_275) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) @@ -1110,7 +937,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) @@ -1122,7 +949,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -1132,7 +959,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -1142,7 +969,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -1152,7 +979,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_250) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_250) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) @@ -1164,7 +991,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -1174,18 +1001,18 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -1196,18 +1023,18 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) - #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -1218,7 +1045,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_150) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_150) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -1229,7 +1056,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) @@ -1240,7 +1067,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_300) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_300) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) @@ -1253,7 +1080,7 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_100) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -1264,7 +1091,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_155) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_155) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -1275,7 +1102,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -1286,7 +1113,7 @@ #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_310) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_310) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -1299,77 +1126,77 @@ #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_100) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_100) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_155) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_155) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_166) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_166) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_206) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_206) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_250) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_250) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_310) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_310) /* Tested! */ - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) - #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_400_200) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_400_200) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -1380,7 +1207,7 @@ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_420_210) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_420_210) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) @@ -1392,7 +1219,7 @@ #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16) -#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_450_225) +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_450_225) /* Tested! */ #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0) #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0)