From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 25 Sep 2019 09:45:30 +0000 (+0800)
Subject: dts: mtmips: update reset controller node for mt7628
X-Git-Tag: v2020.01-rc1~4^2~14
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=6658ebc96a64534c605ef34594c592096a481ed2;p=oweals%2Fu-boot.git

dts: mtmips: update reset controller node for mt7628

This patch updates reset controller node for mt7628

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---

diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index 44fbbd5b25..b0e0ed7ec8 100644
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/clock/mt7628-clk.h>
+#include <dt-bindings/reset/mt7628-reset.h>
 
 / {
 	#address-cells = <1>;
@@ -17,11 +18,6 @@
 		};
 	};
 
-	resetc: reset-controller {
-		compatible = "ralink,rt2880-reset";
-		#reset-cells = <1>;
-	};
-
 	cpuintc: interrupt-controller {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
@@ -57,6 +53,12 @@
 			u-boot,dm-pre-reloc;
 		};
 
+		rstctrl: rstctrl@0x34 {
+			reg = <0x34 0x4>;
+			compatible = "mediatek,mtmips-reset";
+			#reset-cells = <1>;
+		};
+
 		pinctrl: pinctrl@60 {
 			compatible = "mediatek,mt7628-pinctrl";
 			reg = <0x3c 0x2c>, <0x1300 0x100>;
@@ -211,7 +213,7 @@
 			compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
 			reg = <0x100 0x30>;
 
-			resets = <&resetc 8>;
+			resets = <&rstctrl MT7628_TIMER_RST>;
 			reset-names = "wdt";
 
 			interrupt-parent = <&intc>;
@@ -225,7 +227,7 @@
 			interrupt-controller;
 			#interrupt-cells = <1>;
 
-			resets = <&resetc 9>;
+			resets = <&rstctrl MT7628_INT_RST>;
 			reset-names = "intc";
 
 			interrupt-parent = <&cpuintc>;
@@ -248,6 +250,9 @@
 			compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
 			reg = <0x600 0x100>;
 
+			resets = <&rstctrl MT7628_PIO_RST>;
+			reset-names = "pio";
+
 			interrupt-parent = <&intc>;
 			interrupts = <6>;
 
@@ -276,6 +281,10 @@
 		spi0: spi@b00 {
 			compatible = "ralink,mt7621-spi";
 			reg = <0xb00 0x40>;
+
+			resets = <&rstctrl MT7628_SPI_RST>;
+			reset-names = "spi";
+
 			#address-cells = <1>;
 			#size-cells = <0>;
 
@@ -291,7 +300,7 @@
 
 			clocks = <&clkctrl CLK_UART0>;
 
-			resets = <&resetc 12>;
+			resets = <&rstctrl MT7628_UART0_RST>;
 			reset-names = "uart0";
 
 			interrupt-parent = <&intc>;
@@ -309,7 +318,7 @@
 
 			clocks = <&clkctrl CLK_UART1>;
 
-			resets = <&resetc 19>;
+			resets = <&rstctrl MT7628_UART1_RST>;
 			reset-names = "uart1";
 
 			interrupt-parent = <&intc>;
@@ -327,7 +336,7 @@
 
 			clocks = <&clkctrl CLK_UART2>;
 
-			resets = <&resetc 20>;
+			resets = <&rstctrl MT7628_UART2_RST>;
 			reset-names = "uart2";
 
 			interrupt-parent = <&intc>;
@@ -342,6 +351,9 @@
 		reg = <0x10100000 0x10000
 		       0x10110000 0x8000>;
 
+		resets = <&rstctrl MT7628_EPHY_RST>;
+		reset-names = "ephy";
+
 		syscon = <&sysc>;
 	};
 
@@ -353,8 +365,8 @@
 
 		ralink,sysctl = <&sysc>;
 
-		resets = <&resetc 22 &resetc 25>;
-		reset-names = "host", "device";
+		resets = <&rstctrl MT7628_UPHY_RST>;
+		reset-names = "phy";
 
 		clocks = <&clkctrl CLK_UPHY>;
 		clock-names = "cg";