From: Tim Harvey Date: Fri, 8 Aug 2014 05:57:29 +0000 (-0700) Subject: pci: mx6: fix occasional link failures X-Git-Tag: v2014.10-rc2~52^2~14 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=5a82e1a21d1229e7e3d1c64187735794019e9a1b;p=oweals%2Fu-boot.git pci: mx6: fix occasional link failures According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey Acked-by: Marek Vasut Reviewed-by: Fabio Estevam --- diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e6c9..a3982c4553 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void) imx6_pcie_toggle_power(); - /* Enable PCIe */ - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); - enable_pcie_clock(); /* @@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void) */ mdelay(50); + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + imx6_pcie_toggle_reset(); return 0;