From: Kever Yang <kever.yang@rock-chips.com>
Date: Mon, 22 Jul 2019 12:02:01 +0000 (+0800)
Subject: rockchip: add common board file for U-Boot proper
X-Git-Tag: v2019.10-rc1~6^2~20
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=54f17fa05d453618afabff1246c1a16cea304b1b;p=oweals%2Fu-boot.git

rockchip: add common board file for U-Boot proper

Add common board file for Rockchip SoCs to avoid too much
copy-paste work for different SoCs.
This board file in charge for common board_init() and board_late_init()
in U-Boot proper.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 81dee9e5c7..4d983f8fce 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -229,6 +229,13 @@ config TPL_ROCKCHIP_BACK_TO_BROM
           SPL will return to the boot rom, which will then load the U-Boot
           binary to keep going on.
 
+config ROCKCHIP_COMMON_BOARD
+	bool "Rockchip common board file"
+	help
+	  Rockchip SoCs have similar boot process, Common board file is mainly
+	  in charge of common process of board_init() and board_late_init() for
+	  U-Boot proper.
+
 config SPL_ROCKCHIP_COMMON_BOARD
 	bool "Rockchip SPL common board file"
 	depends on SPL
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5cb2c6dcc9..7d2a227794 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -20,6 +20,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 # we can have the preprocessor correctly recognise both 0x0 and 0
 # meaning "turn it off".
 obj-y += boot_mode.o
+obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
 
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
 obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
new file mode 100644
index 0000000000..b2a88e789d
--- /dev/null
+++ b/arch/arm/mach-rockchip/board.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/boot_mode.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int rk_board_late_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setup_boot_mode();
+
+	return rk_board_late_init();
+}
+
+int board_init(void)
+{
+	int ret;
+
+#ifdef CONFIG_DM_REGULATOR
+	ret = regulators_enable_boot_on(false);
+	if (ret)
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+	return 0;
+}
+
+#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data otg_data = {
+	.rx_fifo_sz	= 512,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node;
+	const char *mode;
+	bool matched = false;
+	const void *blob = gd->fdt_blob;
+
+	/* find the usb_otg node */
+	node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
+
+	while (node > 0) {
+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
+		if (mode && strcmp(mode, "otg") == 0) {
+			matched = true;
+			break;
+		}
+
+		node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2");
+	}
+	if (!matched) {
+		debug("Not found usb_otg device\n");
+		return -ENODEV;
+	}
+	otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+	return dwc2_udc_probe(&otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT)
+int fastboot_set_reboot_flag(void)
+{
+	printf("Setting reboot to fastboot flag ...\n");
+	/* Set boot mode to fastboot */
+	writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+
+	return 0;
+}
+#endif