From: Piotr Dymacz Date: Sat, 20 Feb 2016 01:17:26 +0000 (+0100) Subject: Fix CPU PLL dither register definitions; add some other needed defines in common... X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=463ba42dc63bf77eaf4a2ad8febeaceff1943fb5;p=oweals%2Fu-boot_mod.git Fix CPU PLL dither register definitions; add some other needed defines in common QCA header file --- diff --git a/u-boot/cpu/mips/ar7240/qca_clocks.c b/u-boot/cpu/mips/ar7240/qca_clocks.c index 19fd3e5..075584b 100644 --- a/u-boot/cpu/mips/ar7240/qca_clocks.c +++ b/u-boot/cpu/mips/ar7240/qca_clocks.c @@ -1,12 +1,12 @@ /* * Qualcomm/Atheros system clocks related functions * - * Copyright (C) 2015 Piotr Dymacz + * Copyright (C) 2016 Piotr Dymacz * * Partially based on: * Linux/arch/mips/ath79/clock.c * - * SPDX-License-Identifier:GPL-2.0 + * SPDX-License-Identifier: GPL-2.0 */ #include @@ -108,17 +108,17 @@ void qca_sys_clocks(u32 *cpu_clk, *ddr_clk = qca_ref_clk; *ahb_clk = qca_ref_clk; } else { - reg_val = qca_soc_reg_read(QCA_PLL_PLL_DITHER_REG); + reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_REG); - if (reg_val & QCA_PLL_PLL_DITHER_DITHER_EN_MASK) { + if (reg_val & QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK) { reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_CFG_REG); nfrac = (reg_val & QCA_PLL_CPU_PLL_CFG_NFRAC_MASK) >> QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT; } else { /* NFRAC = NFRAC_MIN if DITHER_EN is 0 */ - reg_val = qca_soc_reg_read(QCA_PLL_PLL_DITHER_FRAC_REG); - nfrac = (reg_val & QCA_PLL_PLL_DITHER_FRAC_NFRAC_MIN_MASK) - >> QCA_PLL_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT; + reg_val = qca_soc_reg_read(QCA_PLL_CPU_PLL_DITHER_FRAC_REG); + nfrac = (reg_val & QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK) + >> QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT; } nfracdiv = 1 << 10; diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h index c3e7142..0cdb59e 100644 --- a/u-boot/include/soc/qca_soc_common.h +++ b/u-boot/include/soc/qca_soc_common.h @@ -704,8 +704,8 @@ #if (SOC_TYPE & QCA_AR933X_SOC) #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04 #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08 - #define QCA_PLL_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10 - #define QCA_PLL_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14 + #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10 + #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14 #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40 @@ -806,20 +806,6 @@ #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT 15 #define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT, 2) -/* PLL_DITHER_FRAC register (CPU PLL dither FRAC, AR933x only) */ -#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0 -#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_MAX_MASK BITS(QCA_PLL_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10) -#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT 10 -#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_MIN_MASK BITS(QCA_PLL_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10) -#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT 10 -#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_STEP_MASK BITS(QCA_PLL_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 20) - -/* PLL_DITHER register (CPU PLL dither, AR933x only) */ -#define QCA_PLL_PLL_DITHER_UPDATE_CNT_SHIFT 0 -#define QCA_PLL_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_PLL_DITHER_UPDATE_CNT_SHIFT, 14) -#define QCA_PLL_PLL_DITHER_DITHER_EN_SHIFT 31 -#define QCA_PLL_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_PLL_DITHER_DITHER_EN_SHIFT) - /* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */ #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT 3 #define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_PLLPWD_SHIFT) @@ -928,12 +914,12 @@ #if (SOC_TYPE & QCA_AR933X_SOC) /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */ - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0 - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 10) - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 10 - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 10) - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 20 - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 10) + #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0 + #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10) + #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT 10 + #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10) + #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT 20 + #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 10) /* PLL_DITHER register (CPU PLL dither) */ #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0 @@ -1070,6 +1056,10 @@ #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2 + #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT 16 + #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK (1 << QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT) + #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT 17 + #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT) #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT 18 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT) #else @@ -1231,7 +1221,7 @@ #define QCA_RTC_SYNC_RST_REG QCA_RTC_BASE_REG + 0x40 #define QCA_RTC_SYNC_STATUS_REG QCA_RTC_BASE_REG + 0x44 #define QCA_RTC_SYNC_DERIVED_REG QCA_RTC_BASE_REG + 0x48 -#define QCA_RTC_FORCE_WAKE_REG QCA_RTC_BASE_REG + 0x4C +#define QCA_RTC_SYNC_FORCE_WAKE_REG QCA_RTC_BASE_REG + 0x4C #define QCA_RTC_INTERRUPT_CAUSE_REG QCA_RTC_BASE_REG + 0x50 #define QCA_RTC_INTERRUPT_EN_REG QCA_RTC_BASE_REG + 0x54 #define QCA_RTC_INTERRUPT_MASK_REG QCA_RTC_BASE_REG + 0x58 @@ -1276,6 +1266,12 @@ #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT 5 #define QCA_RTC_SYNC_STATUS_PLL_CHANGING_MASK (1 << QCA_RTC_SYNC_STATUS_PLL_CHANGING_SHIFT) +/* RTC_SYNC_FORCE_WAKE register (RTC force wake) */ +#define QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT 0 +#define QCA_RTC_SYNC_FORCE_WAKE_EN_MASK (1 << QCA_RTC_SYNC_FORCE_WAKE_EN_SHIFT) +#define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT 1 +#define QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK (1 << QCA_RTC_SYNC_FORCE_WAKE_MACINTR_SHIFT) + /* * SPI serial flash registers */