From: Tom Rini <trini@konsulko.com>
Date: Wed, 9 Oct 2019 20:22:03 +0000 (-0400)
Subject: Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot... 
X-Git-Tag: v2020.01-rc1~30
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=44fb0d6c9f5147a41c710032869e5e01b3c9e310;p=oweals%2Fu-boot.git

Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.01

FPGA:
- Enable fpga loading on Versal
- Minor fix

Microblaze:
- Fix LMB configurations to support initrds
- Some other cleanups

Zynq:
- Minor config/dt changes
- Add distro boot support for usb1 and mmc1
- Remove Xilinx private boot commands and use only distro boot

ZynqMP:
- Kconfig cleanups, defconfig updates
- Update some dt files
- Add firmware driver for talking to PMUFW
- Extend distro boot support for jtag
- Add new IDs
- Add system controller configurations
- Convert code to talk firmware via mailbox or SMCs

Versal:
- Add board_late_init()
- Add run time DT memory setup
- Add DFU support
- Extend distro boot support for jtag and dfu
- Add clock driver
- Tune mini configurations

Xilinx:
- Improve documentation (boot scripts, dt binding)
- Enable run time initrd_high calculation
- Define default SYS_PROMPT
- Add zynq/zynqmp virtual defconfig

Drivers:
- Add Xilinx mailbox driver for talking to firmware
- Clean zynq_gem for Versal
- Move ZYNQ_HISPD_BROKEN to Kconfig
- Wire genphy_init() in phy.c
- Add Xilinx gii2rgmii bridge
- Cleanup zynq_sdhci
- dwc3 fix
- zynq_gpio fix
- axi_emac fix

Others:
- apalis-tk1 - clean config file
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44fb0d6c9f5147a41c710032869e5e01b3c9e310