From: Wolfgang Denk Date: Sat, 10 Jun 2006 17:27:47 +0000 (+0200) Subject: Merge with /home/hs/U-Boot/u-boot-dev X-Git-Tag: LABEL_2006_06_30_2020~10 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=4176c799645d8b35224345d899006993397635c1;p=oweals%2Fu-boot.git Merge with /home/hs/U-Boot/u-boot-dev --- 4176c799645d8b35224345d899006993397635c1 diff --cc CHANGELOG index 3b81ff618d,aac832dcc9..a7e38bdb0e --- a/CHANGELOG +++ b/CHANGELOG @@@ -2,21 -2,22 +2,28 @@@ Changes since U-Boot 1.1.4: ====================================================================== -* Add Altera Nios-II boards EP1C20, EP1S10 and EP1S40 - Patch from Scott McNutt, 11 Aug 2005 ++* Add MCF5282 support (without preloader) ++ relocate ichache_State to ram ++ u-boot can run from internal flash ++ Add EB+MCF-EV123 board support. ++ Add m68k Boards to MAKEALL ++ Patch from Jens Scharsig, 08 Aug 2005 ++ +* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards + Patch by Scott McNutt, 08 Jun 2006 + +* Nios II - Add EPCS Controller bootrom work-around + -When booting from an epcs controller, the epcs bootrom may leave the + slave select in an asserted state causing soft reset hang. This + patch ensures slave select is negated at reset. + Patch by Scott McNutt, 08 Jun 2006 -* Update PK1C20 board for Nios-II 5.0 - Patch from Scott McNutt, 11 Aug 2005 +* Update PK1C20 board -Update base addresses for standard configuration -Eliminate use of CACHE_BYPASS in board code + Patch by Scott McNutt, 08 Jun 2006 -* Add EPCS Controller bootrom work-around for Nios-II - Patch from Scott McNutt, 11 Aug 2005 - -When booting from an epcs controller, the epcs bootrom may leave the - slave select in an asserted state causing soft reset hang. This - patch ensures slave select is negated at reset. - -* Fix I/O Macros and mini-app stubs for Nios-II - Patch from Scott McNutt, 11 Aug 2005 +* Nios II - Fix I/O Macros and mini-app stubs -Fix asm/io.h macros -Eliminate use of CACHE_BYPASS in cpu code -Eliminate assembler warnings diff --cc MAKEALL index 28b6d9c3e4,75ec51336c..6778b3bd26 --- a/MAKEALL +++ b/MAKEALL @@@ -255,29 -255,34 +255,38 @@@ LIST_x86="${LIST_I486} ######################################################################### LIST_nios=" \ -- ADNPESC1 ADNPESC1_base_32 \ ++ ADNPESC1 ADNPESC1_base_32 \ ADNPESC1_DNPEVA2_base_32 \ -- DK1C20 DK1C20_standard_32 \ -- DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \ ++ DK1C20 DK1C20_standard_32 \ ++ DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \ " ######################################################################### ## Nios-II Systems ######################################################################### --LIST_nios2="PCI5441 PK1C20 EP1C20 EP1S10 EP1S40" ++LIST_nios2=" \ ++ EP1C20 EP1S10 EP1S40 \ ++ PCI5441 PK1C20 \ ++" ######################################################################### ## MicroBlaze Systems ######################################################################### --LIST_microblaze="suzaku" ++LIST_microblaze=" \ ++ suzaku ++" ######################################################################### -## M68K Systems +## ColdFire Systems ######################################################################### - LIST_coldfire="cobra5272 M5272C3 M5282EVB TASREG r5200 M5271EVB" -LIST_m68k="\ - cobra5272 \ - EB+MCF-EV123 EB+MCF-EV123_internal \ - M5272C3 M5282EVB \ - TASREG \ ++LIST_coldfire=" \ ++ cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \ ++ M5271EVB M5272C3 M5282EVB TASREG \ ++ r5200 M5271EVB \ + " #----------------------------------------------------------------------- diff --cc Makefile index 7424adc7c7,86640a6bbe..440ab2c627 --- a/Makefile +++ b/Makefile @@@ -1300,9 -1280,9 +1300,6 @@@ VoVPN-GW_100MHz_config: unconfi ZPC1900_config: unconfig @./mkconfig $(@:_config=) ppc mpc8260 zpc1900 --#======================================================================== --# M68K --#======================================================================== ######################################################################### ## Coldfire ######################################################################### @@@ -1310,6 -1290,6 +1307,19 @@@ cobra5272_config : unconfig @./mkconfig $(@:_config=) m68k mcf52x2 cobra5272 ++EB+MCF-EV123_config : unconfig ++ @ >include/config.h ++ @echo "TEXT_BASE = 0xFFE00000"|tee board/BuS/EB+MCF-EV123/textbase.mk ++ @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS ++ ++EB+MCF-EV123_internal_config : unconfig ++ @ >include/config.h ++ @echo "TEXT_BASE = 0xF0000000"|tee board/BuS/EB+MCF-EV123/textbase.mk ++ @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS ++ ++M5271EVB_config : unconfig ++ @./mkconfig $(@:_config=) m68k mcf52x2 m5271evb ++ M5272C3_config : unconfig @./mkconfig $(@:_config=) m68k mcf52x2 m5272c3 @@@ -1319,12 -1299,6 +1329,9 @@@ M5282EVB_config : unconfi TASREG_config : unconfig @./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd +r5200_config : unconfig + @./mkconfig $(@:_config=) m68k mcf52x2 r5200 + - M5271EVB_config : unconfig - @./mkconfig $(@:_config=) m68k mcf52x2 m5271evb - ######################################################################### ## MPC83xx Systems ######################################################################### diff --cc cpu/mcf52x2/cpu.c index e6e5d9bee9,8795bcccff..aa6b2bd670 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@@ -158,7 -121,20 +162,19 @@@ int watchdog_init (void #ifdef CONFIG_M5282 int checkcpu (void) { - puts ("CPU: Freescale Coldfire MCF5282\n"); - unsigned char resetsource; ++ unsigned char resetsource = MCFRESET_RSR; + - printf ("CPU: MOTOROLA Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", ++ printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", + MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); - puts ("Reset: "); - resetsource = MCFRESET_RSR; - if (resetsource & MCFRESET_RSR_LOL) puts("Lose-of-lock "); - if (resetsource & MCFRESET_RSR_LOC) puts("Lose-of-clock "); - if (resetsource & MCFRESET_RSR_EXT) puts("external "); - if (resetsource & MCFRESET_RSR_POR) puts("Power-on "); - if (resetsource & MCFRESET_RSR_WDR) puts("Watchdog "); - if (resetsource & MCFRESET_RSR_SOFT) puts("Software "); - if (resetsource & MCFRESET_RSR_LVD) puts("Low-voltage "); - puts("\n"); ++ printf ("Reset:%s%s%s%s%s%s%s\n", ++ (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", ++ (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", ++ (resetsource & MCFRESET_RSR_EXT) ? " External" : "", ++ (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", ++ (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", ++ (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", ++ (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "" ++ ); return 0; } diff --cc cpu/mcf52x2/fec.c index f207dd6acb,b8b82d07dc..702563d7db --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@@ -245,19 -242,12 +247,23 @@@ int eth_init (bd_t * bd #endif #undef ea +#ifdef CONFIG_M5271 + /* Clear multicast address hash table + */ + fecp->fec_ghash_table_high = 0; + fecp->fec_ghash_table_low = 0; + + /* Clear individual address hash table + */ + fecp->fec_ihash_table_high = 0; + fecp->fec_ihash_table_low = 0; +#else /* Clear multicast address hash table */ + #ifdef CONFIG_M5282 + fecp->fec_ihash_table_high = 0; + fecp->fec_ihash_table_low = 0; + #else fecp->fec_hash_table_high = 0; fecp->fec_hash_table_low = 0; #endif @@@ -307,14 -305,12 +322,13 @@@ /* Enable MII mode */ --#if 0 /* Full duplex mode */ ++ ++#if 0 /* Full duplex mode */ fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; --#else /* Half duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; - #ifdef CONFIG_M5271 - fecp->fec_r_cntrl |= (PKT_MAXBUF_SIZE << 16); /* set max frame length */ - #endif ++#else /* Half duplex mode */ + fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ + fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; fecp->fec_x_cntrl = 0; #endif /* Set MII speed */ diff --cc cpu/mcf52x2/serial.c index 10117889ad,fe412a0a3a..8be09e34fe --- a/cpu/mcf52x2/serial.c +++ b/cpu/mcf52x2/serial.c @@@ -53,47 -48,72 +53,77 @@@ DECLARE_GLOBAL_DATA_PTR void rs_serial_setbaudrate(int port,int baudrate) { -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271) volatile unsigned char *uartp; - #ifndef CONFIG_M5271 - double clock, fraction; ++# ifndef CONFIG_M5271 + double fraction; - #endif ++# endif + double clock; if (port == 0) -- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); ++ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); else -- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); ++ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); -- clock = DoubleClock(baudrate); /* Set baud above */ ++ clock = DoubleClock(baudrate); /* Set baud above */ - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ - fraction = ((clock - (int)clock) * 16.0) + 0.5; ++ uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ ++ uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ - #ifndef CONFIG_M5271 - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ - uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ ++# ifndef CONFIG_M5271 + fraction = ((clock - (int)clock) * 16.0) + 0.5; - uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ ++ uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ ++# endif #endif ++ + #if defined(CONFIG_M5282) + volatile unsigned char *uartp; + long clock; + - switch (port) - { - case 1: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - break; - case 2: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); - break; - default: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); ++ switch (port) { ++ case 1: ++ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); ++ break; ++ case 2: ++ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); ++ break; ++ default: ++ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + } + - clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */ ++ clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */ + - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */ ++ uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ ++ uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */ + #endif }; --void rs_serial_init(int port,int baudrate) ++void rs_serial_init (int port, int baudrate) { -- volatile unsigned char *uartp; ++ volatile unsigned char *uartp; /* -- * Reset UART, get it into known state... ++ * Reset UART, get it into known state... */ - if (port == 0) - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - else - switch (port) - { - case 1: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - break; - #if defined(CONFIG_M5282) - case 2: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); - break; - #endif - default: - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); ++ switch (port) { ++ case 1: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); ++ break; ++#if defined(CONFIG_M5282) ++ case 2: ++ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); ++ break; ++#endif ++ default: ++ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + } - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ -- uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ ++ uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ ++ uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ + - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ ++ uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ ++ uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ /* * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity. @@@ -101,15 -121,9 +131,15 @@@ uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8; uartp[MCFUART_UMR] = MCFUART_MR2_STOP1; - rs_serial_setbaudrate(port,baudrate); + /* Mask UART interrupts */ + uartp[MCFUART_UIMR] = 0; + /* Set clock Select Register: Tx/Rx clock is timer */ uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; + - rs_serial_setbaudrate(port,baudrate); ++ rs_serial_setbaudrate (port, baudrate); + + /* Enable Tx/Rx */ uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; return; @@@ -169,9 -183,9 +199,8 @@@ void serial_putc(const char c) } void serial_puts (const char *s) { -- while (*s) { ++ while (*s) serial_putc(*s++); -- } } int serial_getc(void) { diff --cc cpu/mcf52x2/start.S index 3ab812b3d4,9a13491fbd..8a83ca5ef7 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@@ -54,12 -54,12 +54,16 @@@ * These vectors are to catch any un-intended traps. */ _vectors: - .long 0x00000000 -#ifndef CONFIG_M5282 -.long _START -#else + - #ifndef CONFIG_R5200 - .long 0x00000000, _START ++.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ ++#if defined(CONFIG_R5200) ++.long 0x400 ++#elif defined(CONFIG_M5282) + .long _start - TEXT_BASE +#else - .long 0x00000000, 0x400 /* Flash offset is 0 until we setup CS0 */ ++.long _START #endif ++ .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@@ -128,7 -131,7 +135,7 @@@ _start movec %d0, %RAMBAR0 #endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ - #if defined(CONFIG_M5282) || defined(CONFIG_M5271) -#ifdef CONFIG_M5282 ++#if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ move.l %d0, 0x40000000 @@@ -137,26 -156,25 +160,38 @@@ _flashbar_setup /* Initialize FLASHBAR: locate internal Flash and validate it */ move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 movec %d0, %RAMBAR0 - #endif + jmp _after_flashbar_copy.L /* Force jump to absolute address */ + _flashbar_setup_end: + nop + _after_flashbar_copy: + #else + /* Setup code to initialize FLASHBAR, if start from external Memory */ + move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + movec %d0, %RAMBAR0 + #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ - /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 - movec %d0, %RAMBAR1 + #endif + /* if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ + #if !defined(CONFIG_MONITOR_IS_IN_RAM) + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR #endif +#ifdef CONFIG_R5200 + move.l #(_flash_setup-CFG_FLASH_BASE), %a0 + move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1 + move.l #(CFG_INIT_RAM_ADDR), %a2 +_copy_flash: + move.l (%a0)+, (%a2)+ + cmp.l %a0, %a1 + bgt.s _copy_flash + jmp CFG_INIT_RAM_ADDR +_after_flash_copy: +#endif + +#if 0 /* invalidate and disable cache */ move.l #0x01000000, %d0 /* Invalidate cache cmd */ movec %d0, %CACR /* Invalidate cache */