From: Bai Ping <ping.bai@nxp.com>
Date: Mon, 22 Jul 2019 01:24:45 +0000 (+0000)
Subject: i.MX7ULP: Correct the clock index
X-Git-Tag: v2020.01-rc1~33^2~163
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=3ed6734e698e4280361f1a509856c50b07861c99;p=oweals%2Fu-boot.git

i.MX7ULP: Correct the clock index

On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c
index b4f2ea875a..85d726fe30 100644
--- a/arch/arm/mach-imx/mx7ulp/scg.c
+++ b/arch/arm/mach-imx/mx7ulp/scg.c
@@ -440,7 +440,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk)
 	case SCG_SCS_SLOW_IRC:
 	case SCG_SCS_FAST_IRC:
 	case SCG_SCS_RTC_OSC:
-		rate = scg_src_get_rate(scg_scs_array[val]);
+		rate = scg_src_get_rate(scg_scs_array[val - 1]);
 		break;
 	case 5:
 		rate = scg_apll_get_rate();