From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Thu, 15 Nov 2012 11:23:24 +0000 (+0000)
Subject: spi: mxc_spi: Fix spi clock glitch durant reset
X-Git-Tag: v2013.01-rc3~9^2~3^2~14
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=3cea335c34;p=oweals%2Fu-boot.git

spi: mxc_spi: Fix spi clock glitch durant reset

Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.

Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
---

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index b6bad98952..859c43fee2 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -140,8 +140,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 	reg_ctrl = reg_read(&regs->ctrl);
 
 	/* Reset spi */
-	reg_write(&regs->ctrl, 0);
-	reg_write(&regs->ctrl, (reg_ctrl | 0x1));
+	reg_write(&regs->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
+	reg_write(&regs->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
 
 	/*
 	 * The following computation is taken directly from Freescale's code.