From: Anton Staaf <robotboy@chromium.org>
Date: Mon, 17 Oct 2011 23:46:08 +0000 (-0700)
Subject: sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
X-Git-Tag: v2011.12-rc1~469
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=3c3f8a7f3e58a9dbf6c2f3e462ad503eae35852a;p=oweals%2Fu-boot.git

sparc: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
---

diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
index 03e8d94bb2..44870e8c90 100644
--- a/arch/sparc/include/asm/cache.h
+++ b/arch/sparc/include/asm/cache.h
@@ -28,4 +28,14 @@
 #include <linux/config.h>
 #include <asm/processor.h>
 
+/*
+ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
+ * use 32-bytes, the cacheline size for Sparc.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
 #endif