From: Jerome Brunet Date: Tue, 13 Nov 2018 10:38:38 +0000 (+0100) Subject: clk: meson: fix clk81 divider calculation X-Git-Tag: v2019.01-rc1~30^2~1 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=2fa77bd12533e29e1b0f1742f66f258700715d52;p=oweals%2Fu-boot.git clk: meson: fix clk81 divider calculation clk81 divider is 0 based (meaning that 0 value in the register means divide by 1). Fix clk81 rate calculation for this. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong --- diff --git a/drivers/clk/clk_meson.c b/drivers/clk/clk_meson.c index 236d7342b7..c44858822d 100644 --- a/drivers/clk/clk_meson.c +++ b/drivers/clk/clk_meson.c @@ -600,7 +600,8 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); reg = reg & ((1 << 7) - 1); - return parent_rate / reg; + /* clk81 divider is zero based */ + return parent_rate / (reg + 1); } static long mpll_rate_from_params(unsigned long parent_rate,