From: Piotr Dymacz <pepe2k@gmail.com>
Date: Thu, 10 Mar 2016 17:15:07 +0000 (+0100)
Subject: Move up DDR_RD_DATA_THIS_CYCLE register setup in new AR933x dram init code
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=2ea1a0bfe084d40dd13e1a0e857c55840d7619f3;p=oweals%2Fu-boot_mod.git

Move up DDR_RD_DATA_THIS_CYCLE register setup in new AR933x dram init code
---

diff --git a/u-boot/cpu/mips/ar7240/ar933x_dram.c b/u-boot/cpu/mips/ar7240/ar933x_dram.c
index 971a4fa..7d0ecbd 100644
--- a/u-boot/cpu/mips/ar7240/ar933x_dram.c
+++ b/u-boot/cpu/mips/ar7240/ar933x_dram.c
@@ -178,6 +178,9 @@ void qca_dram_init(void)
 					  _qca_ddr_cfg2_reg_val(0, 1, 0, 1, 6, 14, 8, 14, 7, 1));
 #endif
 
+	/* AR933x supports only 16-bit memory */
+	qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF);
+
 	if (mem_type == RAM_MEMORY_TYPE_SDR) {
 		/* Enable SDR */
 		qca_soc_reg_write(QCA_SDR_CFG_REG, 1);
@@ -229,8 +232,5 @@ void qca_dram_init(void)
 	/* Enable DDR refresh and setup refresh period */
 	qca_dram_set_en_refresh();
 
-	/* AR933x supports only 16-bit memory */
-	qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF);
-
 	ar933x_ddr_tap_tune();
 }