From: Patrice Chotard Date: Thu, 18 Jan 2018 12:39:34 +0000 (+0100) Subject: ARM: dts: stm32: add stm32429-eval-u-boot dts file X-Git-Tag: v2018.03-rc1~54 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=2d58dddf7a37ea548bb940de2db050f5fe1a582d;p=oweals%2Fu-boot.git ARM: dts: stm32: add stm32429-eval-u-boot dts file _ Add gpio compatible and aliases for stm32f469 _ Add FMC sdram node _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by: Patrice Chotard --- diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi new file mode 100644 index 0000000000..826c942e67 --- /dev/null +++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +/{ + clocks { + u-boot,dm-pre-reloc; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + soc { + u-boot,dm-pre-reloc; + pin-controller { + u-boot,dm-pre-reloc; + }; + + fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; + st,syscfg = <&syscfg>; + pinctrl-0 = <&fmc_pins_d32>; + pinctrl-names = "default"; + st,mem_remap = <4>; + u-boot,dm-pre-reloc; + + /* + * Memory configuration from sdram + * MICRON MT48LC4M32B2B5-7 + */ + bank0: bank@0 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = < 2812 >; + }; + }; + }; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&clk_lse { + u-boot,dm-pre-reloc; +}; + +&clk_i2s_ckin { + u-boot,dm-pre-reloc; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&syscfg { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&gpioa { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiob { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioc { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiod { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioe { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiof { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiog { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioh { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioi { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioj { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiok { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; + + fmc_pins_d32: fmc_d32@0 { + u-boot,dm-pre-reloc; + pins + { + pinmux = , /* D31 */ + , /* D30 */ + , /* D29 */ + , /* D28 */ + , /* D27 */ + , /* D26 */ + , /* D25 */ + , /* D24 */ + , /* D23 */ + , /* D22 */ + , /* D21 */ + , /* D20 */ + , /* D19 */ + , /* D18 */ + , /* D17 */ + , /* D16 */ + + , /* D15 */ + , /* D14 */ + , /* D13 */ + , /* D12 */ + , /* D11 */ + , /* D10 */ + , /* D09 */ + , /* D08 */ + , /* D07 */ + , /* D06 */ + , /* D05 */ + , /* D04 */ + , /* D03 */ + , /* D02 */ + , /* D01 */ + , /* D00 */ + + , /* NBL0 */ + , /* NBL1 */ + , /* NBL2 */ + , /* NBL3 */ + + , /* A15-BA1 */ + , /* A14-BA0 */ + , /* A13 */ + , /* A12 */ + , /* A11 */ + , /* A10 */ + , /* A09 */ + , /* A08 */ + , /* A07 */ + , /* A06 */ + , /* A05 */ + , /* A04 */ + , /* A03 */ + , /* A02 */ + , /* A01 */ + , /* A00 */ + + , /* SDNE0 */ + , /* SDNWE */ + , /* SDNRAS */ + , /* SDNCAS */ + , /* SDCKE0 */ + ; /* SDCLK> */ + slew-rate = <2>; + u-boot,dm-pre-reloc; + }; + }; +};