From: Szabolcs Nagy <nsz@port70.net>
Date: Sun, 24 Jan 2016 20:51:34 +0000 (+0000)
Subject: fix aarch64 atomics to load/store 32bit only
X-Git-Tag: v1.1.13~69
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=2d14fa39b0e3c957ad4f7def033e40ea431ffcfb;p=oweals%2Fmusl.git

fix aarch64 atomics to load/store 32bit only

a_ll/a_sc inline asm used 64bit register operands (%0) instead of 32bit
ones (%w0), this at least broke a_and_64 (which always cleared the top
32bit, leaking memory in malloc).
---

diff --git a/arch/aarch64/atomic_arch.h b/arch/aarch64/atomic_arch.h
index 14fea03b..6b4f1a4d 100644
--- a/arch/aarch64/atomic_arch.h
+++ b/arch/aarch64/atomic_arch.h
@@ -2,7 +2,7 @@
 static inline int a_ll(volatile int *p)
 {
 	int v;
-	__asm__ __volatile__ ("ldaxr %0, %1" : "=r"(v) : "Q"(*p));
+	__asm__ __volatile__ ("ldaxr %w0,%1" : "=r"(v) : "Q"(*p));
 	return v;
 }
 
@@ -10,7 +10,7 @@ static inline int a_ll(volatile int *p)
 static inline int a_sc(volatile int *p, int v)
 {
 	int r;
-	__asm__ __volatile__ ("stlxr %w0,%1,%2" : "=&r"(r) : "r"(v), "Q"(*p) : "memory");
+	__asm__ __volatile__ ("stlxr %w0,%w1,%2" : "=&r"(r) : "r"(v), "Q"(*p) : "memory");
 	return !r;
 }