From: Baruch Siach <baruch@tkos.co.il>
Date: Sun, 11 Nov 2018 10:31:04 +0000 (+0200)
Subject: arm64: mvebu: a8k: autodetect RAM size
X-Git-Tag: v2019.01-rc1~29^2~2
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=2b4d964718c0e78a24f3a5e051e7dd9bc0e547c2;p=oweals%2Fu-boot.git

arm64: mvebu: a8k: autodetect RAM size

Some Armada 8K boards like Macchiatobin and Clearfog GT-8K use RAM from
external DIMM. Hard coding the RAM size in the device-tree is not
convenient. Fortunately, the ATF that initializes the RAM knows the size
of RAM, and U-Boot can query the ATF using a SMC call.

The ATF maps the lower 3G of RAM starting at address 0. Higher RAM is
mapped at 4G. This leaves a 1G hole between 3G and 4G for IO
peripherals. Use a second bi_dram[] entry to describe the higher RAM
area. As a result, CONFIG_NR_DRAM_BANKS must be set to 2 to use more
than 3GB RAM.

This code in this commit is mostly taken from downstream Marvell U-Boot
code by Grzegorz Jaszczyk.

Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index f47273fde9..47bbf69944 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -7,6 +7,7 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <linux/libfdt.h>
+#include <linux/sizes.h>
 #include <pci.h>
 #include <asm/io.h>
 #include <asm/system.h>
@@ -45,15 +46,62 @@ const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
 
 /* DRAM init code ... */
 
+#define MV_SIP_DRAM_SIZE	0x82000010
+
+static u64 a8k_dram_scan_ap_sz(void)
+{
+	struct pt_regs pregs;
+
+	pregs.regs[0] = MV_SIP_DRAM_SIZE;
+	pregs.regs[1] = SOC_REGS_PHY_BASE;
+	smc_call(&pregs);
+
+	return pregs.regs[0];
+}
+
+static void a8k_dram_init_banksize(void)
+{
+	/*
+	 * The firmware (ATF) leaves a 1G whole above the 3G mark for IO
+	 * devices. Higher RAM is mapped at 4G.
+	 *
+	 * Config 2 DRAM banks:
+	 * Bank 0 - max size 4G - 1G
+	 * Bank 1 - ram size - 4G + 1G
+	 */
+	phys_size_t max_bank0_size = SZ_4G - SZ_1G;
+
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size <= max_bank0_size) {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+		return;
+	}
+
+	gd->bd->bi_dram[0].size = max_bank0_size;
+	if (CONFIG_NR_DRAM_BANKS > 1) {
+		gd->bd->bi_dram[1].start = SZ_4G;
+		gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
+	}
+}
+
 int dram_init_banksize(void)
 {
-	fdtdec_setup_memory_banksize();
+	if (CONFIG_IS_ENABLED(ARMADA_8K))
+		a8k_dram_init_banksize();
+	else
+		fdtdec_setup_memory_banksize();
 
 	return 0;
 }
 
 int dram_init(void)
 {
+	if (CONFIG_IS_ENABLED(ARMADA_8K)) {
+		gd->ram_size = a8k_dram_scan_ap_sz();
+		if (gd->ram_size != 0)
+			return 0;
+	}
+
 	if (fdtdec_setup_mem_size_base() != 0)
 		return -EINVAL;