From: Tobias Doerffel Date: Fri, 8 Jul 2016 10:40:14 +0000 (+0200) Subject: sunxi: mmc: increase status register polling rate for data transfers X-Git-Tag: v2016.09-rc1~80^2~22 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=26c0c15786039fb437925c08205702169462e343;p=oweals%2Fu-boot.git sunxi: mmc: increase status register polling rate for data transfers With a recent bunch of SD3.0 cards in our A20-based board we experienced data transfer rates of about 250 KiB/s instead of 10 MiB/s with previous cards from the same vendor (both 4 GB/class 10). By increasing status register polling rate from 1 kHz to 1 MHz we were able to reach the original transfer rates again. With the old cards we now even reach about 16 MiB/s. Signed-off-by: Tobias Doerffel Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index ce2dc4ae41..3be9a90a6b 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -269,18 +269,18 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) unsigned i; unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); unsigned byte_cnt = data->blocksize * data->blocks; - unsigned timeout_msecs = byte_cnt >> 8; - if (timeout_msecs < 2000) - timeout_msecs = 2000; + unsigned timeout_usecs = (byte_cnt >> 8) * 1000; + if (timeout_usecs < 2000000) + timeout_usecs = 2000000; /* Always read / write data through the CPU */ setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); for (i = 0; i < (byte_cnt >> 2); i++) { while (readl(&mmchost->reg->status) & status_bit) { - if (!timeout_msecs--) + if (!timeout_usecs--) return -1; - udelay(1000); + udelay(1); } if (reading)