From: Piotr Dymacz Date: Mon, 12 Aug 2013 22:40:49 +0000 (+0200) Subject: Initial code commit X-Git-Tag: 2013-08-19~6 X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=23eda4af4cb09d14c1649e1a7f3c19b6a2b29788;p=oweals%2Fu-boot_mod.git Initial code commit --- diff --git a/Makefile b/Makefile new file mode 100755 index 0000000..7701505 --- /dev/null +++ b/Makefile @@ -0,0 +1,119 @@ +export BUILD_TOPDIR=$(PWD) +export STAGING_DIR=$(BUILD_TOPDIR)/tmp + +export MAKECMD=make --silent ARCH=mips CROSS_COMPILE=mips-linux-gnu- + +# boot delay (time to autostart boot command) +export CONFIG_BOOTDELAY=1 + +mr3020: export UBOOT_FILE_NAME=uboot_for_tl-mr3020 +mr3020: export MAX_UBOOT_SIZE=64 +mr3020: export COMPRESSED_UBOOT=1 +mr3020: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) mr3020_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +wr703n: export UBOOT_FILE_NAME=uboot_for_tl-wr703n +wr703n: export MAX_UBOOT_SIZE=64 +wr703n: export COMPRESSED_UBOOT=1 +wr703n: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr703n_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +wr720n_v3_CH: export UBOOT_FILE_NAME=uboot_for_tl-wr720n_v3_CH +wr720n_v3_CH: export MAX_UBOOT_SIZE=64 +wr720n_v3_CH: export COMPRESSED_UBOOT=1 +wr720n_v3_CH: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr720n_v3_CH_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +wr710n: export UBOOT_FILE_NAME=uboot_for_tl-wr710n +wr710n: export MAX_UBOOT_SIZE=64 +wr710n: export COMPRESSED_UBOOT=1 +wr710n: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr710n_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +mr3040: export UBOOT_FILE_NAME=uboot_for_tl-mr3040 +mr3040: export MAX_UBOOT_SIZE=64 +mr3040: export COMPRESSED_UBOOT=1 +mr3040: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) mr3040_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +mr10u: export UBOOT_FILE_NAME=uboot_for_tl-mr10u +mr10u: export MAX_UBOOT_SIZE=64 +mr10u: export COMPRESSED_UBOOT=1 +mr10u: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) mr10u_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +wr740n_v4: export UBOOT_FILE_NAME=uboot_for_tl-wr740n_v4 +wr740n_v4: export MAX_UBOOT_SIZE=64 +wr740n_v4: export COMPRESSED_UBOOT=1 +wr740n_v4: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) wr740n_v4_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +mr3220_v2: export UBOOT_FILE_NAME=uboot_for_tl-mr3220_v2 +mr3220_v2: export MAX_UBOOT_SIZE=64 +mr3220_v2: export COMPRESSED_UBOOT=1 +mr3220_v2: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) mr3220_v2_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +wdr3600_43x0: export UBOOT_FILE_NAME=uboot_for_tl-wdr3600-43x0 +wdr3600_43x0: export MAX_UBOOT_SIZE=64 +wdr3600_43x0: export COMPRESSED_UBOOT=1 +wdr3600_43x0: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) db12x_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/tuboot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +carambola2: export UBOOT_FILE_NAME=uboot_for_carambola2 +carambola2: export MAX_UBOOT_SIZE=256 +carambola2: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) carambola2_config + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) ENDIANNESS=-EB V=1 all + @cp $(BUILD_TOPDIR)/u-boot/u-boot.bin $(BUILD_TOPDIR)/bin/temp.bin + @make show_size + +show_size: + @echo -e "\n======= Preparing $(MAX_UBOOT_SIZE)KB file filled with 0xFF... =======" + @`tr "\000" "\377" < /dev/zero | dd ibs=1k count=$(MAX_UBOOT_SIZE) of=$(BUILD_TOPDIR)/bin/$(UBOOT_FILE_NAME).bin` + @echo -e "\n======= Copying U-Boot image... =======" + @`dd if=$(BUILD_TOPDIR)/bin/temp.bin of=$(BUILD_TOPDIR)/bin/$(UBOOT_FILE_NAME).bin conv=notrunc` + @`rm $(BUILD_TOPDIR)/bin/temp.bin` + @echo -e "\n======= U-Boot image ready, size:" `wc -c < $(BUILD_TOPDIR)/bin/$(UBOOT_FILE_NAME).bin`" bytes =======\n" + @`md5sum $(BUILD_TOPDIR)/bin/$(UBOOT_FILE_NAME).bin | awk '{print $$1}' | tr -d '\n' > $(BUILD_TOPDIR)/bin/$(UBOOT_FILE_NAME).md5` + @`echo ' *'$(UBOOT_FILE_NAME).bin >> $(BUILD_TOPDIR)/bin/$(UBOOT_FILE_NAME).md5` + @if [ "`wc -c < $(BUILD_TOPDIR)/bin/$(UBOOT_FILE_NAME).bin`" -gt "`echo '$(MAX_UBOOT_SIZE)*1024' | bc`" ]; then \ + echo -e "\n **********************************"; \ + echo " * U-BOOT IMAGE SIZE TOO BIG! *"; \ + echo -e " **********************************\n"; \ + fi; + +clean: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) clean + @rm -f $(BUILD_TOPDIR)/bin/* + +clean_all: + @cd $(BUILD_TOPDIR)/u-boot/ && $(MAKECMD) distclean + @rm -f $(BUILD_TOPDIR)/bin/* diff --git a/host_util/lzma b/host_util/lzma new file mode 100755 index 0000000..ac81e12 Binary files /dev/null and b/host_util/lzma differ diff --git a/u-boot/CHANGELOG b/u-boot/CHANGELOG new file mode 100755 index 0000000..b6e289e --- /dev/null +++ b/u-boot/CHANGELOG @@ -0,0 +1,4879 @@ +====================================================================== +Changes since U-Boot 1.1.4: +====================================================================== + +* Fix Lite5200B support: initialize SDelay register + See Freescale's AN3221 "MPC5200B SDRAM Initialization and + Configuration", 3.3.1 SDelay--MBAR + 0x0190 + +* Changes/fixes for drivers/cfi_flash.c: + + - Add Intel legacy lock/unlock support to common CFI driver + + On some Intel flash's (e.g. Intel J3) legacy unlocking is + supported, meaning that unlocking of one sector will unlock + all sectors of this bank. Using this feature, unlocking + of all sectors upon startup (via env var "unlock=yes") will + get much faster. + + - Fixed problem with multiple reads of envronment variable + "unlock" as pointed out by Reinhard Arlt & Anders Larsen. + + - Removed unwanted linefeeds from "protect" command when + CFG_FLASH_PROTECTION is enabled. + + - Changed p3p400 board to use CFG_FLASH_PROTECTION + + Patch by Stefan Roese, 01 Apr 2006 + +* Changes/fixes for drivers/cfi_flash.c: + - Correctly handle the cases where CFG_HZ != 1000 (several + XScale-based boards) + - Fix the timeout calculation of buffered writes (off by a + factor of 1000) + Patch by Anders Larsen, 31 Mar 2006 + +* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) + + 405 SDRAM: - The SDRAM parameters can now be defined in the board + config file and the 405 SDRAM controller values will + be calculated upon bootup (see PPChameleonEVB). + When those settings are not defined in the board + config file, the register setup will be as it is now, + so this implementation should not break any current + design using this code. + + Thanks to Andrea Marson from DAVE for this patch. + + 440 DDR: - Added function sdram_tr1_set to auto calculate the + TR1 value for the DDR. + - Added ECC support (see p3p440). + + Patch by Stefan Roese, 17 Mar 2006 + +* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S + Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473] + +* Add support for ymodem protocol download + Patch by Stefano Babic, 29 Mar 2006 + +* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000 + Merge from Markus Klotzbücher's repo, 01 Apr 2006 + +* GCC-4.x fixes: clean up global data pointer initialization for all + boards + +* Update for Delta board: + - redundant NAND environment + - misc Monahans cleanups (remove dead code etc.) + - DA9030 Initialization; some minimal changes to PXA I2C driver to + make it work with the Monahans. + - Make Monahans clock frequency configurable using + CFG_MONAHANS_RUN_MODE_OSC_RATIO and + CFG_MONAHANS_TURBO_RUN_MODE_RATIO. + Merge from Markus Klotzbücher's repo, 25 Mar 2006 + +* Enable Quad UART om MCC200 board. + +* Cleanup MCC200 board configuration; omit non-existent stuff. + +* Add support for MPC859/866 Rev. A.0 + +* Add command for handling DDR ECC registers on MPC8349EE MDS board. + +* Fix DDR ECC bit definitions for MPC83xx. + +* Add initial support for MPC8349E MDS board. + +* Add support for ECC DDR initialization on MPC83xx. + +* Add DMA support for MPC83xx. + +* Add sync in do_reset() routine for MPC83xx after RPR register + was written to. It is need on some targets when BAT translation + is enabled. + +* Add bit definitions for MPC83xx DDR controller registers. + +* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx. + +* Correct shift offsets in icache_status and dcache_status for MPC83xx. + +* Add support for DS1374 RTC chip. + +* Add support for Lite5200B board. + Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006 + +* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific + timer and cpu_reset code from cpu/$(CPU) into the new + cpu/$(CPU)/$(SOC) directories + Patch by Andreas Engel, 13 Mar 2006 + +* Change max size of uncompressed uImage's to 8MByte and add + CFG_BOOTM_LEN to adjust this setting. + + As mentioned by Robin Getz on 2005-05-24 the size of uncompressed + uImages was restricted to 4MBytes. This default size is now + increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN + in the board config file. + + Patch by Stefan Roese, 13 Mar 2006 + +* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c + Patch by Stefan Roese, 13 Mar 2006 + +* cpu/ppc4xx/start.S : exceptions are enabled after relocation + Patch by Cedric Vincent, 06 Jul 2005 + +* au1x00_eth.c: check malloc return value and abort if it failed + Patch by Andrew Dyer, 26 Jul 2005 + +* Change the sequence of events in soft_i2c.c:send_ack() to keep from + incorrectly generating start/stop conditions on the bus. + Patch by Andrew Dyer, 26 Jul 2005 + +* Fix bug in [id]cache_status commands for MPC85xx processors; + should look at LSB of L1CSRn registers to determine if L1 cache is + enabled, not the MSB. + Patch by Murray Jensen, 19 Jul 2005 + +* Fix array overflow with fw_setenv on uninitialised environment + Patch by Murray Jensen, 15 Jul 2005 + +* Add support for EmbeddedPlanet EP88x boards + Patch by Yuli Barcohen, 13 Jul 2005 + +* Remove board specific configuration includes from the common xilinx + ethernet and iic adapter code. + Patch by Michael Libeskind, 12 Jul 2005 + +* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver + Patch by Murray Jensen, 08 Jul 2005 + +* Add (some) definitions for the MPC85xx local bus controller + Patch by Murray Jensen, 08 Jul 2005 + +* Add CPM2 I/O pin functions for MPC85xx processors + Patch by Murray Jensen, 08 Jul 2005 + +* Fix compile problem + +* Added PCI support for MPC8349ADS board + Patch by Kumar Gala 11 Jan 2006 + +* Enable address translation on MPC83xx + Patch by Kumar Gala, 10 Feb 2006 + +* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx + Patch by Kumar Gala, 25 Jan 2006 + +* Fixed defines for MPC83xx SICRL register to match current specs + Patch by Kumar Gala, 23 Jan 2006 + +* Only disable the MPC83xx watchdog if its enabled out of reset. + If its disabled out of reset SW can later enable it if so desired + Patch by Kumar Gala, 11 Jan 2006 + +* Allow config of GPIO direction & data registers at boot on 83xx + Patch by Kumar Gala, 11 Jan 2006 + +* Enable time handling on 83xx + Patch by Kumar Gala, 11 Jan 2006 + +* Make System IO Config Registers board configurable on MPC83xx + Patch by Kumar Gala, 11 Jan 2006 + +* Fixed PCI indirect config ops to handle multiple PCI controllers + We need to adjust the bus number we are trying to access based + on which PCI controller its on + Patch by Kumar Gala, 12 Jan 2006 + +* Report back PCI bus when doing table based device config + Patch by Kumar Gala, 11 Jan 2006 + +* Added support for PCI prefetchable region and BARs + If a host controller sets up a region as prefetchable and + a device's BAR denotes it as prefetchable, allocate the + BAR into the prefetch region. + + If a BAR is prefetchable and no prefetchable region has + been setup by the controller we fall back to allocating + the BAR into the normally memory region. + Patch by Kumar Gala, 11 Jan 2006 + +* Add helper function for generic flat device tree fixups for mpc83xx + Patch by Kumar Gala, 11 Jan 2006 + +* Add support for passing initrd information via flat device tree + Patch by Kumar Gala, 11 Jan 2006 + +* Added OF_STDOUT_PATH and OF_SOC + + OF_STDOUT_PATH specifies the path to the device the kernel can use + for console output + + OF_SOC specifies the proper name of the SOC node if one exists. + Patch by Kumar Gala, 11 Jan 2006 + +* Allow board code to fixup the flat device tree before booting a kernel + Patch by Kumar Gala, 11 Jan 2006 + +* Added CONFIG_ options for bd_t and env in flat dev tree + + CONFIG_OF_HAS_BD_T will put a copy of the bd_t + into the resulting flat device tree. + + CONFIG_OF_HAS_UBOOT_ENV will copy the environment + variables from u-boot into the flat device tree + + Patch by Kumar Gala, 11 Jan 2006 + +* Add support for the DHCP vendor optional bootfile (#67). + Ignores the vendor TFTP server name option (#66). + Patch by Murray Jensen, 30 Jun 2005 + +* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode + Patch by Andy Fleming, 14 Jun 2005 + +* Fix bad register definitions for LTX971 PHY on MPC85xx boards. + Patch by Gerhard Jaeger, 21 Jun 2005 + +* Add netconsole and some more commands to RPXlite_DW board + Patch by Sam Song, 19 Jun 2005 + +* Fix bad declaration on pci_cfgfunc_nothing + Patch by Sam Song, 19 Jun 2005 + +* Adjust "echo" as a default command + Patch by Sam Song, 19 Jun 2005 + +* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC + Patch by KokHow Teh, 16 Jun 2005 + +* Add crc of data to jffs2 (in jffs2_1pass_build_lists()). + Patch by Rick Bronson, 15 Jun 2005 + +* Coding Style cleanup + +* Avoid dereferencing NULL in find_cmd() if no valid commands were found + Patch by Andrew Dyer, 13 Jun 2005 + +* Add ADI Blackfin support + - add support for Analog Devices Blackfin BF533 CPU + - add support for the ADI BF533 Stamp uClinux board + - add support for the ADI BF533 EZKit board + Patches by Richard Klingler, 11 Jun 2005 + +* Add loads of ntohl() in image header handling + Patch by Steven Scholz, 10 Jun 2005 + +* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment + variable to set clock + Patch by Yuli Barcohen, 05 Jun 2005 + +* RPXlite configuration fixes + - Use correct flash sector size + - Use correct memory test end address + - Add support for bzip2 compression + - Various small fixes + Patch by Yuli Barcohen, 05 Jun 2005 + +* Memory configuration changes for ZPC.1900 board + - Fix SDRAM timing on both local bus and 60x bus + - Add support for second flash bank (SIMM) + - Change boot flash base + Patch by Yuli Barcohen, 05 Jun 2005 + +* Add support for Adder boards with 16MB SDRAM; + add support for second FEC on Adder87x board. + Patch by Yuli Barcohen, 05 Jun 2005 + +* Fix conditional for including ks8695eth driver + Patch by Greg Ungerer, 04 Jun 2005 + +* Fix Makefile: include config.mk only after CROSS_COMPILE is defined + Patch by Friedrich Lobenstock, 02 Jun 2005 + +* Fix comment in common/soft_i2c.c + Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005 + +* Cleanup compiler warnings. + Patch by Greg Ungerer, 21 May 2005 + +* Word alignment fixes for word aligned NS16550 UART + Patch by Jean-Paul Saman, 01 Mar 2005 + + Fixes bug with UART that only supports word aligned access: removed + "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some + (broken!) versions of GCC generate byte accesses when encountering + the packed attribute regardless if the struct is already correctly + aligned for a platform. Peripherals that can only handle word + aligned access won't work properly when accessed with byte access. + The struct NS16550 is already word aligned for REG_SIZE = 4, so + there is no need to packed the struct in that case. + +* Fix behaviour if gatewayip is not set + Patch by Robin Gilks, 23 Dec 2004 + +* Fix cleanup for netstart board. + Remove build results from repository + +* Some code cleanup for GCC 4.x + +* Fixes to support environment in NAND flash; + enable NAND flash based environment for delta board. + +* Add support for Intel Monahans CPU on Zylonite and Delta boards + (This is Work in Progress!) + +* Add support for TQM8260-AI boards. + +* Minor code cleanup + +* Merge the new NAND code (testing-NAND brach); see doc/README.nand + Rewrite of NAND code based on what is in 2.6.12 Linux kernel + Patch by Ladislav Michl, 29 Jun 2005 + +* Add lowboot target to mcc200 board + Patch by Stefan Roese, 4 Mar 2006 + +* Fix problem with flash_get_size() from CFI driver update + Patch by Stefan Roese, 1 Mar 2006 + +* Make CFG_NO_FLASH work on ARM systems + Patch by Markus Klotzbuecher, 27 Feb 2006 + +* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock, + use hush shell. + +* Convert mcc200 to use common CFI flash driver + Patch by Stefan Roese, 28 Feb 2006 + +* Add env-variable "unlock" to handle initial state of sectors + (locked/unlocked). + + Only the U-Boot image and it's environment is protected, + all other sectors are unprotected (unlocked) if flash + hardware protection is used (CFG_FLASH_PROTECTION) and + the environment variable "unlock" is set to "yes". + + Patch by Stefan Roese, 28 Feb 2006 + +* Update drivers/cfi_flash.c: + - find_sector() called in both versions of flash_write_cfiword() + Patch by Peter Pearse, 27th Feb 2006 + +* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode + Patch by Jose Maria Lopez, 16 Jan 2006 + +* Add support for AMD/Spansion Flashes in flash_write_cfibuffer + Patch by Alex Bastos and Thomas Schaefer, 2005-08-29 + +* Changes/fixes for drivers/cfi_flash.c: + We *should* check if there are any error bits if the previous call + returned ERR_OK (Otherwise we will have output an error message in + flash_status_check() already.) The original code would only check for + error bits if flash_status_check() returns ERR_TIMEOUT. + Patch by Marcus Hall, 23 Aug 2005 + +* Changes/fixes for drivers/cfi_flash.c: + - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c + - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c + Patch by Sangmoon Kim, 19 Aug 2005 + +* Fixes for drivers/cfi_flash.c: + - Fix wrong timeout value usage in flash_status_check() + - Round write_tout up when converting to msec in flash_get_size() + - Remove clearing flash status at the end of flash_write_cfibuffer() + which sets Intel 28F640J3 flash back to command mode on CSB472 + Patch by Tolunay Orkun, 02 July 2005 + +* Add basic support for the SMMACO4 Board from PanDaCom. + Patch by Heiko Schocher, 20 Feb 2006 + +* Add GIT version information (commid ID) to untagged U-Boot versions + + As done in the linux kernel, the U-Boot version (U_BOOT_VERSION) + of all unreleased (untagged) U-Boot images will be automatically + extended upon compiletime with a part of the GIT commit ID and + possibly with "dirty" if uncommited changes are detected. + + Here an example for the resulting version: + "U-Boot 1.1.4-g3457ac18-dirty" + + The version is now maintained in the toplevel Makefile and the + version headers are autogenerated. + + Patch by Stefan Roese, 9 Feb 2006 + +* Update default environment for INKA4x00 board. + +* Convert CPCI750 to use common CFI flash driver + Patch by Reinhard Arlt, 8 Feb 2006 + +* Various changes to esd HH405 board specific files + Patch by Matthias Fuchs, 07 Feb 2006 + +* Cleanup U-Boot boot messages on ARM. + + To match the U-Boot user interface on ARM platforms to the U-Boot + standard (as on PPC platforms), some messages with debug character + are removed from the default U-Boot build. + Enable DEBUG for lib_arm/board.c to enable debug messages. + New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options. + Patch by Stefan Roese, 24 Jan 2006 + +* Fix various compiler warnings on ppc4xx builds (ELDK 4.0) + Patch by Stefan Roese, 18 Jan 2006 + +* Add VGA support (CT69000) to CPCI750 board. + Insert missing __le32_to_cpu() for filesize in ext2fs_read_file(). + Patch by Reinhard Arlt, 30 Dec 2005 + +* PMC405 and CPCI405: Moved configuration of pci resources + into config file. + PMC405 and CPCI2DP: Added firmware download and booting via pci. + Patch by Matthias Fuchs, 20 Dec 2005 + +* Fix 28F256J3A support on PM520 board + (without bank-switching only 32 MB can be accessed) + +* Fix mkimage bug with multifile images created on 64 bit systems. + +* Add support for 28F256J3A flash (=> 64 MB) on PM520 board + +* Fix compiler problem with at91rm9200dk board. + Patch by Eugen Bigz, 19 Dec 2005 + +====================================================================== +Changes for U-Boot 1.1.4: +====================================================================== + +* Changes to Yellowstone & Yosemite 440EP/GR eval boards: + - Changed GPIO setup to enable another address line in order to + address 64M of FLASH. + - Added function sdram_tr1_set to auto calculate the tr1 value for + the DDR. + Patch by Steven Blakeslee, 12 Dec 2005 + +* MPC5200: Set PCI retry counter to 0 = infinite retry; + The default of 255 is too short for slow devices. + Patch by Martin Nykodym, 12 Dec 2005 + +* Change port configuration for O2DNT (CODEC1 on PSC1). + +* Fix register for PCI async mode on PPC440EP + Patch by Youngchul Bang, 08 Dec 2005 + +* Fix U-Boot linking problems (add .eh_frame segment to linker script) + This segment may be required by some libgcc.a functions + (like _udivdi3). + +* Fix DPRAM offset/size for MPC8541/8555. + Simplify TQM85xx Makefile handling. + +* Fix data overflow (typo?) in rtc/ds1302.c + +* Fix U-Boot compilation for MIPS boards using ELDK 4.0 + +* Add support for TQM8541/8555 boards, TQM85xx support reworked: + - Support for TQM8541/8555 boards added. + - Complete rework of TQM8540/8560 support. + - Common TQM85xx code now supports all current TQM85xx platforms + (TQM8540/8541/8555/8560). + - DDR SDRAM size detection added. + - CAS latency default values can be overwritten by setting "serial#" + to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used. + If problems are detected with this non default CAS latency, + the default values will be used instead. + - Flash size detection added. + - Moved FCC ethernet driver initialization behind TSEC driver init + -> TSEC is first device. + Patch by Stefan Roese, 30 Nov 2005 + +* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. + Patch by John Otken, 23 Nov 2005 + +* Changed PPC44x startup message (cpu info, speed...) to common style: + On PPC44x platforms, the startup message generated in "cpu.c" only + comprised the ppc type and revision but not additional information + like speed etc. Those speed infos where printed in the board specific + code. This new implementation now prints all CPU infos in the common + cpu specific code. No board specific code is needed anymore and + therefore removed from all current 44x implementations. + Patch by Stefan Roese, 27 Nov 2005 + +* Adjust TQM834x PHY addresses for latest hardware revision. + +* Increase malloc arena on TQM5200 board to 256 kB. + With 64 kb uniform flash sector size the old value of 128 kB was + too small. + +* Fix miiphy global data initialization (problem on 4xx boards when + no ethaddr is assigned). Initialization moved from + miiphy_register() to eth_initialize(). + + Based on initial patch for 4xx platform by Matthias Fuchs. + +* Remove unnnecessary #include from include/asm-*/u-boot.h + +* Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code. + The COPYING file was extended to make clear that these files can be + used in non-GPL code, too. + Also, a corresponding note was placed in the headers of the affected files. + +* Add support for Prodrive P3P440 board: + - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c + - CFG_FLASH_QUIET_TEST added to use the common CFI driver + for bank autodetection + Patch by Stefan Roese, 22 Nov 2005 + +* Change all '$(...)' variable references into '${...}' + which makes the environment compatible with the hush shell. + WARNING: Support for the old '$(...)' syntax will be + discontinued in a later version. + +* Minor changes to init flags in TQM834x PCI. + +* Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM) + Patch by Stefan Roese, 15 Nov 2005 + +* New PPC 405EP board added: CMS700 + Added CONFIG_NET_MULTI for VOM405 board. + Added reset_phy() for VOM405 board. + Patch by Matthias Fuchs, 09 Nov 2005 + +* Updated PCI mapping for esd CPCI2DP board. + Add support for error LED. + Patch by Matthias Fuchs, 07 Nov 2005 + +* Fix MPC85xx PCI support (pci_register_hose() before pci config access) + Patch by Stefan Roese, 07 Nov 2005 + +* Correct PPC Timebase register definitions (SPRN_TBRL...) + Patch by Stefan Roese, 07 Nov 2005 + +* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size + Patch by Stefan Roese, 05 Nov 2005 + +* Additional fix for external IRQ config on Yellowstone & Yosemite + Patch by Stefan Roese, 03 Nov 2005 + +* Add support for Ocotea pass 3 with 440GX Rev. F + Patch by Stefan Roese, 01 Nov 2005 + +* Fix external IRQ configuration on Yellowstone & Yosemite + Patch by Stefan Roese, 28 Oct 2005 + +* Add support for multiple PHYs. + Tested on the following boards: + cmcpu2 (at91rm9200/ether.c) + PPChameleon (ppc4xx/4xx_enet.c) + yukon (mpc8220/fec.c) + uc100 (mpc8xx/fec.c) + tqm834x (mpc834x/tsec.c) with EEPRO100 + lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c) + Main changes include: + common/miiphyutil.c + - miiphy_register routine was added to allow multiple PHYs to be registered + - miiphy_read and miiphy_write are now defined in this file, and + require additional argument (char *devname) + - other miiphy_* routines also require additional device name argument + ../lib_i386/board.c + ../lib_ppc/board.c + Calling reset_phy() was moved to be executed *after* eth_initialize(). + This is necessary as now some of the implementations of reset_phy() + may need to use miiphy_reset() which is not allowed before eth_initialize() + as eth_initialize registers all required miiphy_* routines. + Tested on IP860 and PHY initializes properly after this change. + +* Correct includes for flat tree builder. + +* Fix conflicting types (flash_write()) in trab auto_update.c. + +* Add PCI support for the TQM834x board. + +* Add missing 4xx board to MAKEALL + Patch by Stefan Roese, 20 Oct 2005 + +* Fix conflicting types (flash_write()) in esd auto_update.c + Patch by Stefan Roese, 20 Oct 2005 + +* Fix problem with sleep in NetConsole (use get_timer()) + Patch by Stefan Roese, 20 Oct 2005 + +* Add NetConsole Support for AMCC eval boards + Patch by Stefan Roese, 20 Oct 2005 + +* Fix NetConsole support on 4xx (only print eth link on 1st transfer) + Patch by Stefan Roese, 18 Oct 2005 + +* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo. + Fix identation on ext2ls help entry. + Patch by Stefan Roese, 14 Oct 2005 + +* Add support for TQM834x boards. + Cleanup. + +* Cleanup for GCC-4.x + +* Add documentation for Open Firmware Flat Tree and usage. + Patch by Pantelis Antoniou, 13 Oct 2005 + +* Add missing files for Pantelis Antoniou's patch + Patch by Pantelis Antoniou, 04 Sep 2005 + +* Fix problem in ppc4xx eth-driver without ethaddr (only without + CONFIG_NET_MULTI set) + Patch by Stefan Roese, 10 Oct 2005 + +* Fix gzip bmp support (test if malloc fails, warning when truncated). + Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board. + Patch by Stefan Roese, 07 Oct 2005 + +* Add support for OF flat tree for the STXtc board. + Patch by Pantelis Antoniou, 04 Sep 2005 + +* Support passing of OF flat trees to the kernel. + Patch by Pantelis Antoniou, 04 Sep 2005 + +* Cleanup + +* Add support for NetSilicon NS7520 processor. + Patch by Art Shipkowski, 12 May 2005 + +* Add support for AP1000 board. + Patch by James MacAulay, 07 Oct 2005 + +* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200 + Patch by Anders Larsen, 07 Oct 2005 + + The Atmel errata #11 states that the transfer buffer descriptor + table must be aligned on a 16-word boundary. As it turned out, this + is insufficient - it seems the table must be aligned on a boundary + at least as large as the table itself (in Linux this is not an + issue - the table is aligned on a PAGE_SIZE (4096) boundary). + +* Fixed compilation for ARM when using a (standard) hard-FP toolchain + Patch by Anders Larsen, 07 Oct 2005 + +* Cleanup warnings for cpu/arm720t & cpu/arm1136 files. + sed the linker scripts, rather than pre-process them. + Patch by Peter Pearse, 07 Oct 2005 + +* Update make target for ARM supported boards. + Use lowlevel_init() instead of platformsetup() [rename]. + Patch by Peter Pearse, 06 Oct 2005 + +* Fix booting from serial dataflash on AT91RM9200 + Patch by Peter Menzebach, 29 Aug 2005 + +* Add JFFS2 support for TRAB board + Patch by Martin Krause, 25 Aug 2005 + +* Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI + Patch by Marcus Hall, 24 Aug 2005 + +* Fix the machine-id of the Cogent csb637 board + Patch by Anders Larsen, 05 Oct 2005 + +* Complete support for the KwikByte KB920x boards + Patch by Anders Larsen, 05 Oct 2005 + +* Set the AT91RM9200 clock to asynchronous mode + Patch by Anders Larsen, 03 May 2005 + +* Set the AT91RM9200 clock to synchronous mode + Patch by Anders Larsen, 29 Apr 2005 + +* Add support for Cogent csb637 + Patch by Anders Larsen, 29 Apr 2005 + +* Fix dm9161.c initialization + Patch by Anders Larsen, 29 Apr 2005 + +* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005 + (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5) + +* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200 + Patch by Anders Larsen, 29 Apr 2005 + +* Fix device partition intialization for SystemACE disks. + Patch by Stephen Williams, 28 Apr 2005 + +* Added support for KwikByte KB920x boards (based on AT91RM9200) + Patch by Matt ?? , 27 Apr 2005 + +* Add support for S29GL064M-R3 flash chip on xsengine board + Patch by Kurt Stremerch, 18 Apr 2005 + +* E500 update: repoint IVPR to RAM when code is relocated + Patch by Kylo Ginsberg, 13 Apr 2005 + +* Fix loop end test in lib_generic/string.c:strswab() + Patch by Andrew Dyer, October 10, 2005 + Signed-off-by: Andrew Dyer + +* Cleanup + +* Update ARM Integrator boards: + Correct addessing errors in platform files. + Split off common core module data from Integrator header files to + include/armcoremodule.h. + Patch by Peter Pearse, 04 Oct 2005 + +* Make sure only supported compiler options are used + Import "cc-option" shell function from kernel and + use it to get the correct ARM GCC options for individual CPUs + Patch by Peter Pearse, 30 Jun 2005 + +* Fix 440GR to print correct cpu revision + Patch by Stefan Roese, 04 Oct 2005 + +* Change board message on AMCC Yosemite & Yellowstone to common style + Patch by Stefan Roese, 03 Oct 2005 + +* Fix compiler warning + +* Fix FEC PHY addresses for TQM85xx boards + +* Fix uninitialized variable problem in hush shell + Patch by Lars Rostock, 26 Sep 2005 + +* Undo change of f6e20fc6ca... to include/configs/trab.h + (Must have been an accident?) + +* Add support for AT91RM9200 OHCI Controller. + Patch by Eric Benard, 07 Apr 2005 + +* Update ARM mach-types.h + Patch by Eric Benard, 07 Apr 2005 + +* Add support for MP2USB board. + Patch by Eric Benard, 07 Apr 2005 + +* Add board support for armadillo HT1070 + Patch by Rowel Atienza, 06 Apr 2005 + +* Second Ethernet address enabled for MPC885ADS and MPC8272ADS. + Patch by Vitaly Bordug, 30 Mar 2005 + +* Add iopset command on mpc8xx + Patch by Daniel Eisenhut, 25 Mar 2005 + +* Add support for MII in eepro100 driver. + Patch by Gleb Natapov, 21 Mar 2005 + +* Fixes to the Lubbock (PXA 25x) support: + - Resolve the FIXME with respect to saving the u-boot environment. + - Make the default load address land in real memory. + - Fix lan91c96 SMC_{in,out}{b,w,l}() macros + Patch by David Brownell, 10 Mar 2005 + +* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board + Patch by Marc Leeman, 04 Mar 2005 + +* OMAP242x H4 board update + - fix for ES2 differences. + - switch to using the cfi_flash driver. + - fix SRAM build address. + - fix for GP device operation. + - unlock SRAM for GP devices. + - display more device information. + - fix potential deadlock in omap24xx_i2c driver. + - fix DLL load values to match dpllout*1 operation. + - fix 2nd chip select init for combo DDR device. + - add support for CFI Intel 28F256L18 on H4 board. + Patch by Richard Woodruff, 03 Mar 2005 + +* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h + Patch by Steven Scholz, 02 Mar 2005 + +* Fix typo in eth.c + Patch by Ara Avanesyan, 24 Feb 2005 + +* Remove unneeded #include + Patch by Ladislav Michl, 22 Feb 2005 + +* Add cramfs support for m68k + Patch by Zachary Landau, 21 Feb 2005 + +* Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs + Patch by Jeff Angielski, 21 Feb 2005 + +* Fix au1x00_serial baud rate calculation: + remove hardcoded cpu clock divisor and use register instead; + round up instead of truncate + Patch by Andrew Dyer, 15 Feb 2005 + +* Add Xilinx Spartan3 family FPGA support + Patch by Kurt Stremerch, 14 Feb 2005 + +* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET + Patch by Zachary Landau, 11 Feb 2005 + +* Fix VOH405 Support + Patch by Matthias Fuchs, 25 Sep 2005 + +* Added support for PCI bridge on MPC8272ADS + Patch by Vitaly Bordug, Feb 09 2005 + +* Update multicore CM9XX support for Integrator AP to allow booting from flash + Patch by Jean-Paul Saman, 8 Feb 2005 + +* Fix strswab() to reliably find end of string + Patch by Andrew Dyer, 08 Feb 2005 + +* Fix typos in include/ppc440.h + Patch by Andrew E Mileski, 04 Feb 2005 + +* Add Vibren (was Accelent) PXA255 IDP Support + Patch by Cliff Brake, 04 Feb 2005 + +* Fix tools/bmp_logo.c using incorrect offset to pixel data + Patch by Andrew Dyer, 31 Jan 2005 + +* Add ARM946E cpu and core module targets; remap memory to 0x00000000 + Patch by Peter Pearse, 2 Feb 2005 + +* Fix error handling in tools/env/fw_env.c + Patch by Ara Avanesyan, 01 Feb 2005 + +* Fix MGT5100 PSC baudrate calculation + Patch by Sebastian Schau, 27 Jan 2005 + +* OMAP242x fix for GP device booting + - Add SRAM unlock for GP devices. + - Change DDR DLL unlock value to allow DPLLout*1 operation. + Patches by Richard Woodruff, 21 Jan 2005: + +* Add support for AMD's Pb1x00 eval board; + add MII routines to the au1x00 ethernet driver; + add USB ohci driver (work in progress) + Patch by Thomas Sailer, 20 Jan 2005 + +* Update omap5912osk board + Use drivers/cfi_flash.c instead of private flash driver; + Remove hardcoded personalized settings from omap5912osk.h; + Fix spacing with (RO) marks in 'flinfo' output. + Patch by Michael Bendzick, 14 Jan 2005 + +* Fix warnings for PCI code on ixp + Patch by Joe , 13 Jan 2005 + +* virtex2 fix for bogus download error messages + The virtex2 FPGA download code watches for init going active during + a download of config data as an error condition. init also goes + active after a configuration is finished in concert with the done + signal. So far, the code does not check for done active until all + of the configuration data is sent. If configuration data has a few + extra pad bytes at the end, this would cause an error message even + though the download had suceeded. + NOTE: virtex2 slave serial and spartan2 versions may still have the + same problem. + Patch by Andrew Dyer, 12 Jan 2005 + +* Optimize flash_make_cmd in drivers/cfi_flash.c for little endian + Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode" + message when probing for nonexistent flash in little endian mode. + As a side effect more efficient and smaller code is generated, + which is always a Good Thing (TM). + Patch by Ladislav Michl, 24 Sep 2005 + +* Update for TFTP using a fixed UDP port + Use the approved environment variable names. Added "tftpdstp" to + allow ports other than 69 per Tolunay Orkun's recommendation. + Patch by Jerry Van Baren, 12 Jan 2005 + +* Allow to force TFTP to use a fixed UDP port + (Add a configuration option CONFIG_TFTP_PORT and optional env + variable tftpport) + Patch by Jerry Van Baren, 10 Jan 2005 + +* Fix ethernet timeouts on dbau1550 and other au1x00 systems + Patch by Leif Lindholm, 29 Dec 2004 + +* Cleanup: fix broken builds + +* Fix PHY address argument passing with mii info command + Patch by Andrew Dyer, 28 Dec 2004 + +* Cleanup (PPC4xx is AMCC now) + +* esd CPCI2DP board added + Patch by Matthias Fuchs, 22 Sep 2005 + +* esd PMC405 board updated + Patch by Matthias Fuchs, 22 Sep 2005 + +* Add SM501 support to HH405 board. + Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP). + Add support for eeprom write-enable (CFG_EEPROM_WREN). + Patch by Stefan Roese, 22 Sep 2005 + +* Fix autonegotiation in tsec ethernet driver + Patch by Stefan Roese, 21 Sep 2005 + +* Fix bug in auto_update (trab board) + Patch by Martin Krause, 16 Sep 2005 + +* Fix computation of framebuffer palette for 8bpp LCD bitmaps + Patch by Francesco Mandracci, 16 Sep 2005 + +* Update configuration for INKA4x0 board + +* Update configuration for PM854 board + Based on patch by R. Loeffl, 20 Jul 2005 + +* Add PCI support to TQM8540 and TQM8560 boards + Patch by Stefan Roese, 15 Sep 2005 + +* Update AMCC Yosemite to get a consistent setup for all AMCC eval + boards (baudrate, environment...). Flash driver fixed. + Patch by Stefan Roese, 15 Sep 2005 + +* Fix problem in 440GP ethernet driver (ebony). Add support for 2nd + ethernet port on ebony. + Patch by Stefan Roese, 7 Sep 2005 + +* Added support for mtddevnum and mtddevname variables (mtdparts command) + +* Change default console baud rate for stxxtc board + +* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT). + Patch by Stefan Roese, 31 Aug 2005 + +* Fix default command set (don't include CFG_CMD_DISPLAY command) + Patch by Pantelis Antoniou, 02 Sep 2005 + +* Cleanup + +* Enable SM712 driver support for HMI1001 board. + +* Fix problems with ld version 2.16 (dot outside sections problem) + Pointed out by Gerhard Jaeger, 31 Aug 2005; + cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html + +* Prepare U-Boot for gcc-4.x: fix global data pointer initialization + +* Adjust CS3 timings on HMI1001 board for dot matrix display under Linux + +* Add keyboard and dot matrix display support for HMI1001 board. + +* Prepare U-Boot for gcc-4.x + +* Fixed Bamboo port to enable running without DDR-DIMM + (Bamboo has also 64MB onboard DDR) + Patch by Stefan Roese, 24 Aug 2005 + +* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c + now handling all 4xx cpu's + Patch by Stefan Roese, 16 Aug 2005 + +* Fix make dependencies for at91rm9200 and ks8695 cpus + Patch by Steven Scholz, 23 Aug 2005 + +* Add JFFS2 support for TQM5200 board + +* Add esd cpci5200 and pf5200 boards + Patch by Reinhard Arlt, 22 Aug 2005 + +* Fix sysclock for TQM8540 and TQM8560 boards + Patch by Martin Krause, 25 Jul 2005 + +* Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2 + Patch by Martin Krause, 08 Jun 2005 + +* Add new board specific commands for TQM5200/STK52XX + - Sound commands (beep, wav, sound) + - Test commands (led, can, backlight, rs232) + Patch by Martin Krause, 02 May 2005 + +* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz + because of a bug in the AT91RM9200 CPU PLL + Patch by Martin Krause, 22 Apr 2005 + +* Add automatic HW detection for another CMC_PU2 variant + Patch by Martin Krause, 20 Apr 2005 + +* Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration + Patch by Martin Krause, 19 Apr 2005 + +* Fix initialization problem on TQM5200 without SM501 + Patch by Martin Krause, 08 Apr 2005 + +* Add RTC support for STK52XX.200 + Patch by Martin Krause, 07 Apr 2005 + +* Add support for IFM o2dnt board + +* Enable PCI on hmi1001 board + +* Fix return values of the jffs2 commands ls/fsload/fsinfo, + so we can use them to, e.g., check the existence of a file with + "if ls foo; then this; else that; fi" in the hush shell + Patch by Andreas Engel, 16 August 2005 + +* Coding style cleanup + +* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board. + Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005 + +* Check return value of malloc in 440gx_enet.c + Patch by Travis B. Sawyer, 18 Jul 2005 + +* Add Sandburst Metrobox and Sandburst Karef board support packages. + Second serial port on 440GX now defined as a system device. + Add 'Short Etch' code for Cicada PHY within 440gx_enet.c + Patch by Travis B. Sawyer, 12 Jul 2005 + +====================================================================== +Changes for U-Boot 1.1.3: +====================================================================== + +* Minor code cleanup + +* Add forgotten new fils from latest VoiceBlue update + +* Make bootretry feature work with hush shell. + Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too. + Patch by Andreas Engel, 19 Jul 2005 + +* Update Hymod Board Database PHP code in "tools" directory + Patch by Murray Jensen, 01 Jul 2005 + +* Make "tr" command use POSIX compliant; export HOSTOS make variable + Patch by Murray Jensen, 30 Jun 2005 + +* Fix Murray Jensen's mail address. + Patch by Murray Jensen, 30 Jun 2005 + +* Preserve PHY_BMCR during a soft reset. + Patch by Carl Riechers, 24 Jun 2005 + +* VoiceBlue update: eeprom tool can also store firmware version now. + eeprom.bin is runable by jumping at load address. + Patch by Ladislav Michl, 23 May 2005 + +* Move the AT91RM9200DK to the ARM Systems list. + Patch by Anders Larsen, 26 Apr 2005 + +* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3 + Patch by Anders Larsen, 26 Apr 2005 + +* measure_gclk() is needed when DEBUG is enabled + Patch by Bryan O'Donoghue, 25 Apr 2005 + +* Add UPD-Checksum code, fix problem in net.c (return instead of break) + Patch by Reinhard Arlt, 12 Aug 2005 + +* esd PCI405 board updated + Patch by Matthias Fuchs, 28 Jul 2005 + +* esd WUH405 and DU405 board updated + Patch by Matthias Fuchs, 27 Jul 2005 + +* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I) + Patch by Matthias Fuchs, 4 May 2005 + +* Update AMCC Yosemite to get a consistent setup for all AMCC eval + boards (baudrate, environment...). Flash driver fixed. + Patch by Stefan Roese, 11 Aug 2005 + +* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port + Patch by Stefan Roese, 11 Aug 2005 + +* Add NAND FLASH support for AMCC Bamboo 440EP eval board + Patch by Stefan Roese, 11 Aug 2005 + +* Add configuration for IFM AEV FIFO board. + Minor coding style cleanup. + +* Add configuration for IFM SPI eval board + +* Fix CompactFlash problem on HMI1001 board + +* Make new "mtdparts" code build with older compilers + Patch by Andrea Scian, 09 Aug 2005 + +* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to + CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design + with the 405 defines and the linux kernel defines. + Patch by Stefan Roese, 08 Aug 2005 + +* Fix compiler warnings with older GCC versions + +* Add common (with Linux) MTD partition scheme and "mtdparts" command + + Old, obsolete and duplicated code was cleaned up and replace by the + new partitioning method. There are two possible approaches now: + + The first one is to define a single, static partition: + + #undef CONFIG_JFFS2_CMDLINE + #define CONFIG_JFFS2_DEV "nor0" + #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */ + #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */ + #define CONFIG_JFFS2_PART_OFFSET 0x00000000 + + The second method uses the mtdparts command line option and dynamic + partitioning: + + /* mtdparts command line support */ + #define CONFIG_JFFS2_CMDLINE + #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" + #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" + + Command line of course produces bigger images, and may be inappropriate + for some targets, so by default it's off. + +* Fix build problems for PM856 Board + +* Fix sign extension bug in 'fpga loadb' command; + make 'fpga loadb' always print the file header info + Patch by Andrew Dyer, 11 Jan 2005 + +* Fix errors that occur when accessing SystemACE CF + Patch by Jeff Angielski, 09 Jan 2005 + +* Document switching between U-Boot and PlanetCore on RPXlite + by Sam Song, 24 Dec 2004 + +* Fix PowerQUICC II mask detection. + Patch by Eugene Surovegin, 20 Dec 2004 + +* Add support for Altera NIOS DK1C20 board + Patch by Shlomo Kut, 13 Dec 2004 + +* Add support for ep8248 board + Patch by Yuli Barcohen, 12 Dec 2004 + + Minor code cleanup. + +* Fix baudrate setting for KGDB on MPC8260 + Patch by HoJin, 11 Dec 2004 + +* Fix 'mii help' text formatting + Patch by Cory Tusar, 10 Dec 2004 + +* Fix return code of NFS command + Patch by Hiroshi Ito, 11 Dec 2004 + +* Fix typo + +* Fix compiler warnings in cpu/ppc4xx/usbdev.c + Patch by Steven Blakeslee, 04 Aug 2005 + +* Add support for AMCC Bamboo PPC440EP eval board + Patch by Stefan Roese, 04 Aug 2005 + +* Patch by Jon Loeliger + Fix style issues primarily in 85xx and 83xx boards. + - C++ comments + - Trailing white space + - Indentation not by TAB + - Excessive amount of empty lines + - Trailing empty lines + +* Patch by Ron Alder, 11 Jul 2005 + Add Xianghua Xiao and Lunsheng Wang's support for the + GDA MPC8540 EVAL board. + +* Patch by Eran Liberty + Add support for the Freescale MPC8349ADS board. + +* Patch by Jon Loeliger, 25 Jul 2005 + Move the TSEC driver out of cpu/mpc85xx as it will be shared + by the upcoming mpc83xx family as well. + +* Patch by Jon Loeliger, 05 May 2005 + Implemented support for MPC8548CDS board. + Added DDR II support based on SPD values for MPC85xx boards. + This roll-up patch also includes bugfies for the previously + published patches: + DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O + +* Patch by Jon Loeliger, 10 Feb 2005 + Add config option CONFIG_HAS_FEC calling out 8540 FEC features. + +* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005 + For MPC85xxCDS: + Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow + for faster flash parts. + Add documentation for BR/OR for FLASH. + +* Patch by Jon Loeliger 08 Feb 2005 + Determine L2 Cache size dynamically on 85XX boards. + +* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005 + - Convert the CPM2 based functionality to use new CONFIG_CPM2 + option rather than a myriad of CONFIG_MPC8560-like variants. + Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. + Eliminates the CONFIG_MPC8560 option entirely. Distributes the + new CONFIG_CPM2 option to each 8260 board. + +* Add support for MicroSys PM856 board + Patch by Josef Wagner, 03 Aug 2005 + +* Minor fixes to PM854 board + Patch by Josef Wagner, 03 Aug 2005 + +* Adjust configuration of XENIAX board + (chip select and GPIO required for USB operation) + +* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be + routed to the Watchdog handler + Patch by Eugene Surovegin, 18 Jun 2005 + +* (re)enabled scsi commands do_scsi() and do_scsiboot() + Patch by Denis Peter, 06 Dec 2004 + +* Fix endianess problem in TFTP / NFS default filenames + Patch by Hiroshi Ito, 06 Dec 2004 + +* Ignore broadcast status bit in received frames in 8260 FCC ethernet + loopback test code + Patch by Murray Jensen, 18 Jul 2005 + +* Fix typo in mkconfig script (used == instead of =) + Patch by Murray Jensen, 18 Jul 2005 + +* Cleanup build problems on 64 bit build hosts + +* Update MAINTAINERS file + +* Patch by Stefan Roese, 01 Aug 2005: + - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea + (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup" + for details. + - Sycamore (PPC405GPr) eval board added (Walnut port is extended + to run on both 405GP and 405GPr eval boards). + +* Patch by Steven Blakeslee, 27 Jul 2005: + - Add support for AMCC PPC440EP/GR. + - Add support for AMCC Yosemite PPC440EP eval board. + - Add support for AMCC Yellowstone PPC440GR eval board. + +* Minor fixes for PPChameleon Board: + - fix alignment of NAND size + - make code do what the comment says + +* Implement h/w sector protection status synchronization at boot. + The code is provided for, and was tested on, the Yukon/Alaska + and PM520 boards only. + + A bug in flash_real_protect() for the Yukon board was fixed by + adding a function that tells if two banks are on one flash chip. + +* Fix sysmon POST problem: check I2C error codes + This fixes a problem of displaying bogus voltages when the voltages + are so low that the I2C devices start failing while the rest of the + system keeps running. + +* Patch by Cedric Vincent, 6 Jul 2005: + Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c" + +* Patch by Jon Loeliger, 20 Jul 2005: + Add missing PCI IO port definitions. + +* Add CompactFlash support for HMI1001 board. + +* Adjust printed board ID for LWMON board. + +* Fix low-level OHCI transfers for ARM920t and MPC5xxx + +* Add new argument format for flash commands to allow for usage like + "erase $(addr) +$(filesize)", i. e. a size argument can be used and + U-Boot will automaticially find the end of the corresponding sector. + +* Patch by Stefan Roese, 5 Jul 2005: + Update uc100 board PHY setup + +* Patch by Stefan Roese, 1 Jul 2005: + Fix PHY address for CATcenter board (now correct!) + +* Patch by Stefan Roese, 30 Jun 2005: + Fix PHY addresses for PPChameleon and CATcenter boards + Change MAINTAINER for most esd boards + +* Patch by Detlev Zundel, 30 Jun 2005: + Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code + +* Fix baudrate calculation problem on MPC5200 systems + +* Add EEPROM and RTC support for HMI1001 board + +* Patch by Detlev Zundel, 20 Jun 2005: + Fix initialization of low active GPIO pins on inka4x0 board + +* Enable redundant environment, disable HW flash protection of + HMI1001 board + +* Patch by Travis Sawyer, 10 Jun 2005: + Initialize allocated dev and private hw structures + after their respective allocation in 440gx_enet.c + +* Patch by Steven Scholz, 10 Jun 2005: + Fix byteorder problems with second argument of "bootm" with + standalone images; + +* Add support for HMI1001 board + +* Disable "date" and "sntp" commands on TQM866M + +* Fix watchdog reset problems on LWMON board + +* Patch by Juergen Selent, 17 May 2005: + Add support for Funkwerk VoVPN gateway module. + +* Cleanup debug code for MPC8220 FEC driver + +* Extend burst mode RAM test program to take a loop count + (0 = infinite) + +* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on + those boards that use it. + +* Patches by Greg Ungerer, 19 May 2005: + - add support for the KS8695P (ARM 922 based) CPU + - add support for the OpenGear CM4008, CM4116 and CM4148 boards + +* Patch by Steven Scholz, 19 May 2005: + Add support for CONFIG_SERIAL_TAG on ARM boards + +* Add PCI support for Sorcery board. + Code cleanup (especially Sorcery / Alaska / Yukon serial driver). + +* Fix compile problems caused by new burst mode SDRAM test; + make port pins to trigger logic analyzer configurable + +* Fix timer handling on MPC85xx systems + +* Fix debug code in omap5912osk flash driver + +* Add support for MPC8247 based "IDS8247" board. + +* Add support for 2 x TSEC interfaces on the TQM8540 board. + +* On LWMON we must use the watchdog to reset the board as the CPU + genereated HRESET pulse is too short to reset the external + circuitry. + +* Add test tool to exercise SDRAM accesses in burst mode + (as standalone program, MPC8xx/PowerPC only) + +* Increase CFG_MONITOR_LEN for Rattler board to match actual code + size. + +* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of + March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI + added to support LZO and LZARI compression modes (undefined by + default). + +* Fix problem with symbolic links in JFFS2 code. + +* Use linker ASSERT statement to prevent undetected overlapping of + sections on PPChameleon board; other boards might use this, too. + +* Patch by Stefan Roese, 03 May 2005: + Update for P3G4 + Fix problems in cmd_universe.c + +* Patch by Matthias Fuchs, 03 May 2005: + Added missing variable declaration in cmd_nand.c + Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram + +* Fix INKA4x0: use CS1 as gpio_wkup_6 output + +* Fix bug in the SDRAM initialization code for canmb, IceCube and + PM520 boards. + Fix PHY address for canmb board. + +* Cleanup serial console baudrate calculation on AT91RM9200; + get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition + +* Patch by Matthias Fuchs, 18 Apr 2005: + Make PCI target address spaces on PMC405 and CPCI405 boards + configurable via environment variables + +* Auto-size RAM on canmb board. + +* Add support for canmb board + +* Patch by Stefan Roese, 13 Apr 2005: + Update for esd apc405 + +* Fixes for TQM8560 board: + - fix clock rates + - remove debug messages + - fix flash sector protection + +* Patch by Steven Scholz, 07 Apr 2005: + Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C + +* Patches by Steven Scholz, 07 Apr 2005: + Fix compiler warning in altera.c + Fix warning in cpu/arm920t/at91rm9200/i2c.c + +* Patch by Ladislav Michl, 06 Apr 2005: + Fix voiceblue configuration. + +* Patch by Stefan Roese, 06 Apr 2005: + Updates for OCOTEA board: + - Changed U-Boot size from 512kByte to 256kByte + - Fixed flash driver to support boot from soldered user flash + - Added README for switch from PIBS firmware to U-Boot + +* Patch by Travis Sawyer, 05 Apr 2005: + - Change timer frequency for ppc 440 from 10 ms to 1 ms. + Problem found by Andrew Wozniak. + +* Patch by Steven Scholz, 06 Apr 2005: + - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 + - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200 + +* Patches by Robert Whaley, 29 Nov 2004: + - update the pxa-regs.h file for PXA27x chips + - add PXA27x based ADSVIX board + - add support for MMC on PXA27x processors + +* Patch by Andrew E. Mileski, 28 Nov 2004: + Fix PPC4xx SPD SDRAM detection bug + +* Patch by Hiroshi Ito, 26 Nov 2004: + Fix logic of "test -z" and "test -n" commands + +* Patch by Ladislav Michl, 05 Apr 2005: + Add support for VoiceBlue board. + +* Patch by Ladislav Michl, 05 Apr 2005: + Fix netboot_common() prototypes. + +* Patch by Steven Scholz, 05 Apr 2005: + Use i.MX watchdog timer for reset_cpu() + +* Patch by Steven Scholz, 05 Apr 2005: + Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific + subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/ + (now in interupts.c) + +* Add support for MPC8220 based "sorcery" board. + +* Add support for TQM8560 board. + +* Add FEC support for TQM8540 board. + Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC + +* Patch by Martin Krause, 04 Apr 2005: + Update default configuration for CMC_PU2 board. + +* Patch by Steven Scholz, 04 Apr 2005: + - remove all references to CONFIG_INIT_CRITICAL for ARM based boards + - introduce two new configuration options instead: + CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT + +* Patch by Steven Scholz, 04 Apr 2005: + Make sure that MDIO clock does not exceed 2.5 MHz on AT91 + +* Fix timer code for ARM systems: make sure that udelay() does not + reset timers so it's save to use udelay() in timeout code. + +* Patch by Mathias Küster, 23 Nov 2004: + add udelay support for the mcf5282 cpu + +* Patch by Tolunay Orkun, 16 November 2004: + fix incorrect onboard Xilinx CPLD base address + +* Patch by Jerry Van Baren, 08 Nov 2004: + - Add low-boot option for MPC8260ADS board (if lowboot is selected, + the jumper for the HRCW source should select flash. If lowboot is + not selected, the jumper for the HRCW source should select the + BCSR. + - change default load base address to 0x00400000 + +* Patch by Yuli Barcohen, 08 Nov 2004: + Add support for Analogue & Micro Rattler boards. + Tested on Rattler8248. + +* Patch by Andre Renaud, 08 Nov 2004: + Fix watchdog support in common/lcd.c + +* Patch by Marc Leeman, 05 Nov 2003: + Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU + bug only affects the XPC8245 processors + +* Patches by Josef Wagner, 29 Oct 2004: + - Add support for MicroSys CPU87 board + - Add support for MicroSys PM854 board + +* Patch by Jian Zhang, 02 Nov 2004: + Add 16-bit NAND support + +* Patch by Scott McNutt, 01 Nov 2004: + Add missing NIOS/NIOS2 support for "iminfo" command + +* Patch by Detlev Zundel, 29 Oct 2004: + Add missing NIOS/NIOS2 support for "mkimage" tool. + +* Patch by David Adair, 27 Oct 2004: + Add missing 440GX SDRAM Controller reset + +* Patch by Steven Scholz, 25 Oct 2004: + Declare reset_cpu() in include/common.h instead locally + +* Patch by Yusdi Santoso, 22 Oct 2004: + - Add support for HIDDEN_DRAGON board + - fix endianess problem in driver/rtl1839.c + +* Patch by Allen Curtis, 21 Oct 2004: + support multiple serial ports + +* Patch by Richard Klingler, 03 Apr 2005: + Add call to eth_halt() in net/net.c when called functions fail + after eth_init() has been called. + +* Patch by Sam Song, 3 April 2005: + - Update README.Netconsole + - Update README + +* Prepare for SoC rework of ARM code: + - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL + - rename memsetup into lowlevel_init (function name and source files) + Patch by Steven Scholz, 03 Apr 2005: + - create SoC specific directories include/asm-arm/arch-imx and + include/asm-arm/arch-s3c24x0 + +* Fix problems with SNTP support; + enable SNTP support in some boards. + +* Patches by Martin Krause, 01 Apr 2005: + - Fix flash erase timeout on CMC_PU2 + - Add automatic HW detection for CMC_PU2 and CMC_BASIC + +* Patch by Steven Scholz, 13 March 2005: + fix cache enabling for AT91RM9200 + +* Patch by Masami Komiya, 30 Mar 2005: + add SNTP support and expand time server and time offset fields of + DHCP support. See doc/README.SNTP + +* Patch by Steven Scholz, 13 Dec 2004: + Fix bug in at91rm920 ethernet driver + +* Patch by Steven Scholz, 13 Dec 2004: + Remove duplicated code by merging memsetup.S files for + at91rm9200 boards into one cpu/at91rm9200/lowlevel.S + +* Patch by Detlev Zundel, 31 Mar 2005: + Cleanup duplicate definition of overwrite_console() + +* Update TQM5200 configuration; + prepare for Rev. 200 starter kit boards + +* Patch by Scott McNutt, 21 Oct 2004: + Add support for Nios-II EPCS Controller core. + +* Patch by Scott McNutt, 20 Oct 2004: + Nios-II cleanups: + - Add sysid command (Nios-II only). + - Locate default exception trampoline at proper offset. + - Implement I/O routines (readb, writeb, etc) + - Implement do_bootm_linux + +* Patches by Martin Krause, 22 Mar 2005: + - use TQM5200_auto as MAKEALL target for TQM5200 systems + - add support for SM501 graphics controller + - add support for graphic console on TQM5200 + - add support for TQM5200 Rev 200 + - cleanup, fix typo in include/configs/TQM5200.h + +* Patch by Manfred Baral, 17 Mar 2005: + Fix typo + +* Fix RTC configuration for PPChameleon board + +* Cleanup, fix typo in include/configs/TQM5200.h + +* Patch by Stefan Roese, 16 Mar 2005: + Update for esd auto_update and hh405 board + +* Adapt for U-Boot image size (new features enabled) on TQM5200 + +* Update code for TQM8540 board (and 85xx in general): + - Change the name of the Ethernet driver: MOTO ENET -> ENET + - Reformat boot messages + - Enable redundant environment + - Replace the -O2 optimization flag with -mno-string + +* Patch by David Brownell, 10 Mar 2005: + Restore copyright statements in OHCI drivers. + +* Add support for TQM8540 board + +* Patch by Detlev Zundel, 14 Mar 2005: + NC650: changed NAND flash addressing to using UPMB + +* Patch by Stefan Roese, 14 Mar 2005: + Update for esd voh405 fpga image + +* INKA4x0: Allow initialization of LCD backlight dimming from + "brightness" environment variable. + +* Add port initialization for digital I/O on INKA4x0 + +* Patch by Stefan Roese, 01 Mar 2005: + Update for esd boards dp405 and hub405 + +* Fix get_partition_info() parameter error in all other calls + (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c). + +* Enable USB and IDE support for INKA4x0 board + +* Patch by Andrew Dyer, 28 Feb 2005: + fix ext2load passing an incorrect pointer to get_partition_info() + resulting in load failure for devices other than 0 + +* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board + +* Cleanup USB and partition defines + +* Add support for ext2 filesystems and image timestamps to TQM5200 board + +* Add reset code for Coral-P on INKA4x0 board + +* Patch by Martin Krause, 28 Jun 2004: + Update for TRAB board. + +* Fix some missing "volatile"s in MPC5xxx FEC driver + +* Fix cirrus voltage detection (for CPC45) + +* Fix byteorder problem in usbboot and scsiboot commands. + +* Patch by Cajus Hahn, 04 Feb 2005: + - don't insist on leading '/' for filename in ext2load + - set default partition to useful value (1) in ext2load + +* Patch by Andrew Dyer, 08 Jan 2005: + fix wrong return codes in ext2 code + +* Removed '--no-warn-mismatch' option from Makefile. This option + makes 'ld' to overlook binary objects compatibility. + +* Moved $(PLATFORM_LIBS) from the library group (--start-group ... + --end-group) outside of the group. This will make 'ld' to do + _multiple_ search in the library group when resolving symbol + references and do only a _single_ seach in libgcc.a after the group + search. + +* Fix stability problems on CPC45 board again. + +* Make image detection for diskboot / usbboot / scsiboot more robust + (also check header checksum) + +* Update CPC45 board configuration. + +* Add USB and PCI support for INKA4x0 board + +* Fix IDE stability problems on CPC45 board (needs 2 x EIEIO). + +* Code cleanup + +* Patch by Robin Getz, 13 Oct 2004: + Add standalone application to change SMC91C111 MAC addresses, + see examples/README.smc91111_eeprom + +* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004: + Fix Flash support for ARM Integrator CP. + +* Patch by Richard Woodruff, 10 Jan 2005: + Update support for OMAP2420 (ARM11) and H4 board: + o clean up and add new types to H4 memory probe code. + o fix to work with internal boot. + o added PRCM config III operation. + o fix marginal flash timings. + o add revison ATAG usage. + o enable voltage scaling at power chip. + o fix compile error for i2c. + +* Fix network problem (error when receiving multiple ARP packets) + +* Patch by Daniel Poirot, 12 Oct 2004: + Add support for Wind River sbc405 board + +* Patch by Rainer Brestan, 12 Oct 2004: + Make examples/Makefile more robust + +* Patch by Sam Song, 11 October 2004: + - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board + - Adjust CPU:BUS frequency ratio 1:1 when core frequency + less than 50MHz + +* Patch by Sam Song, 10 Oct 2004: + Fix a parameter error in run_command() in main.c + +* Patch by Richard Woodruff, 01 Oct 2004: + add support for the TI OMAP2420 processor and its H4 reference + board + +* Patch by Christian Pellegrin, 24 Sep 2004: + Added support for NE2000 compatible (DP8390, DP83902) NICs. + +* Patch by Leif Lindholm, 23 Sep 2004: + add support for the AMD db1550 board + +* Patch by Travis Sawyer, 15 Sep 2004: + Add CONFIG_SERIAL_MULTI support for ppc4xx, + update README.serial_multi + +* Patches by David Snowdon, 07 Sep 2004: + - add u-boot.hex target in the top level Makefile + - add support for the UNSW/NICTA PLEB 2 board (pleb2) + - use -mtune=xscale and -march=armv5 options for PXA + +* Patch by Florian Schlote, 08 Sep 2004: + Add support for SenTec-COBRA5272-board (Coldfire). + +* Patch by Gleb Natapov, 07 Sep 2004: + mpc824x: set PCI latency timer to a sane value + (is 0 after reset). + +* Patch by Kurt Stremerch, 03 Sep 2004: + Add bitstream configuration option for fpga command (Xilinx only). + +* Patch by Kurt Stremerch, 03 Sep 2004: + Add Xilinx Spartan2E family FPGA support + +* Patch by Jeff Angielski, 02 Sep 2004: + Add Added support for H2 revision of the EP8260 board. + Fixed formatting for some of the EP8260 related source files. + +* Patch by Jon Loeliger, 02 Sep 2004: + Reset monitor size back to 256 so environment can be written + to flash on MPC85xx ADS and CDS releases. + +* Patch by Paolo Broggini, 02 Sep 2004: + Make BSS clearing on ARM systems more robust + +* Patch by Yue Hu and Joe, 01 Sep 2004: + - add PCI support for ixp425; + - add EEPRO100 suppor tfor ixdp425 board. + +* Fix problem with protected sector detection in driver/cfi_flash.c + +====================================================================== +Changes for U-Boot 1.1.2: +====================================================================== + +* Code cleanup, mostly for GCC-3.3.x + +* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to + pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for + additional ethernet addresses. + +* Cleanup drivers/i82365.c - avoid duplication of code + +* Fix bogus "cannot span across banks" flash error message + +* Code cleanup + +* Add support for CompactFlash for the CPC45 Board. + +* Fix problems with CMC_PU2 flash driver. + +* Cleanup: + - avoid trigraph warning in fs/ext2/ext2fs.c + - rename UC100 -> uc100 + +* Add support for UC100 board + +* Patch by Stefan Roese, 16 Dez 2004: + - ext2fs support added + - Tundra universe support added + - Coldfire MCF5249 support added (no preloader needed!) + - MCF5249 board TASREG added + - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405, + VOM405, WUH405 + - some esd boards updated + - memory commands "mdc" and "mwc" added for cyclic read/write + (CONFIG_MX_CYCLIC, see README for further description) + +* Add support for INKA4X0 board + +* Patch by Steven Scholz, 12 Dec 2004: + Fix typo in AT91 memory setup. + +* Patch by Martin Krause, 27 Oct 2004: + - add support for "STK52xx" board (including PS/2 multiplexer) + - add hardware detection for TQM5200 + +* Clean up CMC PU2 flash driver + +* Update MAINTAINERS file + +* Fix bug in MPC823 LCD driver + +* Fix udelay() on AT91RM9200 for delays < 1 ms. + +* Enable long help on CMC PU2 board; + fix reset issue; + increase CPU speed from 179 to 207 MHz. + +* Fix smc91111 ethernet driver for Xaeniax board (need to handle + unaligned tail part specially). + +* Update for AT91RM9200DK and CMC_PU2 boards: + - Enable booting directly from flash + - fix CMC_PU2 flash driver + +* Fix mkimage usage message + +* Map SRAM on NC650 board + +* Work around for Ethernet problems on Xaeniax board + +* Patch by TsiChung Liew, 23 Sep 2004: + - add support for MPC8220 CPU + - Add support for Alaska and Yukon boards + +* Fix configuration for ERIC board (needs more room) + +* Adjust MIPS compiler options at run-time depending on tools version + ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new, + "-mcpu=4kc" for old tools) + +* Add passing of the command line and memory size information to the + kernel on xaeniax board. + +* Enable NAND flash support for NC650 board. + +* Patch by Thomas Lange 07 Oct 2004: + Updated README for DBAu1x00 boards to match current status + +* Patch by Philippe Robin, 28 Sept 2004: + Fix Flash support for Versatile. + +* Patch by Roger Blofeld, 16 Sep 2004: + Fix timeout for DHCP command retry + +* Patch by Pantelis Antoniou, 14 Sep 2004: + Fix early serial hang when CONFIG_SERIAL_MULTI is defined. + +* Patch by Pantelis Antoniou, 14 Sep 2004: + Kick watchdog when bz-decompressing + +* Fix CFG_HZ problems on AT91RM9200 systems + [Remember: CFG_HZ should be 1000 on ALL systems!] + +* Patch by Gridish Shlomi, 30 Aug 2004: + - Add support to revA version of PQ27 and PQ27E. + - Reverted MPC8260ADS baudrate back to original 115200 + +* Patch by Hojin, 17 Sep 2004: + Fix typo in cfi_flash.c + +* Patch by Mark Jonas, 09 September 2004: + mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong + error message + +* Patch by Mark Jonas, 31 August 2004: + Added option CFG_XLB_PIPELINING to enable XLB pipelining. This + improves FTP performance for MPC5200 systems. Enabled for IceCube + by default. + +* Patch by Michael Bendzick, 30 Aug 2004: + - Improve platform.S code for omap1510inn that detects whether code + is running from SDRAM or not. Patch allows SDRAM to be configured + if code is running out of SRAM at 0x20000000. + +* Patch by Frederick Klatt, 30 Aug 2004: + Add support for the Wind River SBC8540/SBC8560 boards + +* Configure SX1 board to use drivers/cfi_flash.c + +* Patches by Michael Bendzick, 30 Aug 2004: + - Configure omap1510inn board to use drivers/cfi_flash.c + - Make drivers/cfi_flash.c protect environment and redundant + environment. + +* Patch by Steven Scholz, 23 Jun 2004: + - Add script (tools/img2brec.sh) to programm U-Boot into + (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L + +* Patches by Scott McNutt, 24 Aug 2004: + - Add support for Altera Nios-II processors. + - Add support for Psyent PCI-5441 board. + - Add support for Psyent PK1C20 board. + +* Patches by Jon Loeliger, 24 Aug 2004: + - Add support for the MPC8541 and MPC8555 CDS boards + - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR + - Convert MPC85xxADS to use common CFI flash driver + - Fix PCI window on MPC85xx; remove unneeded PCI initialization + from board_early_init_f() + - Provide SW workaround for PCI initialization on 85xx CDS + +* Patches by George G. Davis, 24 Aug 2004: + - Enable ramdisk/initrd tagged param support for omap1610h2_config + - Remove static network setup defaults from mx1ads_config + - update ARM boards to use constants from mach-types.h + +* Patch by Gary Jennejohn, 04 Oct 2004: + - fix I2C on at91rm9200 + - add support for Ricoh RS5C372A RTC + +* Patch by Gary Jennejohn, 01 Oct 2004: + - add support for CMC PU2 board + - add support for I2C on at91rm9200 + +* Patch by Gary Jennejohn, 28 Sep 2004: + fix baudrate handling on at91rm9200 + +* Patch by Yuli Barcohen, 22 Aug 2004: + - remove ZPC.1900 board-specific flash driver; + switch the port to generic CFI driver; + - port clean-up + +* Patch by Hinko Kocevar, 21 Aug 2004: + Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB + +* Clean up tools/bmp_logo.c to not add trailing white space + +* Patch by Hinko Kocevar, 21 Aug 2004: + - Group common framebuffer functions in common/lcd.c + - Group common framebuffer macros and #defines in include/lcd.h + - Provide calc_fbsize() for video ATAG + +* Patch by Sam Song, 21 August 2004: + - Fix a typo in README + - Align "(RO)" output for "flinfo" after "protect on" + - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency + ratio 1:1 when core frequency less than 50MHz + +* Patches by Hinko Kocevar, 21 Aug 2004: + - fix some "use of label at end of compound statement" warnings + - Define type of LCD panel on lubbock board if CONFIG_LCD is used + +* Patch by Steven Scholz, 16 Aug 2004: + - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" + - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 + - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ + - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ + into cpu/arm920t/$(SOC)/ + +* Patches by Sean Chang, 09 Aug 2004: + - Added support for both 8 and 16 bit mode access to System ACE CF + through MPU. + - Fixed missing System ACE CF device during get FAT partition info + in fat_register_device function. + - Enabled System ACE CF support on ML300. + +* Patch by Sean Chang, 09 Aug 2004: + Synch defines for saveenv and do_saveenv functions so they get + compiled under the same statement. + +* Patch by Sean Chang, 09 Aug 2004: + - Added I2C support for ML300. + - Added support for ML300 to read out its environment information + stored on the EEPROM. + - Added support to use board specific parameters as part of + U-Boot's environment information. + - Updated MLD files to support configuration for new features + above. + +* Patches by Travis Sawyer, 05 Aug 2004: + - Remove incorrect bridge settings for eth group 6 + - Add call to setup bridge in ppc_440x_eth_initialize + - Fix ppc_440x_eth_init to reset the phy only if its the + first time through, otherwise, just check the phy for the + autonegotiated speed/duplex. This allows the use of netconsole + - only print the speed/duplex the first time the phy is reset. + +* Patch by Shlomo Kut, 29 Mar 2004: + Add support for MKS Instruments "Quantum" board + +* Fix build problem with Cogent boards; + avoid using when using the host compiler + +* Patch by Ganapathi C, 04 Aug 2004: + Fix NFS timeout issue + +* Patch by Yuli Barcohen, 19 Jul 2004: + - Fix host tools building in Cygwin environment + - Fix header files search order for host tools + +* Patch by Tom Armistead, 19 Jul 2004: + Fix kgdb.S support for 74xx_75x cpu + +* Patch by Jon Loeliger, 15 Jul 2004: + Fix MPC85xx I2C driver + +* Fix problems with CDROM drive as slave device on Lite5200 IDE bus. + +* Patch by Stephen Williams, 15 July 2004 + Set the PCI class code for JSE board as part of PCI interface setup + +* Patch by Michael Bendzick, 15 Jul 2004: + Fix problem with writes with odd sizes in drivers/cfi_flash.c when + CFG_FLASH_USE_BUFFER_WRITE is set + +* Patch by Yuli Barcohen, 13 Jul 2004: + Allow clock setting on MPC866/MPC885 series chips according to + environment variable `cpuclk' + +* Patch by Yuli Barcohen, 20 Apr 2004: + Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x + +* Patch by Vincent Dubey, 24 Sep 2004: + Add support for xaeniax board + +* Add comment about non-GPL character of standalone applications to + COPYING file + +* Fix FEC ethernet problem on NSCU board. + +* Patch by Gary Jennejohn, 09 Sep 2004: + allow to use USART1 as console port on at91rm9200dk boards + +* Patch by Stefan Roese, 16 Sep 2004: + Update AR405 board. + +* Fix SysClk handling for PPChameleon and CATcenter boards + +* Patch by Detlev Zundel, 08 Sep 2004: + Update etags build target + +* Improve NetConsole support: add support for broadcast destination + address and buffered input. + +* Cleanup compiler warnings for GCC 3.3.x and later + +* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch + +* Add support for IDS "NC650" board + +* Add automatic update support for LWMON board + +* Clear Block Lock-Bits when erasing flash on LWMON board. + +* Fix return code of "fatload" command + +* Enable MSDOS/VFAT filesystem support for LWMON board + +* Patch by Martin Krause, 03 Aug 2004: + change timing for SM501 graphics controller on TQM5200 module + +* Patch by Mark Jonas, 13 July 2004: + - Total5200 LCD now run in little endian mode. Endianess conversion + is done in hardware. + - Removed last reference to "console" environment variable. + +* Patches by Lars Munch, 12 Jul 2004: + - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk + board specific + - split out the LXT971A PHY from ns_9750_eth.h + - split the dm9161 phy part out of at91rm9200_ether.c + +* Patch by Andreas Engel, 12 Jul 2004: + Replaced hardcoded PL011 clock frequency with config variable. + Fixed wrong CONFIG_CMD_DFL doc. + +* Patch by Thomas Viehweger, 09 Jun 2004: + make it possible to remove chpart when there is only one partition + +* Add support for console over UDP (compatible to Ingo Molnar's + netconsole patch under Linux) + +* Patch by Jon Loeliger, 16 Jul 2004: + - support larger DDR memories up to 2G on the PC8540/8560ADS and + STXGP3 boards + - Made MPC8540/8560ADS be 33Mhz PCI by default. + - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 + and CONFIG_L2_INIT_RAM options. + - Refactor Local Bus initialization out of SDRAM setup. + - Re-implement new version of LBC11/DDR11 errata workarounds. + - Moved board specific PCI init parts out of CPU directory. + - Added TLB entry for PCI-1 IO Memory + - Updated README.mpc85xxads + +* Patch by Sascha Hauer, 28 Jun: + - add generic support for Motorola i.MX architecture + - add support for mx1ads, mx1fs2 and scb9328 boards + +* Patches by Marc Leeman, 23 Jul 2004: + - Add define for the PCI/Memory Buffer Configuration Register + - corrected comments in cpu/mpc824x/cpu_init.c + +* Add support for multiple serial interfaces + (for example to allow modem dial-in / dial-out) + +* Patch by Stefan Roese, 15 Jul 2004: + cpu/ppc4xx/sdram.c rewritten now using get_ram_size() + +* Fix NSCU config; add ethernet wakeup code. + +* Add link for preloader for Motorola Coldfire to README.m68k + +* Patch by Michael Bendzick, 12 Jul 2004: + fix output formatting in drivers/cfi_flash.c + +* Patch by Mark Jonas, 02 Jul 2004: + Fix lowboot (again) on MPC5xxx + +* Patch by Curt Brune, 07 Jul 2004: + relocate exception vectors on arm720t if needed + +* Patch by George G. Davis, 06 Jul 2004: + - update mach-types.h to latest arm.linux.org.uk master list + - Set correct OMAP1610 bi_arch_number for build target + +* Patch by Curt Brune, 06 Jul 2004: + evb4510: add support for timer interrupt; cleanup + +* Patch by Dan Poirot, 06 Jul 2004: + Fix sbc8260 environment variables + +* Cleanup redundand "console" environment variable + +* Patch by Mark Jonas, 05 Jul 2004: + add support for the Total5100's and Total5200's LCD screen + +* Patches by Dan Eisenhut, 01 Jul 2004: + - README fixes. + - Move doc2000.h include to prevent compiler warning on some boards + +* Patch by Mark Jonas, 01 Jul 2004: + Added support for Total5100 and Total5200 (Rev.1 and Rev.2) + MGT5100 and MPC5200 based Freescale platforms. + +* Patch by Philippe Robin, 01 Jul 2004: + Add initialization for Integrator and versatile board files. + +* Patch by Hinko Kocevar, 01 Jun 2004: + Fix VFD FB allocation, add LCD FB allocation on ARM + +* Patch by Martin Krause, 30 Jun 2004: + Add support for TQM5200 board + +* Patch by Martin Krause, 29 Jun 2004: + Add loopw command: infinite write loop on address range + +* Patches by Yasushi Shoji, 29 Jun 2004: + - add empty include/asm-microblaze/processor.h + - add to CREDITS and MAINTAINERS + - add gd initialization + - add MicroBlaze and SUZAKU board to MAKEALL script + - add reset support for SUZAKU + - add flush_cache() for MicroBlaze + - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed + size flash memory on SUZAKU + +* Patch by Prakash Kumar, 27 Jun 2004: + Add support for the PXA250 based Intrinsyc Cerf board. + +* Patch by Yasushi Shoji, 27 Jun 2004: + fix comment in include/common.h + +* Rename SBC8560 into sbc8560 for consistency + +* Patch by Daniel Poirot, 24 Jun 2004: + Add support for Wind River's sbc8240 board + +* Patches by Yasushi Shoji, 26 Jun 2004: + - drivers/serial_xuartlite.c: fix "return 0" in void function + - add microblaze support to mkimage tool + +* Patch by Fred Klatt, 25 Jun 2004: + Add support for WindRiver's sbc8560 board + +* Patch by Nicolas Lacressonniere, 24 Jun 2004 + Small Bugs fixes for "at91rm9200dk" board: + - Timing modifications for SPI DataFlash access + - Fix NAND flash detection bug + +* Patch by Nicolas Lacressonniere, 24 Jun 2004: + Add Support for Flash AT49BV6416 for AT91RM9200DK board + +* Patch by Jon Loeliger, 17 June 2004: + Completion of the 8540ADS/8560ADS updates: + Fix some PCI and Rapid I/O memory maps, + Initialize both TSEC 1 and 2, + Initialize SDRAM + Update MAINTAINER for 85xx boards and README.mpc85xxads + +* Patch by Yuli Barcohen, 16 Jun 2004: + Remove obsolete AdderII port which was superseded by unified + AdderII/Adder87x port + +* Patch by Ladislav Michl, 16 Jun 2004: + Fix gcc-3.3.3 warnings for smc91111.c + +* Patch by Stefan Roese, 02 Jul 2004: + - Fix bug in 405 ethernet driver; allocated data not cleared! + - Fix problem in 405 i2c driver; don't try to print without console! + +* Patch by Paul Ruhland, 11 Jun 2004: + Remove debug code from 'board/lpd7a40x/flash.c' + +* Patch by Andrea Marson, 11 Jun 2004: + Update for PPChameleon board: + - support for SysClk @ 25MHz + - support for Silicon Motion SM712 VGA controller + - some clean ups + +* Patches by Richard Woodruff, 10 Jun 2004: + - fix problems with examples/stubs.c for GCC >= 3.4 + - fix problems with gd initialization + +* Patch by Curt Brune, 17 May 2004: + - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC) + - Add support for ESPD-Inc. EVB4510 Board + +* Patch by Marc Leeman, 11 May 2004: + Fix for MPC8245 - reading PPC Memory from another device with the + PPC as PCI target device corrupts data due to interenal hardware + buffering. + +* Fix "cls" command when used with splash screen + +* Increase NFS download timeout (now 1 min - 10 sec is to short for a + slow download of a big image) + +* Add "cls" function to MPC823 LCD driver so we can reinitialize the + display even after showing a bitmap + +* Patch by Josef Wagner, 04 Jun 2004: + - DDR Ram support for PM520 (MPC5200) + - support for different flash types (PM520) + - USB / IDE / CF-Card / DiskOnChip support for PM520 + - 8 bit boot rom support for PM520/CE520 + - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) + - I2C and RTC support for CPC45 + - support of new flash type (28F160C3T) for CPC45 + +* Fix flash parameters passed to Linux for PPChameleon board + +* Remove eth_init() from lib_arm/board.c; it's done in net.net.c. + +* Patch by Paul Ruhland, 10 Jun 2004: + fix support for Logic SDK-LH7A404 board and clean up the + LH7A404 register macros. + +* Patch by Matthew McClintock, 10 Jun 2004: + Modify code to select correct serial clock on Sandpoint8245 + +* Patch by Robert Schwebel, 10 Jun 2004: + Add support for Intel K3 strata flash. + +* Patch by Thomas Brand, 10 Jun 2004: + Fix "loads" command on DK1S10 board + +* Patch by Yuli Barcohen, 09 Jun 2004: + Add support for 8MB flash SIMM and JFFS2 file system on + Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS). + +* Patch by Yuli Barcohen, 09 Jun 2004: + Add support for Analogue&Micro Adder87x and the older AdderII board. + +* Patch by Ming-Len Wu, 09 Jun 2004: + Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board + +* Patch by Sam Song, 09 Jun 2004: + - Add support for RPXlite_DW board + - Update FLASH driver for 4*AM29DL323DB90VI + - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board + +* Patch by Mark Jonas, 08 June 2004: + - Make MPC5200 boards evaluate the SVR to print processor name and + version in checkcpu() (cpu/mpc5xxx/cpu.c). + +* Patch by Kai-Uwe Bloem, 06 May 2004: + Fix endianess problem in cramfs code + +* Patch by Tom Armistead, 04 Jun 2004: + Add support for MAX6900 RTC + +* Patches by Ladislav Michl, 03 Jun 2004: + - fix cfi_flash.c on LE systems + - let 'make mrproper' delete u-boot.img as well + - turn printf into debug in cfi_flash.c + +* Patch by Kurt Stremerch, 28 May 2004: + Add support for Exys XSEngine board + +* Patch by Martin Krause, 27 May 2004: + Fix a MPC5xxx I2C timing issue in i2c_probe(). + +* Patch by Leif Lindholm, 27 May 2004: + Fix board_init_f() for dbau1x00 board. + +* Patch by Imre Deak, 26 May 2004: + On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3). + Set flash base accordingly, and decide whether to do or skip board + specific setup steps. + +* Patch by Josef Baumgartner, 26 May 2004: + Add missing define in include/asm-m68k/global_data.h + +* Patch by Josef Baumgartner, 25 May 2004: + Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c + +* Patch by Paul Ruhland, 24 May 2004: + fix SDRAM initialization for LPD7A400 board. + +* Patch by Jian Zhang, 20 May 2004: + add support for environment in NAND flash + +* Patch by Yuli Barcohen, 20 May 2004: + Add support for Interphase iSPAN boards. + +* Patches by Paul Ruhland, 17 May 2004: + - Add I/O functions to the smc91111 ethernet driver to support the + Logic LPD7A40x boards. + - Add support for the Logic Zoom LH7A40x based SDK board(s), + specifically the LPD7A400. + +* Patches by Robert Schwebel, 15 May 2004: + - call MAC address reading code also for SMSC91C111; + - make SMSC91C111 timeout configurable, remove duplicate code + - fix get_timer() for PXA + - update doc/README.JFFS2 + - use "bootfile" env variable also for jffs2 + +* Patch by Tolunay Orkun, 14 May 2004: + Add support for Cogent CSB472 board (8MB Flash Rev) + +* Patch by Thomas Viehweger, 14 May 2004: + - flash.h: more flash types added + - immap_8260.h: some bits added (useful for RMII) + - cmd_coninfo.c: typo corrected, printf -> puts + - reduced size by replacing spaces with tab + +* Patch by Robert Schwebel, 13 May 2004: + Add 'imgextract' command: extract one part of a multi file image. + +* Patches by Jon Loeliger, 11 May 2004: + Dynamically handle REV1 and REV2 MPC85xx parts. + (Jon Loeliger, 10-May-2004). + New consistent memory map and Local Access Window across MPC85xx line. + New CCSRBAR at 0xE000_0000 now. + Add RAPID I/O memory map. + New memory map in README.MPC85xxads + (Kumar Gala, 10-May-2004) + Better board and CPU identification on MPC85xx boards at boot. + (Jon Loeliger, 10-May-2004) + SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. + Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. + (Jim Robertson, 10-May-2004) + Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. + Supports multiple PHYs. + (Andy Fleming, 10-May-2004) + Some README.MPC85xxads updates. + (Kumar Gala, 10-May-2004) + Copyright updates for "Freescale" + (Andy Fleming, 10-May-2004) + +* Patch by Stephen Williams, 11 May 2004: + Add flash support for ST M29W040B + Reduce JSE specific flash.c to remove dead code. + +* Patch by Markus Pietrek, 04 May 2004: + Fix clear_bss code for ARM systems (all except s3c44b0 which + doesn't clear BSS at all?) + +* Fix "ping" problem on INC-IP board. Strange problem: + Sometimes the store word instruction hangs while writing to one of + the Switch registers, but only if the next instruction is 16-byte + aligned. Moving the instruction into a separate function somehow + makes the problem go away. + +* Patch by Rishi Bhattacharya, 08 May 2004: + Add support for TI OMAP5912 OSK Board + +* Patch by Sam Song May, 07 May 2004: + Fix typo of UPM table for rmu board + +* Patch by Pantelis Antoniou, 05 May 2004: + - Intracom board update. + - Add Codec POST. + +* Add support for the second Ethernet interface for the 'PPChameleon' + board. + +* Patch by Dave Peverley, 30 Apr 2004: + Add support for OMAP730 Perseus2 Development board + +* Patch by Alan J. Luse, 29 Apr 2004: + Fix flash chip-select (OR0) option register setting on FADS boards. + +* Patch by Alan J. Luse, 29 Apr 2004: + Report MII network speed and duplex setting properly when + auto-negotiate is not enabled. + +* Patch by Jarrett Redd, 29 Apr 2004: + Fix hang on reset on Ocotea board due to flash in wrong mode. + +* Patch by Dave Peverley, 29 Apr 2004: + add MAC address detection to smc91111 driver + +* Patch by David Müller, 28 Apr 2004: + fix typo in lib_arm/board.c + +* Patch by Tolunay Orkun, 20 Apr 2004: + - README update: add CONFIG_CSB272 and csb272_config + - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and + i2cfast environment variable + +* Patch by Yuli Barcohen, 19 Apr 2004: + - Rename DUET_ADS to MPC885ADS + - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY + - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY + - Clean up FADS family port to use the new defines + +* Fix PCI support on CPC45 board + +* Patch by Scott McNutt, 25 Apr 2004: + Add Nios GDB/JTAG Console support: + - Add stubs to support gdb via JTAG. + - Add support for console over JTAG. + - Minor cleanup. + +* Add support for CATcenter board (based on PPChameleon ME module) + +* Patch by Klaus Heydeck, 12 May 2004: + Using external watchdog for KUP4 boards in mpc8xx/cpu.c; + load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c; + various changes to KUP4 board specific files + +* Fix minor network problem on MPC5200: need some delay between + resetting the PHY and sending the first packet. Implemented in a + "natural" way by invoking the PHY reset and initialization code + only once after power on vs. each time the interface is brought up. + +* Add some limited support for low-speed devices to SL811 USB controller + (at least "usb reset" now passes successfully and "usb info" displays + correct information) + +* Change init sequence for multiple network interfaces: initialize + on-chip interfaces before external cards. + +* Fix memory leak in the NAND-specific JFFS2 code + +* Fix SL811 USB controller when attached to a USB hub + +* Fix config option spelling in PM520 config file + +* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by + patches by Pantelis Antoniou, 30 Mar 2004) + +* Fix minor NAND JFFS2 related issue + +* Fixes for SL811 USB controller: + - implement workaround for broken memory stick + - improve error handling + +* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better + cope with congested networks. + +====================================================================== +Changes for U-Boot 1.1.1: +====================================================================== + +* Patch by Travis Sawyer, 23 Apr 2004: + Fix VSC/CIS 8201 phy descrambler interoperability timing due to + errata from Vitesse Semiconductor. + +* Patch by Philippe Robin, 22 Apr 2004: + Fix ethernet configuration for "versatile" board + +* Patch by Kshitij Gupta, 21 Apr 2004: + Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards + +* Patch by Steven Scholz, 24 Feb 2004: + Fix a bug in AT91RM9200 ethernet driver: + The MII interface is now initialized before accessing the PHY. + +* Patch by John Kerl, 19 Apr 2004: + Use U-boot's miiphy.h for PHY register names, rather than + introducing a new header file. + +* Update pci_ids.h from linux-2.4.26 + +* Patch by Masami Komiya, 19 Apr 2004: + Fix problem cause by VLAN function on little endian architecture + without VLAN environment + +* Clean up the TQM8xx_YYMHz configurations; allow to use the same + binary image for all clock frequencies. Implement run-time + optimization of flash access timing based on the actual bus + frequency. + +* Modify KUP4X board configuration to use SL811 driver for USB memory + sticks (including FAT / VFAT filesystem support) + +* Add SL811 Host Controller Interface driver for USB + +* Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README + +* Patch by Pantelis Antoniou, 19 Apr 2004: + Allow to use shell style syntax (i. e. ${var} ) with standard parser. + Minor patches for Intracom boards. + +* Patch by Christian Pell, 19 Apr 2004: + cleanup support for CF/IDE on PCMCIA for PXA25X + +* Temporarily disabled John Kerl's extended MII command code because + "miivals.h" is missing + +* Patches by Mark Jonas, 13 Apr 2004: + - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S + - Add sync instructions to IceCube SDRAM init code + - Move SDRAM chip constants into seperate include files + - Unify DDR and SDR initialization code + - Unify all IceCube (Lite5xxx) target names + +* Patch by John Kerl, 16 Apr 2004: + Enable ranges in mii command, e.g. mii read 0-1f 0 or + mii read 4-7 18-1a. Also add mii dump subcommand for + pretty-printing standard regs 0-5. + +* Patch by Stephen Williams, 16 April 2004: + fix typo in JSE.h; update MAINTAINERS + +* Patch by Matthew S. McClintock, 14 Apr 2004: + fix initdram function for utx8245 board + +* Patch by Markus Pietrek, 14 Apr 2004: + use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag + +* Patch by Reinhard Meyer, 18 Apr 2004: + provide the IDE Reset Function for EMK 5200 boards + +* Patch by Masami Komiya, 12 Apr 2004: + fix pci_hose_write_config_{byte,word}_via_dword problems + +* Patch by Sangmoon Kim, 12 Apr 2004: + Update max RAM size for debris board + +* Patch by Travis Sawyer, 08 Apr 2004: + Add TLB entry for second DIMM slot on ocotea + +* Patch by Masami Komiya, 08 Apr 2004: + add RTL8169 network driver + +* Patch by Dan Malek, 07 Apr 2004: + - Add support for RPC/STx GP3, Motorola 8560 board + - Update 85xx TSEC driver so it searches MII for first available PHY + and uses that one. + - Add functions to support console MII commands. + +* Patch by Tolunay Orkun, 07 Apr 2004: + Move initialization of bi_iic_fast[] + from board_init_f() to board_init_r() + +* Patch by Yasushi Shoji, 07 Apr 2004: + Cleanup microblaze port + +* Patch by Sangmoon Kim, 07 Apr 2004: + Add auto SDRAM module detection for Debris board + +* Patch by Rune Torgersen, 06 Apr 2004: + - Fix some PCI problems on the MPC8266ADS board + - Fix the location of some PCI entries in the immap structure + +* Patch by Yasushi Shoji, 07 Apr 2004: + - add support for microblaze processors + - add support for AtmarkTechno "suzaku" board + +* Configure PPChameleon board to use redundand environment in flash + +* Configure PPChameleon board to use JFFS2 NAND support. + +* Added support for JFFS2 filesystem (read-only) on top of NAND flash + +* Patch by Rune Torgersen, 16 Apr 2004: + LBA48 fixes + +* Patches by Pantelis Antoniou, 16 Apr 2004: + - add support for a new version of an Intracom board and fix + various other things on others. + - add verify support to the crc32 command (define + CONFIG_CRC32_VERIFY to enable it) + - fix FEC driver for MPC8xx systems: + 1. fix compilation problems for boards that use dynamic + allocation of DPRAM + 2. shut down FEC after network transfers + - HUSH parser fixes: + 1. A new test command was added. This is a simplified version of + the one in the bourne shell. + 2. A new exit command was added which terminates the current + executing script. + 3. Fixed handing of $? (exit code of last executed command) + - Fix some compile problems; + add "once" functionality for the netretry variable + +* Patch by George G. Davis, 02 Apr 2004: + add support for Intel Assabet board + +* Patch by Stephen Williams, 01 Apr 2004: + Add support for Picture Elements JSE board + +* Patch by Christian Pell, 01 Apr 2004: + Add CompactFlash support for PXA systems. + +* Patches by Pantelis Antoniou, 30 Mar 2004: + - add auto-complete support to the U-Boot CLI + - add support for NETTA and NETPHONE boards; fix NETVIA board + - add support for the Epson 156x series of graphical displays + (These displays are serial and not suitable for using a normal + framebuffer console on them) + - add infrastructure needed in order to POST any DSPs in a board + - improve and fix various things in the MPC8xx FEC driver: + 1. The new 87x and 88x series of processors have two FECs, + and the new driver supports them both. + 2. Another change in the 87x/88x series is support for + the RMII (Reduced MII) interface. However numerous + changes are needed to make it work since the PHYs + are connected to the same lines. That means that + you have to address them correctly over the MII + interface. + 3. We now correctly match the MII/RMII interface + configuration to what the PHY reports. + - Fix problem when readingthe MII status register. Due to the + internal design of many PHYs you have to read the register + twice. The problem is more apparent in 10Mbit mode. + - add new mode ".jffs2s" for reading from a NAND device: it just + skips over bad blocks. + - add networking support for VLANs (802.1q), and CDP (Cisco + Discovery Protocol) + - some minor patches / cleanup + +* Patch by Yuli Barcohen, 28 Mar 2004: + - Add support for MPC8272 family including MPC8247/8248/8271/8272 + - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS) + - Change configuration method for MPC8260ADS family + +* add startup code to clear the BSS of standalone applications + +* Fix if / elif handling bug in HUSH shell + +====================================================================== +Changes for U-Boot 1.1.0: +====================================================================== + +* Patch by Mark Jonas: Remove config.tmp files only when + unconfiguring the board + +* Adapt RMU board for bigger flash memory + +* Patch by Klaus Heydeck, 13 Mar 2003: + Add support for KUP4X Board + +* Patch by Pavel Bartusek, 21 Mar 2004 + Add Reiserfs support + +* Patch by Hinko Kocevar, 20 Mar 2004 + - Add auto-release for SMSC LAN91c111 driver + - Add save/restore of PTR and PNR regs as suggested in datasheet + +* Patch by Stephen Williams, 19 March 2004 + Increase speed of sector reads from SystemACE, + shorten poll timeout and remove a useless reset + +* Patch by Tolunay Orkun, 19 Mar 2004: + Make GigE PHY 1000Mbps Speed/Duplex detection conditional + (CONFIG_PHY_GIGE) + +* Patch by Brad Kemp, 18 Mar 2004: + prevent machine checks during a PCI scan + +* Patch by Pierre Aubert, 18 Mar 2004: + Fix string cleaning in IDE identification + +* Patch by Pierre Aubert, 18 Mar 2004: + - Unify video mode handling for Chips & Technologies 69000 Video + chip and Silicon Motion SMI 712/710/810 Video chip + - Add selection of the video output (CRT or LCD) via 'videoout' + environment variable for the Silicon Motion + - README update + +* Patch by Pierre Aubert, 18 Mar 2004: + include/common.h typo fix + +* Patches by Tolunay Orkun, 17 Mar 2004: + - Add support for bd->bi_iic_fast[] initialization via environment + variable "i2cfast" (CONFIG_I2CFAST) + - Add "i2cfast" u-boot environment variable support for csb272 + +* Patch by Carl Riechers, 17 Mar 2004: + Ignore '\0' characters in console input for use with telnet and + telco pads. + +* Patch by Leon Kukovec, 17 Mar 2004: + typo fix for strswab prototype #ifdef + +* Patches by Thomas Viehweger, 16 Mar 2004: + - show PCI clock frequency on MPC8260 systems + - add FCC_PSMR_RMII flag for HiP7 processors + - in do_jffs2_fsload(), take load address from load_addr if not set + explicit, update load_addr otherwise + - replaced printf by putc/puts when no formatting is needed + (smaller code size, faster execution) + +* Patch by Phillippe Robin, 16 Mar 2004: + avoid dereferencing NULL pointer in lib_arm/armlinux.c + +* Patch by Stephen Williams, 15 Mar 2004: + Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation + +* Patch by Tolunay Orkun, 15 Mar 2004: + Initialize bi_opbfreq to real OPB frequency via get_OPB_freq() + +* Patch by Travis Sawyer, 15 Mar 2004: + Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port + +* Add start-up delay to make sure power has stabilized before + attempting to switch on USB on SX1 board. + +* Patch by Josef Wagner, 18 Mar 2004: + - Add support for MicroSys XM250 board (PXA255) + - Add support for MicroSys PM828 board (MPC8280) + - Add support for 32 MB Flash on PM825/826 + - new SDRAM refresh rate for PM825/PM826 + - added support for MicroSys PM520 (MPC5200) + - replaced Query by Identify command in CPU86/flash.c + to support 28F160F3B + +* Fix wrap around problem with udelay() on ARM920T + +* Add support for Macronix flash on TRAB board + +* Patch by Pierre Aubert, 15 Mar 2004: + Fix buffer overflow in IDE identification + +* Fix power-off of LCD for out-of-band temperatures on LWMON board + +* Remove redundand #define in IceCube.h + +* Patch by Steven Scholz, 27 Feb 2004: + - Adding get_ticks() and get_tbclk() for AT91RM9200 + - Many white space fixes in cpu/at91rm9200/interrupts.c + +* Patches by Steven Scholz, 20 Feb 2004: + some cleanup in AT91RM9200 related code + +* Patches by Travis Sawyer, 12 Mar 2004: + - Fix Gigabit Ethernet support for 440GX + - Add Gigabit Ethernet Support to MII PHY utilities + +* Patch by Brad Kemp, 12 Mar 2004: + Fixes for drivers/cfi_flash.c: + - Better support for x8/x16 implementations + - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE + - Added defines for AMD command and address constants + +* Patch by Leon Kukovec, 12 Mar 2004: + Fix get_dentfromdir() to correctly handle deleted dentries + +* Patch by George G. Davis, 11 Mar 2004: + Remove hard coded network settings in TI OMAP1610 H2 + default board config + +* Patch by George G. Davis, 11 Mar 2004: + add support for ADS GraphicsClient+ board. + +* Patch by Pierre Aubert, 11 Mar 2004: + - add bitmap command and splash screen support in cfb console + - add [optional] origin in the bitmap display command + +* Patch by Travis Sawyer, 11 Mar 2004: + Fix ocotea board early init interrupt setup. + +* Patch by Thomas Viehweger, 11 Mar 2004: + Remove redundand code; add PCI-specific bits to include/mpc8260.h + +* Patch by Stephan Linz, 09 Mar 2004 + - Add support for the SSV ADNP/ESC1 (Nios Softcore) + +* Patch by George G. Davis, 9 Mar 2004: + fix recent build failure for SA1100 target + +* Patch by Travis Sawyer, 09 Mar 2004: + Support native interrupt mode for the IBM440GX. + Previously it was running in 440GP compatibility mode. + +* Patch by Philippe Robin, 09 Mar 2004: + Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference + Platform support. + +* Patch by Masami Komiya, 08 Mar 2004: + Don't overwrite server IP address or boot file name + when the boot server does not return values + +* Patch by Tolunay Orkun, 5 Mar 2004: + Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC + +* Patch by Tolunay Orkun, 5 Mar 2004: + Fix early board initialization for Cogent CSB272 board + +* Patch by Ed Okerson, 3 Mar 2004: + fix CFI flash writes for little endian systems + +* Patch by Reinhard Meyer, 01 Mar 2004: + generalize USB and IDE support for MPC5200 with according + changes to IceCube.h and TOP5200.h + add Am29LV256 256 MBit FLASH support for TOP5200 boards + add info about USB and IDE to README + +* Patch by Yuli Barcohen, 4 Mar 2004: + Fix problems with GCC 3.3.x which changed handling of global + variables explicitly initialized to zero (now in .bss instead of + .data as before). + +* Patch by Leon Kukovec, 02 Mar 2004: + add strswab() to fix IDE LBA capacity, firmware and model numbers + on little endian machines + +* Patch by Masami Komiya, 02 Mar 2004: + - Remove get_ticks() from NFS code + - Add verification of RPC transaction ID + +* Patch by Pierre Aubert, 02 Mar 2004: + cleanup for IDE and USB drivers for MPC5200 + +* Patch by Travis Sawyer, 01 Mar 2004: + Ocotea: + - Add IBM PPC440GX Ref Platform support (Ocotea) + Original code by Paul Reynolds + Adapted to U-Boot and 440GX port + 440gx_enet.c: + - Add gracious handling of all Ethernet Pin Selections for 440GX + - Add RGMII selection for Cicada CIS8201 Gigabit PHY + ppc440.h: + - Add needed bit definitions + - Fix formatting + +* Patch by Carl Riechers, 1 Mar 2004: + Add PPC440GX prbdv0 divider to fix memory clock calculation. + +* Patch by Stephan Linz, 27 Feb 2004 + - avoid problems for targets without NFS download support + +* Patch by Rune Torgersen, 27 Feb 2004: + - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA) + - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF) + - Added support for 64bit strtoul (CFG_64BIT_STRTOUL) + +* Patch by Masami Komiya, 27 Feb 2004: + Fix rarpboot: add autoload by NFS + +* Patch by Dan Eisenhut, 26 Feb 2004: + fix flash_write return value in saveenv + +* Patch by Stephan Linz, 11 Dec 2003 + expand config.mk to avoid trigraph warnings on NIOS + +* Rename "BMS2003" board into "HMI10" + +* SX1 patches: use "serial#" for USB serial #; use redundand environment + storage; auto-set console on USB port (using preboot command) + +* Add support for SX1 mobile phone; add support for USB-based console + (enable with "setenv stdout usbtty; setenv stdin usbtty") + +* Fix LOWBOOT configuration for MPC5200 with DDR memory + +* Fix SDRAM timings for LITE5200 / IceCube board + +* Handle Auti-MDIX / connection status for INCA-IP + +* Fix USB problems when attempting to read 0 bytes + +* Patch by Travis Sawyer, 26 Feb 2004: + Fix broken compile for XPEDITE1K target. + +* Patch by Stephan Linz, 26 Feb 2004: + Bug fix for NFS code on NIOS targets + +* Patch by Stephen Williams, 26 Feb 2004: + Break up SystemACE reads of large block counts + +* Patch by Pierre Aubert, 26 Feb 2004 + add IDE support for MPC5200 + +* Patch by Masami Komiya, 26 Feb 2004: + add autoload via NFS + +* Patch by Stephen Williams + Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses + elsewhere in the source. + +* Patch by Steven Scholz, 25 Feb 2004: + - Timeouts in FPGA code should be based on CFG_HZ + - Minor cleanup in code for Altera FPGA ACEX1K + +* Patch by Steven Scholz, 25 Feb 2004: + Changed "Directory Hierarchy" section in README + +* Patch by Masami Komiya, 25 Feb 2004: + Reduce copy count in nfs_read_reply() of NFS code + +* Patch by Markus Pietrek, 24 Feb 2004: + NS9750 DevBoard added + +* Patch by Pierre Aubert, 24 Feb 2004 + add USB support for MPC5200 + +* Patch by Steven Scholz, 24 Feb 2004: + - fix MII commands to use values from last command + +* Patch by Torsten Demke, 24 Feb 2004: + Add support for the eXalion platform (SPSW-8240, F-30, F-300) + +* Patch by Rahul Shanbhag, 19 Feb 2004: + Fixes for for OMAP1610 board: + - shift some IRQ specific code to platform.S file + - remove duplicatewatchdog reset code from start.S + +* Make Auto-MDIX Support configurable on INCA-IP board + +* Fix license for mkimage tool + +* Patch by Masami Komiya, 24 Feb 2004: + Update NetBootFileXferSize in NFS code + +* Patch by Scott McNutt, 24 Feb 2004: + fix packet length in NFS code + +* Patch by Masami Komiy, 22 Feb 2004: + Add support for NFS for file download + +* Patch by Andrea Scian, 17 Feb 2004: + Add support for S3C44B0 processor and DAVE B2 board + +* Patch by Steven Scholz, 20 Feb 2004: + - Add support for MII commands on AT91RM9200 boards + - some cleanup in AT91RM9200 ethernet code + +* Patch by Peter Ryser, 20 Feb 2004: + Add support for the Xilinx ML300 platform + +* Patch by Stephan Linz, 17 Feb 2004: + Fix watchdog support for NIOS + +* Patch by Josh Fryman, 16 Feb 2004: + Fix byte-swapping for cfi_flash.c for different bus widths + +* Patch by Jon Diekema, 14 Jeb 2004: + Remove duplicate "FPGA Support" notes from the README file + +* Patches by Reinhard Meyer, 14 Feb 2004: + - update board/emk tree; use common flash driver + - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c + [adapted for other PPC CPUs -- wd] + - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c + +* Patch by Jon Diekema, 13 Feb 2004: + Call show_boot_progress() whenever POST "FAILED" is printed. + +* Patch by Nishant Kamat, 13 Feb 2004: + Add support for TI OMAP1610 H2 Board + Fixes for cpu/arm926ejs/interrupt.c + (based on Richard Woodruff's patch for arm925, 16 Oct 03) + Fix for a timer bug in OMAP1610 Innovator + Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2 + +* Patches by Stephan Linz, 12 Feb 2004: + - add support for NIOS timer with variable period preload counter value + - prepare POST framework support for NIOS targets + +* Patch by Denis Peter, 11 Feb 2004: + add POST support for the MIP405 board + +* Patch by Laurent Mohin, 10 Feb 2004: + Fix buffer overflow in common/usb.c + +* Patch by Tolunay Orkun, 10 Feb 2004: + Add support for Cogent CSB272 board + +* Patch by Thomas Elste, 10 Feb 2004: + Add support for NET+50 CPU and ModNET50 board + +* Patch by Sam Song, 10 Feb 2004: + Fix typos in cfi_flash.c + +* Patch by Leon Kukovec, 10 Feb 2004 + Fixed long dir entry slot id calculation in get_vfatname + +* Patch by Robin Gilks, 10 Feb 2004: + add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==, + !=, <>, <, >, <=, >=) + +* Fix problem with side effects in macros in include/usb.h + +* Patch by David Benson, 13 Nov 2003: + bug 841358 - fix TFTP download size limit + +* Fixing bug 850768: + improper flush_cache() in load_serial() + +* Fixing bug 834943: + MPC8540 - missing volatile declarations + +* Patch by Stephen Williams, 09 Feb 2004: + Add support for Xilinx SystemACE chip: + - New files common/cmd_ace.c and include/systemace.h + - Hook systemace support into cmd_fat and the partition manager + +* Patch by Travis Sawyer, 09 Feb 2004: + Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux + +* Patch by Travis Sawyer, 09 Feb 2004: + o 440GX: + - Fix PCI Indirect access for type 1 config cycles with ppc440. + - Add phymode for 440 enet + - fix pci pre init + o XPedite1K: + - Change board_pre_init to board_early_init_f + - Add user flash to bus controller setup + - Fix pci pre init + - Fix is_pci_host to check GPIO for monarch bit + - Force xpedite1k to pci conventional mode (via #define option) + +* Patch by Brad Kemp, 4 Feb 2004: + - handle the machine check that is generated during the PCI scans + on 82xx processors. + - define the registers used in the IMMR by the PCI subsystem. + +* Patch by Pierre Aubert, 03 Feb 2004: + cpu/mpc5xxx/start.S: copy MBAR into SPR311 + +* Patch by Jeff Angielski, 03 Feb 2004: + Fix copy & paste error in cpu/mpc8260/pci.c + +* Patch by Reinhard Meyer, 24 Jan 2004: + Fix typo in cpu/mpc5xxx/pci_mpc5200.c + +* Add Auto-MDIX support for INCA-IP + +* Some code cleanup + +* Patch by Josef Baumgartner, 10 Feb 2004: + Fixes for Coldfire port + +* Patch by Brad Kemp, 11 Feb 2004: + Fix CFI flash driver problems + +* Make sure to use a bus clock divider of 2 only when running TQM8xxM + modules at CPU clock frequencies above 66 MHz. + +* Optimize flash programming speed for LWMON (by another 100% :-) + +* Patch by Jian Zhang, 3 Feb 2004: + - Changed the incorrect FAT12BUFSIZE + - data_begin in fsdata can be negative. Changed it to be short. + +* Patches by Stephan Linz, 30 Jan 2004: + 1: - board/altera/common/flash.c:flash_erase(): + o allow interrupts befor get_timer() call + o check-up each erased sector and avoid unexpected timeouts + - board/altera/dk1c20/dk1s10.c:board_early_init_f(): + o enclose sevenseg_set() in cpp condition + - remove the ASMI configuration for DK1S10_standard_32 (never present) + - fix some typed in mistakes in the NIOS documentation + 2: - split DK1C20 configuration into several header files: + o two new files for each NIOS CPU description + o U-Boot related part is remaining in DK1C20.h + 3: - split DK1S10 configuration into several header files: + o two new files for each NIOS CPU description + o U-Boot related part is remaining in DK1S10.h + 4: - Add support for the Microtronix Linux Development Kit + NIOS CPU configuration at the Altera Nios Development Kit, + Stratix Edition (DK-1S10) + 5: - Add documentation for the Altera Nios Development Kit, + Stratix Edition (DK-1S10) + 6: - Add support for the Nios Serial Peripharel Interface (SPI) + (master only) + 7: - Add support for the common U-Boot SPI framework at + RTC driver DS1306 + +* Patch by Rahul Shanbhag, 28 Jan 2004: + Fix flash protection/locking handling for OMAP1610 innovator board. + +* Patch by Rolf Peukert, 28 Jan 2004: + fix flash write problems on CSB226 board (write with 32 bit bus width) + +* Patches by Mark Jonas, 16 Jan 2004: + - fix rounding error when calculating baudrates for MPC5200 PSCs + - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same + time which is not supported + +* Patch by Yuli Barcohen, 26 Jan 2004: + Allow bzip2 compression for small memory footprint boards + +* Patch by Brad Kemp, 21 Jan 2004: + Add support for CFI flash driver for both the Intel and the AMD + command sets. + +* Patch by Travis Sawyer, 20 Jan 2004: + Fix pci bridge auto enumeration of sibling p2p bridges. + +* Patch by Tolunay Orkun, 12 Jan 2004: + Add some delays as needed for Intel LXT971A PHY support + +* Patches by Stephan Linz, 09 Jan 2004: + - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c + - make DK1C20 board configuration related to ASMI conform to + documentation + +* Patch by Anders Larsen, 09 Jan 2004: + + ARM memory layout fixes: the abort-stack is now set up in the + correct RAM area, and the BSS is zeroed out as it should be. + + Furthermore, the magic variables 'armboot_end' and 'armboot_end_data' + of the linker scripts are replaced by '__bss_start' and '_end', + resp., which is a further step to eliminate unnecessary differences + between the implementation of the CPU architectures. + +* Patch by liang a lei, 9 Jan 2004: + Fix Intel 28F128J3 ID in include/flash.h + +* Patch by Masami Komiya, 09 Jan 2004: + add support for TB0229 board (NEC VR4131 MIPS processor) + +* Patch by Leon Kukovec, 12 Dec 2003: + changed extern __inline__ into static __inline__ in + include/linux/byteorder/swab.h + +* Patch by Travis Sawyer, 30 Dec 2003: + Add support for IBM PPC440GX. Multiple EMAC Ethernet devices, + select MDI port based on enabled EMAC device. + Add support for XES Inc XPedite1000 440GX + base PrPMC board. + +* Patch by Wolter Kamphuis, 15 Dec 2003: + made CONFIG_SILENT_CONSOLE usable on all architectures + +* Disable date command on TQM866M - there is no RTC on MPC866 + +* Fix variable CPU clock for MPC859/866 systems for low CPU clocks + +* Implement adaptive SDRAM timing configuration based on actual CPU + clock frequency for INCA-IP; fix problem with board hanging when + switching from 150MHz to 100MHz + +* Add PCMCIA CS support for BMS2003 board + +* Add variable CPU clock for MPC859/866 systems (so far only TQM866M): + see doc/README.MPC866 for details; + implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866; + calculate CPU clock frequency from PLL register values. + +* Add support for 128 MB RAM on TQM8xxL/M modules + +* Fix PS/2 keyboard problem caused by statically initialized variable + pointing to a location in flash + +* Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130. + +* The PS/2 mux on the BMS2003 board needs 450 ms after power on + before we can access it; add delay in case we are faster (with no + CF card inserted) + +* Cleanup of some init functions + +* Make sure SCC Ethernet is always stopped by the time we boot Linux + to avoid Linux crashes by early packets coming in. + +* Accelerate flash accesses on LWMON board by using buffered writes + +* Fix typo in Makefile; + fix problem with PARTNUM detection + +* Patch by Reinhard Meyer, 09 Jan 2004: + - add RTC support for MPC5200 based boards (requires RTC_XTAL) + +* Add support for IDE LED on BMS2003 board + (exclusive with status LED!) + +* Add support for PS/2 keyboard (used with PS/2 multiplexor on + BMS2003 board) + +* Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004: + Add common files for "emk" boards + +* Add a common get_ram_size() function and modify the the + board-specific files to invoke that common implementation. + +====================================================================== +Changes for U-Boot 1.0.1: +====================================================================== + +* Set default clock for INCA-IP to 150 MHz + +* Make BMS2003 use a separate config file to avoid #ifdef mess; + add I2C support; add support for DS1337 RTC + +* Add CompactFlash support for BMS2003 board + +* Add support for status LED on BMS2003 board + +* Patch by Scott McNutt, 02 Jan 2004: + Add support for the Nios Active Serial Memory Interface (ASMI) + on Cyclone devices + +* Patch by Andrea Marson, 16 Dec 2003: + Add support for the PPChameleon ME and HI modules + +* Patch by Yuli Barcohen, 22 Dec 2003: + Add support for Motorola DUET ADS board (MPC87x/88x) + +* Patch by Robert Schwebel, 15 Dec 2003: + add support for cramfs (uses JFFS2 command interface) + +* Patches by Stephan Linz, 11 Dec 2003: + - more documentation for NIOS port + - new struct nios_pio_t, struct nios_spi_t + - Reconfiguration for NIOS Development Kit DK1C20: + o move board related code from board/dk1c20 + to board/altera/dk1c20 + o create a new common source path board/altera/common + and move generic flash access stuff into it + o change/expand configuration file DK1C20.h + - Add support for NIOS Development Kit DK1S10 + - Add status LED support for NIOS systems + - Add dual 7-segment LED support for Altera NIOS DevKits + +* Patch by Ronen Shitrit, 10 Dec 2003: + Add support for the Marvell DB64360 / DB64460 development boards + +* Patch by Detlev Zundel, 10 Dec 2003: + fix dependency problem in examples/Makefile + +* Patch by Denis Peter, 8 Dec 2003 + - add support for the PATI board (MPC555) + - add SPI support for the MPC5xx + +* Patch by Anders Larsen, 08 Dec 2003: + add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG + to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target; + cleanup some redundand #defines + +* Patch by André Schwarz, 8 Dec 2003: + fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM): + - TX and RX deskriptors must be quad-word aligned + - does not work with only one TX deskriptor + - standard reset method does not work + +* Patch by Masami Komiya, 08 Dec 2003: + add RTL8139 ethernet driver + +* Patches by Ed Okerson, 07 Dec 2003: + - fix ethernet for the AU1x00 processors in little-endian mode. + - extend memsetup.S for the AU1x00 processors in BE and LE modes + +* Minor code cleanup (coding style) + +* Patch by Reinhard Meyer, 30 Dec 2003: + - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE, + - added CONFIG_PHY_ADDR to include/configs/IceCube.h, + - turned debug print of PHY registers into a function (called in two places) + - added support for EMK MPC5200 based modules + +* Fix MPC8xx PLPRCR_MFD_SHIFT typo + +* Add support for TQM866M modules + +* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash) + +* Fix a few compiler warnings + +* Patch by Reinhard Meyer, 28 Dec 2003: + Add initial support for TOP5200 board + +* Make CPU clock on ICA-IP board controllable by a "cpuclk" + environment variable which can set to "100", "133", or "150". The + CPU clock will be configured accordingly upon next reboot. Other + values are ignored. In case of an invalid or undefined "cpuclk" + value, the compile-time default CPU clock speed will be used. + +* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory + window that is used to access the UART registers by the Linux driver) + +* Patch by Reinhard Meyer, 20 Dec 2003: + Fix clock calculation for the MPC5200 for higher clock frequencies + (above 2**32 / 10 = 429.5 MHz). + +* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration + +* Fix IceCube CLKIN configuration (it's 33.000000MHz) + +* Add new configuration for IceCube board with DDR memory + +* Update TRAB memory configurations + +* Add JFFS2 support for INCA-IP board + +* Patch by Bill Hargen, 09 Dec 2003: + - BUBINGA405EP: changed flash driver to protect top sector containing + first instruction. + - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM. + - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access). + - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1). + - 405EP: added/fixed support for "reginfo" command. + - 4xx: removed spurious MII error messages on "mii info" command. + +* Patch by Bernhard Kuhn, 28 Nov 2003: + add support for Coldfire CPU + add support for Motorola M5272C3 and M5282EVB boards + +* Patch by Pierre Aubert, 24 Nov 2003: + - add a return value for the fpga command + - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT + is defined. If ide_preinit fails, ide_init is aborted. + - fix an endianess problem in fat.h + +* Patch by Wolter Kamphuis, 05 Dec 2003: + Add support for SNMC's QS850/QS823/QS860T boards + +* Patch by Yuli Barcohen, 3 Dec 2003: + "revive" U-Boot support for old Motorola MPC860ADS board + +* Patch by Cam(ilo?), 03 Dec 2003: + make examples build even with broken Montavista objcopy + +* Patch by Pavel Bartusek, 27 Nov 2003: + fix conversion problem with "bootretry" evironment variable + +* Patch by Andre Schwarz, 24 Nov 2003: + add support for mvblue (mvBlueLYNX and mvBlueBOX) boards + +* Patch by Pavel Bartusek, 21 Nov 2003: + set ZMII bridge speed on 440 + +* Patch by Anders Larsen, 17 Nov 2003: + Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h + +* Patches by David Müller, 14 Nov 2003: + - board/mpl/common/common_util.c + * implement support for BZIP2 compressed images + * various cleanups (printf -> puts, ...) + - board/mpl/common/flash.c + * report correct errors to upper layers + * check the erase fail and VPP low bits in status reg + - board/mpl/vcma9/cmd_vcma9.c + - board/mpl/vcma9/flash.c + * various cleanups (printf -> puts, ...) + - common/cmd_usb.c + * fix typo in comment + - cpu/arm920t/usb_ohci.c + * support for S3C2410 is missing in #if line + - drivers/cs8900.c + * reinit some registers in case of error (cable missing, ...) + - fs/fat/fat.c + * support for USB/MMC devices is missing in #if line + - include/configs/MIP405.h + - include/configs/PIP405.h + * enable BZIP2 support + * enlarge malloc space to 1MiB because of BZIP2 support + - include/configs/VCMA9.h + * enable BZIP2 support + * enlarge malloc space to 1MiB because of BZIP2 support + * enable USB support + - lib_arm/armlinux.c + * change calling convention of ARM Linux kernel as + described on http://www.arm.linux.org.uk/developer/booting.php + +* Patch by Thomas Lange, 14 Nov 2003: + Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to + support all these AMD boards. + +* Patch by Thomas Lange, 14 Nov 2003: + Workaround for mips au1x00 physical memory accesses (the au1x00 + uses a 36 bit bus internally and cannot access physical memory + directly. Use the uncached SDRAM address instead of the physical + one.) + +* Patch by Xue Ligong (Joe), 13 Nov 2003: + add Realtek 8019 ethernet driver + +* Patch by Yuli Barcohen, 13 Nov 2003: + MPC826xADS/PQ2FADS cleanup + +* Patch by Anders Larsen, 12 Nov 2003: + Update README to mark the PORTIO commands non-standard + +* Patch by Nicolas Lacressonnière, 12 Nov 2003: + update for for Atmel AT91RM9200DK development kit: + - support for environment variables in DataFlash + - Atmel DataFlash AT45DB1282 support + +* Patch by Jeff Carr, 11 Nov 2003: + add support for new version of 8270 processors + +* Patches by George G. Davis, 05 Nov 2003: + - only pass the ARM linux initrd tag to the kernel when an initrd + is actually present + - update omap1510inn configuration file + +* Patches by Stephan Linz, 3 Nov 2003: + - more endianess fixes for LAN91C111 driver + - CFG_HZ configuration patch for NIOS Cyclone board + +* Patch by Stephan Linz, 28 Oct 2003: + fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c + +* Patch by Steven Scholz, 20 Oct 2003: + - make "mii info " show infor for PHY at "addr" only + - Endian fix for miiphy_info() + +* Patch by Gleb Natapov, 19 Sep 2003: + Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c + +* Patch by Anders Larsen, 17 Sep 2003: + Bring ARM memory layout in sync with the documentation: + stack and malloc-heap are now located _below_ the U-Boot code + +* Accelerate booting on TRAB board: read and check autoupdate image + headers first instead of always reading the whole images. + +* Fix type in MPC5XXX code (pointed out by Victor Wren) + +* Enabled password check on RMU board + +* Fix configuration problem with IceCube in LOWBOOT configuration: + envrionment got embedded, corrupting the image layout. + +* Fix NEC display names (it's 6440 [for 640x480], not 6640). + +* Added BMS2003 board + add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display + +* Fix flash driver for TRAB board (must use Unlock Bypass Reset + command to exit Unlock Bypass Mode); adjust timings for flash, SRAM + and CPLD + +* Use "-fPIC" instead of "-mrelocatable" to prevent problems with + recent tools + +* Add checksum verification to 'imls' command + +* Add bd_info fields needed for 4xx Linux I2C driver + +* Patch by Martin Krause, 4 Nov. 2003: + Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap) + +* Print used network interface when CONFIG_NET_MULTI is set + +* Patch by Bernhard Kuhn, 28 Oct 2003: + Add low boot support for MPC5200 + +* Fix problem with dual PCMCIA support (NSCU) + +* Fix MPC5200 I2C initialization function + +====================================================================== +Changes for U-Boot 1.0.0: +====================================================================== + +* Fix parameter passing to standalone images with bootm command + +* Patch by Kyle Harris, 30 Oct 2003: + Fix build errors for ixdp425 board + +* Patch by David M. Horn, 29 Oct 2003: + Fixes to build under CYGWIN + +* Get IceCube MGT5100 working (again) + +* Fix problems in memory test on some boards (which was not + non-destructive as intended) + +* Patch by Gary Jennejohn, 28 Oct 2003: + Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack + to prevent stack overflow on ARM systems + +* Patch by Stephan Linz, 28 Oct 2003: + fix init sequence error for NIOS port + +* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name + +* Add CONFIG_VERSION_VARIABLE to TRAB configuration + +* Patch by Xiao Xianghua, 23 Oct 2003: + small patch for mpc85xx + +* Fix small problem in MPC5200 I2C driver + +* Fix FCC3 support on ATC board + +* Correct header printing for multi-image files in do_bootm() + +* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED + +* Fix PCI problems on PPChameleon board + +* Patch by Steven Scholz, 18 Oct 2003: + Fix AT91RM9200 ethernet driver + +* Patch by Nye Liu, 17 Oct 2003: + Fix typo in include/mpc8xx.h + +* Patch by Richard Woodruff, 16 Oct 03: + Fixes for cpu/arm925/interrupt.c + - Initialize timestamp & lastdec vars. + - fix timestamp overflows. + - fix lastdec overflow. + - smarter normalization to allow udelay() below 1ms to work. + +* Patch by Scott McNutt, 16 Oct + add networking support for the Altera Nios Development Kit, + Cyclone Edition (DK-1C20) + +* Patch by Jon Diekema, 14 Oct 2003: + add hint about doc/README.silent to README file + +* Add CompactFlash support for NSCU + +* Fix PCI problems on PPChameleonEVB + +* TRAB auto-update: Base decision if we have to strip the image + header on image type as encoded in the header + (include image type patch by Martin Krause, 17 Oct 2003) + +* Patches by Xianghua Xiao, 15 Oct 2003: + + - Added Motorola CPU 8540/8560 support (cpu/85xx) + - Added Motorola MPC8540ADS board support (board/mpc8540ads) + - Added Motorola MPC8560ADS board support (board/mpc8560ads) + +* Fix flash timings on TRAB board + +* Make sure HUSH is initialized for running auto-update scripts + +* Make 5200 reset command _really_ reset the board, without running + any other code after it + +* Fix errors with flash erase when range spans across banks + that are mapped in reverse order + +* Fix flash mapping and display on P3G4 board + +* Patch by Kyle Harris, 15 Jul 2003: + - add support for Intel IXP425 CPU + - add support for IXDP425 eval board + +* Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent + for more information + +* Patch by Steven Scholz, 10 Oct 2003 + - Add support for Altera FPGA ACEX1K + +* Patches by Thomas Lange, 09 Oct 2003: + - fix cmd_ide.c for non ppc boards (read/write functions did not + add ATA base address) + - fix for shannon board + - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code + - Endian swap ATA identity for all big endian CPUs, not just PPC + - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize + args to linux + - add support for dbau1x00 board (MIPS32) + +* Patch by Sangmoon Kim, 07 Oct 2003: + add support for debris board + +* Patch by Martin Krause, 09 Oct 2003: + Fixes for TRAB board + - /board/trab/rs485.c: correct baudrate + - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in + udelay(); fix some timing problems with adc controller + - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power; + modify commands: touch and buzzer + +* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE + (quick & dirty workaround for rogue pointer problem in get_vfatname()); + Use direct function calls for auto_update instead of hush commands + +* Patch by Scott McNutt, 04 Oct 2003: + - add support for Altera Nios-32 CPU + - add support for Nios Cyclone Development Kit (DK-1C20) + +* Patch by Steven Scholz, 29 Sep 2003: + - A second parameter for bootm overwrites the load address for + "Standalone Application" images. + - bootm sets environment variable "filesize" to the resulting + (uncompressed) data length for "Standalone Application" images + when autostart is set to "no". Now you can do something like + if bootm $fpgadata $some_free_ram ; then + fpga load 0 $some_free_ram $filesize + fi + +* Patch by Denis Peter, 25 Sept 2003: + add support for the MIP405 Rev. C board + +* Patch by Yuli Barcohen, 25 Sep 2003: + add support for Zephyr Engineering ZPC.1900 board + +* Patch by Anders Larsen, 23 Sep 2003: + add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only + implemented for the x86 architecture) + +* Patch by Sangmoon Kim, 23 Sep 2003: + fix pll_pci_to_mem_multiplier table for MPC8245 + +* Patch by Anders Larsen, 22 Sep 2003: + enable timed autoboot on PXA + +* Patch by David Müller, 22 Sep 2003: + - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver + returns correct libgcc file path + - "latency" reduction of busy-loop waiting to improve "U-Boot" boot + time on s3c24x0 systems + +* Patch by Jon Diekema, 19 Sep 2003: + - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet + link state to the fault LED. + - In NetLoop, make the Fault LED reflect the link status. The link + status gets updated on entry, and on timeouts. + +* Patch by Anders Larsen, 18 Sep 2003: + allow mkimage to build and run on Cygwin-hosted systems + +* Patch by Frank Müller, 18 Sep 2003: + use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in + cpu/mpc8xx/fec.c + +* Patch by Pantelis Antoniou, 16 Sep 2003: + add tool to compute fileds in the PLPRCR register for MPC86x + +* Use IH_TYPE_FILESYSTEM for TRAB "disk" images. + +* Fix build problems under FreeBSD + +* Add generic filesystem image type + +* Make fatload set filesize environment variable + +* enable basic / medium / high-end configurations for PPChameleonEVB + board; fix NAND code + +* enable TFTP client code to specify to the server the desired + timeout value (see RFC-2349) + +* Improve SDRAM setup for TRAB board + +* Suppress all output with splashscreen configured only if "splashimage" + is set + +* Fix problems with I2C support for mpc5200 + +* Adapt TRAB configuration and auto_update to new memory layout + +* Add configuration for wtk board + +* Add support for the Sharp LQ065T9DR51U LCD display + +* Patch by Rune Torgersen, 17 Sep 2003: + - Fixes for MPC8266 default config + - Allow eth_loopback_test() on 8260 to use a subset of the FCC's + +* Patches by Jon Diekema, 17 Sep 2003: + - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and + env_common.c) + - sbc8260 tweaks + - adjust "help" output + +* Patches by Anders Larsen, 17 Sep 2003: + - fix spelling errors + - set GD_FLG_DEVINIT flag only after device function pointers + are valid + - Allow CFG_ALT_MEMTEST on systems where address zero isn't + writeable + - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs + - trigger watchdog while waiting in serial driver + +* Add auto-update code for TRAB board using USB memory sticks, + support new configuration with more memory + +* disable MPC5200 bus pipelining as workaround for bus contention + +* Modify XLB arbiter priorities on MPC5200 so all devices use same + priority; configure critical interrupts to be handled like external + interrupts + +* Make IPB clock on MGT5100/MPC5200 configurable in board config file; + go back to 66 MHz for stability + +* Patches by Jon Diekema, 15 Sep 2003: + - add description for missing CFG_CMD_* entries in the README file + - sacsng tweaks + +* Patch by Gleb Natapov, 14 Sep 2003: + enable watchdog support for all MPC824x boards that have a watchdog + +* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the + "Non-octet Aligned Frame" errors we see at 100 Mbps + +* Patch by Sharad Gupta, 14 Sep 2003: + fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL]) + +* Patch by llandre, 11 Sep 2003: + update configuration for PPChameleonEVB board + +* Patch by David Müller, 13 Sep 2003: + various changes to VCMA9 board specific files + +* Add I2C support for MGT5100 / MPC5200 + +* Patch by Rune Torgersen, 11 Sep 2003: + Changed default memory option on MPC8266ADS to NOT be Page Based + Interleave, since this doesn't work very well with the standard + 16MB DIMM + +* Patch by George G. Davis, 12 Sep 2003: + fix Makefile settings for sk98 driver + +* Patch by Stefan Roese, 12 Sep 2003: + - new boards added: DP405, HUB405, PLU405, VOH405 + - some esd boards updated + - cpu/ppc4xx/sdram.c: disable memory controller before setting + first values + - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems + +* Patch by Martin Krause, 11 Sep 2003: + add burn-in tests for TRAB board + +* Enable instruction cache on MPC5200 board + +* Patch by Denis Peter, 11 Sep 2003: + - fix USB data pointer assignment for bulk only transfer. + - prevent to display erased directories in FAT filesystem. + +* Change output format for NAND flash - make it look like for other + memory, too + +====================================================================== +Changes for U-Boot 0.4.8: +====================================================================== + +* Add I2C and RTC support for RMU board + +* Patches by Denis Peter, 9 Sep 2003: + add FAT support for IDE, SCSI and USB + +* Patches by Gleb Natapov, 2 Sep 2003: + - cleanup of POST code for unsupported architectures + - MPC824x locks way0 of data cache for use as initial RAM; + this patch unlocks it after relocation to RAM and invalidates + the locked entries. + +* Patch by Gleb Natapov, 30 Aug 2003: + new I2C driver for mpc107 bridge. Now works from flash. + +* Patch by Dave Ellis, 11 Aug 2003: + - JFFS2: fix typo in common/cmd_jffs2.c + - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option + - JFFS2: remove node version 0 warning + - JFFS2: accept JFFS2 PADDING nodes + - SXNI855T: add AM29LV800 support + - SXNI855T: move environment from EEPROM to flash + - SXNI855T: boot from JFFS2 in NOR or NAND flash + +* Patch by Bill Hargen, 11 Aug 2003: + fixes for I2C on MPC8240 + - fix i2c_write routine + - fix iprobe command + - eliminates use of global variables, plus dead code, cleanup. + +* Add support for USB Mass Storage Devices (BBB) + (tested with USB memory sticks only) + +* Avoid flicker on TRAB's VFD + +* Add support for SK98xx driver + +* Add PCI support for SL8245 board + +* Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB) + or 1 x AM29LV652 (two LV065 in one chip = 16 MB); + Run IPB at 133 Mhz; adjust the MII clock frequency accordingly + +* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) + to allow for more accurate baudrate settings + (error now 0.7% at 115 kbps, instead of 3.5% before) + +* Patch by Andreas Mohr, 4 Sep 2003: + Fix a lot of spelling errors + +* Add support for PPChameleon Eval Board + +* Add support for P3G4 board + +* Fix problem with MGT5100 FEC driver: add "early" MAC address + initialization + +* Patch by Yuli Barcohen, 7 Aug 2003: + check BCSR to detect if the board is configured in PCI mode + +====================================================================== +Changes for U-Boot 0.4.7: +====================================================================== + +* Patch by Raghu Krishnaprasad, 7 Aug 2003: + add support for Adder II MPC852T module + +* Patch by George G. Davis, 19 Aug 2003: + fix TI Innovator/OMAP1510 pin configs + +* Patches by Kshitij, 18 Aug 2003 + - add support for arm926ejs cpu core + - add support for TI OMAP 1610 Innovator Board + +* Patch by Yuli Barcohen, 14 Aug 2003: + add support for bzip2 uncompression + +* Add GCC library to examples/Makefile so GCC utility functions will + be resolved, too + +* Add I2C and RTC support for RMU board using software I2C driver + (because of better response to iprobe command); fix problem with + "reset" command + +* Patch by Matthias Fuchs, 28 Aug 2003: + Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to + CONFIG_BOOTP_MAKS (see README). + +* Fix ICU862 environment problem + +* Fix RAM size detection for RMU board + +* Implement "reset" for MGT5100/MPC5200 systems + +====================================================================== +Changes for U-Boot 0.4.6: +====================================================================== + +* Make Ethernet autonegotiation on INCA-IP work for all clock rates; + allow selection of clock frequency as "make" target + +* Implement memory autosizing code for IceCube boards + +* Configure network port on INCA-IP for autonegotiation + +* Fix overflow problem in network timeout code + +* Patch by Richard Woodruff, 8 Aug 2003: + Allow crc32 to be used at address 0x000 (crc32_no_comp, too). + +====================================================================== +Changes for U-Boot 0.4.5: +====================================================================== + +* Update for TQM board defaults: + disable clocks_in_mhz, enable boot count limit + +* Removed tools/gdb from "make all" target. Added make target "gdbtools" + in toplevel directory instead. Removed astest.c from tools/gdb because + it is no longer relevant. + +* Fix PCI support for MPC5200 / IceCube Board + +* Map ISP1362 USB OTG controller for NSCU board + +* Patch by Brad Parker, 02 Aug 2003: + fix sc520_cdp problems + +* Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements) + +* Allow erase command to cross flash bank boundaries + +* Patch by Scott McNutt, 21 Jul 2003: + Add support for LynuxWorks Kernel Downloadable Images (KDIs). + Both LynxOS and BlueCat linux KDIs are supported. + +* Patch by Richard Woodruff, 25 Jul 2003: + use more reliable reset for OMAP/925T + +* Patch by Nye Liu, 25 Jul 2003: + fix typo in mpc8xx.h + +* Patch by Richard Woodruff, 24 Jul 2003: + Fixes for cmd_nand.c: + - Fixed null dereferece which could result in incorrect ECC values. + - Added support for devices with no Ready/Busy signal hooked up. + - Added OMAP1510 read/write protect handling. + - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock + for non-JFFS2. + - Switched default ECC to be JFFS2. + +* Allow crc32 to be used at address 0x000 + +* Provide consistent interface to standalone applications to access + the 'global_data' structure + Provide a doc/README.standalone more useful to users/developers. + +* Make IceCube MGT5100 FEC driver work + +* Implement new mechanism to export U-Boot's functions to standalone + applications: instead of using (PPC-specific) system calls we now + use a jump table; please see doc/README.standalone for details + +* Patch by Dave Westwood, 24 Jul 2003: + added support for Unity OS (a proprietary OS) + +* Patch by Detlev Zundel, 23 Jul 2003: + add "imls" command to print flash table of contents + +* Fix cold boot detection for log buffer reset + +* Return error for invalid length specifiers with "cp.X" etc. + +* Fix startup problem on MIPS + +* Allow for CONFIG_SPLASH_SCREEN even when no explicit + bitmap support is configured + +* Patch by Bill Hargen, 18 Jul 2003: + - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c + +* Patch by Denis Peter, 18 Jul 2003: + - fix memory configuration for MIP405T + - fix printout of baudrate for "loadb " + +* Cleanup of TQM82xx configurations; use "official" board types + to make selection easier. + +* Patch by Martin Krause, 17 Jul 2003: + add delay to get I2C working with "imm" command and s3c24x0_i2c.c + +* Patch by Richard Woodruff, 17 July 03: + - Fixed bug in OMAP1510 baud rate divisor settings. + +* Patch by Nye Liu, 16 July 2003: + MPC860FADS fixes: + - add MPC86xADS support (uses MPC86xADS.h) + - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T) + o PLPRCR changes + o BRG changes (EXTAL/XTAL restricted to 10MHz) + o don't trust gclk() software measurement by default, depend on + CONFIG_8xx_GCLK_FREQ + - add DRAM SIMM not installed detection + - use more "correct" SDRAM initialization sequence + - allow different SDRAM sizes (8xxADS has 8M) + - default DER is 0 + - remove unused MAMR defines from FADS860T.h (all done in fads.c) + - rename MAMR/MBMR defines to be more consistent. Should eventually + be merged into MxMR to better reflect the PowerQUICC datasheet. + +* Patch by Yuli Barcohen, 16 Jul 2003: + support new Motorola PQ2FADS-ZU evaluation board which replaced + MPC8260ADS and MPC8266ADS + +====================================================================== +Changes for U-Boot 0.4.4: +====================================================================== + +* Add support for IceCube board (with MGT5100 and MPC5200 CPUs) + +* Add support for MGT5100 and MPC5200 processors + +* Patch by Lutz Dennig, 15 Jul 2003: + update for R360MPI board + +====================================================================== +Changes for U-Boot 0.4.3: +====================================================================== + +* Patches by Kshitij, 04 Jul 2003 + - added support for arm925t cpu core + - added support for TI OMAP 1510 Innovator Board + +* Patches by Martin Krause, 14 Jul 2003: + - add I2C support for s3c2400 systems (trab board) + - (re-) add "ping" to command table + +* Fix handling of "slow" POST routines + +* Patches by Yuli Barcohen, 13 Jul 2003: + - Correct flash and JFFS2 support for MPC8260ADS + - fix PVR values and clock generation for PowerQUICC II family + (8270/8275/8280) + +* Patch by Bernhard Kuhn, 08 Jul 2003: + - add support for M68K targets + +* Patch by Ken Chou, 3 Jul: + - Fix PCI config table for A3000 + - Fix iobase for natsemi.c + (PCI_BASE_ADDRESS_0 is the IO base register for DP83815) + +* Allow to enable "slow" POST routines by key press on power-on +* Fix temperature dependend switching of LCD backlight on LWMON +* Tweak output format for LWMON + +* Patch by Stefan Roese, 11 Jul 2003: + - Fix bug in CONFIG_VERSION_VARIABLE. + - AR405 config updated. + - OCRTC/ORSG: bsp command added. + - ASH405 bsp update. + +====================================================================== +Changes for U-Boot 0.4.2: +====================================================================== + +* Add support for NSCU board + +* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules + +* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML + mirror bit flash on TQM8xxM modules + +* Patch by Kenneth Johansson, 30 Jun 2003: + get rid of MK_CMD_ENTRY macro; update doc/README.command + +* Patch by Seb James, 30 Jun 2003: + Improve documentation of I2C configuration in README + +* Fix problems with previous log buffer "fixes" + +* Fix minor help text issues + +* "log append" did not append a newline + +====================================================================== +Changes for U-Boot 0.4.1: +====================================================================== + +* Fix some missing commands, cleanup header files + (autoscript, bmp, bsp, fat, mmc, nand, portio, ...) + +* Rewrite command lookup and help command (fix problems with bubble + sort when sorting command name list). Minor cleanup here and there. + +* Merge from "stable branch", tag LABEL_2003_06_28_1800-stable: + - Allow to call sysmon function interactively + - PIC on LWMON board needs delay after power-on + - Add missing RSR definitions for MPC8xx + - Improve log buffer handling: guarantee clean reset after power-on + - Add support for EXBITGEN board (aka "genie") + - Add support for SL8245 board + +* Code cleanup: + - remove trailing white space, trailing empty lines, C++ comments, etc. + - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) + +* Patches by Kenneth Johansson, 25 Jun 2003: + - major rework of command structure + (work done mostly by Michal Cendrowski and Joakim Kristiansen) + +====================================================================== +Changes for U-Boot 0.4.0: +====================================================================== + +* Patches by Robert Schwebel, 26 Jun 2003: + - csb226 configuration updated + - credits for logodl port updated + - innokom configuration updated + - logodl tree update, still with coding style inconsistencies + - added OCM for ppc405 warning to README + +* Patch by Pantelis Antoniou, 25 Jun 2003: + update NetVia with V2 board support + +* Header file cleanup for ARM + +* Patch by Murray Jensen, 24 Jun 2003: + - make sure to use only U-boot provided header files + - fix problems with ".rodata.str1.4" section as used by GCC-3.x + +* Patch by Stefan Roese, 24 Jun 2003: + - Update esd ASH405 board files. + - Update esd DASA_SIM config file. + - Add ping command to some esd boards. + +* Patch by Yuli Barcohen, 23 Jun 2003: + Update for MPC8260ADS board + +* Patch by Murray Jensen, 23 Jun 2003: + - cleanup of GCC 3.x compiler warnings + +* Patch by Rune Torgersen, 4 Jun 2003: + add large memory support for MPC8266ADS board + +* Patch by Richard Woodruff, 19 June 03: + - Enabled standard u-boot device abstraction for ARM + - Enabled console device for ARM + - Initilized bi_baudrate for ARM + +* Patch by Bill Hargen, 23 Apr 2003: + fix byte order for 824x I2C addresses (write op) + +* Patch by Murray Jensen, 20 Jun 2003: + - hymod update + - cleanup (especially for gcc-3.x compilers) + +* Patch by Tom Guilliams, 20 Jun 2003: + added CONFIG_750FX support for IBM 750FX processors + +* Patch by Devin Crumb, 02 Apr 2003: + Fix clock divider rounding problem in drivers/serial.c + +* Patch by Richard Woodruff, 19 June 03: + - Fixed smc91c111 driver to sync with the u-boot environment + (driver/smc91c111.c). + - Added eth_init error return check in NetLoop (net/net.c). + +* Patch by Ken Chou, 19 June 2003: + Added support for A3000 SBC board (Artis Microsystems Inc.) + +* Patches by Murray Jensen, 17 Jun 2003: + - Hymod board database mods: add "who" field and new xilinx chip types + - provide new "init_cmd_timeout()" function so code external to + "common/main.c" can use the "reset_cmd_timeout()" function before + entering the main loop + - add DTT support for adm1021 (new file dtt/adm1021.c; config + slightly different. see include/configs/hymod.h for an example + (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and + CFG_DTT_ADM1021 defined) + - add new "eeprom_probe()" function which has similar args and + behaves in a similar way to "eeprom_read()" etc. + - add 8260 FCC ethernet loopback code (new "eth_loopback_test()" + function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST) + - gdbtools copyright update + - ensure that set_msr() executes the "sync" and "isync" instructions + after the "mtmsr" instruction in cpu/mpc8260/interrupts.c + - 8260 I/O ports fix: Open Drain should be set last when configuring + - add SIU IRQ defines for 8260 + - allow LDSCRIPT override and OBJCFLAGS initialization: change to + config.mk to allow board configurations to override the GNU + linker script, selected via the LDSCRIPT, make variable, and to + give an initial value to the OBJCFLAGS make variable + - 8260 i2c enhancement: + o correctly extends the timeout depending on the size of all + queued messages for both transmit and receive + o will not continue with receive if transmit times out + o ensures that the error callback is done for all queued tx + and rx messages + o correctly detects both tx and rx timeouts, only delivers one to + the callback, and does not overwrite an earlier error + o logic in i2c_probe now correct + - add "vprintf()" function so that "panic()" function can be + technically correct + - many Hymod board changes + +* Patches by Robert Schwebel, 14 Jun 2003: + - add support for Logotronic DL datalogger board + - cleanup serial line after kermit binary download + - add debugX macro (debug level support) + - update mach-types.h to latest arm.linux.org.uk master list. + +* Patches by David Müller, 12 Jun 2003: + - rewrite of the S3C24X0 register definitions stuff + - "driver" for the built-in S3C24X0 RTC + +* Patches by Yuli Barcohen, 12 Jun 2003: + - Add MII support and Ethernet PHY initialization for MPC8260ADS board + - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset + configuration word supplied by FPGA on some MPC8260ADS boards + +* Patch by Pantelis Antoniou, 10 Jun 2003: + Unify status LED interface + +* Add support for DS12887 RTC; add RTC support for ATC board + +* Patch by Nicolas Lacressonniere, 11 Jun 2003: + Modifications for Atmel AT91RM9200DK ARM920T based development kit + - Add Atmel DataFlash support for reading and writing. + - Add possibility to boot a Linux from DataFlash with BOOTM command. + - Add Flash detection on Atmel AT91RM9200DK + (between Atmel AT49BV1614 and AT49BV1614A flashes) + - Replace old Ethernet PHY layer functions + - Change link address + +* Patch by Frank Smith, 9 Jun 2003: + use CRIT_EXCEPTION for machine check on 4xx + +* Patch by Detlev Zundel, 13 Jun 2003: + added implementation of the "carinfo" command in cmd_immap.c + +* Fix CONFIG_NET_MULTI support in include/net.h + +* Patches by Kyle Harris, 13 Mar 2003: + - Add FAT partition support + - Add command support for FAT + - Add command support for MMC + ---- + - Add Intel PXA support for video + - Add Intel PXA support for MMC + ---- + - Enable MMC and FAT for lubbock board + - Other misc changes for lubbock board + +* Patch by Robert Schwebel, April 02, 2003: + fix for SMSC91111 driver + +* Patch by Vladimir Gurevich, 04 Jun 2003: + make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option + +* Patch by Stefan Roese, 05 Jun 2003: + - PPC4xx: Fix bug for initial stack in data cache as pointed out by + Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in + data cache can be used even if the chip select is in use. + - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count + (see README for further description). + - Changed config files of CONFIG_EEPRO100 boards to use the + CFG_RX_ETH_BUFFER define. + +* Add support for RMU board + +* Add support for TQM862L at 100/50 MHz + +* Patch by Pantelis Antoniou, 02 Jun 2003: + major reconstruction of networking code; + add "ping" support (outgoing only!) + +* Patch by Denis Peter, 04 June 2003: + add support for the MIP405T board + +* Patches by Udi Finkelstein, 2 June 2003: + - Added support for custom keyboards, initialized by defining a + board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD . + - Added support for the RBC823 board. + - cpu/mpc8xx/lcd.c now automatically calculates the + Horizontal Pixel Count field. + +* Fix alignment problem in BOOTP (dhcp_leasetime option) + [pointed out by Nicolas Lacressonnière, 2 Jun 2003] + +* Patch by Mark Rakes, 14 May 2003: + add support for Intel e1000 gig cards. + +* Patch by Nye Liu, 3 Jun 2003: + fix critical typo in MAMR definition (include/mpc8xx.h) + +* Fix requirement to align U-Boot image on 16 kB boundaries on PPC. + +* Patch by Klaus Heydeck, 2 Jun 2003 + Minor changes for KUP4K configuration + +* Patch by Marc Singer, 29 May 2003: + Fixed rarp boot method for IA32 and other little-endian CPUs. + +* Patch by Marc Singer, 28 May 2003: + Added port I/O commands. + +* Patch by Matthew McClintock, 28 May 2003 + - cpu/mpc824x/start.S: fix relocation code when booting from RAM + - minor patches for utx8245 + +* Patch by Daniel Engström, 28 May 2003: + x86 update + +* Patch by Dave Ellis, 9 May 2003 + 27 May 2003: + add nand flash support to SXNI855T configuration + fix/extend nand flash support: + - fix 'nand erase' command so does not erase bad blocks + - fix 'nand write' command so does not write to bad blocks + - fix nand_probe() so handles no flash detected properly + - add doc/README.nand + - add .jffs2 and .oob options to nand read/write + - add 'nand bad' command to list bad blocks + - add 'clean' option to 'nand erase' to write JFFS2 clean markers + - make NAND read/write faster + +* Patch by Rune Torgersen, 23 May 2003: + Update for MPC8266ADS board + +* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length + instead CFG_MONITOR_LEN is now only used to determine _at_compile_ + _time_ (!) if the environment is embedded within the U-Boot image, + or in a separate flash sector. + +* Cleanup CFG_DER #defines in config files (wd maintained only) + +* Fix data abort exception handling for arm920t CPU + +* Fix alignment problems with flash driver for TRAB board + +* Patch by Donald White, 21 May 2003: + fix calculation of base address in pci_hose_config_device() + +* Fix bug in command line parsing: "cmd1;cmd2" is supposed to always + execute "cmd2", even if "cmd1" fails. Note that this is different + to "run var1 var2" where the contents of "var2" will NOT be + executed when a command in "var1" fails. + +* Add zero-copy ramdisk support (requires corresponding kernel support!) + +* Patch by Kyle Harris, 20 May 2003: + In preparation for an ixp port, rename cpu/xscale and arch-xscale + into cpu/pxa and arch-pxa. + +* Patch by Stefan Roese, 23 May 2003: + - IBM PPC405EP port added. + - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not + UART0) is used as default U-Boot console. PPC4xx only! + - esd ASH405 board added (PPC405EP based). + - BUBINGA405EP board added (PPC405EP based - IBM Eval Board). + - esd CPCI405AB board added. + - esd PMC405 board added. + - Update of some esd boards. + +* Patch by Denis Peter, 19 Mai 2003: + add support for the MIP405-3 board + +* Patch by Dave Ellis, 22 May 2003: + Fix problem with only partially cleared .bss segment + +* Patch by Rune Torgersen, 12 May 2003: + get PCI to work on a MPC8266ADS board; incorporate change to + cpu/mpc8260/pci.c to enable overrides of PCI memory parameters + +* Patch by Nye Liu, 1 May 2003: + minor patches for the FADS8xx + +* Patch by Thomas Schäfer, 28 Apr 2003: + Fix SPD handling for 256 ECC DIMM on Walnut + +* Add support for arbitrary bitmaps for TRAB's VFD command; + allow to pass boot bitmap addresses in environment variables; + allow for zero boot delay + +* Patch by Christian Geißinger, 19 May 2002: + On TRAB: wait until the dummy byte has been completely sent + +* Patch by David Updegraff, 22 Apr 2003: + update for CrayL1 board + +* Patch by Pantelis Antoniou, 21 Apr 2003: + add boot support for ARTOS (a proprietary OS) + +* Patch by Steven Scholz, 11 Apr 2003: + Add support for RTC DS1338 + +* Patch by Rod Boyce, 24 Jan 2003: + Fix counting of extended partitions in diskboot command + +* Patch by Christophe Lindheimer, 20 May 2003: + allow the use of CFG_LOADS when CFG_NO_FLASH is set + +* Fix SDRAM timing on Purple board + +* Add support for CompactFlash on ATC board + (includes support for Intel 82365 and compatible PC Card controllers, + and Yenta-compatible PCI-to-CardBus controllers) + +* Patch by Mathijs Haarman, 08 May 2003: + Add lan91c96 driver (tested on Lubbock and custom PXA250 board only) + +* Fix problem with usage of "true" (undefined in current versions of bfd.h) + +* Add support for Promess ATC board + +* Patch by Keith Outwater, 28 Apr 2003: + - Miscellaneous corrections and additions to GEN860T board specific code. + - Added GEN860_SC variant to GEN860T. + - Miscellaneous corrections to GEN860T documentation. + - Correct duplicate entry in U-Boot CREDITS file. + - Add GEN860T_SC entry in MAINTAINERS file. + - Update CREDITS file with GEN860T_SC info. + +* Update Smiths Aerospace addresses in MAINTAINERS file + +* Fix error handling in hush's version of "run" command + +* LWMON extensions: + - Splashscreen support + - modem support + - sysmon support + - temperature dependend enabling of LCD + +* Allow booting from old "PPCBoot" disk partitions + +* Add support for TQM8255 Board / MPC8255 CPU + +====================================================================== +Changes for U-Boot 0.3.1: +====================================================================== + +* Make sure Block Lock Bits get cleared in R360MPI flash driver + +* MPC823 LCD driver: Fill color map backwards, to allow for steady + display when Linux takes over + +* Patch by Erwin Rol, 27 Feb 2003: + Add support for RTEMS (this time for real). + +* Add support for "bmp info" and "bmp display" commands to load + bitmap images; this can be used (for example in a "preboot" + command) to display a splash screen very quickly after poweron. + +* Add support for 133 MHz clock on INCA-IP board + +* Patch by Lutz Dennig, 10 Apr 2003: + Update for R360MPI board + +* Add new meaning to "autostart" environment variable: + If set to "no", a standalone image passed to the + "bootm" command will be copied to the load address + (and eventually uncompressed), but NOT be started. + This can be used to load and uncompress arbitrary + data. + +* Patch by Stefan Roese, 10 Apr 2003: + Changed DHCP client to use IP address from server option field #54 + from the OFFER packet in the server option field #54 in the REQUEST + packet. This fixes a problem using a Windows 2000 DHCP server, + where the DHCP-server is not the TFTP-server. + +* Set max brightness for MN11236 displays on TRAB board + +* Add support for TQM862L modules + +====================================================================== +Changes for U-Boot 0.3.0: +====================================================================== + +* Patch by Arun Dharankar, 4 Apr 2003: + Add IDMA example code (tested on 8260 only) + +* Add support for Purple Board (MIPS64 5Kc) + +* Add support for MIPS64 5Kc CPUs + +* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS + +* Patch by Denis Peter, 04 Apr 2003: + - update MIP405-4 board + +* Patch by Stefan Roese, 4 Apr 2003: + - U-Boot version environment variable "ver" added + (CONFIG_VERSION_VARIABLE). + - Changed PPC405GPr version from A to B. + - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1. + +* Patches by Denis Peter, 03 April 2003: + - fix PCI IRQs on MPL boards + - fix two more un-relocated pointer problems + +* Fix behaviour of "run" command: + - print error message iv variable does not exist + - terminate processing of arguments in case of error + +* Patches by Peter Figuli, 10 Mar 2003 + - Add support for BTUART on PXA platform + - Add support for WEP EP250 (PXA) board + +* Fix flash problems on INCA-IP; add tool to allow bruning images to + flash using a BDI2000 + +* Implement fix for I2C Edge Conditions problem for all boards that + use the bit-banging driver (common/soft_i2c.c) + +* Patch by Martin Winistoerfer, 23 Mar 2003 + - Add port to MPC555/556 microcontrollers + - Add support for cmi customer board with + Intel 28F128J3A, 28F320J3A or 28F640J3A flash. + +* Patch by Rick Bronson, 28 Mar 2003: + - fix common/cmd_nand.c + +* Patch by Arun Dharankar, 24 Mar 2003: + - add threads / scheduler example code + +* Add patches by Robert Schwebel, 31 Mar 2003: + - add ctrl-c support for kermit download + - align bdinfo output on ARM + - csb226 board: bring in sync with innokom/memsetup.S + - csb226 board: fix MDREFR handling + - misc doc fixes / extensions + - innokom board: cleanup, MDREFR fix in memsetup.S, config update + - add BOOT_PROGRESS to armlinux.c + +* Add CPU ID, version, and clock speed for INCA-IP + +* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board: + - fix SRAM and SDRAM memory sizing + - add status LED support + - add MAC address for second (SCC1) ethernet port + +* Update default environment for TQM8260 board + +* Patch by Rick Bronson, 16 Mar 2003: + - Add NAND flash support for reading, writing, and erasing NAND + flash (certain forms of which are called SmartMedia). + - Add support for Atmel AT91RM9200DK ARM920T based development kit. + +* Patches by Robert Schwebel, 19 Mar 2003: + - use arm-linux-gcc as default compiler for ARM + - fix i2c fixup code + - fix missing baudrate setting + - added $loadaddr / CFG_LOAD_ADDR support to loadb + - moved "ignoring trailing characters" _before_ u-boot wants to + print out diagnostics messages; removes bogus characters at the + end of transmission + +* Patch by John Zhan, 18 Mar 2003: + Add support for SinoVee Microsystems SC8xx boards + +* Patch by Rolf Offermanns, 21 Mar 2003: + ported the dnp1110 related changes from the current armboot cvs to + current u-boot cvs. smc91111 does not work. problem marked in + smc91111.c, grep for "FIXME". + +* Patch by Brian Auld, 25 Mar 2003: + Add support for STM flash chips on ebony board + +* Add PCI support for MPC8250 Boards (PM825 module) + +* Patch by Stefan Roese, 25 Mar 2003: + - PCI405 update. + +* Patch by Stefan Roese, 20 Mar 2003: + - CPCI4052 update (support for revision 3). + - Set edge conditioning circuitry on PPC405GPr for compatibility + to existing PPC405GP designs. + - Clip udiv to 5 bits on PPC405 (serial.c). + +* Extend INCAIP board support: + - add automatic RAM size detection + - add "bdinfo" command + - pass flash address and size to Linux kernel + - switch to 150 MHz clock + +* Avoid flicker on the TRAB's VFD by synchronizing the enable with + the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100 + boards, version 153 for Rev. 200 boards). + +* Patch by Vladimir Gurevich, 12 Mar 2003: + Fix relocation problem of statically initialized string pointers + in common/cmd_pci.c + +* Patch by Kai-Uwe Blöm, 12 Mar 2003: + Cleanup & bug fixes for JFFS2 code: + - the memory mangement was broken. It caused havoc on malloc by + writing beyond the block boundaries. + - the length calculation for files was wrong, sometimes resulting + in short file reads. + - data copying now optionally takes fragment version numbers into + account, to avoid copying from older data. + See doc/README.JFFS2 for details. + +* Patch by Josef Wagner, 12 Mar 2003: + - 16/32 MB and 50/80 MHz support with auto-detection for IP860 + - ETH05 and BEDBUG support for CU824 + - added support for MicroSys CPC45 + - new BOOTROM/FLASH0 and DOC base for PM826 + +* Patch by Robert Schwebel, 12 Mar 2003: + Fix the chpart command on innokom board + +* Name cleanup: + mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h + s/PPCBoot/U-Boot/ in some files + s/pImage/uImage/ in some files + +* Patch by Detlev Zundel, 15 Jan 2003: + Fix '' command line quoting + +* Patch by The LEOX team, 19 Jan 2003: + - add support for the ELPT860 board + - add support for Dallas ds164x RTC + +* Patches by David Müller, 31 Jan 2003: + - minimal setup for CardBus bridges + - add EEPROM read/write support in the CS8900 driver + - add support for the builtin I2C controller in the Samsung s3c24x0 chips + - add support for MPL's VCMA9 (Samsung s3c2410 based) board + +* Patch by Steven Scholz, 04 Feb 2003: + add support for RTC DS1307 + +* Patch by Reinhard Meyer, 5 Feb 2003: + fix PLPRCR/SCCR init sequence on 8xx to allow for + changes of EBDF by software + +* Patch by Vladimir Gurevich, 07 Feb 2003: + "API-compatibility patch" for 4xx I2C driver + +* TRAB fixes / extensions: + - Restore VFD brightness as saved in environment + - add support for Fujitsu flashes + - make sure both buzzers are turned off (drive low level) + +* Patches by Robert Schwebel, 06 Mar 2003: + - fix bug in BOOTP code (must use NetCopyIP) + - update of CSB226 port + - clear BSS segment on XScale + - added support for i2c_init_board() function + - update to the Innokom plattform + +* Extend support for redundand environments for configurations where + environment size < sector size + +* Patch by Rune Torgersen, 13 Feb 2003: + Add support for Motorola MPC8266ADS board + +* Patch by Kyle Harris, 19 Feb 2003: + patches for the Intel lubbock board: + memsetup.S - general cleanup (based on Robert's csb226 code) + flash.c - overhaul, actually works now + lubbock.c - fix init funcs to return proper value + +* Patch by Kenneth Johansson, 26 Feb 2003: + - Fixed off by one in RFTA calculation. + - No need to abort when LDF is lower than we can program it's only + minimum timing so clamp it to what we can do. + - Takes function pointer to function for reading the spd_nvram. Usefull + for faking data or hardcode a module without the nvram. + - fix other user for above change + - fix some comments. + +* Patches by Brian Waite, 26 Feb 2003: + - fix port for evb64260 board + - fix PCI for evb64260 board + - fix PCI scan + +* Patch by Reinhard Meyer, 1 Mar 2003: + Add support for EMK TOP860 Module + +* Patch by Yuli Barcohen, 02 Mar 2003: + Add SPD EEPROM support for MPC8260ADS board + +* Patch by Robert Schwebel, 21 Jan 2003: + - Add support for Innokom board + - Don't complain if "install" fails + - README cleanup (remove duplicated lines) + - Update PXA header files + +* Add documentation for existing POST code (doc/README.POST) + +* Patch by Laudney Ren, 15 Jan 2003: + Fix handling of redundand environment in "tools/envcrc.c" + +* Patch by Detlev Zundel, 28 Feb 2003: + Add bedbug support for 824x systems + +* Add support for 16 MB flash configuration of TRAB board + +* Patch by Erwin Rol, 27 Feb 2003: + Add support for RTEMS + +* Add image information to README + +* Patch by Stefan Roese, 18 Feb 2003: + CPCIISER4 configuration updated. + +* Patch by Stefan Roese, 17 Feb 2003: + Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port). + +* Patch by Stefan Roese, 13 Feb 2003: + Add "pcidelay" environment variable (in ms, enabled via + CONFIG_PCI_BOOTDELAY). + PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after + RST# to respond to configuration cycles (33MHz -> 1s). + +* Fix dual PCMCIA slot support (when running with just one + slot populated) + +* Add VFD type detection to trab board + +* extend drivers/cs8900.c driver to synchronize ethaddr environment + variable with value in the EEPROM + +* Patch by Stefan Roese, 10 Feb 2003: + Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c) + +* Add support for MIPS32 4Kc CPUs + +* Add support for INCA-IP Board + +====================================================================== +Changes for U-Boot 0.2.2: +====================================================================== + +* Add dual ethernet support on PM826 + +* Add support for LXT971 PHY on PM826 + +* Patch by Tord Andersson, 16 Jan 2003: + Fix flash sector count for TQM8xxL + +* Fix I2C EEPROM problem on ICU862 board (would only write the first + 16 bytes out of each 32 byte block) + +====================================================================== +Changes for U-Boot 0.2.1: +====================================================================== + +* Add support for V37 board + (patch by Jón Benediktsson, 11 Dec 2002) + +* Update baudrate in bd_info when it gets changed + +* Add watchdog trigger points while waiting for serial port + (so far only 8xx -- needed on LWMON with 100ms watchdog) + +* Improve command line tool to access the U-Boot's environment + (figuration of the utility, using a config file) + +* Add single quote support for (old) command line parser + +* Switch LWMON board default config from FRAM to EEPROM; + in POST, EEPROM shows up on 8 addresses + +====================================================================== +Changes for U-Boot 0.2.0: +====================================================================== + +* Use 1-byte-read instead of -write for iprobe() function + Add i2c commands to PM826 config + +* extend I2C POST code: check for list on known addresses + +* Improve log buffer code; use "loglevel" to decide which messages + to log on the console, too (like in Linux); get rid of "logstart" + +* Add command line tool to access the U-Boot's environment + (board-specific for TRAB now, to be fixed later) + +* Patch by Hans-Joerg Frieden, 06 Dec 2002 + Fix misc problems with AmigaOne support + +* Patch by Chris Hallinan, 3 Dec 2002: + minor cleanup to the MPC8245 EPIC driver + +* Patch by Pierre Aubert , 28 Nov 2002 + Add support for external (SIU) interrupts on MPC8xx + +* Patch by Pierre Aubert , 28 Nov 2002 + Fix nested syscalls bug in standalone applications + +* Patch by David Müller, 27 Nov 2002: + fix output of "pciinfo" command for CardBus bridge devices. + +* Fix bug in TQM8260 board detection - boards got stuck when board ID + was not readable + +* Add LED indication for IDE activity on KUP4K board + +* Fix startup problems with VFD display on TRAB + +* Patch by Pierre Aubert, 20 Nov 2002 + Add driver for Epson SED13806 graphic controller. + Add support for BMP logos in cfb_console driver. + +* Added support for both PCMCIA slots (at the same time!) on MPC8xx + +* Patch by Rod Boyce, 21 Nov 2002: + fix PCMCIA on MBX8xx board + +* Patch by Pierre Aubert , 21 Nov 2002 + Add CFG_CPM_POST_WORD_ADDR to make the offset of the + bootmode word in DPRAM configurable + +* Patch by Daniel Engström, 18 Nov 2002: + Fixes for x86 port (mostly strings issues) + +* Patch by Ken Chou, 18 Nov 2002: + Fix for natsemi NIC cards (DP83815) + +* Patch by Pierre Aubert, 19 Nov 2002: + fix a bug for the MII configuration, and some warnings + +* Patch by Thomas Frieden, 13 Nov 2002: + Add code for AmigaOne board + (preliminary merge to U-Boot, still WIP) + +* Patch by Jon Diekema, 12 Nov 2002: + - Adding URL for IEEE OUI lookup + - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED + being defined. + - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and + root-on-nfs macros are designed to switch how the default boot + method gets defined. + +* Patch by Daniel Engström, 13 Nov 2002: + Add support for i386 architecture and AMD SC520 board + +* Patch by Pierre Aubert, 12 Nov 2002: + Add support for DOS filesystem and booting from DOS floppy disk + +* Patch by Jim Sandoz, 07 Nov 2002: + Increase number of network RX buffers (PKTBUFSRX in + "include/net.h") for EEPRO100 based boards (especially SP8240) + which showed "Receiver is not ready" errors when U-Boot was + processing the receive buffers slower than the network controller + was filling them. + +* Patch by Andreas Oberritter, 09 Nov 2002: + Change behaviour of NetLoop(): return -1 for errors, filesize + otherwise; return code 0 is valid an means no file loaded - in this + case the environment still gets updated! + +* Patches by Jon Diekema, 9 Nov 2002: + - improve ADC/DAC clocking on the SACSng board to align + the failing edges of LRCLK and SCLK + - sbc8260 configuration tweaks + - add status LED support for 82xx systems + - wire sspi/sspo commands into command handler; improved error + handlering + - add timestamp support and alternate memory test to the + SACSng configuration + +* Patch by Vince Husovsky, 7 Nov 2002: + Add "-n" to linker options to get rid of "Not enough room for + program headers" problem + +* Patch by David Müller, 05 Nov 2002 + Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ + so we can use an already existing name + +* Patch by Pierre Aubert, 05 Nov 2002 + Hardware relatied improvments in FDC boot code + +* Patch by Holger Schurig, 5 Nov 2002: + Make the PXA really change it's frequency + +* Patch by Pierre Aubert, 05 Nov 2002 + Add support for slave serial Spartan 2 FPGAs + +* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet + drivers + +* Add support for log buffer which can be passed to Linux kernel's + syslog mechanism; used especially for POST results. + +* Patch by Klaus Heydeck, 31 Oct 2002: + Add initial support for kup4k board + +* Patch by Robert Schwebel, 04 Nov 2002: + - use watchdog to reset PXA250 systems + - added progress callbacks to (some of the) ARM code + - update for Cogent CSB226 board + +* Add support for FPS860 board + +* Patch by Guillaume Alexandre,, 04 Nov 2002: + Improve PCI access on 32-bits Compact PCI bus + +* Fix mdelay() on TRAB - this was still the debugging version with + seconds instead of ms. + +* Patch by Robert Schwebel, 1 Nov 2002: + XScale related cleanup (affects all ARM boards) + +* Cleanup of names and README. + +====================================================================== +Notes for U-Boot 0.1.0: +====================================================================== + +This is the initial version of "Das U-Boot", the Universal Boot Loader. + +It is based on version 2.0.0 (the "Halloween Release") of PPCBoot. +For information about the history of the project please see the +PPCBoot project page at http://sourceforge.net/projects/ppcboot + +====================================================================== diff --git a/u-boot/COPYING b/u-boot/COPYING new file mode 100755 index 0000000..f616ab9 --- /dev/null +++ b/u-boot/COPYING @@ -0,0 +1,298 @@ + NOTE! This copyright does *not* cover the so-called "standalone" +applications that use U-Boot services by means of the jump table +provided by U-Boot exactly for this purpose - this is merely +considered normal use of U-Boot, and does *not* fall under the +heading of "derived work". + + The header files "include/image.h" and "include/asm-*/u-boot.h" +define interfaces to U-Boot. Including these (unmodified) header +files in another file is considered normal use of U-Boot, and does +*not* fall under the heading of "derived work". + + Also note that the GPL below is copyrighted by the Free Software +Foundation, but the instance of code that it refers to (the U-Boot +source code) is copyrighted by me and others who actually wrote it. +-- Wolfgang Denk + +======================================================================= + + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. 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You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS diff --git a/u-boot/CREDITS b/u-boot/CREDITS new file mode 100755 index 0000000..f91fa3e --- /dev/null +++ b/u-boot/CREDITS @@ -0,0 +1,458 @@ +# +# Parts of the development effort for this project have been +# sponsored by SIEMENS AG, Austria. Thanks to SIEMENS for +# supporting an Open Source project! +# +# +# This is at least a partial credits-file of individual people that +# have contributed to the U-Boot project. It is sorted by name and +# formatted to allow easy grepping and beautification by scripts. +# The fields are: name (N), email (E), web-address (W), PGP key ID +# and fingerprint (P), description (D), and snail-mail address (S). +# Thanks, +# +# Wolfgang Denk +#---------- + +N: Dr. Bruno Achauer +E: bruno@exet-ag.de +D: Support for NetBSD (both as host and target system) + +N: Guillaume Alexandre +E: guillaume.alexandre@gespac.ch +D: Add PCIPPC6 configuration + +N: Swen Anderson +E: sand@peppercon.de +D: ERIC Support + +N: Pantelis Antoniou +E: panto@intracom.gr +D: NETVIA & NETPHONE board support, ARTOS support. +D: Support for Silicon Turnkey eXpress XTc + +N: Pierre Aubert +E: +D: Support for RPXClassic board + +N: Yuli Barcohen +E: yuli@arabellasw.com +D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards. +D: Support for Zephyr Engineering ZPC.1900 board. +D: Support for Interphase iSPAN boards. +D: Support for Analogue&Micro Adder boards. +D: Support for Analogue&Micro Rattler boards. +W: http://www.arabellasw.com + +N: Jerry van Baren +E: +D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test. + +N: Pavel Bartusek +E: +D: Reiserfs support +W: http://www.elinos.com + +N: Andre Beaudin +E: +D: PCMCIA, Ethernet, TFTP + +N: Jon Benediktsson +E: jonb@marel.is +D: Support for Marel V37 board + +N: Raphael Bossek +E: raphael.bossek@solutions4linux.de +D: 8xxrom-0.3.0 + +N: Cliff Brake +E: cliff.brake@gmail.com +D: Port to Vibren PXA255 IDP platform +W: http://www.vibren.com +W: http://bec-systems.com + +N: Rick Bronson +E: rick@efn.org +D: Atmel AT91RM9200DK and NAND support + +N: David Brown +E: DBrown03@harris.com +D: Extensions to 8xxrom-0.3.0 + +N: Oliver Brown +E: obrown@adventnetworks.com +D: Port to the gw8260 board + +N: Curt Brune +E: curt@cucy.com +D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC) +D: Added support for ESPD-Inc. EVB4510 Board +W: http://www.cucy.com + +N: Jonathan De Bruyne +E: jonathan.debruyne@siemens.atea.be +D: Port to Siemens IAD210 board + +N: Ken Chou +E: kchou@ieee.org +D: Support for A3000 SBC board + +N: Conn Clark +E: clark@esteem.com +D: ESTEEM192E support + +N: Magnus Damm +E: damm@opensource.se +D: 8xxrom + +N: George G. Davis +E: gdavis@mvista.com +D: Board ports for ADS GraphicsClient+ and Intel Assabet + +N: Arun Dharankar +E: ADharankar@ATTBI.Com +D: threads / scheduler example code + +N: Kári Davíðsson +E: kd@flaga.is +D: FLAGA DM Support + +N: Wolfgang Denk +E: wd@denx.de +D: U-Boot initial version, continuing maintenance, ARMBoot merge +W: http://www.denx.de + +N: Dan A. Dickey +E: ddickey@charter.net +D: FADS Support + +N: James F. Dougherty +E: jfd@GigabitNetworks.COM +D: Port to the MOUSSE board + +N: Dave Ellis +E: DGE@sixnetio.com +D: EEPROM Speedup, SXNI855T port + +N: Thomas Elste +E: info@elste.org +D: Port for the ModNET50 Board, NET+50 CPU Port +W: http://www.imms.de + +N: Daniel Engström +E: daniel@omicron.se +D: x86 port, Support for sc520_cdp board + +N: Dr. Wolfgang Grandegger +E: wg@denx.de +D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards +W: www.denx.de + +N: Peter Figuli +E: peposh@etc.sk +D: Support for WEP EP250 (PXA) board + +N: Thomas Frieden +E: ThomasF@hyperion-entertainment.com +D: Support for AmigaOne + +N: Frank Gottschling +E: fgottschling@eltec.de +D: Support for ELTEC MHPC/BAB7xx/ELPPC boards, cfb-console, i8042, SMI LynxEM +W: www.eltec.de + +N: Marius Groeger +E: mgroeger@sysgo.de +D: MBX Support, board specific function interface, EST SBC8260 support; initial support for StrongARM (LART), ARM720TDMI (implementa A7) +W: www.elinos.com + +N: Kirk Haderlie +E: khaderlie@vividimage.com +D: Added TFTP to 8xxrom (-> 0.3.1) + +N: Chris Hallinan +E: clh@net1plus.com +D: DHCP Support + +N: Anne-Sophie Harnois +E: Anne-Sophie.Harnois@nextream.fr +D: Port to Walnut405 board + +N: Andreas Heppel +E: aheppel@sysgo.de +D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!] + +N: August Hoeraendl +E: august.hoerandl@gmx.at +D: Support for the logodl board (PXA2xx) + +N: Josh Huber +E: huber@alum.wpi.edu +D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series. +W: http://www.mclx.com/ + +H: Stuart Hughes +E: stuarth@lineo.com +D: Port to MPC8260ADS board + +H: Rich Ireland +E: r.ireland@computer.org +D: FPGA device configuration driver + +N: Gary Jennejohn +E: garyj@jennejohn.org, gj@denx.de +D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB" +W: www.denx.de + +N: Murray Jensen +E: Murray.Jensen@csiro.au +D: Initial 8260 support; GDB support +D: Port to Cogent+Hymod boards; Hymod Board Database + +N: Yoo. Jonghoon +E: yooth@ipone.co.kr +D: Added port to the RPXlite board + +N: Mark Jonas +E: mark.jonas@freescale.com +D: Support for Freescale Total5200 platform +W: http://www.mobilegt.com/ + +N: Sam Song +E: samsongshu@yahoo.com.cn +D: Port to the RPXlite_DW board + +N: Brad Kemp +E: Brad.Kemp@seranoa.com +D: Port to Windriver ppmc8260 board + +N: Sangmoon Kim +E: dogoil@etinsys.com +D: Support for debris board + +N: Frederick W. Klatt +E: fred.klatt@windriver.com +D: Support for Wind River SBC8540/SBC8560 boards + +N: Thomas Koeller +E: tkoeller@gmx.net +D: Port to Motorola Sandpoint 3 (MPC8240) + +N: Raghu Krishnaprasad +E: Raghu.Krishnaprasad@fci.com +D: Support for Adder-II MPC852T evaluation board +W: http://www.forcecomputers.com + +N: Bernhard Kuhn +E: bkuhn@metrowerks.com +D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards + +N: Prakash Kumar +E: prakash@embedx.com +D Support for Intrinsyc CERF PXA250 board. + +N: Thomas Lange +E: thomas@corelatus.se +D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes + +N: Marc Leeman +E: marc.leeman@barco.com +D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) +W: www.barco.com + +N: The LEOX team +E: team@leox.org +D: Support for LEOX boards, DS164x RTC +W: http://www.leox.org + +N: Leif Lindholm +E: leif.lindholm@i3micro.com +D: Support for AMD dbau1550 board. + +N: Stephan Linz +E: linz@li-pro.net +D: Support for Nios Stratix Development Kit (DK-1S10) +D: Support for SSV ADNP/ESC1 (Nios Cyclone) +W: http://www.li-pro.net + +N: Raymond Lo +E: lo@routefree.com +D: Support for DOS partitions + +N: Dan Malek +E: dan@embeddedalley.com +D: FADSROM, the grandfather of all of this +D: Support for Silicon Turnkey eXpress XTc + +N: Andrea "llandre" Marson +E: andrea.marson@dave-tech.it +D: Port to PPChameleonEVB board +W: www.dave-tech.it + +N: Reinhard Meyer +E: r.meyer@emk-elektronik.de +D: Port to EMK TOP860 Module + +N: Jay Monkman +E: jtm@smoothsmoothie.com +D: EST SBC8260 support + +N: Frank Morauf +E: frank.morauf@salzbrenner.com +D: Support for Embedded Planet RPX Super Board + +N: David Müller +E: d.mueller@elsoft.ch +D: Support for Samsung ARM920T SMDK2410 eval board + +N: Scott McNutt +E: smcnutt@psyent.com +D: Support for Altera Nios-32 CPU +D: Support for Altera Nios-II CPU +D: Support for Nios Cyclone Development Kit (DK-1C20) +W: http://www.psyent.com + +N: Rolf Offermanns +E: rof@sysgo.de +D: Initial support for SSV-DNP1110, SMC91111 driver +W: www.elinos.com + +N: John Otken +E: jotken@softadvances.com +D: Support for AMCC Luan 440SP board + +N: Tolunay Orkun +E: torkun@nextio.com +D: Support for Cogent CSB272 & CSB472 boards + +N: Keith Outwater +E: keith_outwater@mvis.com +D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC) + +N: Frank Panno +E: fpanno@delphintech.com +D: Support for Embedded Planet EP8260 Board + +N: Denis Peter +E: d.peter@mpl.ch +D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ... +D: Support for PIP405 board +D: Support for MIP405 board + +N: Dave Peverley +E: dpeverley@mpc-data.co.uk +W: http://www.mpc-data.co.uk +D: OMAP730 P2 board support + +N: Bill Pitts +E: wlp@mindspring.com +D: BedBug embedded debugger code + +N: Daniel Poirot +E: dan.poirot@windriver.com +D: Support for the Wind River sbc405, sbc8240 board +W: http://www.windriver.com + +N: Stefan Roese +E: stefan.roese@esd-electronics.com +D: AMCC PPC401/403/405GP Support; Windows environment support + +N: Erwin Rol +E: erwin@muffin.org +D: boot support for RTEMS + +N: Paul Ruhland +E: pruhland@rochester.rr.com +D: Port to Logic Zoom LH7A40x SDK board(s) + +N: Neil Russell +E: caret@c-side.com +D: Author of LiMon-1.4.2, which contributed some ideas + +N: Travis B. Sawyer +E: travis.sawyer@sandburst.com +D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea) + +N: Paolo Scaffardi +E: arsenio@tin.it +D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more + +N: Robert Schwebel +E: r.schwebel@pengutronix.de +D: Support for csb226, logodl and innokom boards (PXA2xx) + +N: Art Shipkowski +E: art@videon-central.com +D: Support for NetSilicon NS7520 + +N: Yasushi Shoji +E: yashi@atmark-techno.com +D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board + +N: Kurt Stremerch +E: kurt@exys.be +D: Support for Exys XSEngine board + +N: Andrea Scian +E: andrea.scian@dave-tech.it +D: Port to B2 board +W: www.dave-tech.it + +N: Rob Taylor +E: robt@flyingpig.com +D: Port to MBX860T and Sandpoint8240 + +N: Erik Theisen +E: etheisen@mindspring.com +D: MBX8xx and many other patches + +N: Jim Thompson +E: jim@musenki.com +D: Support for MUSENKI board + +N: Rune Torgersen +E: +D: Support for Motorola MPC8266ADS board + +N: Greg Ungerer +E: greg.ungerer@opengear.com +D: Support for ks8695 CPU, and OpenGear cmXXXX boards + +N: David Updegraff +E: dave@cray.com +D: Port to Cray L1 board; DHCP vendor extensions + +N: Christian Vejlbo +E: christian.vejlbo@tellabs.com +D: FADS860T ethernet support + +N: Robert Whaley +E: rwhaley@applieddata.net +D: Port to ARM PXA27x adsvix SBC + +N: Martin Winistoerfer +E: martinwinistoerfer@gmx.ch +D: Port to MPC555/556 microcontrollers and support for cmi board + +N: Ming-Len Wu +E: minglen_wu@techware.com.tw +D: Motorola MX1ADS board support +W: http://www.techware.com.tw/ + +N: Xianghua Xiao +E: x.xiao@motorola.com +D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards. + +N: John Zhan +E: zhanz@sinovee.com +D: Support for SinoVee Microsystems SC8xx SBC + +N: Alex Zuepke +E: azu@sysgo.de +D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM +W: www.elinos.com + +N: James MacAulay +E: james.macaulay@amirix.com +D: Suppport for Amirix AP1000 +W: www.amirix.com diff --git a/u-boot/Makefile b/u-boot/Makefile new file mode 100755 index 0000000..64f8de5 --- /dev/null +++ b/u-boot/Makefile @@ -0,0 +1,505 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +VERSION = 1 +PATCHLEVEL = 1 +SUBLEVEL = 4 +EXTRAVERSION = +U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) +VERSION_FILE = include/version_autogenerated.h + +HOSTARCH := $(shell uname -m | \ + sed -e s/i.86/i386/ \ + -e s/sun4u/sparc64/ \ + -e s/arm.*/arm/ \ + -e s/sa110/arm/ \ + -e s/powerpc/ppc/ \ + -e s/macppc/ppc/) + +HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \ + sed -e 's/\(cygwin\).*/cygwin/') + +export HOSTARCH HOSTOS + +# Deal with colliding definitions from tcsh etc. +VENDOR= + +######################################################################### + +TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi) +export TOPDIR + +ifeq ($(COMPRESSED_UBOOT),1) +COMPRESSED_UBOOT = 1 +export export COMPRESSED_UBOOT +endif + +ifeq (include/config.mk,$(wildcard include/config.mk)) +# load ARCH, BOARD, and CPU configuration +include include/config.mk +export ARCH CPU BOARD VENDOR SOC +ifndef CROSS_COMPILE +ifeq ($(HOSTARCH),ppc) +CROSS_COMPILE = +else +ifeq ($(ARCH),ppc) +CROSS_COMPILE = powerpc-linux- +endif +ifeq ($(ARCH),arm) +CROSS_COMPILE = arm-linux- +endif +ifeq ($(ARCH),i386) +ifeq ($(HOSTARCH),i386) +CROSS_COMPILE = +else +CROSS_COMPILE = i386-linux- +endif +endif +ifeq ($(ARCH),mips) +CROSS_COMPILE = mips-linux- +endif +ifeq ($(ARCH),nios) +CROSS_COMPILE = nios-elf- +endif +ifeq ($(ARCH),nios2) +CROSS_COMPILE = nios2-elf- +endif +ifeq ($(ARCH),m68k) +CROSS_COMPILE = m68k-elf- +endif +ifeq ($(ARCH),microblaze) +CROSS_COMPILE = mb- +endif +ifeq ($(ARCH),blackfin) +CROSS_COMPILE = bfin-elf- +endif +endif +endif + +export CROSS_COMPILE + +# load other configuration +include $(TOPDIR)/config.mk + + +######################################################################### +# U-Boot objects....order is important (i.e. start must be first) +OBJS = cpu/$(CPU)/start.o + +ifeq ($(COMPRESSED_UBOOT),1) +OBJS_BOOTSTRAP = cpu/$(CPU)/start_bootstrap.o +endif + +LIBS = lib_generic/libgeneric.a +LIBS += common/libcommon.a +LIBS += board/$(BOARDDIR)/lib$(BOARD).a +LIBS += cpu/$(CPU)/lib$(CPU).a + +ifdef SOC +LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a +endif + +LIBS += lib_$(ARCH)/lib$(ARCH).a +LIBS += drivers/libdrivers.a +LIBS += net/libnet.a +LIBS += rtc/librtc.a +LIBS += httpd/libhttpd.a +LIBS += $(BOARDLIBS) + +ifeq ($(COMPRESSED_UBOOT),1) +LIBS_BOOTSTRAP = lib_bootstrap/libbootstrap.a +LIBS_BOOTSTRAP += board/$(BOARDDIR)/lib$(BOARD).a +LIBS_BOOTSTRAP += cpu/$(CPU)/lib$(CPU).a +LIBS_BOOTSTRAP += cpu/$(CPU)/$(SOC)/lib$(SOC).a +endif + +.PHONY : $(LIBS) + +ifeq ($(COMPRESSED_UBOOT),1) +.PHONY : $(LIBS_BOOTSTRAP) +endif + +# Add GCC lib +PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc + +# The "tools" are needed early, so put this first +# Don't include stuff already done in $(LIBS) +SUBDIRS = tools + +.PHONY : $(SUBDIRS) + +######################################################################### +######################################################################### + +ALL = u-boot.srec u-boot.bin System.map + +ifeq ($(COMPRESSED_UBOOT),1) +all: $(ALL) tuboot.bin +else +all: $(ALL) +endif + +u-boot.hex: u-boot + $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ + +u-boot.srec: u-boot + $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ + +u-boot.bin: u-boot + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +u-boot.img: u-boot.bin + ./tools/mkimage -A $(ARCH) -T firmware -C none \ + -a $(TEXT_BASE) -e 0 \ + -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ + sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ + -d $< $@ + +u-boot.dis: u-boot + $(OBJDUMP) -d $< > $@ + +u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) + UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ + $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ + --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \ + -Map u-boot.map -o u-boot + +$(LIBS): + $(MAKE) -C `dirname $@` + +$(SUBDIRS): + $(MAKE) -C $@ all + +ifeq ($(COMPRESSED_UBOOT),1) +LZMA = $(BUILD_TOPDIR)/host_util/lzma + +tuboot.bin: System.map bootstrap.bin u-boot.lzimg + @cat bootstrap.bin > $@ + @cat u-boot.lzimg >> $@ + +u-boot.lzimg: $(obj)u-boot.bin System.map + @rm -rf u-boot.bin.lzma + #$(LZMA) e $(obj)u-boot.bin u-boot.bin.lzma + $(LZMA) --best --keep $(obj)u-boot.bin + ./tools/mkimage -A mips -T firmware -C lzma \ + -a 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \ + -e 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \ + -n 'u-boot image' -d $(obj)u-boot.bin.lzma $@ + +bootstrap.bin: bootstrap + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +bootstrap: depend version $(SUBDIRS) $(OBJS_BOOTSTRAP) $(LIBS_BOOTSTRAP) $(LDSCRIPT_BOOTSTRAP) + UNDEF_SYM=`$(OBJDUMP) -x $(LIBS_BOOTSTRAP) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ + $(LD) $(LDFLAGS_BOOTSTRAP) $$UNDEF_SYM $(OBJS_BOOTSTRAP) \ + --start-group $(LIBS_BOOTSTRAP) --end-group $(PLATFORM_LIBS) \ + -Map bootstrap.map -o bootstrap + +$(LIBS_BOOTSTRAP): + $(MAKE) -C `dirname $@` +endif + +version: + @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \ + echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \ + echo "\"" >> $(VERSION_FILE) + +gdbtools: + $(MAKE) -C tools/gdb || exit 1 + +depend dep: + @for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done + +tags: + ctags -w `find $(SUBDIRS) include \ + lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ + net disk rtc dtt drivers drivers/sk98lin common \ + \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)` + +etags: + etags -a `find $(SUBDIRS) include \ + lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ + net disk rtc dtt drivers drivers/sk98lin common \ + \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)` + +System.map: u-boot + @$(NM) $< | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > System.map + +######################################################################### +else +all install u-boot u-boot.srec depend dep: + @echo "System not configured - see README" >&2 + @ exit 1 +endif + +######################################################################### + +unconfig: + @rm -f include/config.h include/config.mk board/*/config.tmp + +#======================================================================== +# MIPS +#======================================================================== +######################################################################### +## MIPS32 AR7100 (24K) +######################################################################### + +hornet_common_config : + @ >include/config.h + @echo "#define CONFIG_AR7240 1" >>include/config.h + @echo "#define CONFIG_MACH_HORNET 1" >>include/config.h + @echo "#define CONFIG_HORNET_1_1_WAR 1" >>include/config.h + @echo "#define NEW_DDR_TAP_CAL 1" >>include/config.h + +ifdef CONFIG_BOOTDELAY + @echo "#define CONFIG_BOOTDELAY "$(CONFIG_BOOTDELAY) >>include/config.h +endif + + @echo "#define CONFIG_DELAY_TO_AUTORUN_HTTPD 3" >>include/config.h + @echo "#define CONFIG_DELAY_TO_AUTORUN_CONSOLE 5" >>include/config.h + @echo "#define CONFIG_DELAY_TO_AUTORUN_NETCONSOLE 7" >>include/config.h + + # max delay time for button pressing + @echo "#define CONFIG_MAX_BUTTON_PRESSING 10" >>include/config.h + + # don't show info about console (in, out, err...) + @echo "#define CFG_CONSOLE_INFO_QUIET" >>include/config.h + + @./mkconfig -a ap121 mips mips ap121 ar7240 ar7240 + +wr703n_config : unconfig hornet_common_config + @echo '======= Configuring for TP-Link TL-WR703N at:' `date` '=======' + @echo "#define CONFIG_FOR_TPLINK_WR703N_V1 1" >> include/config.h + @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h + @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-WR703N\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h + +wr720n_v3_CH_config : unconfig hornet_common_config + @echo '======= Configuring for TP-Link TL-WR720N v3 CH at:' `date` '=======' + @echo "#define CONFIG_FOR_TPLINK_WR720N_V3 1" >> include/config.h + @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h + @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-WR720N v3 CH\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h + +wr710n_config : unconfig hornet_common_config + @echo '======= Configuring for TP-Link TL-WR710N at:' `date` '=======' + @echo "#define CONFIG_FOR_TPLINK_WR710N_V1 1" >> include/config.h + @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h + @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-WR710N\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h + +mr3020_config : unconfig hornet_common_config + @echo '======= Configuring for TP-Link TL-MR3020 at:' `date` '=======' + @echo "#define CONFIG_FOR_TPLINK_MR3020_V1 1" >> include/config.h + @echo "#define GPIO_INTERNET_LED_BIT 27" >> include/config.h + @echo "#define GPIO_INTERNET_LED_ON 0" >> include/config.h + @echo "#define GPIO_WPS_LED_BIT 26" >> include/config.h + @echo "#define GPIO_WPS_LED_ON 0" >> include/config.h + @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h + @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h + @echo "#define GPIO_ETH_LED_BIT 17" >> include/config.h + @echo "#define GPIO_ETH_LED_ON 0" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR3020\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h + +mr3040_config : unconfig hornet_common_config + @echo '======= Configuring for TP-Link TL-MR3040 at:' `date` '=======' + @echo "#define CONFIG_FOR_TPLINK_MR3040_V1V2 1" >> include/config.h + @echo "#define GPIO_INTERNET_LED_BIT 27" >> include/config.h + @echo "#define GPIO_INTERNET_LED_ON 0" >> include/config.h + @echo "#define GPIO_WLAN_LED_BIT 26" >> include/config.h + @echo "#define GPIO_WLAN_LED_ON 0" >> include/config.h + @echo "#define GPIO_ETH_LED_BIT 17" >> include/config.h + @echo "#define GPIO_ETH_LED_ON 0" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR3040\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h + +mr10u_config : unconfig hornet_common_config + @echo '======= Configuring for TP-Link TL-MR10U at:' `date` '=======' + @echo "#define CONFIG_FOR_TPLINK_MR10U_V1 1" >> include/config.h + @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h + @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR10U\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h + +wr740n_v4_config : unconfig hornet_common_config + @echo '======= Configuring for TP-Link TL-WR740N v4 at:' `date` '=======' + @echo "#define CONFIG_FOR_TPLINK_WR740N_V4 1" >> include/config.h + @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h + @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h + @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h + @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h + @echo "#define GPIO_LAN1_LED_BIT 14" >> include/config.h + @echo "#define GPIO_LAN1_LED_ON 1" >> include/config.h + @echo "#define GPIO_LAN2_LED_BIT 15" >> include/config.h + @echo "#define GPIO_LAN2_LED_ON 1" >> include/config.h + @echo "#define GPIO_LAN3_LED_BIT 16" >> include/config.h + @echo "#define GPIO_LAN3_LED_ON 1" >> include/config.h + @echo "#define GPIO_LAN4_LED_BIT 17" >> include/config.h + @echo "#define GPIO_LAN4_LED_ON 0" >> include/config.h + @echo "#define GPIO_INTERNET_LED_BIT 13" >> include/config.h + @echo "#define GPIO_INTERNET_LED_ON 1" >> include/config.h + @echo "#define GPIO_QSS_LED_BIT 1" >> include/config.h + @echo "#define GPIO_QSS_LED_ON 1" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-WR74xN/D v4\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h + +mr3220_v2_config : unconfig hornet_common_config + @echo '======= Configuring for TP-Link TL-MR3220 v2 at:' `date` '=======' + @echo "#define CONFIG_FOR_TPLINK_MR3220_V2 1" >> include/config.h + @echo "#define GPIO_SYS_LED_BIT 27" >> include/config.h + @echo "#define GPIO_SYS_LED_ON 0" >> include/config.h + @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h + @echo "#define GPIO_WLAN_LED_ON 1" >> include/config.h + @echo "#define GPIO_LAN1_LED_BIT 14" >> include/config.h + @echo "#define GPIO_LAN1_LED_ON 1" >> include/config.h + @echo "#define GPIO_LAN2_LED_BIT 15" >> include/config.h + @echo "#define GPIO_LAN2_LED_ON 1" >> include/config.h + @echo "#define GPIO_LAN3_LED_BIT 16" >> include/config.h + @echo "#define GPIO_LAN3_LED_ON 1" >> include/config.h + @echo "#define GPIO_LAN4_LED_BIT 17" >> include/config.h + @echo "#define GPIO_LAN4_LED_ON 0" >> include/config.h + @echo "#define GPIO_INTERNET_LED_BIT 13" >> include/config.h + @echo "#define GPIO_INTERNET_LED_ON 1" >> include/config.h + @echo "#define GPIO_QSS_LED_BIT 1" >> include/config.h + @echo "#define GPIO_QSS_LED_ON 1" >> include/config.h + @echo "#define GPIO_USB_LED_BIT 26" >> include/config.h + @echo "#define GPIO_USB_LED_ON 1" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for TL-MR3220 v2\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 4" >> include/config.h + +carambola2_config : unconfig + @echo '======= Configuring for 8devices Carambola2 at:' `date` '=======' + @ >include/config.h + @echo "#undef COMPRESSED_UBOOT" >>include/config.h + @echo "#define CONFIG_AR7240 1" >>include/config.h + @echo "#define CONFIG_MACH_HORNET 1" >>include/config.h + @echo "#define CONFIG_HORNET_1_1_WAR 1" >>include/config.h + @echo "#define NEW_DDR_TAP_CAL 1" >>include/config.h + @echo "#define CONFIG_40MHZ_XTAL_SUPPORT 1" >>include/config.h + +ifdef CONFIG_BOOTDELAY + @echo "#define CONFIG_BOOTDELAY "$(CONFIG_BOOTDELAY) >>include/config.h +endif + + @echo "#define CONFIG_DELAY_TO_AUTORUN_HTTPD 3" >>include/config.h + @echo "#define CONFIG_DELAY_TO_AUTORUN_CONSOLE 5" >>include/config.h + @echo "#define CONFIG_DELAY_TO_AUTORUN_NETCONSOLE 7" >>include/config.h + + # max delay time for button pressing + @echo "#define CONFIG_MAX_BUTTON_PRESSING 10" >>include/config.h + + # don't show info about console (in, out, err...) + @echo "#define CFG_CONSOLE_INFO_QUIET" >>include/config.h + + @./mkconfig -a ap121 mips mips ap121 ar7240 ar7240 + + @echo "#define CONFIG_FOR_8DEVICES_CARAMBOLA2 1" >> include/config.h + @echo "#define GPIO_WLAN_LED_BIT 0" >> include/config.h + @echo "#define GPIO_WLAN_LED_ON 0" >> include/config.h + @echo "#define GPIO_RST_BUTTON_BIT 11" >> include/config.h + @echo "#define BOARD_CUSTOM_STRING \"AP121 (AR9331) U-Boot for CARAMBOLA2 v1\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 16" >> include/config.h + +db12x_config : unconfig + @echo '======= Configuring for TP-Link TL-WDR3600/43x0 at:' `date` '=======' + @ >include/config.h + @echo "#define CONFIG_WASP_SUPPORT 1" >>include/config.h + @echo "#undef CFG_ATHRS26_PHY" >>include/config.h + @echo "#define DDR2_32BIT_SUPPORT 1" >>include/config.h + @echo "#define CONFIG_AG7240_GE0_IS_CONNECTED 1" >>include/config.h + @echo "#define CONFIG_AR7240 1" >>include/config.h + @echo "#define CONFIG_WASP 1" >>include/config.h + +ifdef CONFIG_BOOTDELAY + @echo "#define CONFIG_BOOTDELAY "$(CONFIG_BOOTDELAY) >>include/config.h +endif + + @echo "#define CONFIG_DELAY_TO_AUTORUN_HTTPD 3" >>include/config.h + @echo "#define CONFIG_DELAY_TO_AUTORUN_CONSOLE 5" >>include/config.h + @echo "#define CONFIG_DELAY_TO_AUTORUN_NETCONSOLE 7" >>include/config.h + + # max delay time for button pressing + @echo "#define CONFIG_MAX_BUTTON_PRESSING 10" >>include/config.h + + # don't show info about console (in, out, err...) + @echo "#define CFG_CONSOLE_INFO_QUIET" >>include/config.h + + @echo "#define CONFIG_ATHRS17_PHY 1" >>include/config.h + @echo "#define CFG_AG7240_NMACS 1" >>include/config.h + @echo "#define BOARD_CUSTOM_STRING \"DB120 (AR9344) U-Boot for TL-WDR3600/43x0\"" >>include/config.h + @echo "#define DEFAULT_FLASH_SIZE_IN_MB 8" >> include/config.h + + @./mkconfig -a db12x mips mips db12x ar7240 ar7240 + +######################################################################### +######################################################################### +######################################################################### + +clean: + @echo Making $@ + @find . -type f \ + \( -name 'core' -o -name '*.bak' -o -name '*~' \ + -o -name '*.o' -o -name '*.a' -o -name .depend \) -print \ + | xargs rm -f + @rm -f tools/mkimage tools/envcrc + @rm -f lib_bootstrap/*.o + @rm -f lib_bootstrap/*.a + @rm -f bootstrap bootstrap.bin tuboot.bin u-boot.lzimg u-boot.bin.lzma bootstrap.map + +clobber: clean + @echo Making $@ + @find . -type f \( -name .depend \ + -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \ + -print0 \ + | xargs -0 rm -f + @rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h + @rm -fr *.*~ + @rm -f u-boot u-boot.map u-boot.hex $(ALL) + @rm -f tools/crc32.c tools/environment.c + @rm -f cpu/mpc824x/bedbug_603e.c + @rm -f include/asm/proc include/asm/arch include/asm + +mrproper \ +distclean: clobber unconfig + +backup: + F=`basename $(TOPDIR)` ; cd .. ; \ + gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F + +######################################################################### diff --git a/u-boot/README b/u-boot/README new file mode 100755 index 0000000..ae9e10f --- /dev/null +++ b/u-boot/README @@ -0,0 +1,3549 @@ +# +# (C) Copyright 2000 - 2005 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +Summary: +======== + +This directory contains the source code for U-Boot, a boot loader for +Embedded boards based on PowerPC, ARM, MIPS and several other +processors, which can be installed in a boot ROM and used to +initialize and test the hardware or to download and run application +code. + +The development of U-Boot is closely related to Linux: some parts of +the source code originate in the Linux source tree, we have some +header files in common, and special provision has been made to +support booting of Linux images. + +Some attention has been paid to make this software easily +configurable and extendable. For instance, all monitor commands are +implemented with the same call interface, so that it's very easy to +add new commands. Also, instead of permanently adding rarely used +code (for instance hardware test utilities) to the monitor, you can +load and run it dynamically. + + +Status: +======= + +In general, all boards for which a configuration option exists in the +Makefile have been tested to some extent and can be considered +"working". In fact, many of them are used in production systems. + +In case of problems see the CHANGELOG and CREDITS files to find out +who contributed the specific port. + + +Where to get help: +================== + +In case you have questions about, problems with or contributions for +U-Boot you should send a message to the U-Boot mailing list at +. There is also an archive of +previous traffic on the mailing list - please search the archive +before asking FAQ's. Please see +http://lists.sourceforge.net/lists/listinfo/u-boot-users/ + + +Where we come from: +=================== + +- start from 8xxrom sources +- create PPCBoot project (http://sourceforge.net/projects/ppcboot) +- clean up code +- make it easier to add custom boards +- make it possible to add other [PowerPC] CPUs +- extend functions, especially: + * Provide extended interface to Linux boot loader + * S-Record download + * network boot + * PCMCIA / CompactFLash / ATA disk / SCSI ... boot +- create ARMBoot project (http://sourceforge.net/projects/armboot) +- add other CPU families (starting with ARM) +- create U-Boot project (http://sourceforge.net/projects/u-boot) + + +Names and Spelling: +=================== + +The "official" name of this project is "Das U-Boot". The spelling +"U-Boot" shall be used in all written text (documentation, comments +in source files etc.). Example: + + This is the README file for the U-Boot project. + +File names etc. shall be based on the string "u-boot". Examples: + + include/asm-ppc/u-boot.h + + #include + +Variable names, preprocessor constants etc. shall be either based on +the string "u_boot" or on "U_BOOT". Example: + + U_BOOT_VERSION u_boot_logo + IH_OS_U_BOOT u_boot_hush_start + + +Versioning: +=========== + +U-Boot uses a 3 level version number containing a version, a +sub-version, and a patchlevel: "U-Boot-2.34.5" means version "2", +sub-version "34", and patchlevel "4". + +The patchlevel is used to indicate certain stages of development +between released versions, i. e. officially released versions of +U-Boot will always have a patchlevel of "0". + + +Directory Hierarchy: +==================== + +- board Board dependent files +- common Misc architecture independent functions +- cpu CPU specific files + - 74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs + - arm720t Files specific to ARM 720 CPUs + - arm920t Files specific to ARM 920 CPUs + - at91rm9200 Files specific to Atmel AT91RM9200 CPU + - imx Files specific to Freescale MC9328 i.MX CPUs + - s3c24x0 Files specific to Samsung S3C24X0 CPUs + - arm925t Files specific to ARM 925 CPUs + - arm926ejs Files specific to ARM 926 CPUs + - arm1136 Files specific to ARM 1136 CPUs + - i386 Files specific to i386 CPUs + - ixp Files specific to Intel XScale IXP CPUs + - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs + - mips Files specific to MIPS CPUs + - mpc5xx Files specific to Freescale MPC5xx CPUs + - mpc5xxx Files specific to Freescale MPC5xxx CPUs + - mpc8xx Files specific to Freescale MPC8xx CPUs + - mpc8220 Files specific to Freescale MPC8220 CPUs + - mpc824x Files specific to Freescale MPC824x CPUs + - mpc8260 Files specific to Freescale MPC8260 CPUs + - mpc85xx Files specific to Freescale MPC85xx CPUs + - nios Files specific to Altera NIOS CPUs + - nios2 Files specific to Altera Nios-II CPUs + - ppc4xx Files specific to AMCC PowerPC 4xx CPUs + - pxa Files specific to Intel XScale PXA CPUs + - s3c44b0 Files specific to Samsung S3C44B0 CPUs + - sa1100 Files specific to Intel StrongARM SA1100 CPUs +- disk Code for disk drive partition handling +- doc Documentation (don't expect too much) +- drivers Commonly used device drivers +- dtt Digital Thermometer and Thermostat drivers +- examples Example code for standalone applications, etc. +- include Header Files +- lib_arm Files generic to ARM architecture +- lib_generic Files generic to all architectures +- lib_i386 Files generic to i386 architecture +- lib_m68k Files generic to m68k architecture +- lib_mips Files generic to MIPS architecture +- lib_nios Files generic to NIOS architecture +- lib_ppc Files generic to PowerPC architecture +- net Networking code +- post Power On Self Test +- rtc Real Time Clock drivers +- tools Tools to build S-Record or U-Boot images, etc. + +Software Configuration: +======================= + +Configuration is usually done using C preprocessor defines; the +rationale behind that is to avoid dead code whenever possible. + +There are two classes of configuration variables: + +* Configuration _OPTIONS_: + These are selectable by the user and have names beginning with + "CONFIG_". + +* Configuration _SETTINGS_: + These depend on the hardware etc. and should not be meddled with if + you don't know what you're doing; they have names beginning with + "CFG_". + +Later we will add a configuration tool - probably similar to or even +identical to what's used for the Linux kernel. Right now, we have to +do the configuration by hand, which means creating some symbolic +links and editing some configuration files. We use the TQM8xxL boards +as an example here. + + +Selection of Processor Architecture and Board Type: +--------------------------------------------------- + +For all supported boards there are ready-to-use default +configurations available; just type "make _config". + +Example: For a TQM823L module type: + + cd u-boot + make TQM823L_config + +For the Cogent platform, you need to specify the cpu type as well; +e.g. "make cogent_mpc8xx_config". And also configure the cogent +directory according to the instructions in cogent/README. + + +Configuration Options: +---------------------- + +Configuration depends on the combination of board and CPU type; all +such information is kept in a configuration file +"include/configs/.h". + +Example: For a TQM823L module, all configuration settings are in +"include/configs/TQM823L.h". + + +Many of the options are named exactly as the corresponding Linux +kernel configuration options. The intention is to make it easier to +build a config tool - later. + + +The following options need to be configured: + +- CPU Type: Define exactly one of + + PowerPC based CPUs: + ------------------- + CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860 + or CONFIG_MPC5xx + or CONFIG_MPC8220 + or CONFIG_MPC824X, CONFIG_MPC8260 + or CONFIG_MPC85xx + or CONFIG_IOP480 + or CONFIG_405GP + or CONFIG_405EP + or CONFIG_440 + or CONFIG_MPC74xx + or CONFIG_750FX + + ARM based CPUs: + --------------- + CONFIG_SA1110 + CONFIG_ARM7 + CONFIG_PXA250 + CONFIG_CPU_MONAHANS + + MicroBlaze based CPUs: + ---------------------- + CONFIG_MICROBLAZE + + Nios-2 based CPUs: + ---------------------- + CONFIG_NIOS2 + + +- Board Type: Define exactly one of + + PowerPC based boards: + --------------------- + + CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCI405 + CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC2 + CONFIG_AMX860 CONFIG_GTH CONFIG_PCIPPC6 + CONFIG_AP1000 CONFIG_gw8260 CONFIG_pcu_e + CONFIG_AR405 CONFIG_hermes CONFIG_PIP405 + CONFIG_BAB7xx CONFIG_hymod CONFIG_PM826 + CONFIG_c2mon CONFIG_IAD210 CONFIG_ppmc8260 + CONFIG_CANBT CONFIG_ICU862 CONFIG_QS823 + CONFIG_CCM CONFIG_IP860 CONFIG_QS850 + CONFIG_CMI CONFIG_IPHASE4539 CONFIG_QS860T + CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RBC823 + CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXClassic + CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXlite + CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_RPXsuper + CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_rsdproto + CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_sacsng + CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8240 + CONFIG_CSB272 CONFIG_LANTEC CONFIG_Sandpoint8245 + CONFIG_CU824 CONFIG_LITE5200B CONFIG_sbc8260 + CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8560 + CONFIG_DB64360 CONFIG_MBX CONFIG_SM850 + CONFIG_DB64460 CONFIG_MBX860T CONFIG_SPD823TS + CONFIG_DU405 CONFIG_MHPC CONFIG_STXGP3 + CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_SXNI855T + CONFIG_EBONY CONFIG_MOUSSE CONFIG_TQM823L + CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM8260 + CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM850L + CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM855L + CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM860L + CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TTTech + CONFIG_ETX094 CONFIG_MVS1 CONFIG_UTX8245 + CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_V37 + CONFIG_FADS823 CONFIG_NETTA CONFIG_W7OLMC + CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMG + CONFIG_FADS860T CONFIG_NX823 CONFIG_WALNUT + CONFIG_FLAGADM CONFIG_OCRTC CONFIG_ZPC1900 + CONFIG_FPS850L CONFIG_ORSG CONFIG_ZUMA + CONFIG_FPS860L CONFIG_OXC + + ARM based boards: + ----------------- + + CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250, + CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110, + CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, + CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, + CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400, + CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, + CONFIG_SHANNON, CONFIG_P2_OMAP730, CONFIG_SMDK2400, + CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9 + + MicroBlaze based boards: + ------------------------ + + CONFIG_SUZAKU + + Nios-2 based boards: + ------------------------ + + CONFIG_PCI5441 CONFIG_PK1C20 + + +- CPU Module Type: (if CONFIG_COGENT is defined) + Define exactly one of + CONFIG_CMA286_60_OLD +--- FIXME --- not tested yet: + CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P, + CONFIG_CMA287_23, CONFIG_CMA287_50 + +- Motherboard Type: (if CONFIG_COGENT is defined) + Define exactly one of + CONFIG_CMA101, CONFIG_CMA102 + +- Motherboard I/O Modules: (if CONFIG_COGENT is defined) + Define one or more of + CONFIG_CMA302 + +- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined) + Define one or more of + CONFIG_LCD_HEARTBEAT - update a character position on + the lcd display every second with + a "rotator" |\-/|\-/ + +- Board flavour: (if CONFIG_MPC8260ADS is defined) + CONFIG_ADSTYPE + Possible values are: + CFG_8260ADS - original MPC8260ADS + CFG_8266ADS - MPC8266ADS + CFG_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR + CFG_8272ADS - MPC8272ADS + +- MPC824X Family Member (if CONFIG_MPC824X is defined) + Define exactly one of + CONFIG_MPC8240, CONFIG_MPC8245 + +- 8xx CPU Options: (if using an MPC8xx cpu) + CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if + get_gclk_freq() cannot work + e.g. if there is no 32KHz + reference PIT/RTC clock + CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK + or XTAL/EXTAL) + +- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU): + CFG_8xx_CPUCLK_MIN + CFG_8xx_CPUCLK_MAX + CONFIG_8xx_CPUCLK_DEFAULT + See doc/README.MPC866 + + CFG_MEASURE_CPUCLK + + Define this to measure the actual CPU clock instead + of relying on the correctness of the configured + values. Mostly useful for board bringup to make sure + the PLL is locked at the intended frequency. Note + that this requires a (stable) reference clock (32 kHz + RTC clock or CFG_8XX_XIN) + +- Intel Monahans options: + CFG_MONAHANS_RUN_MODE_OSC_RATIO + + Defines the Monahans run mode to oscillator + ratio. Valid values are 8, 16, 24, 31. The core + frequency is this value multiplied by 13 MHz. + + CFG_MONAHANS_TURBO_RUN_MODE_RATIO + + Defines the Monahans turbo mode to oscillator + ratio. Valid values are 1 (default if undefined) and + 2. The core frequency as calculated above is multiplied + by this value. + +- Linux Kernel Interface: + CONFIG_CLOCKS_IN_MHZ + + U-Boot stores all clock information in Hz + internally. For binary compatibility with older Linux + kernels (which expect the clocks passed in the + bd_info data to be in MHz) the environment variable + "clocks_in_mhz" can be defined so that U-Boot + converts clock data to MHZ before passing it to the + Linux kernel. + When CONFIG_CLOCKS_IN_MHZ is defined, a definition of + "clocks_in_mhz=1" is automatically included in the + default environment. + + CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] + + When transfering memsize parameter to linux, some versions + expect it to be in bytes, others in MB. + Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. + + CONFIG_OF_FLAT_TREE + + New kernel versions are expecting firmware settings to be + passed using flat open firmware trees. + The environment variable "disable_of", when set, disables this + functionality. + + CONFIG_OF_FLAT_TREE_MAX_SIZE + + The maximum size of the constructed OF tree. + + OF_CPU - The proper name of the cpus node. + OF_SOC - The proper name of the soc node. + OF_TBCLK - The timebase frequency. + OF_STDOUT_PATH - The path to the console device + + CONFIG_OF_HAS_BD_T + + The resulting flat device tree will have a copy of the bd_t. + Space should be pre-allocated in the dts for the bd_t. + + CONFIG_OF_HAS_UBOOT_ENV + + The resulting flat device tree will have a copy of u-boot's + environment variables + + CONFIG_OF_BOARD_SETUP + + Board code has addition modification that it wants to make + to the flat device tree before handing it off to the kernel + +- Serial Ports: + CFG_PL010_SERIAL + + Define this if you want support for Amba PrimeCell PL010 UARTs. + + CFG_PL011_SERIAL + + Define this if you want support for Amba PrimeCell PL011 UARTs. + + CONFIG_PL011_CLOCK + + If you have Amba PrimeCell PL011 UARTs, set this variable to + the clock speed of the UARTs. + + CONFIG_PL01x_PORTS + + If you have Amba PrimeCell PL010 or PL011 UARTs on your board, + define this to a list of base addresses for each (supported) + port. See e.g. include/configs/versatile.h + + +- Console Interface: + Depending on board, define exactly one serial port + (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, + CONFIG_8xx_CONS_SCC1, ...), or switch off the serial + console by defining CONFIG_8xx_CONS_NONE + + Note: if CONFIG_8xx_CONS_NONE is defined, the serial + port routines must be defined elsewhere + (i.e. serial_init(), serial_getc(), ...) + + CONFIG_CFB_CONSOLE + Enables console device for a color framebuffer. Needs following + defines (cf. smiLynxEM, i8042, board/eltec/bab7xx) + VIDEO_FB_LITTLE_ENDIAN graphic memory organisation + (default big endian) + VIDEO_HW_RECTFILL graphic chip supports + rectangle fill + (cf. smiLynxEM) + VIDEO_HW_BITBLT graphic chip supports + bit-blit (cf. smiLynxEM) + VIDEO_VISIBLE_COLS visible pixel columns + (cols=pitch) + VIDEO_VISIBLE_ROWS visible pixel rows + VIDEO_PIXEL_SIZE bytes per pixel + VIDEO_DATA_FORMAT graphic data format + (0-5, cf. cfb_console.c) + VIDEO_FB_ADRS framebuffer address + VIDEO_KBD_INIT_FCT keyboard int fct + (i.e. i8042_kbd_init()) + VIDEO_TSTC_FCT test char fct + (i.e. i8042_tstc) + VIDEO_GETC_FCT get char fct + (i.e. i8042_getc) + CONFIG_CONSOLE_CURSOR cursor drawing on/off + (requires blink timer + cf. i8042.c) + CFG_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c) + CONFIG_CONSOLE_TIME display time/date info in + upper right corner + (requires CFG_CMD_DATE) + CONFIG_VIDEO_LOGO display Linux logo in + upper left corner + CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of + linux_logo.h for logo. + Requires CONFIG_VIDEO_LOGO + CONFIG_CONSOLE_EXTRA_INFO + addional board info beside + the logo + + When CONFIG_CFB_CONSOLE is defined, video console is + default i/o. Serial console can be forced with + environment 'console=serial'. + + When CONFIG_SILENT_CONSOLE is defined, all console + messages (by U-Boot and Linux!) can be silenced with + the "silent" environment variable. See + doc/README.silent for more information. + +- Console Baudrate: + CONFIG_BAUDRATE - in bps + Select one of the baudrates listed in + CFG_BAUDRATE_TABLE, see below. + CFG_BRGCLK_PRESCALE, baudrate prescale + +- Interrupt driven serial port input: + CONFIG_SERIAL_SOFTWARE_FIFO + + PPC405GP only. + Use an interrupt handler for receiving data on the + serial port. It also enables using hardware handshake + (RTS/CTS) and UART's built-in FIFO. Set the number of + bytes the interrupt driven input buffer should have. + + Leave undefined to disable this feature, including + disable the buffer and hardware handshake. + +- Console UART Number: + CONFIG_UART1_CONSOLE + + AMCC PPC4xx only. + If defined internal UART1 (and not UART0) is used + as default U-Boot console. + +- Boot Delay: CONFIG_BOOTDELAY - in seconds + Delay before automatically booting the default image; + set to -1 to disable autoboot. + + See doc/README.autoboot for these options that + work with CONFIG_BOOTDELAY. None are required. + CONFIG_BOOT_RETRY_TIME + CONFIG_BOOT_RETRY_MIN + CONFIG_AUTOBOOT_KEYED + CONFIG_AUTOBOOT_PROMPT + CONFIG_AUTOBOOT_DELAY_STR + CONFIG_AUTOBOOT_STOP_STR + CONFIG_AUTOBOOT_DELAY_STR2 + CONFIG_AUTOBOOT_STOP_STR2 + CONFIG_ZERO_BOOTDELAY_CHECK + CONFIG_RESET_TO_RETRY + +- Autoboot Command: + CONFIG_BOOTCOMMAND + Only needed when CONFIG_BOOTDELAY is enabled; + define a command string that is automatically executed + when no character is read on the console interface + within "Boot Delay" after reset. + + CONFIG_BOOTARGS + This can be used to pass arguments to the bootm + command. The value of CONFIG_BOOTARGS goes into the + environment value "bootargs". + + CONFIG_RAMBOOT and CONFIG_NFSBOOT + The value of these goes into the environment as + "ramboot" and "nfsboot" respectively, and can be used + as a convenience, when switching between booting from + ram and nfs. + +- Pre-Boot Commands: + CONFIG_PREBOOT + + When this option is #defined, the existence of the + environment variable "preboot" will be checked + immediately before starting the CONFIG_BOOTDELAY + countdown and/or running the auto-boot command resp. + entering interactive mode. + + This feature is especially useful when "preboot" is + automatically generated or modified. For an example + see the LWMON board specific code: here "preboot" is + modified when the user holds down a certain + combination of keys on the (special) keyboard when + booting the systems + +- Serial Download Echo Mode: + CONFIG_LOADS_ECHO + If defined to 1, all characters received during a + serial download (using the "loads" command) are + echoed back. This might be needed by some terminal + emulations (like "cu"), but may as well just take + time on others. This setting #define's the initial + value of the "loads_echo" environment variable. + +- Kgdb Serial Baudrate: (if CFG_CMD_KGDB is defined) + CONFIG_KGDB_BAUDRATE + Select one of the baudrates listed in + CFG_BAUDRATE_TABLE, see below. + +- Monitor Functions: + CONFIG_COMMANDS + Most monitor functions can be selected (or + de-selected) by adjusting the definition of + CONFIG_COMMANDS; to select individual functions, + #define CONFIG_COMMANDS by "OR"ing any of the + following values: + + #define enables commands: + ------------------------- + CFG_CMD_ASKENV * ask for env variable + CFG_CMD_AUTOSCRIPT Autoscript Support + CFG_CMD_BDI bdinfo + CFG_CMD_BEDBUG * Include BedBug Debugger + CFG_CMD_BMP * BMP support + CFG_CMD_BSP * Board specific commands + CFG_CMD_BOOTD bootd + CFG_CMD_CACHE * icache, dcache + CFG_CMD_CONSOLE coninfo + CFG_CMD_DATE * support for RTC, date/time... + CFG_CMD_DHCP * DHCP support + CFG_CMD_DIAG * Diagnostics + CFG_CMD_DOC * Disk-On-Chip Support + CFG_CMD_DTT * Digital Therm and Thermostat + CFG_CMD_ECHO echo arguments + CFG_CMD_EEPROM * EEPROM read/write support + CFG_CMD_ELF * bootelf, bootvx + CFG_CMD_ENV saveenv + CFG_CMD_FDC * Floppy Disk Support + CFG_CMD_FAT * FAT partition support + CFG_CMD_FDOS * Dos diskette Support + CFG_CMD_FLASH flinfo, erase, protect + CFG_CMD_FPGA FPGA device initialization support + CFG_CMD_HWFLOW * RTS/CTS hw flow control + CFG_CMD_I2C * I2C serial bus support + CFG_CMD_IDE * IDE harddisk support + CFG_CMD_IMI iminfo + CFG_CMD_IMLS List all found images + CFG_CMD_IMMAP * IMMR dump support + CFG_CMD_IRQ * irqinfo + CFG_CMD_ITEST Integer/string test of 2 values + CFG_CMD_JFFS2 * JFFS2 Support + CFG_CMD_KGDB * kgdb + CFG_CMD_LOADB loadb + CFG_CMD_LOADS loads + CFG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, + loop, loopw, mtest + CFG_CMD_MISC Misc functions like sleep etc + CFG_CMD_MMC * MMC memory mapped support + CFG_CMD_MII * MII utility commands + CFG_CMD_NAND * NAND support + CFG_CMD_NET bootp, tftpboot, rarpboot + CFG_CMD_PCI * pciinfo + CFG_CMD_PCMCIA * PCMCIA support + CFG_CMD_PING * send ICMP ECHO_REQUEST to network host + CFG_CMD_PORTIO * Port I/O + CFG_CMD_REGINFO * Register dump + CFG_CMD_RUN run command in env variable + CFG_CMD_SAVES * save S record dump + CFG_CMD_SCSI * SCSI Support + CFG_CMD_SDRAM * print SDRAM configuration information + (requires CFG_CMD_I2C) + CFG_CMD_SETGETDCR Support for DCR Register access (4xx only) + CFG_CMD_SPI * SPI serial bus support + CFG_CMD_USB * USB support + CFG_CMD_VFD * VFD support (TRAB) + CFG_CMD_BSP * Board SPecific functions + CFG_CMD_CDP * Cisco Discover Protocol support + ----------------------------------------------- + CFG_CMD_ALL all + + CONFIG_CMD_DFL Default configuration; at the moment + this is includes all commands, except + the ones marked with "*" in the list + above. + + If you don't define CONFIG_COMMANDS it defaults to + CONFIG_CMD_DFL in include/cmd_confdefs.h. A board can + override the default settings in the respective + include file. + + EXAMPLE: If you want all functions except of network + support you can write: + + #define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET) + + + Note: Don't enable the "icache" and "dcache" commands + (configuration option CFG_CMD_CACHE) unless you know + what you (and your U-Boot users) are doing. Data + cache cannot be enabled on systems like the 8xx or + 8260 (where accesses to the IMMR region must be + uncached), and it cannot be disabled on all other + systems where we (mis-) use the data cache to hold an + initial stack and some data. + + + XXX - this list needs to get updated! + +- Watchdog: + CONFIG_WATCHDOG + If this variable is defined, it enables watchdog + support. There must be support in the platform specific + code for a watchdog. For the 8xx and 8260 CPUs, the + SIU Watchdog feature is enabled in the SYPCR + register. + +- U-Boot Version: + CONFIG_VERSION_VARIABLE + If this variable is defined, an environment variable + named "ver" is created by U-Boot showing the U-Boot + version as printed by the "version" command. + This variable is readonly. + +- Real-Time Clock: + + When CFG_CMD_DATE is selected, the type of the RTC + has to be selected, too. Define exactly one of the + following options: + + CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx + CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC + CONFIG_RTC_MC146818 - use MC146818 RTC + CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC + CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC + CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC + CONFIG_RTC_DS164x - use Dallas DS164x RTC + CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC + + Note that if the RTC uses I2C, then the I2C interface + must also be configured. See I2C Support, below. + +- Timestamp Support: + + When CONFIG_TIMESTAMP is selected, the timestamp + (date and time) of an image is printed by image + commands like bootm or iminfo. This option is + automatically enabled when you select CFG_CMD_DATE . + +- Partition Support: + CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION + and/or CONFIG_ISO_PARTITION + + If IDE or SCSI support is enabled (CFG_CMD_IDE or + CFG_CMD_SCSI) you must configure support for at least + one partition type as well. + +- IDE Reset method: + CONFIG_IDE_RESET_ROUTINE - this is defined in several + board configurations files but used nowhere! + + CONFIG_IDE_RESET - is this is defined, IDE Reset will + be performed by calling the function + ide_set_reset(int reset) + which has to be defined in a board specific file + +- ATAPI Support: + CONFIG_ATAPI + + Set this to enable ATAPI support. + +- LBA48 Support + CONFIG_LBA48 + + Set this to enable support for disks larger than 137GB + Also look at CFG_64BIT_LBA ,CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL + Whithout these , LBA48 support uses 32bit variables and will 'only' + support disks up to 2.1TB. + + CFG_64BIT_LBA: + When enabled, makes the IDE subsystem use 64bit sector addresses. + Default is 32bit. + +- SCSI Support: + At the moment only there is only support for the + SYM53C8XX SCSI controller; define + CONFIG_SCSI_SYM53C8XX to enable it. + + CFG_SCSI_MAX_LUN [8], CFG_SCSI_MAX_SCSI_ID [7] and + CFG_SCSI_MAX_DEVICE [CFG_SCSI_MAX_SCSI_ID * + CFG_SCSI_MAX_LUN] can be adjusted to define the + maximum numbers of LUNs, SCSI ID's and target + devices. + CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) + +- NETWORK Support (PCI): + CONFIG_E1000 + Support for Intel 8254x gigabit chips. + + CONFIG_EEPRO100 + Support for Intel 82557/82559/82559ER chips. + Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom + write routine for first time initialisation. + + CONFIG_TULIP + Support for Digital 2114x chips. + Optional CONFIG_TULIP_SELECT_MEDIA for board specific + modem chip initialisation (KS8761/QS6611). + + CONFIG_NATSEMI + Support for National dp83815 chips. + + CONFIG_NS8382X + Support for National dp8382[01] gigabit chips. + +- NETWORK Support (other): + + CONFIG_DRIVER_LAN91C96 + Support for SMSC's LAN91C96 chips. + + CONFIG_LAN91C96_BASE + Define this to hold the physical address + of the LAN91C96's I/O space + + CONFIG_LAN91C96_USE_32_BIT + Define this to enable 32 bit addressing + + CONFIG_DRIVER_SMC91111 + Support for SMSC's LAN91C111 chip + + CONFIG_SMC91111_BASE + Define this to hold the physical address + of the device (I/O space) + + CONFIG_SMC_USE_32_BIT + Define this if data bus is 32 bits + + CONFIG_SMC_USE_IOFUNCS + Define this to use i/o functions instead of macros + (some hardware wont work with macros) + +- USB Support: + At the moment only the UHCI host controller is + supported (PIP405, MIP405, MPC5200); define + CONFIG_USB_UHCI to enable it. + define CONFIG_USB_KEYBOARD to enable the USB Keyboard + and define CONFIG_USB_STORAGE to enable the USB + storage devices. + Note: + Supported are USB Keyboards and USB Floppy drives + (TEAC FD-05PUB). + MPC5200 USB requires additional defines: + CONFIG_USB_CLOCK + for 528 MHz Clock: 0x0001bbbb + CONFIG_USB_CONFIG + for differential drivers: 0x00001000 + for single ended drivers: 0x00005000 + + +- MMC Support: + The MMC controller on the Intel PXA is supported. To + enable this define CONFIG_MMC. The MMC can be + accessed from the boot prompt by mapping the device + to physical memory similar to flash. Command line is + enabled with CFG_CMD_MMC. The MMC driver also works with + the FAT fs. This is enabled with CFG_CMD_FAT. + +- Journaling Flash filesystem support: + CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, + CONFIG_JFFS2_NAND_DEV + Define these for a default partition on a NAND device + + CFG_JFFS2_FIRST_SECTOR, + CFG_JFFS2_FIRST_BANK, CFG_JFFS2_NUM_BANKS + Define these for a default partition on a NOR device + + CFG_JFFS_CUSTOM_PART + Define this to create an own partition. You have to provide a + function struct part_info* jffs2_part_info(int part_num) + + If you define only one JFFS2 partition you may also want to + #define CFG_JFFS_SINGLE_PART 1 + to disable the command chpart. This is the default when you + have not defined a custom partition + +- Keyboard Support: + CONFIG_ISA_KEYBOARD + + Define this to enable standard (PC-Style) keyboard + support + + CONFIG_I8042_KBD + Standard PC keyboard driver with US (is default) and + GERMAN key layout (switch via environment 'keymap=de') support. + Export function i8042_kbd_init, i8042_tstc and i8042_getc + for cfb_console. Supports cursor blinking. + +- Video support: + CONFIG_VIDEO + + Define this to enable video support (for output to + video). + + CONFIG_VIDEO_CT69000 + + Enable Chips & Technologies 69000 Video chip + + CONFIG_VIDEO_SMI_LYNXEM + Enable Silicon Motion SMI 712/710/810 Video chip. The + video output is selected via environment 'videoout' + (1 = LCD and 2 = CRT). If videoout is undefined, CRT is + assumed. + + For the CT69000 and SMI_LYNXEM drivers, videomode is + selected via environment 'videomode'. Two diferent ways + are possible: + - "videomode=num" 'num' is a standard LiLo mode numbers. + Following standard modes are supported (* is default): + + Colors 640x480 800x600 1024x768 1152x864 1280x1024 + -------------+--------------------------------------------- + 8 bits | 0x301* 0x303 0x305 0x161 0x307 + 15 bits | 0x310 0x313 0x316 0x162 0x319 + 16 bits | 0x311 0x314 0x317 0x163 0x31A + 24 bits | 0x312 0x315 0x318 ? 0x31B + -------------+--------------------------------------------- + (i.e. setenv videomode 317; saveenv; reset;) + + - "videomode=bootargs" all the video parameters are parsed + from the bootargs. (See drivers/videomodes.c) + + + CONFIG_VIDEO_SED13806 + Enable Epson SED13806 driver. This driver supports 8bpp + and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP + or CONFIG_VIDEO_SED13806_16BPP + +- Keyboard Support: + CONFIG_KEYBOARD + + Define this to enable a custom keyboard support. + This simply calls drv_keyboard_init() which must be + defined in your board-specific files. + The only board using this so far is RBC823. + +- LCD Support: CONFIG_LCD + + Define this to enable LCD support (for output to LCD + display); also select one of the supported displays + by defining one of these: + + CONFIG_NEC_NL6448AC33: + + NEC NL6448AC33-18. Active, color, single scan. + + CONFIG_NEC_NL6448BC20 + + NEC NL6448BC20-08. 6.5", 640x480. + Active, color, single scan. + + CONFIG_NEC_NL6448BC33_54 + + NEC NL6448BC33-54. 10.4", 640x480. + Active, color, single scan. + + CONFIG_SHARP_16x9 + + Sharp 320x240. Active, color, single scan. + It isn't 16x9, and I am not sure what it is. + + CONFIG_SHARP_LQ64D341 + + Sharp LQ64D341 display, 640x480. + Active, color, single scan. + + CONFIG_HLD1045 + + HLD1045 display, 640x480. + Active, color, single scan. + + CONFIG_OPTREX_BW + + Optrex CBL50840-2 NF-FW 99 22 M5 + or + Hitachi LMG6912RPFC-00T + or + Hitachi SP14Q002 + + 320x240. Black & white. + + Normally display is black on white background; define + CFG_WHITE_ON_BLACK to get it inverted. + +- Splash Screen Support: CONFIG_SPLASH_SCREEN + + If this option is set, the environment is checked for + a variable "splashimage". If found, the usual display + of logo, copyright and system information on the LCD + is suppressed and the BMP image at the address + specified in "splashimage" is loaded instead. The + console is redirected to the "nulldev", too. This + allows for a "silent" boot where a splash screen is + loaded very quickly after power-on. + +- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP + + If this option is set, additionally to standard BMP + images, gzipped BMP images can be displayed via the + splashscreen support or the bmp command. + +- Compression support: + CONFIG_BZIP2 + + If this option is set, support for bzip2 compressed + images is included. If not, only uncompressed and gzip + compressed images are supported. + + NOTE: the bzip2 algorithm requires a lot of RAM, so + the malloc area (as defined by CFG_MALLOC_LEN) should + be at least 4MB. + +- MII/PHY support: + CONFIG_PHY_ADDR + + The address of PHY on MII bus. + + CONFIG_PHY_CLOCK_FREQ (ppc4xx) + + The clock frequency of the MII bus + + CONFIG_PHY_GIGE + + If this option is set, support for speed/duplex + detection of Gigabit PHY is included. + + CONFIG_PHY_RESET_DELAY + + Some PHY like Intel LXT971A need extra delay after + reset before any MII register access is possible. + For such PHY, set this option to the usec delay + required. (minimum 300usec for LXT971A) + + CONFIG_PHY_CMD_DELAY (ppc4xx) + + Some PHY like Intel LXT971A need extra delay after + command issued before MII status register can be read + +- Ethernet address: + CONFIG_ETHADDR + CONFIG_ETH2ADDR + CONFIG_ETH3ADDR + + Define a default value for ethernet address to use + for the respective ethernet interface, in case this + is not determined automatically. + +- IP address: + CONFIG_IPADDR + + Define a default value for the IP address to use for + the default ethernet interface, in case this is not + determined through e.g. bootp. + +- Server IP address: + CONFIG_SERVERIP + + Defines a default value for theIP address of a TFTP + server to contact when using the "tftboot" command. + +- BOOTP Recovery Mode: + CONFIG_BOOTP_RANDOM_DELAY + + If you have many targets in a network that try to + boot using BOOTP, you may want to avoid that all + systems send out BOOTP requests at precisely the same + moment (which would happen for instance at recovery + from a power failure, when all systems will try to + boot, thus flooding the BOOTP server. Defining + CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be + inserted before sending out BOOTP requests. The + following delays are insterted then: + + 1st BOOTP request: delay 0 ... 1 sec + 2nd BOOTP request: delay 0 ... 2 sec + 3rd BOOTP request: delay 0 ... 4 sec + 4th and following + BOOTP requests: delay 0 ... 8 sec + +- DHCP Advanced Options: + CONFIG_BOOTP_MASK + + You can fine tune the DHCP functionality by adding + these flags to the CONFIG_BOOTP_MASK define: + + CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS + serverip from a DHCP server, it is possible that more + than one DNS serverip is offered to the client. + If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS + serverip will be stored in the additional environment + variable "dnsip2". The first DNS serverip is always + stored in the variable "dnsip", when CONFIG_BOOTP_DNS + is added to the CONFIG_BOOTP_MASK. + + CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable + to do a dynamic update of a DNS server. To do this, they + need the hostname of the DHCP requester. + If CONFIG_BOOP_SEND_HOSTNAME is added to the + CONFIG_BOOTP_MASK, the content of the "hostname" + environment variable is passed as option 12 to + the DHCP server. + + - CDP Options: + CONFIG_CDP_DEVICE_ID + + The device id used in CDP trigger frames. + + CONFIG_CDP_DEVICE_ID_PREFIX + + A two character string which is prefixed to the MAC address + of the device. + + CONFIG_CDP_PORT_ID + + A printf format string which contains the ascii name of + the port. Normally is set to "eth%d" which sets + eth0 for the first ethernet, eth1 for the second etc. + + CONFIG_CDP_CAPABILITIES + + A 32bit integer which indicates the device capabilities; + 0x00000010 for a normal host which does not forwards. + + CONFIG_CDP_VERSION + + An ascii string containing the version of the software. + + CONFIG_CDP_PLATFORM + + An ascii string containing the name of the platform. + + CONFIG_CDP_TRIGGER + + A 32bit integer sent on the trigger. + + CONFIG_CDP_POWER_CONSUMPTION + + A 16bit integer containing the power consumption of the + device in .1 of milliwatts. + + CONFIG_CDP_APPLIANCE_VLAN_TYPE + + A byte containing the id of the VLAN. + +- Status LED: CONFIG_STATUS_LED + + Several configurations allow to display the current + status using a LED. For instance, the LED will blink + fast while running U-Boot code, stop blinking as + soon as a reply to a BOOTP request was received, and + start blinking slow once the Linux kernel is running + (supported by a status LED driver in the Linux + kernel). Defining CONFIG_STATUS_LED enables this + feature in U-Boot. + +- CAN Support: CONFIG_CAN_DRIVER + + Defining CONFIG_CAN_DRIVER enables CAN driver support + on those systems that support this (optional) + feature, like the TQM8xxL modules. + +- I2C Support: CONFIG_HARD_I2C | CONFIG_SOFT_I2C + + These enable I2C serial bus commands. Defining either of + (but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will + include the appropriate I2C driver for the selected cpu. + + This will allow you to use i2c commands at the u-boot + command line (as long as you set CFG_CMD_I2C in + CONFIG_COMMANDS) and communicate with i2c based realtime + clock chips. See common/cmd_i2c.c for a description of the + command line interface. + + CONFIG_HARD_I2C selects the CPM hardware driver for I2C. + + CONFIG_SOFT_I2C configures u-boot to use a software (aka + bit-banging) driver instead of CPM or similar hardware + support for I2C. + + There are several other quantities that must also be + defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C. + + In both cases you will need to define CFG_I2C_SPEED + to be the frequency (in Hz) at which you wish your i2c bus + to run and CFG_I2C_SLAVE to be the address of this node (ie + the cpu's i2c node address). + + Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c) + sets the cpu up as a master node and so its address should + therefore be cleared to 0 (See, eg, MPC823e User's Manual + p.16-473). So, set CFG_I2C_SLAVE to 0. + + That's all that's required for CONFIG_HARD_I2C. + + If you use the software i2c interface (CONFIG_SOFT_I2C) + then the following macros need to be defined (examples are + from include/configs/lwmon.h): + + I2C_INIT + + (Optional). Any commands necessary to enable the I2C + controller or configure ports. + + eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) + + I2C_PORT + + (Only for MPC8260 CPU). The I/O port to use (the code + assumes both bits are on the same port). Valid values + are 0..3 for ports A..D. + + I2C_ACTIVE + + The code necessary to make the I2C data line active + (driven). If the data line is open collector, this + define can be null. + + eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) + + I2C_TRISTATE + + The code necessary to make the I2C data line tri-stated + (inactive). If the data line is open collector, this + define can be null. + + eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) + + I2C_READ + + Code that returns TRUE if the I2C data line is high, + FALSE if it is low. + + eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) + + I2C_SDA(bit) + + If is TRUE, sets the I2C data line high. If it + is FALSE, it clears it (low). + + eg: #define I2C_SDA(bit) \ + if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA + + I2C_SCL(bit) + + If is TRUE, sets the I2C clock line high. If it + is FALSE, it clears it (low). + + eg: #define I2C_SCL(bit) \ + if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL + + I2C_DELAY + + This delay is invoked four times per clock cycle so this + controls the rate of data transfer. The data rate thus + is 1 / (I2C_DELAY * 4). Often defined to be something + like: + + #define I2C_DELAY udelay(2) + + CFG_I2C_INIT_BOARD + + When a board is reset during an i2c bus transfer + chips might think that the current transfer is still + in progress. On some boards it is possible to access + the i2c SCLK line directly, either by using the + processor pin as a GPIO or by having a second pin + connected to the bus. If this option is defined a + custom i2c_init_board() routine in boards/xxx/board.c + is run early in the boot sequence. + + CONFIG_I2CFAST (PPC405GP|PPC405EP only) + + This option enables configuration of bi_iic_fast[] flags + in u-boot bd_info structure based on u-boot environment + variable "i2cfast". (see also i2cfast) + +- SPI Support: CONFIG_SPI + + Enables SPI driver (so far only tested with + SPI EEPROM, also an instance works with Crystal A/D and + D/As on the SACSng board) + + CONFIG_SPI_X + + Enables extended (16-bit) SPI EEPROM addressing. + (symmetrical to CONFIG_I2C_X) + + CONFIG_SOFT_SPI + + Enables a software (bit-bang) SPI driver rather than + using hardware support. This is a general purpose + driver that only requires three general I/O port pins + (two outputs, one input) to function. If this is + defined, the board configuration must define several + SPI configuration items (port pins to use, etc). For + an example, see include/configs/sacsng.h. + +- FPGA Support: CONFIG_FPGA_COUNT + + Specify the number of FPGA devices to support. + + CONFIG_FPGA + + Used to specify the types of FPGA devices. For example, + #define CONFIG_FPGA CFG_XILINX_VIRTEX2 + + CFG_FPGA_PROG_FEEDBACK + + Enable printing of hash marks during FPGA configuration. + + CFG_FPGA_CHECK_BUSY + + Enable checks on FPGA configuration interface busy + status by the configuration function. This option + will require a board or device specific function to + be written. + + CONFIG_FPGA_DELAY + + If defined, a function that provides delays in the FPGA + configuration driver. + + CFG_FPGA_CHECK_CTRLC + Allow Control-C to interrupt FPGA configuration + + CFG_FPGA_CHECK_ERROR + + Check for configuration errors during FPGA bitfile + loading. For example, abort during Virtex II + configuration if the INIT_B line goes low (which + indicated a CRC error). + + CFG_FPGA_WAIT_INIT + + Maximum time to wait for the INIT_B line to deassert + after PROB_B has been deasserted during a Virtex II + FPGA configuration sequence. The default time is 500 + mS. + + CFG_FPGA_WAIT_BUSY + + Maximum time to wait for BUSY to deassert during + Virtex II FPGA configuration. The default is 5 mS. + + CFG_FPGA_WAIT_CONFIG + + Time to wait after FPGA configuration. The default is + 200 mS. + +- Configuration Management: + CONFIG_IDENT_STRING + + If defined, this string will be added to the U-Boot + version information (U_BOOT_VERSION) + +- Vendor Parameter Protection: + + U-Boot considers the values of the environment + variables "serial#" (Board Serial Number) and + "ethaddr" (Ethernet Address) to be parameters that + are set once by the board vendor / manufacturer, and + protects these variables from casual modification by + the user. Once set, these variables are read-only, + and write or delete attempts are rejected. You can + change this behviour: + + If CONFIG_ENV_OVERWRITE is #defined in your config + file, the write protection for vendor parameters is + completely disabled. Anybody can change or delete + these parameters. + + Alternatively, if you #define _both_ CONFIG_ETHADDR + _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default + ethernet address is installed in the environment, + which can be changed exactly ONCE by the user. [The + serial# is unaffected by this, i. e. it remains + read-only.] + +- Protected RAM: + CONFIG_PRAM + + Define this variable to enable the reservation of + "protected RAM", i. e. RAM which is not overwritten + by U-Boot. Define CONFIG_PRAM to hold the number of + kB you want to reserve for pRAM. You can overwrite + this default value by defining an environment + variable "pram" to the number of kB you want to + reserve. Note that the board info structure will + still show the full amount of RAM. If pRAM is + reserved, a new environment variable "mem" will + automatically be defined to hold the amount of + remaining RAM in a form that can be passed as boot + argument to Linux, for instance like that: + + setenv bootargs ... mem=\${mem} + saveenv + + This way you can tell Linux not to use this memory, + either, which results in a memory region that will + not be affected by reboots. + + *WARNING* If your board configuration uses automatic + detection of the RAM size, you must make sure that + this memory test is non-destructive. So far, the + following board configurations are known to be + "pRAM-clean": + + ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL, + HERMES, IP860, RPXlite, LWMON, LANTEC, + PCU_E, FLAGADM, TQM8260 + +- Error Recovery: + CONFIG_PANIC_HANG + + Define this variable to stop the system in case of a + fatal error, so that you have to reset it manually. + This is probably NOT a good idea for an embedded + system where you want to system to reboot + automatically as fast as possible, but it may be + useful during development since you can try to debug + the conditions that lead to the situation. + + CONFIG_NET_RETRY_COUNT + + This variable defines the number of retries for + network operations like ARP, RARP, TFTP, or BOOTP + before giving up the operation. If not defined, a + default value of 5 is used. + +- Command Interpreter: + CFG_AUTO_COMPLETE + + Enable auto completion of commands using TAB. + + CFG_HUSH_PARSER + + Define this variable to enable the "hush" shell (from + Busybox) as command line interpreter, thus enabling + powerful command line syntax like + if...then...else...fi conditionals or `&&' and '||' + constructs ("shell scripts"). + + If undefined, you get the old, much simpler behaviour + with a somewhat smaller memory footprint. + + + CFG_PROMPT_HUSH_PS2 + + This defines the secondary prompt string, which is + printed when the command interpreter needs more input + to complete a command. Usually "> ". + + Note: + + In the current implementation, the local variables + space and global environment variables space are + separated. Local variables are those you define by + simply typing `name=value'. To access a local + variable later on, you have write `$name' or + `${name}'; to execute the contents of a variable + directly type `$name' at the command prompt. + + Global environment variables are those you use + setenv/printenv to work with. To run a command stored + in such a variable, you need to use the run command, + and you must not use the '$' sign to access them. + + To store commands and special characters in a + variable, please use double quotation marks + surrounding the whole text of the variable, instead + of the backslashes before semicolons and special + symbols. + +- Default Environment: + CONFIG_EXTRA_ENV_SETTINGS + + Define this to contain any number of null terminated + strings (variable = value pairs) that will be part of + the default environment compiled into the boot image. + + For example, place something like this in your + board's config file: + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "myvar1=value1\0" \ + "myvar2=value2\0" + + Warning: This method is based on knowledge about the + internal format how the environment is stored by the + U-Boot code. This is NOT an official, exported + interface! Although it is unlikely that this format + will change soon, there is no guarantee either. + You better know what you are doing here. + + Note: overly (ab)use of the default environment is + discouraged. Make sure to check other ways to preset + the environment like the autoscript function or the + boot command first. + +- DataFlash Support: + CONFIG_HAS_DATAFLASH + + Defining this option enables DataFlash features and + allows to read/write in Dataflash via the standard + commands cp, md... + +- SystemACE Support: + CONFIG_SYSTEMACE + + Adding this option adds support for Xilinx SystemACE + chips attached via some sort of local bus. The address + of the chip must alsh be defined in the + CFG_SYSTEMACE_BASE macro. For example: + + #define CONFIG_SYSTEMACE + #define CFG_SYSTEMACE_BASE 0xf0000000 + + When SystemACE support is added, the "ace" device type + becomes available to the fat commands, i.e. fatls. + +- TFTP Fixed UDP Port: + CONFIG_TFTP_PORT + + If this is defined, the environment variable tftpsrcp + is used to supply the TFTP UDP source port value. + If tftpsrcp isn't defined, the normal pseudo-random port + number generator is used. + + Also, the environment variable tftpdstp is used to supply + the TFTP UDP destination port value. If tftpdstp isn't + defined, the normal port 69 is used. + + The purpose for tftpsrcp is to allow a TFTP server to + blindly start the TFTP transfer using the pre-configured + target IP address and UDP port. This has the effect of + "punching through" the (Windows XP) firewall, allowing + the remainder of the TFTP transfer to proceed normally. + A better solution is to properly configure the firewall, + but sometimes that is not allowed. + +- Show boot progress: + CONFIG_SHOW_BOOT_PROGRESS + + Defining this option allows to add some board- + specific code (calling a user-provided function + "show_boot_progress(int)") that enables you to show + the system's boot progress on some display (for + example, some LED's) on your board. At the moment, + the following checkpoints are implemented: + + Arg Where When + 1 common/cmd_bootm.c before attempting to boot an image + -1 common/cmd_bootm.c Image header has bad magic number + 2 common/cmd_bootm.c Image header has correct magic number + -2 common/cmd_bootm.c Image header has bad checksum + 3 common/cmd_bootm.c Image header has correct checksum + -3 common/cmd_bootm.c Image data has bad checksum + 4 common/cmd_bootm.c Image data has correct checksum + -4 common/cmd_bootm.c Image is for unsupported architecture + 5 common/cmd_bootm.c Architecture check OK + -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi, standalone) + 6 common/cmd_bootm.c Image Type check OK + -6 common/cmd_bootm.c gunzip uncompression error + -7 common/cmd_bootm.c Unimplemented compression type + 7 common/cmd_bootm.c Uncompression OK + -8 common/cmd_bootm.c Wrong Image Type (not kernel, multi, standalone) + 8 common/cmd_bootm.c Image Type check OK + -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX) + 9 common/cmd_bootm.c Start initial ramdisk verification + -10 common/cmd_bootm.c Ramdisk header has bad magic number + -11 common/cmd_bootm.c Ramdisk header has bad checksum + 10 common/cmd_bootm.c Ramdisk header is OK + -12 common/cmd_bootm.c Ramdisk data has bad checksum + 11 common/cmd_bootm.c Ramdisk data has correct checksum + 12 common/cmd_bootm.c Ramdisk verification complete, start loading + -13 common/cmd_bootm.c Wrong Image Type (not PPC Linux Ramdisk) + 13 common/cmd_bootm.c Start multifile image verification + 14 common/cmd_bootm.c No initial ramdisk, no multifile, continue. + 15 common/cmd_bootm.c All preparation done, transferring control to OS + + -30 lib_ppc/board.c Fatal error, hang the system + -31 post/post.c POST test failed, detected by post_output_backlog() + -32 post/post.c POST test failed, detected by post_run_single() + + -1 common/cmd_doc.c Bad usage of "doc" command + -1 common/cmd_doc.c No boot device + -1 common/cmd_doc.c Unknown Chip ID on boot device + -1 common/cmd_doc.c Read Error on boot device + -1 common/cmd_doc.c Image header has bad magic number + + -1 common/cmd_ide.c Bad usage of "ide" command + -1 common/cmd_ide.c No boot device + -1 common/cmd_ide.c Unknown boot device + -1 common/cmd_ide.c Unknown partition table + -1 common/cmd_ide.c Invalid partition type + -1 common/cmd_ide.c Read Error on boot device + -1 common/cmd_ide.c Image header has bad magic number + + -1 common/cmd_nand.c Bad usage of "nand" command + -1 common/cmd_nand.c No boot device + -1 common/cmd_nand.c Unknown Chip ID on boot device + -1 common/cmd_nand.c Read Error on boot device + -1 common/cmd_nand.c Image header has bad magic number + + -1 common/env_common.c Environment has a bad CRC, using default + + +Modem Support: +-------------- + +[so far only for SMDK2400 and TRAB boards] + +- Modem support endable: + CONFIG_MODEM_SUPPORT + +- RTS/CTS Flow control enable: + CONFIG_HWFLOW + +- Modem debug support: + CONFIG_MODEM_SUPPORT_DEBUG + + Enables debugging stuff (char screen[1024], dbg()) + for modem support. Useful only with BDI2000. + +- Interrupt support (PPC): + + There are common interrupt_init() and timer_interrupt() + for all PPC archs. interrupt_init() calls interrupt_init_cpu() + for cpu specific initialization. interrupt_init_cpu() + should set decrementer_count to appropriate value. If + cpu resets decrementer automatically after interrupt + (ppc4xx) it should set decrementer_count to zero. + timer_interrupt() calls timer_interrupt_cpu() for cpu + specific handling. If board has watchdog / status_led + / other_activity_monitor it works automatically from + general timer_interrupt(). + +- General: + + In the target system modem support is enabled when a + specific key (key combination) is pressed during + power-on. Otherwise U-Boot will boot normally + (autoboot). The key_pressed() fuction is called from + board_init(). Currently key_pressed() is a dummy + function, returning 1 and thus enabling modem + initialization. + + If there are no modem init strings in the + environment, U-Boot proceed to autoboot; the + previous output (banner, info printfs) will be + supressed, though. + + See also: doc/README.Modem + + +Configuration Settings: +----------------------- + +- CFG_LONGHELP: Defined when you want long help messages included; + undefine this when you're short of memory. + +- CFG_PROMPT: This is what U-Boot prints on the console to + prompt for user input. + +- CFG_CBSIZE: Buffer size for input from the Console + +- CFG_PBSIZE: Buffer size for Console output + +- CFG_MAXARGS: max. Number of arguments accepted for monitor commands + +- CFG_BARGSIZE: Buffer size for Boot Arguments which are passed to + the application (usually a Linux kernel) when it is + booted + +- CFG_BAUDRATE_TABLE: + List of legal baudrate settings for this board. + +- CFG_CONSOLE_INFO_QUIET + Suppress display of console information at boot. + +- CFG_CONSOLE_IS_IN_ENV + If the board specific function + extern int overwrite_console (void); + returns 1, the stdin, stderr and stdout are switched to the + serial port, else the settings in the environment are used. + +- CFG_CONSOLE_OVERWRITE_ROUTINE + Enable the call to overwrite_console(). + +- CFG_CONSOLE_ENV_OVERWRITE + Enable overwrite of previous console environment settings. + +- CFG_MEMTEST_START, CFG_MEMTEST_END: + Begin and End addresses of the area used by the + simple memory test. + +- CFG_ALT_MEMTEST: + Enable an alternate, more extensive memory test. + +- CFG_MEMTEST_SCRATCH: + Scratch address used by the alternate memory test + You only need to set this if address zero isn't writeable + +- CFG_TFTP_LOADADDR: + Default load address for network file downloads + +- CFG_LOADS_BAUD_CHANGE: + Enable temporary baudrate change while serial download + +- CFG_SDRAM_BASE: + Physical start address of SDRAM. _Must_ be 0 here. + +- CFG_MBIO_BASE: + Physical start address of Motherboard I/O (if using a + Cogent motherboard) + +- CFG_FLASH_BASE: + Physical start address of Flash memory. + +- CFG_MONITOR_BASE: + Physical start address of boot monitor code (set by + make config files to be same as the text base address + (TEXT_BASE) used when linking) - same as + CFG_FLASH_BASE when booting from flash. + +- CFG_MONITOR_LEN: + Size of memory reserved for monitor code, used to + determine _at_compile_time_ (!) if the environment is + embedded within the U-Boot image, or in a separate + flash sector. + +- CFG_MALLOC_LEN: + Size of DRAM reserved for malloc() use. + +- CFG_BOOTM_LEN: + Normally compressed uImages are limited to an + uncompressed size of 8 MBytes. If this is not enough, + you can define CFG_BOOTM_LEN in your board config file + to adjust this setting to your needs. + +- CFG_BOOTMAPSZ: + Maximum size of memory mapped by the startup code of + the Linux kernel; all data that must be processed by + the Linux kernel (bd_info, boot arguments, eventually + initrd image) must be put below this limit. + +- CFG_MAX_FLASH_BANKS: + Max number of Flash memory banks + +- CFG_MAX_FLASH_SECT: + Max number of sectors on a Flash chip + +- CFG_FLASH_ERASE_TOUT: + Timeout for Flash erase operations (in ms) + +- CFG_FLASH_WRITE_TOUT: + Timeout for Flash write operations (in ms) + +- CFG_FLASH_LOCK_TOUT + Timeout for Flash set sector lock bit operation (in ms) + +- CFG_FLASH_UNLOCK_TOUT + Timeout for Flash clear lock bits operation (in ms) + +- CFG_FLASH_PROTECTION + If defined, hardware flash sectors protection is used + instead of U-Boot software protection. + +- CFG_DIRECT_FLASH_TFTP: + + Enable TFTP transfers directly to flash memory; + without this option such a download has to be + performed in two steps: (1) download to RAM, and (2) + copy from RAM to flash. + + The two-step approach is usually more reliable, since + you can check if the download worked before you erase + the flash, but in some situations (when sytem RAM is + too limited to allow for a tempory copy of the + downloaded image) this option may be very useful. + +- CFG_FLASH_CFI: + Define if the flash driver uses extra elements in the + common flash structure for storing flash geometry. + +- CFG_FLASH_CFI_DRIVER + This option also enables the building of the cfi_flash driver + in the drivers directory + +- CFG_FLASH_QUIET_TEST + If this option is defined, the common CFI flash doesn't + print it's warning upon not recognized FLASH banks. This + is useful, if some of the configured banks are only + optionally available. + +- CFG_RX_ETH_BUFFER: + Defines the number of ethernet receive buffers. On some + ethernet controllers it is recommended to set this value + to 8 or even higher (EEPRO100 or 405 EMAC), since all + buffers can be full shortly after enabling the interface + on high ethernet traffic. + Defaults to 4 if not defined. + +The following definitions that deal with the placement and management +of environment data (variable area); in general, we support the +following configurations: + +- CFG_ENV_IS_IN_FLASH: + + Define this if the environment is in flash memory. + + a) The environment occupies one whole flash sector, which is + "embedded" in the text segment with the U-Boot code. This + happens usually with "bottom boot sector" or "top boot + sector" type flash chips, which have several smaller + sectors at the start or the end. For instance, such a + layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In + such a case you would place the environment in one of the + 4 kB sectors - with U-Boot code before and after it. With + "top boot sector" type flash chips, you would put the + environment in one of the last sectors, leaving a gap + between U-Boot and the environment. + + - CFG_ENV_OFFSET: + + Offset of environment data (variable area) to the + beginning of flash memory; for instance, with bottom boot + type flash chips the second sector can be used: the offset + for this sector is given here. + + CFG_ENV_OFFSET is used relative to CFG_FLASH_BASE. + + - CFG_ENV_ADDR: + + This is just another way to specify the start address of + the flash sector containing the environment (instead of + CFG_ENV_OFFSET). + + - CFG_ENV_SECT_SIZE: + + Size of the sector containing the environment. + + + b) Sometimes flash chips have few, equal sized, BIG sectors. + In such a case you don't want to spend a whole sector for + the environment. + + - CFG_ENV_SIZE: + + If you use this in combination with CFG_ENV_IS_IN_FLASH + and CFG_ENV_SECT_SIZE, you can specify to use only a part + of this flash sector for the environment. This saves + memory for the RAM copy of the environment. + + It may also save flash memory if you decide to use this + when your environment is "embedded" within U-Boot code, + since then the remainder of the flash sector could be used + for U-Boot code. It should be pointed out that this is + STRONGLY DISCOURAGED from a robustness point of view: + updating the environment in flash makes it always + necessary to erase the WHOLE sector. If something goes + wrong before the contents has been restored from a copy in + RAM, your target system will be dead. + + - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND + + These settings describe a second storage area used to hold + a redundand copy of the environment data, so that there is + a valid backup copy in case there is a power failure during + a "saveenv" operation. + +BE CAREFUL! Any changes to the flash layout, and some changes to the +source code will make it necessary to adapt /u-boot.lds* +accordingly! + + +- CFG_ENV_IS_IN_NVRAM: + + Define this if you have some non-volatile memory device + (NVRAM, battery buffered SRAM) which you want to use for the + environment. + + - CFG_ENV_ADDR: + - CFG_ENV_SIZE: + + These two #defines are used to determin the memory area you + want to use for environment. It is assumed that this memory + can just be read and written to, without any special + provision. + +BE CAREFUL! The first access to the environment happens quite early +in U-Boot initalization (when we try to get the setting of for the +console baudrate). You *MUST* have mappend your NVRAM area then, or +U-Boot will hang. + +Please note that even with NVRAM we still use a copy of the +environment in RAM: we could work on NVRAM directly, but we want to +keep settings there always unmodified except somebody uses "saveenv" +to save the current settings. + + +- CFG_ENV_IS_IN_EEPROM: + + Use this if you have an EEPROM or similar serial access + device and a driver for it. + + - CFG_ENV_OFFSET: + - CFG_ENV_SIZE: + + These two #defines specify the offset and size of the + environment area within the total memory of your EEPROM. + + - CFG_I2C_EEPROM_ADDR: + If defined, specified the chip address of the EEPROM device. + The default address is zero. + + - CFG_EEPROM_PAGE_WRITE_BITS: + If defined, the number of bits used to address bytes in a + single page in the EEPROM device. A 64 byte page, for example + would require six bits. + + - CFG_EEPROM_PAGE_WRITE_DELAY_MS: + If defined, the number of milliseconds to delay between + page writes. The default is zero milliseconds. + + - CFG_I2C_EEPROM_ADDR_LEN: + The length in bytes of the EEPROM memory array address. Note + that this is NOT the chip address length! + + - CFG_I2C_EEPROM_ADDR_OVERFLOW: + EEPROM chips that implement "address overflow" are ones + like Catalyst 24WC04/08/16 which has 9/10/11 bits of + address and the extra bits end up in the "chip address" bit + slots. This makes a 24WC08 (1Kbyte) chip look like four 256 + byte chips. + + Note that we consider the length of the address field to + still be one byte because the extra address bits are hidden + in the chip address. + + - CFG_EEPROM_SIZE: + The size in bytes of the EEPROM device. + + +- CFG_ENV_IS_IN_DATAFLASH: + + Define this if you have a DataFlash memory device which you + want to use for the environment. + + - CFG_ENV_OFFSET: + - CFG_ENV_ADDR: + - CFG_ENV_SIZE: + + These three #defines specify the offset and size of the + environment area within the total memory of your DataFlash placed + at the specified address. + +- CFG_ENV_IS_IN_NAND: + + Define this if you have a NAND device which you want to use + for the environment. + + - CFG_ENV_OFFSET: + - CFG_ENV_SIZE: + + These two #defines specify the offset and size of the environment + area within the first NAND device. + + - CFG_ENV_OFFSET_REDUND + + This setting describes a second storage area of CFG_ENV_SIZE + size used to hold a redundant copy of the environment data, + so that there is a valid backup copy in case there is a + power failure during a "saveenv" operation. + + Note: CFG_ENV_OFFSET and CFG_ENV_OFFSET_REDUND must be aligned + to a block boundary, and CFG_ENV_SIZE must be a multiple of + the NAND devices block size. + +- CFG_SPI_INIT_OFFSET + + Defines offset to the initial SPI buffer area in DPRAM. The + area is used at an early stage (ROM part) if the environment + is configured to reside in the SPI EEPROM: We need a 520 byte + scratch DPRAM area. It is used between the two initialization + calls (spi_init_f() and spi_init_r()). A value of 0xB00 seems + to be a good choice since it makes it far enough from the + start of the data area as well as from the stack pointer. + +Please note that the environment is read-only as long as the monitor +has been relocated to RAM and a RAM copy of the environment has been +created; also, when using EEPROM you will have to use getenv_r() +until then to read environment variables. + +The environment is protected by a CRC32 checksum. Before the monitor +is relocated into RAM, as a result of a bad CRC you will be working +with the compiled-in default environment - *silently*!!! [This is +necessary, because the first environment variable we need is the +"baudrate" setting for the console - if we have a bad CRC, we don't +have any device yet where we could complain.] + +Note: once the monitor has been relocated, then it will complain if +the default environment is used; a new CRC is computed as soon as you +use the "saveenv" command to store a valid environment. + +- CFG_FAULT_ECHO_LINK_DOWN: + Echo the inverted Ethernet link state to the fault LED. + + Note: If this option is active, then CFG_FAULT_MII_ADDR + also needs to be defined. + +- CFG_FAULT_MII_ADDR: + MII address of the PHY to check for the Ethernet link state. + +- CFG_64BIT_VSPRINTF: + Makes vsprintf (and all *printf functions) support printing + of 64bit values by using the L quantifier + +- CFG_64BIT_STRTOUL: + Adds simple_strtoull that returns a 64bit value + +Low Level (hardware related) configuration options: +--------------------------------------------------- + +- CFG_CACHELINE_SIZE: + Cache Line Size of the CPU. + +- CFG_DEFAULT_IMMR: + Default address of the IMMR after system reset. + + Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU, + and RPXsuper) to be able to adjust the position of + the IMMR register after a reset. + +- Floppy Disk Support: + CFG_FDC_DRIVE_NUMBER + + the default drive number (default value 0) + + CFG_ISA_IO_STRIDE + + defines the spacing between fdc chipset registers + (default value 1) + + CFG_ISA_IO_OFFSET + + defines the offset of register from address. It + depends on which part of the data bus is connected to + the fdc chipset. (default value 0) + + If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and + CFG_FDC_DRIVE_NUMBER are undefined, they take their + default value. + + if CFG_FDC_HW_INIT is defined, then the function + fdc_hw_init() is called at the beginning of the FDC + setup. fdc_hw_init() must be provided by the board + source code. It is used to make hardware dependant + initializations. + +- CFG_IMMR: Physical address of the Internal Memory. + DO NOT CHANGE unless you know exactly what you're + doing! (11-4) [MPC8xx/82xx systems only] + +- CFG_INIT_RAM_ADDR: + + Start address of memory area that can be used for + initial data and stack; please note that this must be + writable memory that is working WITHOUT special + initialization, i. e. you CANNOT use normal RAM which + will become available only after programming the + memory controller and running certain initialization + sequences. + + U-Boot uses the following memory types: + - MPC8xx and MPC8260: IMMR (internal memory of the CPU) + - MPC824X: data cache + - PPC4xx: data cache + +- CFG_GBL_DATA_OFFSET: + + Offset of the initial data structure in the memory + area defined by CFG_INIT_RAM_ADDR. Usually + CFG_GBL_DATA_OFFSET is chosen such that the initial + data is located at the end of the available space + (sometimes written as (CFG_INIT_RAM_END - + CFG_INIT_DATA_SIZE), and the initial stack is just + below that area (growing from (CFG_INIT_RAM_ADDR + + CFG_GBL_DATA_OFFSET) downward. + + Note: + On the MPC824X (or other systems that use the data + cache for initial memory) the address chosen for + CFG_INIT_RAM_ADDR is basically arbitrary - it must + point to an otherwise UNUSED address space between + the top of RAM and the start of the PCI space. + +- CFG_SIUMCR: SIU Module Configuration (11-6) + +- CFG_SYPCR: System Protection Control (11-9) + +- CFG_TBSCR: Time Base Status and Control (11-26) + +- CFG_PISCR: Periodic Interrupt Status and Control (11-31) + +- CFG_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) + +- CFG_SCCR: System Clock and reset Control Register (15-27) + +- CFG_OR_TIMING_SDRAM: + SDRAM timing + +- CFG_MAMR_PTA: + periodic timer for refresh + +- CFG_DER: Debug Event Register (37-47) + +- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CFG_REMAP_OR_AM, + CFG_PRELIM_OR_AM, CFG_OR_TIMING_FLASH, CFG_OR0_REMAP, + CFG_OR0_PRELIM, CFG_BR0_PRELIM, CFG_OR1_REMAP, CFG_OR1_PRELIM, + CFG_BR1_PRELIM: + Memory Controller Definitions: BR0/1 and OR0/1 (FLASH) + +- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE, + CFG_OR_TIMING_SDRAM, CFG_OR2_PRELIM, CFG_BR2_PRELIM, + CFG_OR3_PRELIM, CFG_BR3_PRELIM: + Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM) + +- CFG_MAMR_PTA, CFG_MPTPR_2BK_4K, CFG_MPTPR_1BK_4K, CFG_MPTPR_2BK_8K, + CFG_MPTPR_1BK_8K, CFG_MAMR_8COL, CFG_MAMR_9COL: + Machine Mode Register and Memory Periodic Timer + Prescaler definitions (SDRAM timing) + +- CFG_I2C_UCODE_PATCH, CFG_I2C_DPMEM_OFFSET [0x1FC0]: + enable I2C microcode relocation patch (MPC8xx); + define relocation offset in DPRAM [DSP2] + +- CFG_SPI_UCODE_PATCH, CFG_SPI_DPMEM_OFFSET [0x1FC0]: + enable SPI microcode relocation patch (MPC8xx); + define relocation offset in DPRAM [SCC4] + +- CFG_USE_OSCCLK: + Use OSCM clock mode on MBX8xx board. Be careful, + wrong setting might damage your board. Read + doc/README.MBX before setting this variable! + +- CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) + Offset of the bootmode word in DPRAM used by post + (Power On Self Tests). This definition overrides + #define'd default value in commproc.h resp. + cpm_8260.h. + +- CFG_PCI_SLV_MEM_LOCAL, CFG_PCI_SLV_MEM_BUS, CFG_PICMR0_MASK_ATTRIB, + CFG_PCI_MSTR0_LOCAL, CFG_PCIMSK0_MASK, CFG_PCI_MSTR1_LOCAL, + CFG_PCIMSK1_MASK, CFG_PCI_MSTR_MEM_LOCAL, CFG_PCI_MSTR_MEM_BUS, + CFG_CPU_PCI_MEM_START, CFG_PCI_MSTR_MEM_SIZE, CFG_POCMR0_MASK_ATTRIB, + CFG_PCI_MSTR_MEMIO_LOCAL, CFG_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START, + CFG_PCI_MSTR_MEMIO_SIZE, CFG_POCMR1_MASK_ATTRIB, CFG_PCI_MSTR_IO_LOCAL, + CFG_PCI_MSTR_IO_BUS, CFG_CPU_PCI_IO_START, CFG_PCI_MSTR_IO_SIZE, + CFG_POCMR2_MASK_ATTRIB: (MPC826x only) + Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. + +- CONFIG_ETHER_ON_FEC[12] + Define to enable FEC[12] on a 8xx series processor. + +- CONFIG_FEC[12]_PHY + Define to the hardcoded PHY address which corresponds + to the given FEC; i. e. + #define CONFIG_FEC1_PHY 4 + means that the PHY with address 4 is connected to FEC1 + + When set to -1, means to probe for first available. + +- CONFIG_FEC[12]_PHY_NORXERR + The PHY does not have a RXERR line (RMII only). + (so program the FEC to ignore it). + +- CONFIG_RMII + Enable RMII mode for all FECs. + Note that this is a global option, we can't + have one FEC in standard MII mode and another in RMII mode. + +- CONFIG_CRC32_VERIFY + Add a verify option to the crc32 command. + The syntax is: + + => crc32 -v
+ + Where address/count indicate a memory area + and crc32 is the correct crc32 which the + area should have. + +- CONFIG_LOOPW + Add the "loopw" memory command. This only takes effect if + the memory commands are activated globally (CFG_CMD_MEM). + +- CONFIG_MX_CYCLIC + Add the "mdc" and "mwc" memory commands. These are cyclic + "md/mw" commands. + Examples: + + => mdc.b 10 4 500 + This command will print 4 bytes (10,11,12,13) each 500 ms. + + => mwc.l 100 12345678 10 + This command will write 12345678 to address 100 all 10 ms. + + This only takes effect if the memory commands are activated + globally (CFG_CMD_MEM). + +- CONFIG_SKIP_LOWLEVEL_INIT +- CONFIG_SKIP_RELOCATE_UBOOT + + [ARM only] If these variables are defined, then + certain low level initializations (like setting up + the memory controller) are omitted and/or U-Boot does + not relocate itself into RAM. + Normally these variables MUST NOT be defined. The + only exception is when U-Boot is loaded (to RAM) by + some other boot loader or by a debugger which + performs these intializations itself. + + +Building the Software: +====================== + +Building U-Boot has been tested in native PPC environments (on a +PowerBook G3 running LinuxPPC 2000) and in cross environments +(running RedHat 6.x and 7.x Linux on x86, Solaris 2.6 on a SPARC, and +NetBSD 1.5 on x86). + +If you are not using a native PPC environment, it is assumed that you +have the GNU cross compiling tools available in your path and named +with a prefix of "powerpc-linux-". If this is not the case, (e.g. if +you are using Monta Vista's Hard Hat Linux CDK 1.2) you must change +the definition of CROSS_COMPILE in Makefile. For HHL on a 4xx CPU, +change it to: + + CROSS_COMPILE = ppc_4xx- + + +U-Boot is intended to be simple to build. After installing the +sources you must configure U-Boot for one specific board type. This +is done by typing: + + make NAME_config + +where "NAME_config" is the name of one of the existing +configurations; the following names are supported: + + ADCIOP_config FPS860L_config omap730p2_config + ADS860_config GEN860T_config pcu_e_config + Alaska8220_config + AR405_config GENIETV_config PIP405_config + at91rm9200dk_config GTH_config QS823_config + CANBT_config hermes_config QS850_config + cmi_mpc5xx_config hymod_config QS860T_config + cogent_common_config IP860_config RPXlite_config + cogent_mpc8260_config IVML24_config RPXlite_DW_config + cogent_mpc8xx_config IVMS8_config RPXsuper_config + CPCI405_config JSE_config rsdproto_config + CPCIISER4_config LANTEC_config Sandpoint8240_config + csb272_config lwmon_config sbc8260_config + CU824_config MBX860T_config sbc8560_33_config + DUET_ADS_config MBX_config sbc8560_66_config + EBONY_config MPC8260ADS_config SM850_config + ELPT860_config MPC8540ADS_config SPD823TS_config + ESTEEM192E_config MPC8540EVAL_config stxgp3_config + ETX094_config MPC8560ADS_config SXNI855T_config + FADS823_config NETVIA_config TQM823L_config + FADS850SAR_config omap1510inn_config TQM850L_config + FADS860T_config omap1610h2_config TQM855L_config + FPS850L_config omap1610inn_config TQM860L_config + omap5912osk_config walnut_config + omap2420h4_config Yukon8220_config + ZPC1900_config + +Note: for some board special configuration names may exist; check if + additional information is available from the board vendor; for + instance, the TQM823L systems are available without (standard) + or with LCD support. You can select such additional "features" + when chosing the configuration, i. e. + + make TQM823L_config + - will configure for a plain TQM823L, i. e. no LCD support + + make TQM823L_LCD_config + - will configure for a TQM823L with U-Boot console on LCD + + etc. + + +Finally, type "make all", and you should get some working U-Boot +images ready for download to / installation on your system: + +- "u-boot.bin" is a raw binary image +- "u-boot" is an image in ELF binary format +- "u-boot.srec" is in Motorola S-Record format + + +Please be aware that the Makefiles assume you are using GNU make, so +for instance on NetBSD you might need to use "gmake" instead of +native "make". + + +If the system board that you have is not listed, then you will need +to port U-Boot to your hardware platform. To do this, follow these +steps: + +1. Add a new configuration option for your board to the toplevel + "Makefile" and to the "MAKEALL" script, using the existing + entries as examples. Note that here and at many other places + boards and other names are listed in alphabetical sort order. Please + keep this order. +2. Create a new directory to hold your board specific code. Add any + files you need. In your board directory, you will need at least + the "Makefile", a ".c", "flash.c" and "u-boot.lds". +3. Create a new configuration file "include/configs/.h" for + your board +3. If you're porting U-Boot to a new CPU, then also create a new + directory to hold your CPU specific code. Add any files you need. +4. Run "make _config" with your new name. +5. Type "make", and you should get a working "u-boot.srec" file + to be installed on your target system. +6. Debug and solve any problems that might arise. + [Of course, this last step is much harder than it sounds.] + + +Testing of U-Boot Modifications, Ports to New Hardware, etc.: +============================================================== + +If you have modified U-Boot sources (for instance added a new board +or support for new devices, a new CPU, etc.) you are expected to +provide feedback to the other developers. The feedback normally takes +the form of a "patch", i. e. a context diff against a certain (latest +official or latest in CVS) version of U-Boot sources. + +But before you submit such a patch, please verify that your modifi- +cation did not break existing code. At least make sure that *ALL* of +the supported boards compile WITHOUT ANY compiler warnings. To do so, +just run the "MAKEALL" script, which will configure and build U-Boot +for ALL supported system. Be warned, this will take a while. You can +select which (cross) compiler to use by passing a `CROSS_COMPILE' +environment variable to the script, i. e. to use the cross tools from +MontaVista's Hard Hat Linux you can type + + CROSS_COMPILE=ppc_8xx- MAKEALL + +or to build on a native PowerPC system you can type + + CROSS_COMPILE=' ' MAKEALL + +See also "U-Boot Porting Guide" below. + + +Monitor Commands - Overview: +============================ + +go - start application at address 'addr' +run - run commands in an environment variable +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +tftpboot- boot image via network using TFTP protocol + and env variables "ipaddr" and "serverip" + (and eventually "gatewayip") +rarpboot- boot image via network using RARP/TFTP protocol +diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd' +loads - load S-Record file over serial line +loadb - load binary file over serial line (kermit mode) +md - memory display +mm - memory modify (auto-incrementing) +nm - memory modify (constant address) +mw - memory write (fill) +cp - memory copy +cmp - memory compare +crc32 - checksum calculation +imd - i2c memory display +imm - i2c memory modify (auto-incrementing) +inm - i2c memory modify (constant address) +imw - i2c memory write (fill) +icrc32 - i2c checksum calculation +iprobe - probe to discover valid I2C chip addresses +iloop - infinite loop on address range +isdram - print SDRAM configuration information +sspi - SPI utility commands +base - print or set address offset +printenv- print environment variables +setenv - set environment variables +saveenv - save environment variables to persistent storage +protect - enable or disable FLASH write protection +erase - erase FLASH memory +flinfo - print FLASH memory information +bdinfo - print Board Info structure +iminfo - print header information for application image +coninfo - print console devices and informations +ide - IDE sub-system +loop - infinite loop on address range +loopw - infinite write loop on address range +mtest - simple RAM test +icache - enable or disable instruction cache +dcache - enable or disable data cache +reset - Perform RESET of the CPU +echo - echo args to console +version - print monitor version +help - print online help +? - alias for 'help' + + +Monitor Commands - Detailed Description: +======================================== + +TODO. + +For now: just type "help ". + + +Environment Variables: +====================== + +U-Boot supports user configuration using Environment Variables which +can be made persistent by saving to Flash memory. + +Environment Variables are set using "setenv", printed using +"printenv", and saved to Flash using "saveenv". Using "setenv" +without a value can be used to delete a variable from the +environment. As long as you don't save the environment you are +working with an in-memory copy. In case the Flash area containing the +environment is erased by accident, a default environment is provided. + +Some configuration options can be set using Environment Variables: + + baudrate - see CONFIG_BAUDRATE + + bootdelay - see CONFIG_BOOTDELAY + + bootcmd - see CONFIG_BOOTCOMMAND + + bootargs - Boot arguments when booting an RTOS image + + bootfile - Name of the image to load with TFTP + + autoload - if set to "no" (any string beginning with 'n'), + "bootp" will just load perform a lookup of the + configuration from the BOOTP server, but not try to + load any image using TFTP + + autostart - if set to "yes", an image loaded using the "bootp", + "rarpboot", "tftpboot" or "diskboot" commands will + be automatically started (by internally calling + "bootm") + + If set to "no", a standalone image passed to the + "bootm" command will be copied to the load address + (and eventually uncompressed), but NOT be started. + This can be used to load and uncompress arbitrary + data. + + i2cfast - (PPC405GP|PPC405EP only) + if set to 'y' configures Linux I2C driver for fast + mode (400kHZ). This environment variable is used in + initialization code. So, for changes to be effective + it must be saved and board must be reset. + + initrd_high - restrict positioning of initrd images: + If this variable is not set, initrd images will be + copied to the highest possible address in RAM; this + is usually what you want since it allows for + maximum initrd size. If for some reason you want to + make sure that the initrd image is loaded below the + CFG_BOOTMAPSZ limit, you can set this environment + variable to a value of "no" or "off" or "0". + Alternatively, you can set it to a maximum upper + address to use (U-Boot will still check that it + does not overwrite the U-Boot stack and data). + + For instance, when you have a system with 16 MB + RAM, and want to reserve 4 MB from use by Linux, + you can do this by adding "mem=12M" to the value of + the "bootargs" variable. However, now you must make + sure that the initrd image is placed in the first + 12 MB as well - this can be done with + + setenv initrd_high 00c00000 + + If you set initrd_high to 0xFFFFFFFF, this is an + indication to U-Boot that all addresses are legal + for the Linux kernel, including addresses in flash + memory. In this case U-Boot will NOT COPY the + ramdisk at all. This may be useful to reduce the + boot time on your system, but requires that this + feature is supported by your Linux kernel. + + ipaddr - IP address; needed for tftpboot command + + loadaddr - Default load address for commands like "bootp", + "rarpboot", "tftpboot", "loadb" or "diskboot" + + loads_echo - see CONFIG_LOADS_ECHO + + serverip - TFTP server IP address; needed for tftpboot command + + bootretry - see CONFIG_BOOT_RETRY_TIME + + bootdelaykey - see CONFIG_AUTOBOOT_DELAY_STR + + bootstopkey - see CONFIG_AUTOBOOT_STOP_STR + + ethprime - When CONFIG_NET_MULTI is enabled controls which + interface is used first. + + ethact - When CONFIG_NET_MULTI is enabled controls which + interface is currently active. For example you + can do the following + + => setenv ethact FEC ETHERNET + => ping 192.168.0.1 # traffic sent on FEC ETHERNET + => setenv ethact SCC ETHERNET + => ping 10.0.0.1 # traffic sent on SCC ETHERNET + + netretry - When set to "no" each network operation will + either succeed or fail without retrying. + When set to "once" the network operation will + fail when all the available network interfaces + are tried once without success. + Useful on scripts which control the retry operation + themselves. + + tftpsrcport - If this is set, the value is used for TFTP's + UDP source port. + + tftpdstport - If this is set, the value is used for TFTP's UDP + destination port instead of the Well Know Port 69. + + vlan - When set to a value < 4095 the traffic over + ethernet is encapsulated/received over 802.1q + VLAN tagged frames. + +The following environment variables may be used and automatically +updated by the network boot commands ("bootp" and "rarpboot"), +depending the information provided by your boot server: + + bootfile - see above + dnsip - IP address of your Domain Name Server + dnsip2 - IP address of your secondary Domain Name Server + gatewayip - IP address of the Gateway (Router) to use + hostname - Target hostname + ipaddr - see above + netmask - Subnet Mask + rootpath - Pathname of the root filesystem on the NFS server + serverip - see above + + +There are two special Environment Variables: + + serial# - contains hardware identification information such + as type string and/or serial number + ethaddr - Ethernet address + +These variables can be set only once (usually during manufacturing of +the board). U-Boot refuses to delete or overwrite these variables +once they have been set once. + + +Further special Environment Variables: + + ver - Contains the U-Boot version string as printed + with the "version" command. This variable is + readonly (see CONFIG_VERSION_VARIABLE). + + +Please note that changes to some configuration parameters may take +only effect after the next boot (yes, that's just like Windoze :-). + + +Command Line Parsing: +===================== + +There are two different command line parsers available with U-Boot: +the old "simple" one, and the much more powerful "hush" shell: + +Old, simple command line parser: +-------------------------------- + +- supports environment variables (through setenv / saveenv commands) +- several commands on one line, separated by ';' +- variable substitution using "... ${name} ..." syntax +- special characters ('$', ';') can be escaped by prefixing with '\', + for example: + setenv bootcmd bootm \${address} +- You can also escape text by enclosing in single apostrophes, for example: + setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off' + +Hush shell: +----------- + +- similar to Bourne shell, with control structures like + if...then...else...fi, for...do...done; while...do...done, + until...do...done, ... +- supports environment ("global") variables (through setenv / saveenv + commands) and local shell variables (through standard shell syntax + "name=value"); only environment variables can be used with "run" + command + +General rules: +-------------- + +(1) If a command line (or an environment variable executed by a "run" + command) contains several commands separated by semicolon, and + one of these commands fails, then the remaining commands will be + executed anyway. + +(2) If you execute several variables with one call to run (i. e. + calling run with a list af variables as arguments), any failing + command will cause "run" to terminate, i. e. the remaining + variables are not executed. + +Note for Redundant Ethernet Interfaces: +======================================= + +Some boards come with redundant ethernet interfaces; U-Boot supports +such configurations and is capable of automatic selection of a +"working" interface when needed. MAC assignment works as follows: + +Network interfaces are numbered eth0, eth1, eth2, ... Corresponding +MAC addresses can be stored in the environment as "ethaddr" (=>eth0), +"eth1addr" (=>eth1), "eth2addr", ... + +If the network interface stores some valid MAC address (for instance +in SROM), this is used as default address if there is NO correspon- +ding setting in the environment; if the corresponding environment +variable is set, this overrides the settings in the card; that means: + +o If the SROM has a valid MAC address, and there is no address in the + environment, the SROM's address is used. + +o If there is no valid address in the SROM, and a definition in the + environment exists, then the value from the environment variable is + used. + +o If both the SROM and the environment contain a MAC address, and + both addresses are the same, this MAC address is used. + +o If both the SROM and the environment contain a MAC address, and the + addresses differ, the value from the environment is used and a + warning is printed. + +o If neither SROM nor the environment contain a MAC address, an error + is raised. + + +Image Formats: +============== + +The "boot" commands of this monitor operate on "image" files which +can be basicly anything, preceeded by a special header; see the +definitions in include/image.h for details; basicly, the header +defines the following image properties: + +* Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD, + 4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks, + LynxOS, pSOS, QNX, RTEMS, ARTOS; + Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS). +* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86, + IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; + Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC). +* Compression Type (uncompressed, gzip, bzip2) +* Load Address +* Entry Point +* Image Name +* Image Timestamp + +The header is marked by a special Magic Number, and both the header +and the data portions of the image are secured against corruption by +CRC32 checksums. + + +Linux Support: +============== + +Although U-Boot should support any OS or standalone application +easily, the main focus has always been on Linux during the design of +U-Boot. + +U-Boot includes many features that so far have been part of some +special "boot loader" code within the Linux kernel. Also, any +"initrd" images to be used are no longer part of one big Linux image; +instead, kernel and "initrd" are separate images. This implementation +serves several purposes: + +- the same features can be used for other OS or standalone + applications (for instance: using compressed images to reduce the + Flash memory footprint) + +- it becomes much easier to port new Linux kernel versions because + lots of low-level, hardware dependent stuff are done by U-Boot + +- the same Linux kernel image can now be used with different "initrd" + images; of course this also means that different kernel images can + be run with the same "initrd". This makes testing easier (you don't + have to build a new "zImage.initrd" Linux image when you just + change a file in your "initrd"). Also, a field-upgrade of the + software is easier now. + + +Linux HOWTO: +============ + +Porting Linux to U-Boot based systems: +--------------------------------------- + +U-Boot cannot save you from doing all the necessary modifications to +configure the Linux device drivers for use with your target hardware +(no, we don't intend to provide a full virtual machine interface to +Linux :-). + +But now you can ignore ALL boot loader code (in arch/ppc/mbxboot). + +Just make sure your machine specific header file (for instance +include/asm-ppc/tqm8xx.h) includes the same definition of the Board +Information structure as we define in include/u-boot.h, and make +sure that your definition of IMAP_ADDR uses the same value as your +U-Boot configuration in CFG_IMMR. + + +Configuring the Linux kernel: +----------------------------- + +No specific requirements for U-Boot. Make sure you have some root +device (initial ramdisk, NFS) for your target system. + + +Building a Linux Image: +----------------------- + +With U-Boot, "normal" build targets like "zImage" or "bzImage" are +not used. If you use recent kernel source, a new build target +"uImage" will exist which automatically builds an image usable by +U-Boot. Most older kernels also have support for a "pImage" target, +which was introduced for our predecessor project PPCBoot and uses a +100% compatible format. + +Example: + + make TQM850L_config + make oldconfig + make dep + make uImage + +The "uImage" build target uses a special tool (in 'tools/mkimage') to +encapsulate a compressed Linux kernel image with header information, +CRC32 checksum etc. for use with U-Boot. This is what we are doing: + +* build a standard "vmlinux" kernel image (in ELF binary format): + +* convert the kernel into a raw binary image: + + ${CROSS_COMPILE}-objcopy -O binary \ + -R .note -R .comment \ + -S vmlinux linux.bin + +* compress the binary image: + + gzip -9 linux.bin + +* package compressed binary image for U-Boot: + + mkimage -A ppc -O linux -T kernel -C gzip \ + -a 0 -e 0 -n "Linux Kernel Image" \ + -d linux.bin.gz uImage + + +The "mkimage" tool can also be used to create ramdisk images for use +with U-Boot, either separated from the Linux kernel image, or +combined into one file. "mkimage" encapsulates the images with a 64 +byte header containing information about target architecture, +operating system, image type, compression method, entry points, time +stamp, CRC32 checksums, etc. + +"mkimage" can be called in two ways: to verify existing images and +print the header information, or to build new images. + +In the first form (with "-l" option) mkimage lists the information +contained in the header of an existing U-Boot image; this includes +checksum verification: + + tools/mkimage -l image + -l ==> list image header information + +The second form (with "-d" option) is used to build a U-Boot image +from a "data file" which is used as image payload: + + tools/mkimage -A arch -O os -T type -C comp -a addr -e ep \ + -n name -d data_file image + -A ==> set architecture to 'arch' + -O ==> set operating system to 'os' + -T ==> set image type to 'type' + -C ==> set compression type 'comp' + -a ==> set load address to 'addr' (hex) + -e ==> set entry point to 'ep' (hex) + -n ==> set image name to 'name' + -d ==> use image data from 'datafile' + +Right now, all Linux kernels for PowerPC systems use the same load +address (0x00000000), but the entry point address depends on the +kernel version: + +- 2.2.x kernels have the entry point at 0x0000000C, +- 2.3.x and later kernels have the entry point at 0x00000000. + +So a typical call to build a U-Boot image would read: + + -> tools/mkimage -n '2.4.4 kernel for TQM850L' \ + > -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \ + > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \ + > examples/uImage.TQM850L + Image Name: 2.4.4 kernel for TQM850L + Created: Wed Jul 19 02:34:59 2000 + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327.86 kB = 0.32 MB + Load Address: 0x00000000 + Entry Point: 0x00000000 + +To verify the contents of the image (or check for corruption): + + -> tools/mkimage -l examples/uImage.TQM850L + Image Name: 2.4.4 kernel for TQM850L + Created: Wed Jul 19 02:34:59 2000 + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327.86 kB = 0.32 MB + Load Address: 0x00000000 + Entry Point: 0x00000000 + +NOTE: for embedded systems where boot time is critical you can trade +speed for memory and install an UNCOMPRESSED image instead: this +needs more space in Flash, but boots much faster since it does not +need to be uncompressed: + + -> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz + -> tools/mkimage -n '2.4.4 kernel for TQM850L' \ + > -A ppc -O linux -T kernel -C none -a 0 -e 0 \ + > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \ + > examples/uImage.TQM850L-uncompressed + Image Name: 2.4.4 kernel for TQM850L + Created: Wed Jul 19 02:34:59 2000 + Image Type: PowerPC Linux Kernel Image (uncompressed) + Data Size: 792160 Bytes = 773.59 kB = 0.76 MB + Load Address: 0x00000000 + Entry Point: 0x00000000 + + +Similar you can build U-Boot images from a 'ramdisk.image.gz' file +when your kernel is intended to use an initial ramdisk: + + -> tools/mkimage -n 'Simple Ramdisk Image' \ + > -A ppc -O linux -T ramdisk -C gzip \ + > -d /LinuxPPC/images/SIMPLE-ramdisk.image.gz examples/simple-initrd + Image Name: Simple Ramdisk Image + Created: Wed Jan 12 14:01:50 2000 + Image Type: PowerPC Linux RAMDisk Image (gzip compressed) + Data Size: 566530 Bytes = 553.25 kB = 0.54 MB + Load Address: 0x00000000 + Entry Point: 0x00000000 + + +Installing a Linux Image: +------------------------- + +To downloading a U-Boot image over the serial (console) interface, +you must convert the image to S-Record format: + + objcopy -I binary -O srec examples/image examples/image.srec + +The 'objcopy' does not understand the information in the U-Boot +image header, so the resulting S-Record file will be relative to +address 0x00000000. To load it to a given address, you need to +specify the target address as 'offset' parameter with the 'loads' +command. + +Example: install the image to address 0x40100000 (which on the +TQM8xxL is in the first Flash bank): + + => erase 40100000 401FFFFF + + .......... done + Erased 8 sectors + + => loads 40100000 + ## Ready for S-Record download ... + ~>examples/image.srec + 1 2 3 4 5 6 7 8 9 10 11 12 13 ... + ... + 15989 15990 15991 15992 + [file transfer complete] + [connected] + ## Start Addr = 0x00000000 + + +You can check the success of the download using the 'iminfo' command; +this includes a checksum verification so you can be sure no data +corruption happened: + + => imi 40100000 + + ## Checking Image at 40100000 ... + Image Name: 2.2.13 for initrd on TQM850L + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327 kB = 0 MB + Load Address: 00000000 + Entry Point: 0000000c + Verifying Checksum ... OK + + +Boot Linux: +----------- + +The "bootm" command is used to boot an application that is stored in +memory (RAM or Flash). In case of a Linux kernel image, the contents +of the "bootargs" environment variable is passed to the kernel as +parameters. You can check and modify this variable using the +"printenv" and "setenv" commands: + + + => printenv bootargs + bootargs=root=/dev/ram + + => setenv bootargs root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 + + => printenv bootargs + bootargs=root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 + + => bootm 40020000 + ## Booting Linux kernel at 40020000 ... + Image Name: 2.2.13 for NFS on TQM850L + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 381681 Bytes = 372 kB = 0 MB + Load Address: 00000000 + Entry Point: 0000000c + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK + Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:35:17 MEST 2000 + Boot arguments: root=/dev/nfs rw nfsroot=10.0.0.2:/LinuxPPC nfsaddrs=10.0.0.99:10.0.0.2 + time_init: decrementer frequency = 187500000/60 + Calibrating delay loop... 49.77 BogoMIPS + Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000] + ... + +If you want to boot a Linux kernel with initial ram disk, you pass +the memory addresses of both the kernel and the initrd image (PPBCOOT +format!) to the "bootm" command: + + => imi 40100000 40200000 + + ## Checking Image at 40100000 ... + Image Name: 2.2.13 for initrd on TQM850L + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327 kB = 0 MB + Load Address: 00000000 + Entry Point: 0000000c + Verifying Checksum ... OK + + ## Checking Image at 40200000 ... + Image Name: Simple Ramdisk Image + Image Type: PowerPC Linux RAMDisk Image (gzip compressed) + Data Size: 566530 Bytes = 553 kB = 0 MB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + + => bootm 40100000 40200000 + ## Booting Linux kernel at 40100000 ... + Image Name: 2.2.13 for initrd on TQM850L + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 335725 Bytes = 327 kB = 0 MB + Load Address: 00000000 + Entry Point: 0000000c + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK + ## Loading RAMDisk Image at 40200000 ... + Image Name: Simple Ramdisk Image + Image Type: PowerPC Linux RAMDisk Image (gzip compressed) + Data Size: 566530 Bytes = 553 kB = 0 MB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + Loading Ramdisk ... OK + Linux version 2.2.13 (wd@denx.local.net) (gcc version 2.95.2 19991024 (release)) #1 Wed Jul 19 02:32:08 MEST 2000 + Boot arguments: root=/dev/ram + time_init: decrementer frequency = 187500000/60 + Calibrating delay loop... 49.77 BogoMIPS + ... + RAMDISK: Compressed image found at block 0 + VFS: Mounted root (ext2 filesystem). + + bash# + +More About U-Boot Image Types: +------------------------------ + +U-Boot supports the following image types: + + "Standalone Programs" are directly runnable in the environment + provided by U-Boot; it is expected that (if they behave + well) you can continue to work in U-Boot after return from + the Standalone Program. + "OS Kernel Images" are usually images of some Embedded OS which + will take over control completely. Usually these programs + will install their own set of exception handlers, device + drivers, set up the MMU, etc. - this means, that you cannot + expect to re-enter U-Boot except by resetting the CPU. + "RAMDisk Images" are more or less just data blocks, and their + parameters (address, size) are passed to an OS kernel that is + being started. + "Multi-File Images" contain several images, typically an OS + (Linux) kernel image and one or more data images like + RAMDisks. This construct is useful for instance when you want + to boot over the network using BOOTP etc., where the boot + server provides just a single image file, but you want to get + for instance an OS kernel and a RAMDisk image. + + "Multi-File Images" start with a list of image sizes, each + image size (in bytes) specified by an "uint32_t" in network + byte order. This list is terminated by an "(uint32_t)0". + Immediately after the terminating 0 follow the images, one by + one, all aligned on "uint32_t" boundaries (size rounded up to + a multiple of 4 bytes). + + "Firmware Images" are binary images containing firmware (like + U-Boot or FPGA images) which usually will be programmed to + flash memory. + + "Script files" are command sequences that will be executed by + U-Boot's command interpreter; this feature is especially + useful when you configure U-Boot to use a real shell (hush) + as command interpreter. + + +Standalone HOWTO: +================= + +One of the features of U-Boot is that you can dynamically load and +run "standalone" applications, which can use some resources of +U-Boot like console I/O functions or interrupt services. + +Two simple examples are included with the sources: + +"Hello World" Demo: +------------------- + +'examples/hello_world.c' contains a small "Hello World" Demo +application; it is automatically compiled when you build U-Boot. +It's configured to run at address 0x00040004, so you can play with it +like that: + + => loads + ## Ready for S-Record download ... + ~>examples/hello_world.srec + 1 2 3 4 5 6 7 8 9 10 11 ... + [file transfer complete] + [connected] + ## Start Addr = 0x00040004 + + => go 40004 Hello World! This is a test. + ## Starting application at 0x00040004 ... + Hello World + argc = 7 + argv[0] = "40004" + argv[1] = "Hello" + argv[2] = "World!" + argv[3] = "This" + argv[4] = "is" + argv[5] = "a" + argv[6] = "test." + argv[7] = "" + Hit any key to exit ... + + ## Application terminated, rc = 0x0 + +Another example, which demonstrates how to register a CPM interrupt +handler with the U-Boot code, can be found in 'examples/timer.c'. +Here, a CPM timer is set up to generate an interrupt every second. +The interrupt service routine is trivial, just printing a '.' +character, but this is just a demo program. The application can be +controlled by the following keys: + + ? - print current values og the CPM Timer registers + b - enable interrupts and start timer + e - stop timer and disable interrupts + q - quit application + + => loads + ## Ready for S-Record download ... + ~>examples/timer.srec + 1 2 3 4 5 6 7 8 9 10 11 ... + [file transfer complete] + [connected] + ## Start Addr = 0x00040004 + + => go 40004 + ## Starting application at 0x00040004 ... + TIMERS=0xfff00980 + Using timer 1 + tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0xfff009b0 + +Hit 'b': + [q, b, e, ?] Set interval 1000000 us + Enabling timer +Hit '?': + [q, b, e, ?] ........ + tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0 +Hit '?': + [q, b, e, ?] . + tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0 +Hit '?': + [q, b, e, ?] . + tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0 +Hit '?': + [q, b, e, ?] . + tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0 +Hit 'e': + [q, b, e, ?] ...Stopping timer +Hit 'q': + [q, b, e, ?] ## Application terminated, rc = 0x0 + + +Minicom warning: +================ + +Over time, many people have reported problems when trying to use the +"minicom" terminal emulation program for serial download. I (wd) +consider minicom to be broken, and recommend not to use it. Under +Unix, I recommend to use C-Kermit for general purpose use (and +especially for kermit binary protocol download ("loadb" command), and +use "cu" for S-Record download ("loads" command). + +Nevertheless, if you absolutely want to use it try adding this +configuration to your "File transfer protocols" section: + + Name Program Name U/D FullScr IO-Red. Multi + X kermit /usr/bin/kermit -i -l %l -s Y U Y N N + Y kermit /usr/bin/kermit -i -l %l -r N D Y N N + + +NetBSD Notes: +============= + +Starting at version 0.9.2, U-Boot supports NetBSD both as host +(build U-Boot) and target system (boots NetBSD/mpc8xx). + +Building requires a cross environment; it is known to work on +NetBSD/i386 with the cross-powerpc-netbsd-1.3 package (you will also +need gmake since the Makefiles are not compatible with BSD make). +Note that the cross-powerpc package does not install include files; +attempting to build U-Boot will fail because is +missing. This file has to be installed and patched manually: + + # cd /usr/pkg/cross/powerpc-netbsd/include + # mkdir powerpc + # ln -s powerpc machine + # cp /usr/src/sys/arch/powerpc/include/ansi.h powerpc/ansi.h + # ${EDIT} powerpc/ansi.h ## must remove __va_list, _BSD_VA_LIST + +Native builds *don't* work due to incompatibilities between native +and U-Boot include files. + +Booting assumes that (the first part of) the image booted is a +stage-2 loader which in turn loads and then invokes the kernel +proper. Loader sources will eventually appear in the NetBSD source +tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the +meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz + + +Implementation Internals: +========================= + +The following is not intended to be a complete description of every +implementation detail. However, it should help to understand the +inner workings of U-Boot and make it easier to port it to custom +hardware. + + +Initial Stack, Global Data: +--------------------------- + +The implementation of U-Boot is complicated by the fact that U-Boot +starts running out of ROM (flash memory), usually without access to +system RAM (because the memory controller is not initialized yet). +This means that we don't have writable Data or BSS segments, and BSS +is not initialized as zero. To be able to get a C environment working +at all, we have to allocate at least a minimal stack. Implementation +options for this are defined and restricted by the CPU used: Some CPU +models provide on-chip memory (like the IMMR area on MPC8xx and +MPC826x processors), on others (parts of) the data cache can be +locked as (mis-) used as memory, etc. + + Chris Hallinan posted a good summary of these issues to the + u-boot-users mailing list: + + Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)? + From: "Chris Hallinan" + Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET) + ... + + Correct me if I'm wrong, folks, but the way I understand it + is this: Using DCACHE as initial RAM for Stack, etc, does not + require any physical RAM backing up the cache. The cleverness + is that the cache is being used as a temporary supply of + necessary storage before the SDRAM controller is setup. It's + beyond the scope of this list to expain the details, but you + can see how this works by studying the cache architecture and + operation in the architecture and processor-specific manuals. + + OCM is On Chip Memory, which I believe the 405GP has 4K. It + is another option for the system designer to use as an + initial stack/ram area prior to SDRAM being available. Either + option should work for you. Using CS 4 should be fine if your + board designers haven't used it for something that would + cause you grief during the initial boot! It is frequently not + used. + + CFG_INIT_RAM_ADDR should be somewhere that won't interfere + with your processor/board/system design. The default value + you will find in any recent u-boot distribution in + walnut.h should work for you. I'd set it to a value larger + than your SDRAM module. If you have a 64MB SDRAM module, set + it above 400_0000. Just make sure your board has no resources + that are supposed to respond to that address! That code in + start.S has been around a while and should work as is when + you get the config right. + + -Chris Hallinan + DS4.COM, Inc. + +It is essential to remember this, since it has some impact on the C +code for the initialization procedures: + +* Initialized global data (data segment) is read-only. Do not attempt + to write it. + +* Do not use any unitialized global data (or implicitely initialized + as zero data - BSS segment) at all - this is undefined, initiali- + zation is performed later (when relocating to RAM). + +* Stack space is very limited. Avoid big data buffers or things like + that. + +Having only the stack as writable memory limits means we cannot use +normal global data to share information beween the code. But it +turned out that the implementation of U-Boot can be greatly +simplified by making a global data structure (gd_t) available to all +functions. We could pass a pointer to this data as argument to _all_ +functions, but this would bloat the code. Instead we use a feature of +the GCC compiler (Global Register Variables) to share the data: we +place a pointer (gd) to the global data into a register which we +reserve for this purpose. + +When choosing a register for such a purpose we are restricted by the +relevant (E)ABI specifications for the current architecture, and by +GCC's implementation. + +For PowerPC, the following registers have specific use: + R1: stack pointer + R2: TOC pointer + R3-R4: parameter passing and return values + R5-R10: parameter passing + R13: small data area pointer + R30: GOT pointer + R31: frame pointer + + (U-Boot also uses R14 as internal GOT pointer.) + + ==> U-Boot will use R29 to hold a pointer to the global data + + Note: on PPC, we could use a static initializer (since the + address of the global data structure is known at compile time), + but it turned out that reserving a register results in somewhat + smaller code - although the code savings are not that big (on + average for all boards 752 bytes for the whole U-Boot image, + 624 text + 127 data). + +On ARM, the following registers are used: + + R0: function argument word/integer result + R1-R3: function argument word + R9: GOT pointer + R10: stack limit (used only if stack checking if enabled) + R11: argument (frame) pointer + R12: temporary workspace + R13: stack pointer + R14: link register + R15: program counter + + ==> U-Boot will use R8 to hold a pointer to the global data + +NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope, +or current versions of GCC may "optimize" the code too much. + +Memory Management: +------------------ + +U-Boot runs in system state and uses physical addresses, i.e. the +MMU is not used either for address mapping nor for memory protection. + +The available memory is mapped to fixed addresses using the memory +controller. In this process, a contiguous block is formed for each +memory type (Flash, SDRAM, SRAM), even when it consists of several +physical memory banks. + +U-Boot is installed in the first 128 kB of the first Flash bank (on +TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After +booting and sizing and initializing DRAM, the code relocates itself +to the upper end of DRAM. Immediately below the U-Boot code some +memory is reserved for use by malloc() [see CFG_MALLOC_LEN +configuration setting]. Below that, a structure with global Board +Info data is placed, followed by the stack (growing downward). + +Additionally, some exception handler code is copied to the low 8 kB +of DRAM (0x00000000 ... 0x00001FFF). + +So a typical memory configuration with 16 MB of DRAM could look like +this: + + 0x0000 0000 Exception Vector code + : + 0x0000 1FFF + 0x0000 2000 Free for Application Use + : + : + + : + : + 0x00FB FF20 Monitor Stack (Growing downward) + 0x00FB FFAC Board Info Data and permanent copy of global data + 0x00FC 0000 Malloc Arena + : + 0x00FD FFFF + 0x00FE 0000 RAM Copy of Monitor Code + ... eventually: LCD or video framebuffer + ... eventually: pRAM (Protected RAM - unchanged by reset) + 0x00FF FFFF [End of RAM] + + +System Initialization: +---------------------- + +In the reset configuration, U-Boot starts at the reset entry point +(on most PowerPC systens at address 0x00000100). Because of the reset +configuration for CS0# this is a mirror of the onboard Flash memory. +To be able to re-map memory U-Boot then jumps to its link address. +To be able to implement the initialization code in C, a (small!) +initial stack is set up in the internal Dual Ported RAM (in case CPUs +which provide such a feature like MPC8xx or MPC8260), or in a locked +part of the data cache. After that, U-Boot initializes the CPU core, +the caches and the SIU. + +Next, all (potentially) available memory banks are mapped using a +preliminary mapping. For example, we put them on 512 MB boundaries +(multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash +on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is +programmed for SDRAM access. Using the temporary configuration, a +simple memory test is run that determines the size of the SDRAM +banks. + +When there is more than one SDRAM bank, and the banks are of +different size, the largest is mapped first. For equal size, the first +bank (CS2#) is mapped first. The first mapping is always for address +0x00000000, with any additional banks following immediately to create +contiguous memory starting from 0. + +Then, the monitor installs itself at the upper end of the SDRAM area +and allocates memory for use by malloc() and for the global Board +Info data; also, the exception vector code is copied to the low RAM +pages, and the final stack is set up. + +Only after this relocation will you have a "normal" C environment; +until that you are restricted in several ways, mostly because you are +running from ROM, and because the code will have to be relocated to a +new address in RAM. + + +U-Boot Porting Guide: +---------------------- + +[Based on messages by Jerry Van Baren in the U-Boot-Users mailing +list, October 2002] + + +int main (int argc, char *argv[]) +{ + sighandler_t no_more_time; + + signal (SIGALRM, no_more_time); + alarm (PROJECT_DEADLINE - toSec (3 * WEEK)); + + if (available_money > available_manpower) { + pay consultant to port U-Boot; + return 0; + } + + Download latest U-Boot source; + + Subscribe to u-boot-users mailing list; + + if (clueless) { + email ("Hi, I am new to U-Boot, how do I get started?"); + } + + while (learning) { + Read the README file in the top level directory; + Read http://www.denx.de/twiki/bin/view/DULG/Manual ; + Read the source, Luke; + } + + if (available_money > toLocalCurrency ($2500)) { + Buy a BDI2000; + } else { + Add a lot of aggravation and time; + } + + Create your own board support subdirectory; + + Create your own board config file; + + while (!running) { + do { + Add / modify source code; + } until (compiles); + Debug; + if (clueless) + email ("Hi, I am having problems..."); + } + Send patch file to Wolfgang; + + return 0; +} + +void no_more_time (int sig) +{ + hire_a_guru(); +} + + +Coding Standards: +----------------- + +All contributions to U-Boot should conform to the Linux kernel +coding style; see the file "Documentation/CodingStyle" in your Linux +kernel source directory. + +Please note that U-Boot is implemented in C (and to some small parts +in Assembler); no C++ is used, so please do not use C++ style +comments (//) in your code. + +Please also stick to the following formatting rules: +- remove any trailing white space +- use TAB characters for indentation, not spaces +- make sure NOT to use DOS '\r\n' line feeds +- do not add more than 2 empty lines to source files +- do not add trailing empty lines to source files + +Submissions which do not conform to the standards may be returned +with a request to reformat the changes. + + +Submitting Patches: +------------------- + +Since the number of patches for U-Boot is growing, we need to +establish some rules. Submissions which do not conform to these rules +may be rejected, even when they contain important and valuable stuff. + +Patches shall be sent to the u-boot-users mailing list. + +When you send a patch, please include the following information with +it: + +* For bug fixes: a description of the bug and how your patch fixes + this bug. Please try to include a way of demonstrating that the + patch actually fixes something. + +* For new features: a description of the feature and your + implementation. + +* A CHANGELOG entry as plaintext (separate from the patch) + +* For major contributions, your entry to the CREDITS file + +* When you add support for a new board, don't forget to add this + board to the MAKEALL script, too. + +* If your patch adds new configuration options, don't forget to + document these in the README file. + +* The patch itself. If you are accessing the CVS repository use "cvs + update; cvs diff -puRN"; else, use "diff -purN OLD NEW". If your + version of diff does not support these options, then get the latest + version of GNU diff. + + The current directory when running this command shall be the top + level directory of the U-Boot source tree, or it's parent directory + (i. e. please make sure that your patch includes sufficient + directory information for the affected files). + + We accept patches as plain text, MIME attachments or as uuencoded + gzipped text. + +* If one logical set of modifications affects or creates several + files, all these changes shall be submitted in a SINGLE patch file. + +* Changesets that contain different, unrelated modifications shall be + submitted as SEPARATE patches, one patch per changeset. + + +Notes: + +* Before sending the patch, run the MAKEALL script on your patched + source tree and make sure that no errors or warnings are reported + for any of the boards. + +* Keep your modifications to the necessary minimum: A patch + containing several unrelated changes or arbitrary reformats will be + returned with a request to re-formatting / split it. + +* If you modify existing code, make sure that your new code does not + add to the memory footprint of the code ;-) Small is beautiful! + When adding new features, these should compile conditionally only + (using #ifdef), and the resulting code with the new feature + disabled must not need more memory than the old code without your + modification. + +* Remember that there is a size limit of 40 kB per message on the + u-boot-users mailing list. Compression may help. diff --git a/u-boot/board/ar7240/ap121/Makefile b/u-boot/board/ar7240/ap121/Makefile new file mode 100755 index 0000000..768e929 --- /dev/null +++ b/u-boot/board/ar7240/ap121/Makefile @@ -0,0 +1,22 @@ +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/ar7240_flash.o ../common/ar7240_s26_phy.o +SOBJS = ../common/lowlevel_init.o + +ifeq ($(BOARD), ap121) +SOBJS += hornet_pll_init.o +endif + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/board/ar7240/ap121/ap121.c b/u-boot/board/ar7240/ap121/ap121.c new file mode 100755 index 0000000..10c654d --- /dev/null +++ b/u-boot/board/ar7240/ap121/ap121.c @@ -0,0 +1,310 @@ +#include +#include +#include +#include +#include +#include +#include "ar7240_soc.h" + +#ifndef COMPRESSED_UBOOT +extern void ar7240_ddr_initial_config(uint32_t refresh); +#endif +extern int ar7240_ddr_find_size(void); +extern void hornet_ddr_tap_init(void); + +#define SETBITVAL(val, pos, bit) do {ulong bitval = (bit) ? 0x1 : 0x0; (val) = ((val) & ~(0x1 << (pos))) | ( (bitval) << (pos));} while(0) + +void led_toggle(void){ + unsigned int gpio; + + gpio = ar7240_reg_rd(AR7240_GPIO_OUT); + +#if defined(CONFIG_FOR_TPLINK_MR3020_V1) + gpio ^= 1 << GPIO_WPS_LED_BIT; +#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined(CONFIG_FOR_TPLINK_WR710N_V1) + gpio ^= 1 << GPIO_SYS_LED_BIT; +#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2) + gpio ^= 1 << GPIO_INTERNET_LED_BIT; +#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) + gpio ^= 1 << GPIO_SYS_LED_BIT; +#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2) + gpio ^= 1 << GPIO_SYS_LED_BIT; +#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + gpio ^= 1 << GPIO_WLAN_LED_BIT; +#else + #error "Custom GPIO in leg_toggle() not defined!" +#endif + + ar7240_reg_wr(AR7240_GPIO_OUT, gpio); +} + +void all_led_on(void){ + unsigned int gpio; + + gpio = ar7240_reg_rd(AR7240_GPIO_OUT); + +#if defined(CONFIG_FOR_TPLINK_MR3020_V1) + SETBITVAL(gpio, GPIO_WPS_LED_BIT, GPIO_WPS_LED_ON); + SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON); + SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); + SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON); +#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined (CONFIG_FOR_TPLINK_WR710N_V1) + SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON); +#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2) + SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON); + SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); + SETBITVAL(gpio, GPIO_ETH_LED_BIT, GPIO_ETH_LED_ON); +#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) + SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON); +#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2) + SETBITVAL(gpio, GPIO_SYS_LED_BIT, GPIO_SYS_LED_ON); + SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); + SETBITVAL(gpio, GPIO_LAN1_LED_BIT, GPIO_LAN1_LED_ON); + SETBITVAL(gpio, GPIO_LAN2_LED_BIT, GPIO_LAN2_LED_ON); + SETBITVAL(gpio, GPIO_LAN3_LED_BIT, GPIO_LAN3_LED_ON); + SETBITVAL(gpio, GPIO_LAN4_LED_BIT, GPIO_LAN4_LED_ON); + SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, GPIO_INTERNET_LED_ON); + SETBITVAL(gpio, GPIO_QSS_LED_BIT, GPIO_QSS_LED_ON); + + #ifdef CONFIG_FOR_TPLINK_MR3220_V2 + SETBITVAL(gpio, GPIO_USB_LED_BIT, GPIO_USB_LED_ON); + #endif +#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + SETBITVAL(gpio, GPIO_WLAN_LED_BIT, GPIO_WLAN_LED_ON); +#else + #error "Custom GPIO in all_led_on() not defined!" +#endif + + ar7240_reg_wr(AR7240_GPIO_OUT, gpio); +} + +void all_led_off(void){ + unsigned int gpio; + + gpio = ar7240_reg_rd(AR7240_GPIO_OUT); + +#if defined(CONFIG_FOR_TPLINK_MR3020_V1) + SETBITVAL(gpio, GPIO_WPS_LED_BIT, !GPIO_WPS_LED_ON); + SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON); + SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON); + SETBITVAL(gpio, GPIO_ETH_LED_BIT, !GPIO_ETH_LED_ON); +#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined (CONFIG_FOR_TPLINK_WR710N_V1) + SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON); +#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2) + SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON); + SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON); + SETBITVAL(gpio, GPIO_ETH_LED_BIT, !GPIO_ETH_LED_ON); +#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) + SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON); +#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) || defined(CONFIG_FOR_TPLINK_MR3220_V2) + SETBITVAL(gpio, GPIO_SYS_LED_BIT, !GPIO_SYS_LED_ON); + SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON); + SETBITVAL(gpio, GPIO_LAN1_LED_BIT, !GPIO_LAN1_LED_ON); + SETBITVAL(gpio, GPIO_LAN2_LED_BIT, !GPIO_LAN2_LED_ON); + SETBITVAL(gpio, GPIO_LAN3_LED_BIT, !GPIO_LAN3_LED_ON); + SETBITVAL(gpio, GPIO_LAN4_LED_BIT, !GPIO_LAN4_LED_ON); + SETBITVAL(gpio, GPIO_INTERNET_LED_BIT, !GPIO_INTERNET_LED_ON); + SETBITVAL(gpio, GPIO_QSS_LED_BIT, !GPIO_QSS_LED_ON); + + #ifdef CONFIG_FOR_TPLINK_MR3220_V2 + SETBITVAL(gpio, GPIO_USB_LED_BIT, !GPIO_USB_LED_ON); + #endif +#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + SETBITVAL(gpio, GPIO_WLAN_LED_BIT, !GPIO_WLAN_LED_ON); +#else + #error "Custom GPIO in all_led_off() not defined!" +#endif + + ar7240_reg_wr(AR7240_GPIO_OUT, gpio); +} + +// get button status +#ifndef GPIO_RST_BUTTON_BIT + #error "GPIO_RST_BUTTON_BIT not defined!" +#endif +int reset_button_status(void){ + if(ar7240_reg_rd(AR7240_GPIO_IN) & (1 << GPIO_RST_BUTTON_BIT)){ +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + return(0); +#else + return(1); +#endif + } else { +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + return(1); +#else + return(0); +#endif + } +} + +void gpio_config(void){ +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + /* Disable clock obs + * clk_obs1(gpio13/bit8), clk_obs2(gpio14/bit9), clk_obs3(gpio15/bit10), + * clk_obs4(gpio16/bit11), clk_obs5(gpio17/bit12) + * clk_obs0(gpio1/bit19), 6(gpio11/bit20) + */ + ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & ~((0x1f<<8)|(0x3<<19)))); + + + /* Enable eth Switch LEDs */ + ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | (0x1f<<3))); + + + //Turn on status leds: + //set output enable + ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) |(1<<0))); + + //set WLAN LED output to low (reverse polarity LED) + //ar7240_reg_wr(AR7240_GPIO_CLEAR, (1<<0)); + + /* Clear AR7240_GPIO_FUNC BIT2 to ensure that software can control LED5(GPIO16) and LED6(GPIO17) */ + ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & ~(0x1<<2))); +#else + /* Disable clock obs + * clk_obs1(gpio13/bit8), clk_obs2(gpio14/bit9), clk_obs3(gpio15/bit10), + * clk_obs4(gpio16/bit11), clk_obs5(gpio17/bit12) + * clk_obs0(gpio1/bit19), 6(gpio11/bit20) + */ + + ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xEF84E0FB)); + + /* Disable EJTAG functionality to enable GPIO functionality */ + ar7240_reg_wr(AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) | 0x8001)); + + /* Set HORNET_BOOTSTRAP_STATUS BIT18 to ensure that software can control GPIO26 and GPIO27 */ + ar7240_reg_wr(HORNET_BOOTSTRAP_STATUS, (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) | (0x1<<18))); +#endif + +#if defined(CONFIG_FOR_TPLINK_MR3020_V1) + + /* LED's GPIOs on MR3020: + * + * 0 => WLAN + * 17 => ETH + * 26 => WPS + * 27 => INTERNET + * + */ + + /* set OE, added by zcf, 20110509 */ + ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xC020001)); + + /* Disable clock obs, added by zcf, 20110509 */ + //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f)); +#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) || defined(CONFIG_FOR_TPLINK_WR720N_V3) || defined(CONFIG_FOR_TPLINK_WR710N_V1) + + /* LED's GPIOs on WR703N/WR720Nv3/WR710N: + * + * 27 => SYS + * + */ + + /* set OE, added by zcf, 20110714 */ + ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0x8000000)); +#elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2) + + /* LED's GPIOs on MR3040: + * + * 26 => WLAN + * 17 => ETH + * 27 => INTERNET + * + */ + + /* set OE, added by zcf, 20110509 */ + ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xC020000)); + + /* Disable clock obs, added by zcf, 20110509 */ + //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f)); +#elif defined(CONFIG_FOR_TPLINK_MR10U_V1) + + /* LED's GPIOs on MR10U: + * + * 27 => SYS + * + */ + + /* set OE, added by zcf, 20110714 */ + ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0x8000000)); +#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) + + /* LED's GPIOs on WR740Nv4: + * + * 0 => WLAN + * 1 => QSS + * 13 => INTERNET + * 14 => LAN1 + * 15 => LAN2 + * 16 => LAN3 + * 17 => LAN4 + * 27 => SYS + * + */ + + /* set OE, added by zcf, 20110509 */ + ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0x803E003)); + + /* Disable clock obs, added by zcf, 20110509 */ + //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f)); +#elif defined(CONFIG_FOR_TPLINK_MR3220_V2) + + /* LED's GPIOs on MR3220v2: + * + * 0 => WLAN + * 1 => QSS + * 13 => INTERNET + * 14 => LAN1 + * 15 => LAN2 + * 16 => LAN3 + * 17 => LAN4 + * 26 => USB + * 27 => SYS + * + */ + + /* set OE, added by zcf, 20110509 */ + ar7240_reg_wr(AR7240_GPIO_OE, (ar7240_reg_rd(AR7240_GPIO_OE) | 0xC03E003)); + + /* Disable clock obs, added by zcf, 20110509 */ + //ar7240_reg_wr (AR7240_GPIO_FUNC, (ar7240_reg_rd(AR7240_GPIO_FUNC) & 0xffe7e07f)); +#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + // TODO: check GPIO config for C2 +#else + #error "Custom GPIO config in gpio_config() not defined!" +#endif +} + +int ar7240_mem_config(void){ +#ifndef COMPRESSED_UBOOT + ar7240_ddr_initial_config(CFG_DDR_REFRESH_VAL); +#endif + + /* Default tap values for starting the tap_init*/ + ar7240_reg_wr(AR7240_DDR_TAP_CONTROL0, CFG_DDR_TAP0_VAL); + ar7240_reg_wr(AR7240_DDR_TAP_CONTROL1, CFG_DDR_TAP1_VAL); + + gpio_config(); + all_led_off(); + +#ifndef COMPRESSED_UBOOT + ar7240_ddr_tap_init(); +#else + hornet_ddr_tap_init(); +#endif + + // return memory size + return(ar7240_ddr_find_size()); +} + +long int initdram(){ + return((long int)ar7240_mem_config()); +} + +#ifndef COMPRESSED_UBOOT +int checkboard(void){ + printf(BOARD_CUSTOM_STRING"\n\n"); + return(0); +} +#endif diff --git a/u-boot/board/ar7240/ap121/config.mk b/u-boot/board/ar7240/ap121/config.mk new file mode 100755 index 0000000..34198a1 --- /dev/null +++ b/u-boot/board/ar7240/ap121/config.mk @@ -0,0 +1,7 @@ +# ROM version +ifeq ($(COMPRESSED_UBOOT),1) +TEXT_BASE = 0x80010000 +BOOTSTRAP_TEXT_BASE = 0x9F000000 +else +TEXT_BASE = 0x9F000000 +endif \ No newline at end of file diff --git a/u-boot/board/ar7240/ap121/hornet_pll_init.S b/u-boot/board/ar7240/ap121/hornet_pll_init.S new file mode 100755 index 0000000..a718490 --- /dev/null +++ b/u-boot/board/ar7240/ap121/hornet_pll_init.S @@ -0,0 +1,373 @@ +#include +#include +#include +#include +#include +#include + + .globl hornet_pll_init + .text + .align 4 + +/* + * Helper macros. + * These Clobber t7, t8 and t9 + */ +/* or t8, t8, t9; \ */ +#define set_reg(_reg, _val) \ + li t7, KSEG1ADDR(_reg); \ + lw t8, 0(t7); \ + li t9, _val; \ + sw t9, 0(t7); + +hornet_pll_init: + +#if 1 +/* These three wlan reset will avoid original issue, +so full chip reset isn't needed here. */ + set_reg(0xb806001c, 0x00c06b30) + nop + set_reg(0xb806001c, 0x00c06330) + nop + set_reg(0xb806001c, 0x00c06b30) + nop + set_reg(0xb806001c, 0x00c06330) + nop +reset_wlan: + set_reg(0xb806001c, 0x00c06b30) + nop + set_reg(0xb806001c, 0x00c06330) + nop + + li t5, 0x20 +check_val: + beq zero, t5, reset_wlan + addi t5, t5, -1 + li t6, 0xb80600ac + lw t7, 0(t6) + li t8, 0x10 + and t7, t7, t8 + bne zero, t7, check_val + + set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110e) + nop +#else +/* clear wlan reset bit in RESET_Register 0x1c */ + set_reg(AR7240_RESET, 0x00c06b30) + nop + set_reg(AR7240_RESET, 0x00c06330) + nop + +/* cleck bootstrap status, wait for bit4 on, then clear bit16 */ +wait_loop0: + li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS) + lw t7, 0(t6) + li t8, 0x10 + and t7, t7, t8 + bne zero, t7, wait_loop0 + nop + set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110e) + nop +#endif + +/* RTC reset */ + set_reg(0x1810704c, 0x00000003) + nop + nop + set_reg(0x18107040, 0x00000000) + nop + nop + set_reg(0x18107040, 0x00000001) + nop +wait_loop1: + li t6, KSEG1ADDR(0x18107044) + lw t7, 0(t6) + li t8, 0x2 + and t7, t7, t8 + bne t8, t7, wait_loop1 + nop + + /* AHB/APH reset */ + set_reg(0x18104000, 0x00000003) + nop + set_reg(0x18104000, 0x00000000) + nop + + /* MAC reset */ + set_reg(0x18107000, 0x0000000F) + nop + set_reg(0x18107000, 0x00000000) + nop + +#if 1 /* fetch pmu1.refv and ctrl2.tx from OTP */ + li t1, KSEG1ADDR(0x18114014) + lw t2, 0(t1) +otp_loop0: + li t3, KSEG1ADDR(0x18115f18) + lw t4, 0(t3) + nop + li t5, 0x7 + and t4, t4, t5 + li t5, 0x4 + bne t4, t5, otp_loop0 + nop + + li t6, KSEG1ADDR(0x18115f1c) + lw t7, 0(t6) + nop + li t8, 0x80000080 + and t9, t7, t8 + beq t8, t9, fetch_otp +otp_loop0_end: + + li t1, KSEG1ADDR(0x18114004) + lw t2, 0(t1) +otp_loop1: + li t3, KSEG1ADDR(0x18115f18) + lw t4, 0(t3) + nop + li t5, 0x7 + and t4, t4, t5 + li t5, 0x4 + bne t4, t5, otp_loop1 + nop + + li t6, KSEG1ADDR(0x18115f1c) + lw t7, 0(t6) + nop + li t8, 0x80000080 + and t9, t7, t8 +default_pmu: + li t5, 0x80 /* default 0x031c4386 */ + bne t8, t9, otp_end +otp_loop1_end: + +fetch_otp: + srl t8, t7, 0x18 + li t1, 0xf + and t2, t1 , t7 /* USB */ + and t5, t1 , t8 /* PMU */ + +check_pmu: + li t0, 0x4 /* PMU range should be 0x4~0xa */ + bgt t0, t5, default_pmu + nop + li t0, 0xa /* PMU range should be 0x4~0xa */ + blt t0, t5, default_pmu + nop + li t0, 0x4 + sll t5, t5, t0 + +otp_end: +#endif + +#if 1 /* Program PMU */ +#define PMU_TEST_NO 1000 + li t6, KSEG1ADDR(0x18116c40) + li t9, 0xbd000010 + li t0, 0 + li t1, 0 + li t2, 0 + + li t3, PMU_TEST_NO + sw t3, 12(t9) +pmu_loop0: + beq zero, t3, pmu_loop0_end + nop + addi t3, t3, -1 + + li t7, 0x10180000 /* ldo_tune 0x3 */ + nop + sw t7, 4(t6) + nop + lw t8, 4(t6) + nop + beq t8, t7, pmu_loop0_end + nop + + addiu t0, t0, 1 + b pmu_loop0 + nop +pmu_loop0_end: + + li t3, PMU_TEST_NO +pmu_loop1: + beq zero, t3, pmu_loop1_end + nop + addi t3, t3, -1 + + //li t7, 0x031c4326 /* 1.100V */ + //li t7, 0x031c4336 /* 1.125V */ + //li t7, 0x031c4346 /* 1.150V */ + //li t7, 0x031c4356 /* 1.175V */ + //li t7, 0x031c4366 /* 1.200V */ + //li t7, 0x031c4376 /* 1.225V */ + li t7, 0x031c4386 /* 1.250V (DEFAULT) */ + //li t7, 0x031c4396 /* 1.275V */ + //li t7, 0x031c43a6 /* 1.300V */ + nop +#if 1 /* from OTP */ + li t8, 0xffffff0f + and t7, t7, t8 + or t7, t7, t5 +#endif + sw t7, 0(t6) + nop + lw t8, 0(t6) + nop + beq t8, t7, pmu_loop1_end + nop + + addiu t1, t1, 1 + b pmu_loop1 + nop +pmu_loop1_end: + + li t3, PMU_TEST_NO +pmu_loop2: + beq zero, t3, pmu_loop2_end + nop + addi t3, t3, -1 + + li t7, 0x10380000 /* ldo_tune 0x3 */ + nop + sw t7, 4(t6) + nop + lw t8, 4(t6) + nop + beq t8, t7, pmu_loop2_end + nop + + addiu t2, t2, 1 + b pmu_loop2 + nop +pmu_loop2_end: + + sw t0, 0(t9) + nop + sw t1, 4(t9) + nop + sw t2, 8(t9) + nop +#endif + +#if 1 /* Program ki, kd */ + /* Program ki/kd */ +#if CONFIG_40MHZ_XTAL_SUPPORT + set_reg(0x18116244, 0x19e82f01) +#else + set_reg(0x18116244, 0x18e82f01) +#endif + nop + + /* Program phase shift */ + li t6, KSEG1ADDR(0x18116248) + lw t7, 0(t6) + li t8, 0xc07fffff + and t7, t7, t8 + li t8, 0x800000 + or t7, t7, t8 + sw t7, 0(t6) + nop +#endif + +/* max AHB Master wait time out ... */ +// set_reg(0xb800009c, 0xfffff) +// nop + +/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */ + set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL1) + nop + +/* set SETTLE_TIME in CPU PLL */ + set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL) + nop + +pll_unlock_handler: + +/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */ + set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL1) + nop + +wait_loop2: + li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) + lw t7, 0(t6) + li t8, 0x80000000 + and t7, t7, t8 + bne zero, t7, wait_loop2 + nop + +/* put frac bit19:10 configuration */ + set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL) + nop + +/* clear PLL power down bit in CPU PLLl configuration */ + set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL2) + nop +wait_loop3: + li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) + lw t7, 0(t6) + li t8, 0x80000000 + and t7, t7, t8 + bne zero, t7, wait_loop3 + nop + +/* confirm DDR PLL lock */ + li t3, 100 + li t4, 0 +start_meas0: + addi t4, t4, 1 + bgt t4, t3, pll_unlock_handler + nop + li t5, 5 +start_meas: + li t6, KSEG1ADDR(0x18116248) + lw t7, 0(t6) + li t8, 0xbfffffff + and t7, t7, t8 + sw t7, 0(t6) + nop + +/* delay */ + li t9, 10 +delayloop0: + subu t9, t9, 1 + bne t9, zero, delayloop0 + nop + + li t8, 0x40000000 + or t7, t7, t8 + sw t7, 0(t6) + nop + +meas_done_statue: + li t6, KSEG1ADDR(0x1811624c) + lw t7, 0(t6) + li t8, 0x8 + and t7, t7, t8 + beq zero, t7, meas_done_statue + nop + +meas_result: + li t6, KSEG1ADDR(0x18116248) + lw t7, 0(t6) + li t8, 0x007ffff8 + and t7, t7, t8 + srl t7, t7, 3 + li t8, 0x4000 + bgt t7, t8, start_meas0 + nop + addi t5, t5, -1 + bne zero, t5, start_meas + nop + +/* clear PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */ + set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL2) + nop + +/* Sync mode , Set Bit 8 of DDR Tap Conrtol 3 register */ + set_reg(AR7240_DDR_TAP_CONTROL3, 0x10105); + nop + + jr ra + nop diff --git a/u-boot/board/ar7240/ap121/u-boot-bootstrap.lds b/u-boot/board/ar7240/ap121/u-boot-bootstrap.lds new file mode 100755 index 0000000..0b3bfb9 --- /dev/null +++ b/u-boot/board/ar7240/ap121/u-boot-bootstrap.lds @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start_bootstrap) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = .; + _gp = ALIGN(16); + + .got : { + __got_start_bootstrap = .; + *(.got) + __got_end_bootstrap = .; + } + + . = ALIGN(4); + .sdata : { *(.sdata*) } + + uboot_end_data_bootstrap = .; + num_got_entries = (__got_end_bootstrap - __got_start_bootstrap) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss*) } + .bss : { *(.bss*) . = ALIGN(4); } + uboot_end_bootstrap = .; +} diff --git a/u-boot/board/ar7240/ap121/u-boot.lds b/u-boot/board/ar7240/ap121/u-boot.lds new file mode 100755 index 0000000..f6f24b7 --- /dev/null +++ b/u-boot/board/ar7240/ap121/u-boot.lds @@ -0,0 +1,43 @@ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = .; + _gp = ALIGN(16); + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + . = ALIGN(4); + .sdata : { *(.sdata*) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss*) } + .bss : { *(.bss*) . = ALIGN(4); } + uboot_end = .; +} diff --git a/u-boot/board/ar7240/common/ar7240_flash.c b/u-boot/board/ar7240/common/ar7240_flash.c new file mode 100755 index 0000000..03f878f --- /dev/null +++ b/u-boot/board/ar7240/common/ar7240_flash.c @@ -0,0 +1,299 @@ +#include +#include +#include +#include +#include "ar7240_soc.h" +#include "ar7240_flash.h" + +#define SIZE_INBYTES_4MBYTES (4 * 1024 * 1024) +#define SIZE_INBYTES_8MBYTES (2 * SIZE_INBYTES_4MBYTES) +#define SIZE_INBYTES_16MBYTES (2 * SIZE_INBYTES_8MBYTES) + +#define SIZE_INBYTES_4KBYTES (4 * 1024) +#define SIZE_INBYTES_64KBYTES (16 * SIZE_INBYTES_4KBYTES) + +#ifndef DEFAULT_FLASH_SIZE_IN_MB +#error "DEFAULT_FLASH_SIZE_IN_MB not defined!" +#endif + +extern void led_toggle(void); +extern void all_led_off(void); + +/* + * globals + */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/* + * statics + */ +static void ar7240_spi_write_enable(void); +static void ar7240_spi_poll(void); +static void ar7240_spi_write_page(uint32_t addr, uint8_t * data, int len); +static void ar7240_spi_sector_erase(uint32_t addr); + +/* + * Returns JEDEC ID from SPI flash + */ +static ulong read_id(void){ + unsigned int flashid = 0; + + ar7240_reg_wr_nf(AR7240_SPI_FS, 1); + ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS); + + ar7240_spi_bit_banger(0x9F); + + ar7240_spi_delay_8(); + ar7240_spi_delay_8(); + ar7240_spi_delay_8(); + ar7240_spi_delay_8(); + + flashid = ar7240_reg_rd(AR7240_SPI_RD_STATUS); + + /* + * We have 3 bytes: + * - manufacture ID (1b) + * - product ID (2b) + */ + flashid = flashid >> 8; + + ar7240_spi_done(); + + return((ulong)flashid); +} + +static void flash_set_geom(int size, int sector_count, int sector_size){ + int i; + flash_info_t *info = &flash_info[0]; + + info->size = size; + info->sector_count = sector_count; + info->sector_size = sector_size; + + for(i = 0; i < info->sector_count; i++){ + info->start[i] = CFG_FLASH_BASE + (i * info->sector_size); + info->protect[i] = 0; + } +} + +unsigned long flash_init(void){ + flash_info_t *info; + + info = &flash_info[0]; + + // spi flash clock + ar7240_reg_wr(AR7240_SPI_FS, 0x01); + ar7240_reg_wr(AR7240_SPI_CLOCK, AR7240_SPI_CONTROL); + ar7240_reg_wr(AR7240_SPI_FS, 0x0); + + // get flash id + info->flash_id = read_id(); + + puts("FLASH: "); + + // fill flash info based on JEDEC ID + switch(info->flash_id){ + /* + * 4M flash chips + */ + case 0x010215: // tested + flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES); + puts("Spansion S25FL032P (4 MB)"); + break; + + case 0x1F4700: + flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES); + puts("Atmel AT25DF321 (4 MB)"); + break; + + case 0x1C3016: // tested + flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES); + puts("EON EN25Q32 (4 MB)"); + break; + + case 0x202016: + flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES); + puts("Micron M25P32 (4 MB)"); + break; + + case 0xEF4016: + flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES); + puts("Winbond W25Q32 (4 MB)"); + break; + + case 0xC22016: + flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES); + puts("Macronix MX25L320 (4 MB)"); + break; + + /* + * 8M flash chips + */ + case 0x010216: + flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES); + puts("Spansion S25FL064P (8 MB)"); + break; + + case 0x1F4800: + flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES); + puts("Atmel AT25DF641 (8 MB)"); + break; + + case 0x1C3017: // tested + flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES); + puts("EON EN25Q64 (8 MB)"); + break; + + case 0x202017: + flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES); + puts("Micron M25P64 (8 MB)"); + break; + + case 0xEF4017: // tested + flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES); + puts("Winbond W25Q64 (8 MB)"); + break; + + case 0xC22017: // tested + case 0xC22617: + flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES); + puts("Macronix MX25L64 (8 MB)"); + break; + + case 0xBF254B: + flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES); + puts("SST 25VF064C (8 MB)"); + break; + + /* + * 16M flash chips + */ + case 0xEF4018: // tested + flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES); + puts("Winbond W25Q128 (16 MB)"); + break; + + case 0xC22018: + case 0xC22618: + flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES); + puts("Macronix MX25L128 (16 MB)"); + break; + + /* + * Unknown flash + */ + default: +#if (DEFAULT_FLASH_SIZE_IN_MB == 4) + flash_set_geom(SIZE_INBYTES_4MBYTES, 64, SIZE_INBYTES_64KBYTES); + puts("Unknown type (using only 4 MB)\n"); +#elif (DEFAULT_FLASH_SIZE_IN_MB == 8) + flash_set_geom(SIZE_INBYTES_8MBYTES, 128, SIZE_INBYTES_64KBYTES); + puts("Unknown type (using only 8 MB)\n"); +#elif (DEFAULT_FLASH_SIZE_IN_MB == 16) + flash_set_geom(SIZE_INBYTES_16MBYTES, 256, SIZE_INBYTES_64KBYTES); + puts("Unknown type (using only 16 MB)\n"); +#endif + printf("\nPlease, send request to add support\nfor your flash - JEDEC ID: 0x%06lX", info->flash_id); + info->flash_id = FLASH_CUSTOM; + break; + } + + return(info->size); +} + +int flash_erase(flash_info_t *info, int s_first, int s_last){ + int i, j, sector_size = info->size / info->sector_count; + + printf("Erasing: "); + + j = 0; + + for(i = s_first; i <= s_last; i++){ + ar7240_spi_sector_erase(i * sector_size); + + if(j == 39){ + puts("\n "); + j = 0; + } + puts("#"); + led_toggle(); + j++; + } + + ar7240_spi_done(); + all_led_off(); + printf("\n\n"); + + return(0); +} + +/* + * Write a buffer from memory to flash: + * 0. Assumption: Caller has already erased the appropriate sectors. + * 1. call page programming for every 256 bytes + */ +int write_buff(flash_info_t *info, uchar *source, ulong addr, ulong len){ + int total = 0, len_this_lp, bytes_this_page; + ulong dst; + uchar *src; + + printf("Writting at address: 0x%08lX\n", addr); + addr = addr - CFG_FLASH_BASE; + + while(total < len){ + src = source + total; + dst = addr + total; + bytes_this_page = AR7240_SPI_PAGE_SIZE - (addr % AR7240_SPI_PAGE_SIZE); + len_this_lp = ((len - total) > bytes_this_page) ? bytes_this_page : (len - total); + ar7240_spi_write_page(dst, src, len_this_lp); + total += len_this_lp; + } + + ar7240_spi_done(); + printf("\n"); + + return(0); +} + +static void ar7240_spi_write_enable(){ + ar7240_reg_wr_nf(AR7240_SPI_FS, 1); + ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS); + ar7240_spi_bit_banger(AR7240_SPI_CMD_WREN); + ar7240_spi_go(); +} + +static void ar7240_spi_poll(){ + int rd; + + do { + ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS); + ar7240_spi_bit_banger(AR7240_SPI_CMD_RD_STATUS); + ar7240_spi_delay_8(); + rd = (ar7240_reg_rd(AR7240_SPI_RD_STATUS) & 1); + } while(rd); +} + +static void ar7240_spi_write_page(uint32_t addr, uint8_t *data, int len){ + int i; + uint8_t ch; + + ar7240_spi_write_enable(); + ar7240_spi_bit_banger(AR7240_SPI_CMD_PAGE_PROG); + ar7240_spi_send_addr(addr); + + for(i = 0; i < len; i++){ + ch = *(data + i); + ar7240_spi_bit_banger(ch); + } + + ar7240_spi_go(); + ar7240_spi_poll(); +} + +static void ar7240_spi_sector_erase(uint32_t addr){ + ar7240_spi_write_enable(); + ar7240_spi_bit_banger(AR7240_SPI_CMD_SECTOR_ERASE); + ar7240_spi_send_addr(addr); + ar7240_spi_go(); + ar7240_spi_poll(); +} diff --git a/u-boot/board/ar7240/common/ar7240_flash.h b/u-boot/board/ar7240/common/ar7240_flash.h new file mode 100755 index 0000000..f5d857d --- /dev/null +++ b/u-boot/board/ar7240/common/ar7240_flash.h @@ -0,0 +1,55 @@ +#ifndef _FLASH_H +#define _FLASH_H + +#include "ar7240_soc.h" + +#define AR7240_SPI_FS 0x1F000000 +#define AR7240_SPI_CLOCK 0x1F000004 +#define AR7240_SPI_WRITE 0x1F000008 +#define AR7240_SPI_READ 0x1F000000 +#define AR7240_SPI_RD_STATUS 0x1F00000c + +#define AR7240_SPI_CS_DIS 0x70000 +#define AR7240_SPI_CE_LOW 0x60000 +#define AR7240_SPI_CE_HIGH 0x60100 + +#define AR7240_SPI_CMD_WRITE_SR 0x01 +#define AR7240_SPI_CMD_WREN 0x06 +#define AR7240_SPI_CMD_RD_STATUS 0x05 +#define AR7240_SPI_CMD_FAST_READ 0x0B +#define AR7240_SPI_CMD_PAGE_PROG 0x02 +#define AR7240_SPI_CMD_SECTOR_ERASE 0xD8 +#define AR7240_SPI_CMD_CHIP_ERASE 0xC7 + +#define AR7240_SPI_PAGE_SIZE 256 + +#define display(_x) ar7240_reg_wr_nf(0x18040008, (_x)) + +/* + * primitives + */ +#define ar7240_be_msb(_val, _i) (((_val) & (1 << (7 - _i))) >> (7 - _i)) + +#define ar7240_spi_bit_banger(_byte) do{ \ + int i; \ + for(i = 0; i < 8; i++){ \ + ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CE_LOW | ar7240_be_msb(_byte, i)); \ + ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CE_HIGH | ar7240_be_msb(_byte, i)); \ + } \ +} while(0); + +#define ar7240_spi_go() do { \ + ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CE_LOW); \ + ar7240_reg_wr_nf(AR7240_SPI_WRITE, AR7240_SPI_CS_DIS); \ +} while(0); + +#define ar7240_spi_send_addr(__a) do { \ + ar7240_spi_bit_banger(((__a & 0xff0000) >> 16)); \ + ar7240_spi_bit_banger(((__a & 0x00ff00) >> 8)); \ + ar7240_spi_bit_banger(__a & 0x0000ff); \ +} while (0) + +#define ar7240_spi_delay_8() ar7240_spi_bit_banger(0) +#define ar7240_spi_done() ar7240_reg_wr_nf(AR7240_SPI_FS, 0) + +#endif /*_FLASH_H*/ diff --git a/u-boot/board/ar7240/common/ar7240_pci.c b/u-boot/board/ar7240/common/ar7240_pci.c new file mode 100755 index 0000000..945a742 --- /dev/null +++ b/u-boot/board/ar7240/common/ar7240_pci.c @@ -0,0 +1,246 @@ +/*****************************************************************************/ +/*! file ap93_pci.c +** /brief PCI support for AP91/93 board +** +** This provides the support code required for PCI support on the AP91/93 +** board in the U-Boot environment. This board is a Python based system +** with a Merlin WLAN interface. This file also contains the support +** for initialization of the Merlin radios on the PCi bus, required for +** pre-configuration for use by Linux. +** +** Copyright (c) 2008 Atheros Communications Inc. All rights reserved. +** +*/ + +#include +#include +#include +#include +#include +#include +#include +#include "ar7240_soc.h" + +/* +** PCI controller "hose" value +*/ +static int ar7240_local_write_config(int where, int size, uint32_t value){ + ar7240_reg_wr((AR7240_PCI_CRP + where),value); + return(0); +} + +/* +** We will use the ART configuration information stored in flash to initialize +** these devices as required. +*/ + +// TODO: calibration data doesn't exist? +/* +void plat_dev_init(void){ + u32 val; + u32 addr; + u32 BaseAddr = 0x10000000; + u32 CalAddr = WLANCAL; + volatile u16 *calData; + calData = (u16 *)CalAddr; + + if(calData[0] != 0xa55a && calData[0] != 0x5aa5){ + printf("BOARD IS NOT CALIBRATED!!!\n"); + return; + } +} +*/ + +/******************************************************************************/ +/*! +** \brief pci host initialization +** +** Sets up the PCI controller on the host. For AR7240 this may not be necessary, +** but this function is required for board support. +** +** We want a 1:1 mapping between PCI and DDR for inbound and outbound. +** The PCI<---AHB decoding works as follows: +** +** 8 registers in the DDR unit provide software configurable 32 bit offsets +** for each of the eight 16MB PCI windows in the 128MB. The offsets will be +** added to any address in the 16MB segment before being sent to the PCI unit. +** +** Essentially for any AHB address generated by the CPU, +** 1. the MSB four bits are stripped off, [31:28], +** 2. Bit 27 is used to decide between the lower 128Mb (PCI) or the rest of +** the AHB space +** 3. Bits 26:24 are used to access one of the 8 window registers and are +** masked off. +** 4. If it is a PCI address, then the WINDOW offset in the WINDOW register +** corresponding to the next 3 bits (bit 26:24) is ADDED to the address, +** to generate the address to PCI unit. +** +** eg. CPU address = 0x100000ff +** window 0 offset = 0x10000000 +** This points to lowermost 16MB window in PCI space. +** So the resulting address would be 0x000000ff+0x10000000 +** = 0x100000ff +** +** eg2. CPU address = 0x120000ff +** WINDOW 2 offset = 0x12000000 +** resulting address would be 0x000000ff+0x12000000 +** = 0x120000ff +** +** There is no translation for inbound access (PCI device as a master) +** +** \return N/A +*/ + +/* +static int ar7240_pcibios_init(void){ + if(is_ar9341()){ + return(0); + } + + if(((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0){ + printf("***** Warning *****: PCIe WLAN H/W not found !!!\n"); + return(0); + } + + return(1); +} +*/ + +#define pci_udelay(n) do { uint32_t i; for(i = 0; i < ((n)/10); i++) udelay(10); } while(0) + +int pci_init_board(void){ + uint32_t cmd = 0, reg_val; + + reg_val = ar7240_reg_rd(0xb804006c); + ar7240_reg_wr(0xb804006c, reg_val | 2); + + ar7240_reg_wr(0xb804000c, 1 << 2); + + pci_udelay(100000); + + /* + if((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0){ + ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX, + PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) | + PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) | + PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) | + PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0) + ); + } else { + printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__); + } + */ + + ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE); // core in reset + pci_udelay(10000); + + ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset + pci_udelay(10000); + + ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset + pci_udelay(10000); + + ar7240_reg_wr(0x180f0000, 0x1ffc0); // ltssm is disabled + pci_udelay(100); + + ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0); // End point in reset + pci_udelay(100000); + + //ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); + + /* + if((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0){ + ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, + PCIE_PLL_CONFIG_REFDIV_SET(1) | + PCIE_PLL_CONFIG_BYPASS_SET(1) | + PCIE_PLL_CONFIG_PLLPWD_SET(1) + ); + pci_udelay(10000); + + ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, + PCIE_PLL_CONFIG_REFDIV_SET(1) | + PCIE_PLL_CONFIG_BYPASS_SET(1) | + PCIE_PLL_CONFIG_PLLPWD_SET(0) + ); + pci_udelay(1000); + + ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, + ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) & + (~PCIE_PLL_CONFIG_BYPASS_SET(1)) + ); + pci_udelay(1000); + } else { + */ + ar7240_reg_wr_nf(0xb8116c04, (0x0 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7)); + pci_udelay(10000); + + ar7240_reg_wr_nf(0xb8116c08, (6 << 23)); + pci_udelay(10000); + + ar7240_reg_wr_nf(0xb8050010, 0x40010800); + pci_udelay(10000); + + ar7240_reg_wr_nf(0xb8050014, 0xc013fffe); + pci_udelay(10000); + + ar7240_reg_wr_nf(0xb8050018, 0x00138000); + pci_udelay(10000); + + ar7240_reg_wr_nf(0xb8050010, 0x00010800); + pci_udelay(100000); + + ar7240_reg_wr_nf(0xb8050010, 0x00000800); + pci_udelay(10000); + /* + } + */ + + ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset + pci_udelay(10000); + + ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); // phy out of reset + pci_udelay(10000); + + ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE); // core out of reset + pci_udelay(1000); + + cmd = PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | + PCI_COMMAND_INVALIDATE | + PCI_COMMAND_PARITY | + PCI_COMMAND_SERR | + PCI_COMMAND_FAST_BACK; + + ar7240_local_write_config(PCI_COMMAND, 4, cmd); // pci cmd reg init + ar7240_local_write_config(0x20, 4, 0x1ff01000); // membase setting + ar7240_local_write_config(0x24, 4, 0x1ff01000); // prefetch membase setting + + //if((is_ar7241() || is_ar7242() || is_wasp())){ + ar7240_reg_wr(0x180f0000, 0x1ffc1); // ltssm enable + //} else { + // ar7240_reg_wr(0x180f0000, 0x1); + //} + pci_udelay(100000); + + ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4); // EP out of reset + //pci_udelay(100000); + + /* + * Delay increased from 100 to 1000, so as to + * get the correct status from PCI LCL RESET register + */ + // pci_udelay(100000); + + /* + * Check if the WLAN PCI-E H/W is present, If the + * WLAN H/W is not present, skip the PCI platform + * initialization code and return + */ + //if(((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0){ + // printf("## Error: PCIe WLAN Module not found!\n"); + //} + + //plat_dev_init(); + + return(0); +} diff --git a/u-boot/board/ar7240/common/ar7240_s26_phy.c b/u-boot/board/ar7240/common/ar7240_s26_phy.c new file mode 100755 index 0000000..f9c662c --- /dev/null +++ b/u-boot/board/ar7240/common/ar7240_s26_phy.c @@ -0,0 +1,837 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright © 2007 Atheros Communications, Inc., All Rights Reserved. + */ + +/* + * Manage the atheros ethernet PHY. + * + * All definitions in this file are operating system independent! + */ + +#include +#include +#include +#include +#include "phy.h" +#include +#include "ar7240_soc.h" +#include "ar7240_s26_phy.h" + +/* PHY selections and access functions */ +#define DRV_PRINT(DBG_SW,X) + +#define ATHR_LAN_PORT_VLAN 1 +#define ATHR_WAN_PORT_VLAN 2 +#define ENET_UNIT_LAN 1 +#define ENET_UNIT_WAN 0 + +#define ATHR_PHY0_ADDR 0x0 +#define ATHR_PHY1_ADDR 0x1 +#define ATHR_PHY2_ADDR 0x2 +#define ATHR_PHY3_ADDR 0x3 +#define ATHR_PHY4_ADDR 0x4 + +#define TRUE 1 +#define FALSE 0 + +/* + * Track per-PHY port information. + */ +typedef struct { + int isEnetPort; /* normal enet port */ + int isPhyAlive; /* last known state of link */ + int ethUnit; /* MAC associated with this phy port */ + uint32_t phyBase; + uint32_t phyAddr; /* PHY registers associated with this phy port */ + uint32_t VLANTableSetting; /* Value to be written to VLAN table */ +} athrPhyInfo_t; + +/* + * Per-PHY information, indexed by PHY unit number. + */ +static athrPhyInfo_t athrPhyInfo[] = { + /* port 1 -- LAN port 1 */ + { TRUE, FALSE, ENET_UNIT_LAN, 0, ATHR_PHY0_ADDR, ATHR_LAN_PORT_VLAN }, + + /* port 2 -- LAN port 2 */ + { TRUE, FALSE, ENET_UNIT_LAN, 0, ATHR_PHY1_ADDR, ATHR_LAN_PORT_VLAN }, + + /* port 3 -- LAN port 3 */ + { TRUE, FALSE, ENET_UNIT_LAN, 0, ATHR_PHY2_ADDR, ATHR_LAN_PORT_VLAN }, + + /* port 4 -- LAN port 4 */ + { TRUE, FALSE, ENET_UNIT_LAN, 0, ATHR_PHY3_ADDR, ATHR_LAN_PORT_VLAN }, + + /* port 5 -- WAN Port 5 */ + { TRUE, FALSE, ENET_UNIT_WAN, 0, ATHR_PHY4_ADDR, ATHR_LAN_PORT_VLAN }, + + /* port 0 -- cpu port 0 */ + { FALSE, TRUE, ENET_UNIT_LAN, 0, 0x00, ATHR_LAN_PORT_VLAN }, +}; + +static uint8_t athr26_init_flag = 0; +static uint8_t athr26_init_flag1 = 0; + +/* Range of valid PHY IDs is [MIN..MAX] */ +#define ATHR_PHY_MAX 5 +#define ATHR_ID_MIN 0 +#define ATHR_ID_MAX (ATHR_PHY_MAX-1) + +/* Convenience macros to access myPhyInfo */ +#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort) +#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive) +#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit) +#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase) +#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr) +#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting) +#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) (ATHR_IS_ENET_PORT(phyUnit) && ATHR_ETHUNIT(phyUnit) == (ethUnit)) +#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit) == ENET_UNIT_LAN)) + +/* Forward references */ +int athrs26_phy_is_link_alive(int phyUnit); +uint32_t athrs26_reg_read(uint32_t reg_addr); +unsigned int s26_rd_phy(unsigned int phy_addr, unsigned int reg_addr); +void athrs26_reg_write(uint32_t reg_addr, uint32_t reg_val); +void s26_wr_phy(unsigned int phy_addr, unsigned int reg_addr, unsigned int write_data); + +void athrs26_powersave_off(int phy_addr){ + s26_wr_phy(phy_addr, ATHR_DEBUG_PORT_ADDRESS, 0x29); + s26_wr_phy(phy_addr, ATHR_DEBUG_PORT_DATA, 0x36c0); +} + +void athrs26_sleep_off(int phy_addr){ + s26_wr_phy(phy_addr, ATHR_DEBUG_PORT_ADDRESS, 0xb); + s26_wr_phy(phy_addr, ATHR_DEBUG_PORT_DATA, 0x3c00); +} + +void athrs26_reg_init(void){ + uint32_t ar7240_revid; +#if S26_PHY_DEBUG + uint32_t rd_val; +#endif + + /* if using header for register configuration, we have to */ + /* configure s26 register after frame transmission is enabled */ + if(athr26_init_flag){ + return; + } + + ar7240_revid = ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK; + + if(ar7240_revid == AR7240_REV_1_0){ +#ifdef S26_FORCE_100M + s26_wr_phy(ATHR_PHY4_ADDR, ATHR_PHY_FUNC_CONTROL, 0x800); + s26_wr_phy(ATHR_PHY4_ADDR, ATHR_PHY_CONTROL, 0xa100); +#endif +#ifdef S26_FORCE_10M + athrs26_powersave_off(ATHR_PHY4_ADDR); + athrs26_sleep_off(ATHR_PHY4_ADDR); + s26_wr_phy(ATHR_PHY4_ADDR,ATHR_PHY_FUNC_CONTROL,0x800); + s26_wr_phy(ATHR_PHY4_ADDR,ATHR_PHY_CONTROL,0x8100); + s26_wr_phy(ATHR_PHY4_ADDR,ATHR_DEBUG_PORT_ADDRESS,0x0); + s26_wr_phy(ATHR_PHY4_ADDR,ATHR_DEBUG_PORT_DATA,0x12ee); + s26_wr_phy(ATHR_PHY4_ADDR,ATHR_DEBUG_PORT_ADDRESS,0x3); + s26_wr_phy(ATHR_PHY4_ADDR,ATHR_DEBUG_PORT_DATA,0x3bf0); + s26_wr_phy(ATHR_PHY4_ADDR,ATHR_PHY_CONTROL,0x8100); +#endif + } else { + s26_wr_phy(ATHR_PHY4_ADDR, ATHR_PHY_CONTROL, 0x9000); + } + +#if S26_PHY_DEBUG + rd_val = s26_rd_phy(ATHR_PHY4_ADDR,ATHR_PHY_FUNC_CONTROL); + printf("S26 PHY FUNC CTRL (%d) :%x\n",ATHR_PHY4_ADDR, rd_val); + + rd_val = s26_rd_phy(ATHR_PHY4_ADDR,ATHR_PHY_CONTROL); + printf("S26 PHY CTRL (%d) :%x\n",ATHR_PHY4_ADDR, rd_val); +#endif + + athr26_init_flag = 1; +} + +void athrs26_reg_init_lan(void){ + int i = 60; + int phyUnit; + //uint32_t phyBase = 0; + uint32_t phyAddr = 0; + uint32_t ar7240_revid; +#if S26_PHY_DEBUG + uint32_t rd_val; +#endif + + /* if using header for register configuration, we have to */ + /* configure s26 register after frame transmission is enabled */ + if(athr26_init_flag1){ + return; + } + + /* reset switch */ + athrs26_reg_write(0x0, athrs26_reg_read(0x0) | 0x80000000); + + while(i--){ + if(!is_ar933x()){ + sysMsDelay(100); + } + + if(!(athrs26_reg_read(0x0) & 0x80000000)){ + break; + } + } + + for(phyUnit = 0; phyUnit < ATHR_PHY_MAX - 1; phyUnit++){ + //phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + ar7240_revid = ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK; + if(ar7240_revid == AR7240_REV_1_0){ +#ifdef S26_FORCE_100M + /* + * Force MDI and MDX to alternate ports + * Phy 0 and 2 -- MDI + * Phy 1 and 3 -- MDX + */ + if(phyUnit % 2){ + s26_wr_phy(phyAddr, ATHR_PHY_FUNC_CONTROL, 0x820); + } else { + s26_wr_phy(phyAddr, ATHR_PHY_FUNC_CONTROL, 0x800); + } + + s26_wr_phy(phyAddr, ATHR_PHY_CONTROL, 0xa100); +#endif + +#ifdef S26_FORCE_10M + /* + * Force MDI and MDX to alternate ports + * Phy 0 and 2 -- MDI + * Phy 1 and 3 -- MDX + */ + if(phyUnit%2){ + s26_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x820); + } else { + s26_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x800); + } + + athrs26_powersave_off(phyAddr); + athrs26_sleep_off(phyAddr); + + s26_wr_phy(phyAddr,ATHR_PHY_CONTROL,0x8100); + s26_wr_phy(phyAddr,ATHR_DEBUG_PORT_ADDRESS,0x0); + s26_wr_phy(phyAddr,ATHR_DEBUG_PORT_DATA,0x12ee); + s26_wr_phy(phyAddr,ATHR_DEBUG_PORT_ADDRESS,0x3); + s26_wr_phy(phyAddr,ATHR_DEBUG_PORT_DATA,0x3bf0); + s26_wr_phy(phyAddr,ATHR_PHY_CONTROL,0x8100); +#endif + } else { + s26_wr_phy(phyAddr, ATHR_PHY_CONTROL, 0x9000); + } + +#if S26_PHY_DEBUG + rd_val = s26_rd_phy(phyAddr,ATHR_PHY_ID1); + printf("S26 PHY ID (%d) :%x\n",phyAddr,rd_val); + + rd_val = s26_rd_phy(phyAddr,ATHR_PHY_CONTROL); + printf("S26 PHY CTRL (%d) :%x\n",phyAddr,rd_val); + + rd_val = s26_rd_phy(phyAddr,ATHR_PHY_STATUS); + printf("S26 ATHR PHY STATUS (%d) :%x\n",phyAddr,rd_val); +#endif + } + + /* + * CPU port Enable + */ + athrs26_reg_write(CPU_PORT_REGISTER, (1 << 8)); + + /* + * status[1:0]=2'h2; - (0x10 - 1000 Mbps , 0x0 - 10 Mbps) + * status[2]=1'h1; - Tx Mac En + * status[3]=1'h1; - Rx Mac En + * status[4]=1'h1; - Tx Flow Ctrl En + * status[5]=1'h1; - Rx Flow Ctrl En + * status[6]=1'h1; - Duplex Mode + */ + athrs26_reg_write(PORT_STATUS_REGISTER1, 0x200); /* LAN - 1 */ + athrs26_reg_write(PORT_STATUS_REGISTER2, 0x200); /* LAN - 2 */ + athrs26_reg_write(PORT_STATUS_REGISTER3, 0x200); /* LAN - 3 */ + athrs26_reg_write(PORT_STATUS_REGISTER4, 0x200); /* LAN - 4 */ + + /* QM Control */ + athrs26_reg_write(0x38, 0xc000050e); + + /* + * status[11]=1'h0; - CPU Disable + * status[7] = 1'b1; - Learn One Lock + * status[14] = 1'b0; - Learn Enable + */ + /* Atheros Header Disable */ + athrs26_reg_write(PORT_CONTROL_REGISTER0, 0x4004); + + /* Tag Priority Mapping */ + athrs26_reg_write(0x70, 0xfa50); + + /* Enable ARP packets to CPU port */ + athrs26_reg_write(S26_ARL_TBL_CTRL_REG, (athrs26_reg_read(S26_ARL_TBL_CTRL_REG) | 0x100000)); + +#if S26_PHY_DEBUG + rd_val = athrs26_reg_read ( CPU_PORT_REGISTER ); + printf("S26 CPU_PORT_REGISTER :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_STATUS_REGISTER0 ); + printf("S26 PORT_STATUS_REGISTER0 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_STATUS_REGISTER1 ); + printf("S26 PORT_STATUS_REGISTER1 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_STATUS_REGISTER2 ); + printf("S26 PORT_STATUS_REGISTER2 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_STATUS_REGISTER3 ); + printf("S26 PORT_STATUS_REGISTER3 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_STATUS_REGISTER4 ); + printf("S26 PORT_STATUS_REGISTER4 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_CONTROL_REGISTER0 ); + printf("S26 PORT_CONTROL_REGISTER0 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_CONTROL_REGISTER1 ); + printf("S26 PORT_CONTROL_REGISTER1 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_CONTROL_REGISTER2 ); + printf("S26 PORT_CONTROL_REGISTER2 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_CONTROL_REGISTER3 ); + printf("S26 PORT_CONTROL_REGISTER3 :%x\n",rd_val); + + rd_val = athrs26_reg_read ( PORT_CONTROL_REGISTER4 ); + printf("S26 PORT_CONTROL_REGISTER4 :%x\n",rd_val); +#endif + + athr26_init_flag1 = 1; +} + +/****************************************************************************** + * + * athrs26_phy_is_link_alive - test to see if the specified link is alive + * + * RETURNS: + * TRUE --> link is alive + * FALSE --> link is down + */ +int athrs26_phy_is_link_alive(int phyUnit){ + uint16_t phyHwStatus; + //uint32_t phyBase; + uint32_t phyAddr; + + //phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + phyHwStatus = s26_rd_phy(phyAddr, ATHR_PHY_SPEC_STATUS); + + if(phyHwStatus & ATHR_STATUS_LINK_PASS){ + return(TRUE); + } + + return(FALSE); +} + +/****************************************************************************** + * + * athrs26_phy_setup - reset and setup the PHY associated with + * the specified MAC unit number. + * + * Resets the associated PHY port. + * + * RETURNS: + * TRUE --> associated PHY is alive + * FALSE --> no LINKs on this ethernet unit + */ +int athrs26_phy_setup(int ethUnit){ + int phyUnit; + int liveLinks = 0; + uint16_t phyHwStatus; + uint16_t timeout; + //uint32_t phyBase = 0; + uint32_t phyAddr = 0; + uint32_t ar7240_revid; + int foundPhy = FALSE; +#if S26_PHY_DEBUG + uint32_t rd_val = 0; +#endif + + /* See if there's any configuration data for this enet */ + /* start auto negogiation on each phy */ + for(phyUnit = 0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + foundPhy = TRUE; + //phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + s26_wr_phy(phyAddr, ATHR_AUTONEG_ADVERT, ATHR_ADVERTISE_ALL); + +#if S26_PHY_DEBUG + rd_val = s26_rd_phy(phyAddr,ATHR_AUTONEG_ADVERT ); + printf("%s ATHR_AUTONEG_ADVERT %d :%x\n",__func__,phyAddr, rd_val); +#endif + + ar7240_revid = ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK; + + if(ar7240_revid != AR7240_REV_1_0){ + s26_wr_phy(phyAddr, ATHR_PHY_CONTROL, ATHR_CTRL_AUTONEGOTIATION_ENABLE | ATHR_CTRL_SOFTWARE_RESET); + } + +#if S26_PHY_DEBUG + rd_val = s26_rd_phy(phyAddr,ATHR_AUTONEG_ADVERT ); + rd_val = s26_rd_phy(phyAddr,ATHR_PHY_CONTROL); + printf("%s ATHR_PHY_CONTROL %d :%x\n",__func__,phyAddr, rd_val); +#endif + } + + if(!foundPhy){ + /* No PHY's configured for this ethUnit */ + return(FALSE); + } + + /* + * After the phy is reset, it takes a little while before + * it can respond properly. + */ + if(!is_ar933x()){ + if(ethUnit == ENET_UNIT_LAN){ + sysMsDelay(1000); + } else { + sysMsDelay(3000); + } + } + + /* + * Wait up to 3 seconds for ALL associated PHYs to finish + * autonegotiation. The only way we get out of here sooner is + * if ALL PHYs are connected AND finish autonegotiation. + */ + for(phyUnit = 0; (phyUnit < ATHR_PHY_MAX); phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + timeout = 20; + + for(;;){ + phyHwStatus = s26_rd_phy(phyAddr, ATHR_PHY_CONTROL); + + if(ATHR_RESET_DONE(phyHwStatus)){ + DRV_PRINT(DRV_DEBUG_PHYSETUP, ("Port %d, Neg Success\n", phyUnit)); + break; + } + + if(timeout == 0){ + DRV_PRINT(DRV_DEBUG_PHYSETUP, ("Port %d, Negogiation timeout\n", phyUnit)); + break; + } + + if(--timeout == 0){ + DRV_PRINT(DRV_DEBUG_PHYSETUP, ("Port %d, Negogiation timeout\n", phyUnit)); + break; + } + + if(!is_ar933x()){ + sysMsDelay(150); + } + } + + /* fix IOT */ + s26_wr_phy(phyUnit, 29, 0x14); + s26_wr_phy(phyUnit, 30, 0x1352); + +#ifdef S26_VER_1_0 + //turn off power saving + s26_wr_phy(phyUnit, 29, 41); + s26_wr_phy(phyUnit, 30, 0); + printf("def_ S26_VER_1_0\n"); +#endif + } + + /* + * All PHYs have had adequate time to autonegotiate. + * Now initialize software status. + * + * It's possible that some ports may take a bit longer + * to autonegotiate; but we can't wait forever. They'll + * get noticed by mv_phyCheckStatusChange during regular + * polling activities. + */ + for(phyUnit = 0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + if(athrs26_phy_is_link_alive(phyUnit)){ + liveLinks++; + ATHR_IS_PHY_ALIVE(phyUnit) = TRUE; + } else { + ATHR_IS_PHY_ALIVE(phyUnit) = FALSE; + } + + DRV_PRINT(DRV_DEBUG_PHYSETUP, ("eth%d: Phy Specific Status=%4.4x\n", ethUnit, s26_rd_phy(ATHR_PHYADDR(phyUnit),ATHR_PHY_SPEC_STATUS))); + } + + return(liveLinks > 0); +} + +/****************************************************************************** + * + * athrs26_phy_is_fdx - Determines whether the phy ports associated with the + * specified device are FULL or HALF duplex. + * + * RETURNS: + * 1 --> FULL + * 0 --> HALF + */ +int athrs26_phy_is_fdx(int ethUnit){ + int phyUnit; + //uint32_t phyBase; + //uint32_t phyAddr; + uint16_t phyHwStatus; + int ii = 200; + + if(ethUnit == ENET_UNIT_LAN){ + return(TRUE); + } + + for(phyUnit = 0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + if(athrs26_phy_is_link_alive(phyUnit)){ + + //phyBase = ATHR_PHYBASE(phyUnit); + //phyAddr = ATHR_PHYADDR(phyUnit); + + do { + phyHwStatus = s26_rd_phy(ATHR_PHYADDR(phyUnit), ATHR_PHY_SPEC_STATUS); + sysMsDelay(10); + } while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii); + + if(phyHwStatus & ATHER_STATUS_FULL_DEPLEX){ + return(TRUE); + } + } + } + + return(FALSE); +} + +/****************************************************************************** + * + * athrs26_phy_speed - Determines the speed of phy ports associated with the + * specified device. + * + * RETURNS: + * _10BASET, _100BASET; + * _1000BASET; + */ + +int athrs26_phy_speed(int ethUnit){ + int phyUnit; + uint16_t phyHwStatus; + //uint32_t phyBase; + uint32_t phyAddr; + int ii = 200; + + if(ethUnit == ENET_UNIT_LAN){ + return(_1000BASET); + } + + for(phyUnit = 0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + if(athrs26_phy_is_link_alive(phyUnit)){ + + //phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + do { + phyHwStatus = s26_rd_phy(ATHR_PHYADDR(phyUnit), ATHR_PHY_SPEC_STATUS); + sysMsDelay(10); + } while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii); + + phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >> ATHER_STATUS_LINK_SHIFT); + + switch(phyHwStatus){ + case 0: + return(_10BASET); + case 1: +#ifdef CONFIG_MACH_HORNET + /* For IEEE 100M voltage test */ + s26_wr_phy(phyAddr, ATHR_DEBUG_PORT_ADDRESS, 0x4); + s26_wr_phy(phyAddr, ATHR_DEBUG_PORT_DATA, 0xebbb); + s26_wr_phy(phyAddr, ATHR_DEBUG_PORT_ADDRESS, 0x5); + s26_wr_phy(phyAddr, ATHR_DEBUG_PORT_DATA, 0x2c47); +#endif /* CONFIG_MACH_HORNET */ + return(_100BASET); + case 2: + return(_1000BASET); + default: + printf("## Error: unkown eth speed!\n"); + } + } + } + + return(_10BASET); +} + +/***************************************************************************** + * + * athr_phy_is_up -- checks for significant changes in PHY state. + * + * A "significant change" is: + * dropped link (e.g. ethernet cable unplugged) OR + * autonegotiation completed + link (e.g. ethernet cable plugged in) + * + * When a PHY is plugged in, phyLinkGained is called. + * When a PHY is unplugged, phyLinkLost is called. + */ + +int athrs26_phy_is_up(int ethUnit){ + int phyUnit; + int linkCount = 0; + int lostLinks = 0; + int gainedLinks = 0; + uint16_t phyHwStatus, phyHwControl; + athrPhyInfo_t *lastStatus; + //uint32_t phyBase; + //uint32_t phyAddr; + + for(phyUnit = 0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + //phyBase = ATHR_PHYBASE(phyUnit); + //phyAddr = ATHR_PHYADDR(phyUnit); + + lastStatus = &athrPhyInfo[phyUnit]; + + if(lastStatus->isPhyAlive){ /* last known link status was ALIVE */ + + phyHwStatus = s26_rd_phy(ATHR_PHYADDR(phyUnit), ATHR_PHY_SPEC_STATUS); + + /* See if we've lost link */ + if(phyHwStatus & ATHR_STATUS_LINK_PASS){ /* check realtime link */ + linkCount++; + } else { + phyHwStatus = s26_rd_phy(ATHR_PHYADDR(phyUnit), ATHR_PHY_STATUS); + /* If realtime failed check link in latch register before + * asserting link down. + */ + if(phyHwStatus & ATHR_LATCH_LINK_PASS){ + linkCount++; + } else { + lostLinks++; + } + + DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n", ethUnit, phyUnit)); + lastStatus->isPhyAlive = FALSE; + } + } else { /* last known link status was DEAD */ + + /* Check for reset complete */ + phyHwStatus = s26_rd_phy(ATHR_PHYADDR(phyUnit), ATHR_PHY_STATUS); + + if(!ATHR_RESET_DONE(phyHwStatus)){ + continue; + } + + phyHwControl = s26_rd_phy(ATHR_PHYADDR(phyUnit), ATHR_PHY_CONTROL); + + /* Check for AutoNegotiation complete */ + if((!(phyHwControl & ATHR_CTRL_AUTONEGOTIATION_ENABLE)) || ATHR_AUTONEG_DONE(phyHwStatus)){ + phyHwStatus = s26_rd_phy(ATHR_PHYADDR(phyUnit), ATHR_PHY_SPEC_STATUS); + + if(phyHwStatus & ATHR_STATUS_LINK_PASS){ + gainedLinks++; + linkCount++; + DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n", ethUnit, phyUnit)); + lastStatus->isPhyAlive = TRUE; + } + } + } + } + + return(linkCount); + +#if S26_PHY_DEBUG + if(linkCount == 0){ + if(lostLinks){ + /* We just lost the last link for this MAC */ + phyLinkLost(ethUnit); + } + } else { + if(gainedLinks == linkCount){ + /* We just gained our first link(s) for this MAC */ + phyLinkGained(ethUnit); + } + } +#endif +} + +uint32_t athrs26_reg_read(unsigned int s26_addr){ + unsigned int addr_temp; + unsigned int s26_rd_csr_low, s26_rd_csr_high, s26_rd_csr; + unsigned int data, unit = 0; + unsigned int phy_address, reg_address; + + addr_temp = (s26_addr & 0xfffffffc) >> 2; + data = addr_temp >> 7; + + phy_address = 0x1f; + reg_address = 0x10; + + if(is_ar7240()){ + unit = 0; + } else if(is_ar7241() || is_ar7242() || is_ar933x()){ + unit = 1; + } + + phy_reg_write(unit, phy_address, reg_address, data); + + phy_address = (0x17 & ((addr_temp >> 4) | 0x10)); + reg_address = ((addr_temp << 1) & 0x1e); + s26_rd_csr_low = (uint32_t)phy_reg_read(unit, phy_address, reg_address); + + reg_address = reg_address | 0x1; + s26_rd_csr_high = (uint32_t)phy_reg_read(unit, phy_address, reg_address); + s26_rd_csr = (s26_rd_csr_high << 16) | s26_rd_csr_low; + + return(s26_rd_csr); +} + +void athrs26_reg_write(unsigned int s26_addr, unsigned int s26_write_data){ + unsigned int addr_temp; + unsigned int data, unit = 0; + unsigned int phy_address, reg_address; + + addr_temp = (s26_addr & 0xfffffffc) >> 2; + data = addr_temp >> 7; + + phy_address = 0x1f; + reg_address = 0x10; + + if(is_ar7240()){ + unit = 0; + } else if(is_ar7241() || is_ar7242() || is_ar933x()){ + unit = 1; + } + +#ifdef CONFIG_MACH_HORNET + //The write sequence , 0x98: L->H, 0x40 H->L, 0x50 H->L , others should not care. + if(s26_addr!=0x98){ + //printf("[%s:%d] unit=%d\n",__FUNCTION__,__LINE__,unit); + phy_reg_write(unit, phy_address, reg_address, data); + + phy_address = 0x17 & ((addr_temp >> 4) | 0x10); + reg_address = ((addr_temp << 1) & 0x1e) | 0x1; + data = s26_write_data >> 16; + phy_reg_write(unit, phy_address, reg_address, data); + + reg_address = reg_address & 0x1e; + data = s26_write_data & 0xffff; + phy_reg_write(unit, phy_address, reg_address, data); + } else { + phy_reg_write(unit, phy_address, reg_address, data); + + phy_address = (0x17 & ((addr_temp >> 4) | 0x10)); + reg_address = ((addr_temp << 1) & 0x1e); + + data = s26_write_data & 0xffff; + phy_reg_write(unit, phy_address, reg_address, data); + + reg_address = (((addr_temp << 1) & 0x1e) | 0x1); + data = s26_write_data >> 16; + phy_reg_write(unit, phy_address, reg_address, data); + } +#else + phy_reg_write(unit, phy_address, reg_address, data); + + phy_address = (0x17 & ((addr_temp >> 4) | 0x10)); + reg_address = ((addr_temp << 1) & 0x1e); + data = s26_write_data & 0xffff; + phy_reg_write(unit, phy_address, reg_address, data); + + reg_address = (((addr_temp << 1) & 0x1e) | 0x1); + data = s26_write_data >> 16; + phy_reg_write(unit, phy_address, reg_address, data); +#endif +} + +unsigned int s26_rd_phy(unsigned int phy_addr, unsigned int reg_addr){ + unsigned int rddata; + unsigned int i = 0; + + // MDIO_CMD is set for read + rddata = athrs26_reg_read(0x98); + rddata = (rddata & 0x0) | (reg_addr << 16) | (phy_addr << 21) | (1 << 27) | (1 << 30) | (1 << 31); + athrs26_reg_write(0x98, rddata); + + rddata = athrs26_reg_read(0x98); + rddata = rddata & (1 << 31); + + // Check MDIO_BUSY status + while(rddata){ + // TODO: do we need this? + i++; + + if(i > 824) { + //printf("## Error: MDIO_BUSY!\n"); + break; + } + + rddata = athrs26_reg_read(0x98); + rddata = rddata & (1 << 31); + } + + // Read the data from phy + rddata = athrs26_reg_read(0x98) & 0xffff; + + return(rddata); +} + +void s26_wr_phy(unsigned int phy_addr, unsigned int reg_addr, unsigned int write_data){ + unsigned int rddata; + + // MDIO_CMD is set for read + rddata = athrs26_reg_read(0x98); + rddata = (rddata & 0x0) | (write_data & 0xffff) | (reg_addr << 16) | (phy_addr << 21) | (0 << 27) | (1 << 30) | (1 << 31); + athrs26_reg_write(0x98, rddata); + + rddata = athrs26_reg_read(0x98); + rddata = rddata & (1 << 31); + + // Check MDIO_BUSY status + while(rddata){ + rddata = athrs26_reg_read(0x98); + rddata = rddata & (1 << 31); + } + +} + +int athrs26_mdc_check(void){ + int i; + + for(i = 0; i < 4000; i++){ + if(athrs26_reg_read(0x10c) != 0x18007fff){ + return(-1); + } + } + + return(0); +} diff --git a/u-boot/board/ar7240/common/ar7240_s26_phy.h b/u-boot/board/ar7240/common/ar7240_s26_phy.h new file mode 100755 index 0000000..e6586b4 --- /dev/null +++ b/u-boot/board/ar7240/common/ar7240_s26_phy.h @@ -0,0 +1,106 @@ +#ifndef _ATHRS26_PHY_H +#define _ATHRS26_PHY_H + +/*****************/ +/* PHY Registers */ +/*****************/ +#define ATHR_PHY_CONTROL 0 +#define ATHR_PHY_STATUS 1 +#define ATHR_PHY_ID1 2 +#define ATHR_PHY_ID2 3 +#define ATHR_AUTONEG_ADVERT 4 +#define ATHR_LINK_PARTNER_ABILITY 5 +#define ATHR_AUTONEG_EXPANSION 6 +#define ATHR_NEXT_PAGE_TRANSMIT 7 +#define ATHR_LINK_PARTNER_NEXT_PAGE 8 +#define ATHR_1000BASET_CONTROL 9 +#define ATHR_1000BASET_STATUS 10 +#define ATHR_PHY_FUNC_CONTROL 16 +#define ATHR_PHY_SPEC_STATUS 17 +#define ATHR_DEBUG_PORT_ADDRESS 29 +#define ATHR_DEBUG_PORT_DATA 30 + +/* ATHR_PHY_CONTROL fields */ +#define ATHR_CTRL_SOFTWARE_RESET 0x8000 +#define ATHR_CTRL_SPEED_LSB 0x2000 +#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200 +#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100 +#define ATHR_CTRL_SPEED_MSB 0x0040 + +#define ATHR_RESET_DONE(phy_control) (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0) + +/* Phy status fields */ +#define ATHR_STATUS_AUTO_NEG_DONE 0x0020 +#define ATHR_AUTONEG_DONE(ip_phy_status) (((ip_phy_status) & (ATHR_STATUS_AUTO_NEG_DONE)) == (ATHR_STATUS_AUTO_NEG_DONE)) + +/* Link Partner ability */ +#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100 +#define ATHR_LINK_100BASETX 0x0080 +#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040 +#define ATHR_LINK_10BASETX 0x0020 + +/* Advertisement register */ +#define ATHR_ADVERTISE_NEXT_PAGE 0x8000 +#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800 +#define ATHR_ADVERTISE_PAUSE 0x0400 +#define ATHR_ADVERTISE_100FULL 0x0100 +#define ATHR_ADVERTISE_100HALF 0x0080 +#define ATHR_ADVERTISE_10FULL 0x0040 +#define ATHR_ADVERTISE_10HALF 0x0020 + +#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL) + +/* 1000BASET_CONTROL */ +#define ATHR_ADVERTISE_1000FULL 0x0200 + +/* Phy Specific status fields */ +#define ATHER_STATUS_LINK_MASK 0xC000 +#define ATHER_STATUS_LINK_SHIFT 14 +#define ATHER_STATUS_FULL_DEPLEX 0x2000 +#define ATHR_STATUS_LINK_PASS 0x0400 +#define ATHR_LATCH_LINK_PASS 0x0004 +#define ATHR_STATUS_RESOVLED 0x0800 + +/*phy debug portregister */ +#define ATHER_DEBUG_SERDES_REG 5 + +/* Serdes debug fields */ +#define ATHER_SERDES_BEACON 0x0100 + +/* S26 CSR Registers */ + +#define PORT_STATUS_REGISTER0 0x0100 +#define PORT_STATUS_REGISTER1 0x0200 +#define PORT_STATUS_REGISTER2 0x0300 +#define PORT_STATUS_REGISTER3 0x0400 +#define PORT_STATUS_REGISTER4 0x0500 +#define PORT_STATUS_REGISTER5 0x0600 + +#define RATE_LIMIT_REGISTER0 0x010C +#define RATE_LIMIT_REGISTER1 0x020C +#define RATE_LIMIT_REGISTER2 0x030C +#define RATE_LIMIT_REGISTER3 0x040C +#define RATE_LIMIT_REGISTER4 0x050C +#define RATE_LIMIT_REGISTER5 0x060C + +#define PORT_CONTROL_REGISTER0 0x0104 +#define PORT_CONTROL_REGISTER1 0x0204 +#define PORT_CONTROL_REGISTER2 0x0204 +#define PORT_CONTROL_REGISTER3 0x0204 +#define PORT_CONTROL_REGISTER4 0x0204 +#define PORT_CONTROL_REGISTER5 0x0204 + +#define CPU_PORT_REGISTER 0x0078 +#define MDIO_CTRL_REGISTER 0x0098 + +#define S26_ARL_TBL_FUNC_REG0 0x0050 +#define S26_ARL_TBL_FUNC_REG1 0x0054 +#define S26_ARL_TBL_FUNC_REG2 0x0058 +#define S26_ARL_TBL_CTRL_REG 0x005c + +#define sysMsDelay(_x) udelay((_x) * 1000) + +#define S26_FORCE_100M 1 + +#endif /* ifndef _ATHRS26_PHY_H */ diff --git a/u-boot/board/ar7240/common/athrs17_phy.c b/u-boot/board/ar7240/common/athrs17_phy.c new file mode 100755 index 0000000..40fe37f --- /dev/null +++ b/u-boot/board/ar7240/common/athrs17_phy.c @@ -0,0 +1,520 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright © 2007 Atheros Communications, Inc., All Rights Reserved. + */ + +/* + * Manage the atheros ethernet PHY. + * + * All definitions in this file are operating system independent! + */ + +#include +#include +#include +#include +#include "phy.h" +#include +#include "ar7240_soc.h" +#include "athrs17_phy.h" + +#define ATHR_LAN_PORT_VLAN 1 +#define ATHR_WAN_PORT_VLAN 2 +#define ENET_UNIT_GE0 0 +#define ENET_UNIT_GE1 1 +#define TRUE 1 +#define FALSE 0 + +#define ATHR_PHY0_ADDR 0x0 +#define ATHR_PHY1_ADDR 0x1 +#define ATHR_PHY2_ADDR 0x2 +#define ATHR_PHY3_ADDR 0x3 +#define ATHR_PHY4_ADDR 0x4 +#define ATHR_IND_PHY 4 + +#define MODULE_NAME "ATHRS17" +#define S17_PHY_DEBUG 1 + +/* + * Track per-PHY port information. + */ +typedef struct { + int isEnetPort; /* normal enet port */ + int isPhyAlive; /* last known state of link */ + int ethUnit; /* MAC associated with this phy port */ + uint32_t phyBase; + uint32_t phyAddr; /* PHY registers associated with this phy port */ + uint32_t VLANTableSetting; /* Value to be written to VLAN table */ +} athrPhyInfo_t; + +/* + * Per-PHY information, indexed by PHY unit number. + */ +static athrPhyInfo_t athrPhyInfo[] = { + /* phy port 0 -- LAN port 0 */ + {TRUE, FALSE, ENET_UNIT_GE0, 0, ATHR_PHY0_ADDR, ATHR_LAN_PORT_VLAN}, + + /* phy port 1 -- LAN port 1 */ + {TRUE, FALSE, ENET_UNIT_GE0, 0, ATHR_PHY1_ADDR, ATHR_LAN_PORT_VLAN}, + + /* phy port 2 -- LAN port 2 */ + {TRUE, FALSE, ENET_UNIT_GE0, 0, ATHR_PHY2_ADDR, ATHR_LAN_PORT_VLAN}, + + /* phy port 3 -- LAN port 3 */ + {TRUE, FALSE, ENET_UNIT_GE0, 0, ATHR_PHY3_ADDR, ATHR_LAN_PORT_VLAN}, + + /* phy port 4 -- WAN port or LAN port 4 */ + /* Send to all ports */ + {TRUE, FALSE, ENET_UNIT_GE0, 0, ATHR_PHY4_ADDR, ATHR_LAN_PORT_VLAN}, + + /* phy port 5 -- CPU port (no RJ45 connector) */ + /* Send to all ports */ + {FALSE, TRUE, ENET_UNIT_GE0, 0, 0x00, ATHR_LAN_PORT_VLAN}, +}; + +static uint8_t athr17_init_flag = 0; + +#define ATHR_PHY_MAX 5 + +/* Range of valid PHY IDs is [MIN..MAX] */ +#define ATHR_ID_MIN 0 +#define ATHR_ID_MAX (ATHR_PHY_MAX-1) + +/* Convenience macros to access myPhyInfo */ +#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort) +#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive) +#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit) +#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase) +#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr) +#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting) + +#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \ + (ATHR_IS_ENET_PORT(phyUnit) && \ + ATHR_ETHUNIT(phyUnit) == (ethUnit)) + +#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_GE0)) + +/* Forward references */ +int athrs17_phy_is_link_alive(int phyUnit); +uint32_t athrs17_reg_read(uint32_t reg_addr); +void athrs17_reg_write(uint32_t reg_addr, uint32_t reg_val); + +#define sysMsDelay(_x) udelay((_x) * 1000) + +void athrs17_reg_init(){ + int phy_addr = 0; + + /* if using header for register configuration, we have to */ + /* configure s17 register after frame transmission is enabled */ + if(athr17_init_flag){ + return; + } + + /* configure the RGMII */ + athrs17_reg_write(0x624 , 0x7f7f7f7f); + athrs17_reg_write(0x10 , 0x40000000); + athrs17_reg_write(0x4 , 0x07600000); + athrs17_reg_write(0xc , 0x01000000); + athrs17_reg_write(0x7c , 0x0000007e); + + /* AR8327/AR8328 v1.0 fixup */ + if((athrs17_reg_read(0x0) & 0xffff) == 0x1201){ + for(phy_addr = 0x0; phy_addr <= ATHR_PHY_MAX; phy_addr++){ + /* For 100M waveform */ + phy_reg_write(0, phy_addr, 0x1d, 0x0); + phy_reg_write(0, phy_addr, 0x1e, 0x02ea); + + /* Turn On Gigabit Clock */ + phy_reg_write(0, phy_addr, 0x1d, 0x3d); + phy_reg_write(0, phy_addr, 0x1e, 0x68a0); + } + } + + /* set the WAN Port(Port1) Disable Mode(can not receive or transmit any frames) */ + // TODO: why WAN should be disabled? + //athrs17_reg_write(0x066c, athrs17_reg_read(0x066c) & 0xfff8ffff); + + athr17_init_flag = 1; +} + +/****************************************************************************** +* +* athrs17_phy_is_link_alive - test to see if the specified link is alive +* +* RETURNS: +* TRUE --> link is alive +* FALSE --> link is down +*/ +int athrs17_phy_is_link_alive(int phyUnit){ + uint16_t phyHwStatus; + //uint32_t phyBase; + //uint32_t phyAddr; + + //phyBase = ATHR_PHYBASE(phyUnit); + //phyAddr = ATHR_PHYADDR(phyUnit); + + phyHwStatus = phy_reg_read(ATHR_PHYBASE(phyUnit), ATHR_PHYADDR(phyUnit), ATHR_PHY_SPEC_STATUS); + + if(phyHwStatus & ATHR_STATUS_LINK_PASS){ + return(TRUE); + } + + return(FALSE); +} + +/****************************************************************************** +* +* athrs17_phy_setup - reset and setup the PHY associated with +* the specified MAC unit number. +* +* Resets the associated PHY port. +* +* RETURNS: +* TRUE --> associated PHY is alive +* FALSE --> no LINKs on this ethernet unit +*/ +int athrs17_phy_setup(int ethUnit){ + int phyUnit; + uint16_t phyHwStatus; + uint16_t timeout; + int liveLinks = 0; + uint32_t phyBase = 0; + int foundPhy = FALSE; + uint32_t phyAddr = 0; + + /* See if there's any configuration data for this enet */ + /* start auto negogiation on each phy */ + for(phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + foundPhy = TRUE; + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + phy_reg_write(phyBase, phyAddr, ATHR_AUTONEG_ADVERT, ATHR_ADVERTISE_ALL); + phy_reg_write(phyBase, phyAddr, ATHR_1000BASET_CONTROL, ATHR_ADVERTISE_1000FULL); + + /* Reset PHYs*/ + phy_reg_write(phyBase, phyAddr, ATHR_PHY_CONTROL, ATHR_CTRL_AUTONEGOTIATION_ENABLE | ATHR_CTRL_SOFTWARE_RESET); + } + + if(!foundPhy){ + /* No PHY's configured for this ethUnit */ + return(FALSE); + } + + /* + * After the phy is reset, it takes a little while before + * it can respond properly. + */ + sysMsDelay(1000); + + /* + * Wait up to 3 seconds for ALL associated PHYs to finish + * autonegotiation. The only way we get out of here sooner is + * if ALL PHYs are connected AND finish autonegotiation. + */ + for(phyUnit = 0; (phyUnit < ATHR_PHY_MAX); phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + // TODO: maybe we can lower this value + timeout = 10; + + for(;;){ + phyHwStatus = phy_reg_read(phyBase, phyAddr, ATHR_PHY_CONTROL); + + if(ATHR_RESET_DONE(phyHwStatus)){ + //printf("Port %d, Neg Success\n", phyUnit); + break; + } + + sysMsDelay(20); + + timeout--; + + if(timeout <= 0){ + printf("## Error: negotiation timed out on ethernet port: %d\n", phyUnit); + break; + } + } + } + + /* + * All PHYs have had adequate time to autonegotiate. + * Now initialize software status. + * + * It's possible that some ports may take a bit longer + * to autonegotiate; but we can't wait forever. They'll + * get noticed by mv_phyCheckStatusChange during regular + * polling activities. + */ + for(phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + if(athrs17_phy_is_link_alive(phyUnit)){ + liveLinks++; + ATHR_IS_PHY_ALIVE(phyUnit) = TRUE; + } else { + ATHR_IS_PHY_ALIVE(phyUnit) = FALSE; + } + + //printf("eth%d: Phy Specific Status=%4.4x\n", ethUnit, phy_reg_read(ATHR_PHYBASE(phyUnit), ATHR_PHYADDR(phyUnit), ATHR_PHY_SPEC_STATUS)); + } + + return(liveLinks > 0); +} + +/****************************************************************************** +* +* athrs17_phy_is_fdx - Determines whether the phy ports associated with the +* specified device are FULL or HALF duplex. +* +* RETURNS: +* 1 --> FULL +* 0 --> HALF +*/ +int athrs17_phy_is_fdx(int ethUnit){ + int phyUnit; + uint32_t phyBase; + uint32_t phyAddr; + uint16_t phyHwStatus; + int ii = 200; + + if(ethUnit == ENET_UNIT_GE0){ + return(TRUE); + } + + for(phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + if(athrs17_phy_is_link_alive(phyUnit)){ + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + do { + phyHwStatus = phy_reg_read(phyBase, phyAddr, + ATHR_PHY_SPEC_STATUS); + + if(phyHwStatus & ATHR_STATUS_RESOVLED){ + break; + } + + sysMsDelay(10); + } while(--ii); + + if(phyHwStatus & ATHER_STATUS_FULL_DEPLEX){ + return(TRUE); + } + } + } + + return(FALSE); +} + +/****************************************************************************** +* +* athrs17_phy_speed - Determines the speed of phy ports associated with the +* specified device. +* +* RETURNS: +* AG7240_PHY_SPEED_10T, AG7240_PHY_SPEED_100TX; +* AG7240_PHY_SPEED_1000T; +*/ +int athrs17_phy_speed(int ethUnit){ + int phyUnit; + uint16_t phyHwStatus; + uint32_t phyBase; + uint32_t phyAddr; + int ii = 200; + + if(ethUnit == ENET_UNIT_GE0){ + return(_1000BASET); + } + + for(phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + if(athrs17_phy_is_link_alive(phyUnit)){ + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + do { + phyHwStatus = phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS); + + if(phyHwStatus & ATHR_STATUS_RESOVLED){ + break; + } + + sysMsDelay(10); + } while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii); + + phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >> ATHER_STATUS_LINK_SHIFT); + + switch(phyHwStatus){ + case 0: + return(_10BASET); + break; + case 1: + return(_100BASET); + break; + case 2: + return(_1000BASET); + break; + default: + //printf("## Error: unkown speed read!\n"); + break; + } + } + } + + return(_10BASET); +} + +/***************************************************************************** +* +* athr_phy_is_up -- checks for significant changes in PHY state. +* +* A "significant change" is: +* dropped link (e.g. ethernet cable unplugged) OR +* autonegotiation completed + link (e.g. ethernet cable plugged in) +* +* When a PHY is plugged in, phyLinkGained is called. +* When a PHY is unplugged, phyLinkLost is called. +*/ +int athrs17_phy_is_up(int ethUnit){ + int phyUnit; + uint16_t phyHwStatus, phyHwControl; + athrPhyInfo_t *lastStatus; + int linkCount = 0; + int lostLinks = 0; + int gainedLinks = 0; + uint32_t phyBase; + uint32_t phyAddr; + + for(phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++){ + if(!ATHR_IS_ETHUNIT(phyUnit, ethUnit)){ + continue; + } + + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + lastStatus = &athrPhyInfo[phyUnit]; + + if(lastStatus->isPhyAlive){ /* last known link status was ALIVE */ + phyHwStatus = phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS); + + /* See if we've lost link */ + if(phyHwStatus & ATHR_STATUS_LINK_PASS){ + linkCount++; + } else { + lostLinks++; + //printf("\nenet%d port%d down\n", ethUnit, phyUnit); + lastStatus->isPhyAlive = FALSE; + } + } else { /* last known link status was DEAD */ + /* Check for reset complete */ + phyHwStatus = phy_reg_read(phyBase, phyAddr, ATHR_PHY_STATUS); + if(!ATHR_RESET_DONE(phyHwStatus)){ + continue; + } + + phyHwControl = phy_reg_read(phyBase, phyAddr, ATHR_PHY_CONTROL); + + /* Check for AutoNegotiation complete */ + if((!(phyHwControl & ATHR_CTRL_AUTONEGOTIATION_ENABLE)) || ATHR_AUTONEG_DONE(phyHwStatus)){ + phyHwStatus = phy_reg_read(phyBase, phyAddr, + ATHR_PHY_SPEC_STATUS); + + if(phyHwStatus & ATHR_STATUS_LINK_PASS){ + gainedLinks++; + linkCount++; + //printf("\nenet%d port%d up\n", ethUnit, phyUnit); + lastStatus->isPhyAlive = TRUE; + } + } + } + } + + return(linkCount); +} + +uint32_t athrs17_reg_read(uint32_t reg_addr){ + uint32_t reg_word_addr; + uint32_t phy_addr, tmp_val, reg_val; + uint16_t phy_val; + uint8_t phy_reg; + + /* change reg_addr to 16-bit word address, 32-bit aligned */ + reg_word_addr = (reg_addr & 0xfffffffc) >> 1; + + /* configure register high address */ + phy_addr = 0x18; + phy_reg = 0x0; + phy_val = (uint16_t)((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */ + phy_reg_write(0, phy_addr, phy_reg, phy_val); + + /* For some registers such as MIBs, since it is read/clear, we should */ + /* read the lower 16-bit register then the higher one */ + + /* read register in lower address */ + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t)(reg_word_addr & 0x1f); /* bit4-0 of reg address */ + reg_val = (uint32_t)phy_reg_read(0, phy_addr, phy_reg); + + /* read register in higher address */ + reg_word_addr++; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t)(reg_word_addr & 0x1f); /* bit4-0 of reg address */ + tmp_val = (uint32_t)phy_reg_read(0, phy_addr, phy_reg); + reg_val |= (tmp_val << 16); + + return(reg_val); +} + +void athrs17_reg_write(uint32_t reg_addr, uint32_t reg_val){ + uint32_t reg_word_addr; + uint32_t phy_addr; + uint16_t phy_val; + uint8_t phy_reg; + + /* change reg_addr to 16-bit word address, 32-bit aligned */ + reg_word_addr = (reg_addr & 0xfffffffc) >> 1; + + /* configure register high address */ + phy_addr = 0x18; + phy_reg = 0x0; + phy_val = (uint16_t)((reg_word_addr >> 8) & 0x1ff); /* bit16-8 of reg address */ + phy_reg_write(0, phy_addr, phy_reg, phy_val); + + /* For some registers such as ARL and VLAN, since they include BUSY bit */ + /* in lower address, we should write the higher 16-bit register then the */ + /* lower one */ + + /* read register in higher address */ + reg_word_addr++; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t)(reg_word_addr & 0x1f); /* bit4-0 of reg address */ + phy_val = (uint16_t)((reg_val >> 16) & 0xffff); + phy_reg_write(0, phy_addr, phy_reg, phy_val); + + /* write register in lower address */ + reg_word_addr--; + phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */ + phy_reg = (uint8_t)(reg_word_addr & 0x1f); /* bit4-0 of reg address */ + phy_val = (uint16_t)(reg_val & 0xffff); + phy_reg_write(0, phy_addr, phy_reg, phy_val); +} diff --git a/u-boot/board/ar7240/common/athrs17_phy.h b/u-boot/board/ar7240/common/athrs17_phy.h new file mode 100755 index 0000000..dd5fcaa --- /dev/null +++ b/u-boot/board/ar7240/common/athrs17_phy.h @@ -0,0 +1,92 @@ +#ifndef _ATHRS17_PHY_H +#define _ATHRS17_PHY_H + +/*****************/ +/* PHY Registers */ +/*****************/ +#define ATHR_PHY_CONTROL 0 +#define ATHR_PHY_STATUS 1 +#define ATHR_PHY_ID1 2 +#define ATHR_PHY_ID2 3 +#define ATHR_AUTONEG_ADVERT 4 +#define ATHR_LINK_PARTNER_ABILITY 5 +#define ATHR_AUTONEG_EXPANSION 6 +#define ATHR_NEXT_PAGE_TRANSMIT 7 +#define ATHR_LINK_PARTNER_NEXT_PAGE 8 +#define ATHR_1000BASET_CONTROL 9 +#define ATHR_1000BASET_STATUS 10 +#define ATHR_PHY_SPEC_CONTROL 16 +#define ATHR_PHY_SPEC_STATUS 17 +#define ATHR_DEBUG_PORT_ADDRESS 29 +#define ATHR_DEBUG_PORT_DATA 30 + +/* ATHR_PHY_CONTROL fields */ +#define ATHR_CTRL_SOFTWARE_RESET 0x8000 +#define ATHR_CTRL_SPEED_LSB 0x2000 +#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200 +#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100 +#define ATHR_CTRL_SPEED_MSB 0x0040 + +#define ATHR_RESET_DONE(phy_control) (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0) + +/* Phy status fields */ +#define ATHR_STATUS_AUTO_NEG_DONE 0x0020 +#define ATHR_AUTONEG_DONE(ip_phy_status) (((ip_phy_status) & (ATHR_STATUS_AUTO_NEG_DONE)) == (ATHR_STATUS_AUTO_NEG_DONE)) + +/* Link Partner ability */ +#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100 +#define ATHR_LINK_100BASETX 0x0080 +#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040 +#define ATHR_LINK_10BASETX 0x0020 + +/* Advertisement register. */ +#define ATHR_ADVERTISE_NEXT_PAGE 0x8000 +#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800 +#define ATHR_ADVERTISE_PAUSE 0x0400 +#define ATHR_ADVERTISE_100FULL 0x0100 +#define ATHR_ADVERTISE_100HALF 0x0080 +#define ATHR_ADVERTISE_10FULL 0x0040 +#define ATHR_ADVERTISE_10HALF 0x0020 + +#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \ + ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \ + ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL) + +/* 1000BASET_CONTROL */ +#define ATHR_ADVERTISE_1000FULL 0x0200 + +/* Phy Specific status fields */ +#define ATHER_STATUS_LINK_MASK 0xC000 +#define ATHER_STATUS_LINK_SHIFT 14 +#define ATHER_STATUS_FULL_DEPLEX 0x2000 +#define ATHR_STATUS_LINK_PASS 0x0400 +#define ATHR_STATUS_RESOVLED 0x0800 + +/*phy debug port register */ +#define ATHER_DEBUG_SERDES_REG 5 + +/* Serdes debug fields */ +#define ATHER_SERDES_BEACON 0x0100 + +/* S17 CSR Registers */ +#define S17_ENABLE_CPU_BROADCAST (1 << 26) +#define S17_PHY_LINK_CHANGE_REG 0x4 +#define S17_PHY_LINK_UP 0x400 +#define S17_PHY_LINK_DOWN 0x800 +#define S17_PHY_LINK_DUPLEX_CHANGE 0x2000 +#define S17_PHY_LINK_SPEED_CHANGE 0x4000 +#define S17_PHY_LINK_INTRS (PHY_LINK_UP | PHY_LINK_DOWN | PHY_LINK_DUPLEX_CHANGE | PHY_LINK_SPEED_CHANGE) + +#ifdef CONFIG_AR7242_S17_PHY +#undef HEADER_REG_CONF +#undef HEADER_EN +#endif + +void athrs17_reg_init(void); +int athrs17_phy_is_up(int unit); +int athrs17_phy_is_fdx(int unit); +int athrs17_phy_speed(int unit); +int athrs17_phy_setup(int unit); + +#endif diff --git a/u-boot/board/ar7240/common/lowlevel_init.S b/u-boot/board/ar7240/common/lowlevel_init.S new file mode 100755 index 0000000..a19988d --- /dev/null +++ b/u-boot/board/ar7240/common/lowlevel_init.S @@ -0,0 +1,89 @@ +#include +#include +#include +#include +#include +#include + +/* + * Helper macros. + * These Clobber t7, t8 and t9 + */ +#define clear_mask(_reg, _mask) \ + li t7, KSEG1ADDR(_reg); \ + lw t8, 0(t7); \ + li t9, ~_mask; \ + and t8, t8, t9; \ + sw t8, 0(t7) + +#define set_val(_reg, _mask, _val) \ + li t7, KSEG1ADDR(_reg); \ + lw t8, 0(t7); \ + li t9, ~_mask; \ + and t8, t8, t9; \ + li t9, _val; \ + or t8, t8, t9; \ + sw t8, 0(t7) + +#define set_val_f(_reg, _mask, _val) \ + li t7, KSEG1ADDR(_reg); \ + lw t8, 0(t7); \ + li t9, ~_mask; \ + and t8, t8, t9; \ + li t6, KSEG1ADDR(_val); \ + lw t9, 0(t6); \ + or t8, t8, t9; \ + sw t8, 0(t7) + + +#define get_val(_reg, _mask, _shift, _res_reg) \ + li t7, KSEG1ADDR(_reg); \ + lw t8, 0(t7); \ + li t9, _mask; \ + and t8, t8, t9; \ + srl _res_reg, t8, _shift \ + +#define pll_clr(_mask) \ + clear_mask(AR7240_CPU_PLL_CONFIG, _mask) + +#define pll_set(_mask, _val) \ + set_val(AR7240_CPU_PLL_CONFIG, _mask, _val) + +#define pll_set_f(_mask, _val) \ + set_val_f(AR7240_CPU_PLL_CONFIG, _mask, _val) + +#define pll_get(_mask, _shift, _res_reg) \ + get_val(AR7240_CPU_PLL_CONFIG, _mask, _shift, _res_reg) + +#define clk_clr(_mask) \ + clear_mask(AR7240_CPU_CLOCK_CONTROL, _mask) + +#define clk_set(_mask, _val) \ + set_val(AR7240_CPU_CLOCK_CONTROL, _mask, _val) + +#define clk_get(_mask, _shift, _res_reg) \ + get_val(AR7240_CPU_CLOCK_CONTROL, _mask, _shift, _res_reg) + + +/****************************************************************************** + * first level initialization: + * + * 0) If clock cntrl reset switch is already set, we're recovering from + * "divider reset"; goto 3. + * 1) Setup divide ratios. + * 2) Reset. + * 3) Setup pll's, wait for lock. + * + *****************************************************************************/ + +.globl lowlevel_init + +lowlevel_init: + /* + * The code below is for the real chip. Wont work on FPGA + */ + + b hornet_pll_init + jr ra + nop + diff --git a/u-boot/board/ar7240/common/lowlevel_init_934x.S b/u-boot/board/ar7240/common/lowlevel_init_934x.S new file mode 100755 index 0000000..b791cdb --- /dev/null +++ b/u-boot/board/ar7240/common/lowlevel_init_934x.S @@ -0,0 +1,240 @@ +#include +#include +#include +#include +#include +#include + +/* + * Helper macros. + * These Clobber t7, t8 and t9 + */ +#define cpu_ddr_control_set(_mask, _val) set_val(AR934X_CPU_DDR_CLOCK_CONTROL, _mask, _val) + +#define set_val(_reg, _mask, _val) \ + li t7, KSEG1ADDR(_reg); \ + lw t8, 0(t7); \ + li t9, ~_mask; \ + and t8, t8, t9; \ + li t9, _val; \ + or t8, t8, t9; \ + sw t8, 0(t7) + +#define set_bb_pll(reg, val) \ + li t7, KSEG1ADDR(reg); \ + li t8, val; \ + sw t8, 0(t7); + +#define set_srif_pll(reg, val) \ + li t7, KSEG1ADDR(reg); \ + li t8, val; \ + sw t8, 0(t7); + +#define set_srif_pll_reg(reg, _r) \ + li t7, KSEG1ADDR(reg); \ + sw _r, 0(t7); + +#define inc_loop_count(loc) \ + li t9, loc; \ + lw t7, 0(t9); \ + addi t7, t7, 1; \ + sw t7, 0(t9); + +#define clear_loop_count(loc) \ + li t9, loc; \ + sw zero, 0(t9); + +/****************************************************************************** + * first level initialization: + * + * 0) If clock cntrl reset switch is already set, we're recovering from + * "divider reset"; goto 3. + * 1) Setup divide ratios. + * 2) Reset. + * 3) Setup pll's, wait for lock. + * + *****************************************************************************/ + +.globl lowlevel_init + .type lowlevel_init, @function + .text + .align 4 + +lowlevel_init: + set_bb_pll(DPLL2_ADDRESS_c4, 0x13210f00); + set_bb_pll(DPLL3_ADDRESS_c8, 0x03000000); + set_bb_pll(DPLL2_ADDRESS_44, 0x13210f00); + set_bb_pll(DPLL3_ADDRESS_48, 0x03000000); + set_bb_pll(DPLL3_ADDRESS_88, 0x03000000); + +setup_ref40_val: + li t5, CPU_PLL_CONFIG_NINT_VAL_40 + li t6, DDR_PLL_CONFIG_NINT_VAL_40 + li t7, CPU_PLL_NFRAC_40 + li t9, DDR_PLL_NFRAC_40 + b 1f + nop + +1: + li t4, (CPU_PLL_DITHER_DITHER_EN_SET(0) | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)); + or t4, t4, t7 + + li t8, (CPU_PLL_CONFIG_REF_DIV_VAL | CPU_PLL_CONFIG_RANGE_VAL | CPU_PLL_CONFIG_OUT_DIV_VAL2); + or t5, t5, t8 + + li t8, (DDR_PLL_CONFIG_REF_DIV_VAL | DDR_PLL_CONFIG_RANGE_VAL | DDR_PLL_CONFIG_OUT_DIV_VAL2); + or t6, t6, t8 + + li t3, (DDR_PLL_DITHER_DITHER_EN_SET(0) | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)); + or t3, t3, t9 + +pll_bypass_set: + cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1)); + cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1)); + cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1)); + +init_cpu_pll: + li t7, KSEG1ADDR(AR934X_CPU_PLL_CONFIG); + li t8, CPU_PLL_CONFIG_PLLPWD_SET(1) + or t8, t8, t5 + sw t8, 0(t7); + +init_ddr_pll: + li t7, KSEG1ADDR(AR934X_DDR_PLL_CONFIG); + li t8, DDR_PLL_CONFIG_PLLPWD_SET(1) + or t8, t8, t6 + sw t8, 0(t7); + +init_ahb_pll: + li t7, KSEG1ADDR(AR934X_CPU_DDR_CLOCK_CONTROL); + li t8, (CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | \ + CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR | \ + CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR | \ + CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU | \ + CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | \ + CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV | \ + CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) | \ + CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) | \ + CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1)); + sw t8, 0(t7); + li t4, 0x41c00000; + li t5, 0x41680000; + j 2f + nop + +/* CPU */ +2: + clear_loop_count(ATH_CPU_COUNT_LOC); + +cpu_pll_is_not_locked: + inc_loop_count(ATH_CPU_COUNT_LOC); + set_srif_pll(0xb81161c4, (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16)); + set_srif_pll_reg(0xb81161c0, t4); + set_srif_pll(0xb81161c4, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16)); + set_srif_pll(0xb81161c8, (6 << 23)); + set_srif_pll(0xb81161c4, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7)); + +cpu_clear_do_meas1: + li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS) + lw t8, 0(t7) + li t9, ~CPU_DPLL3_DO_MEAS_SET(1) + and t8, t8, t9 + sw t8, 0(t7) + +cpu_set_do_meas: + li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS) + lw t8, 0(t7) + li t9, CPU_DPLL3_DO_MEAS_SET(1) + or t8, t8, t9 + sw t8, 0(t7) + li t7, KSEG1ADDR(CPU_DPLL4_ADDRESS) + +cpu_wait_for_meas_done: + lw t8, 0(t7) + andi t8, t8, CPU_DPLL4_MEAS_DONE_SET(1) + beqz t8, cpu_wait_for_meas_done + nop + +cpu_clear_do_meas2: + li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS) + lw t8, 0(t7) + li t9, ~CPU_DPLL3_DO_MEAS_SET(1) + and t8, t8, t9 + sw t8, 0(t7) + +cpu_read_sqsum_dvc: + li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS) + lw t8, 0(t7) + li t9, CPU_DPLL3_SQSUM_DVC_MASK + and t8, t8, t9 + sra t8, t8, CPU_DPLL3_SQSUM_DVC_LSB + li t9, 0x40000 + subu t8, t8, t9 + bgez t8, cpu_pll_is_not_locked + nop + +/* DDR */ + clear_loop_count(ATH_DDR_COUNT_LOC) + +ddr_pll_is_not_locked: + inc_loop_count(ATH_DDR_COUNT_LOC) + set_srif_pll(0xb8116244, (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16)); + set_srif_pll_reg(0xb8116240, t5); + set_srif_pll(0xb8116244, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16)); + set_srif_pll(0xb8116248, (6 << 23)); + set_srif_pll(0xb8116244, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7)); + +ddr_clear_do_meas1: + li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS) + lw t8, 0(t7) + li t9, ~DDR_DPLL3_DO_MEAS_SET(1) + and t8, t8, t9 + sw t8, 0(t7) + +ddr_set_do_meas: + li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS) + lw t8, 0(t7) + li t9, DDR_DPLL3_DO_MEAS_SET(1) + or t8, t8, t9 + sw t8, 0(t7) + li t7, KSEG1ADDR(DDR_DPLL4_ADDRESS) + +ddr_wait_for_meas_done: + lw t8, 0(t7) + andi t8, t8, DDR_DPLL4_MEAS_DONE_SET(1) + beqz t8, ddr_wait_for_meas_done + nop + +ddr_clear_do_meas2: + li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS) + lw t8, 0(t7) + li t9, ~DDR_DPLL3_DO_MEAS_SET(1) + and t8, t8, t9 + sw t8, 0(t7) + +ddr_read_sqsum_dvc: + li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS) + lw t8, 0(t7) + li t9, DDR_DPLL3_SQSUM_DVC_MASK + and t8, t8, t9 + sra t8, t8, DDR_DPLL3_SQSUM_DVC_LSB + li t9, 0x40000 + subu t8, t8, t9 + bgez t8, ddr_pll_is_not_locked + nop + +pll_bypass_unset: + cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0)); + cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0)); + cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0)); + +ddr_pll_dither_unset: + li t7, KSEG1ADDR(AR934X_DDR_PLL_DITHER); + sw t3, 0(t7); + +cpu_pll_dither_unset: + li t7, KSEG1ADDR(AR934X_CPU_PLL_DITHER); + sw t4, 0(t7); + + jr ra + nop diff --git a/u-boot/board/ar7240/common/phy.h b/u-boot/board/ar7240/common/phy.h new file mode 100755 index 0000000..f90e9bf --- /dev/null +++ b/u-boot/board/ar7240/common/phy.h @@ -0,0 +1,15 @@ +#ifndef _PHY_H +#define _PHY_H + +#include +/* + * This file defines the interface between MAC and various phy switches. + */ +extern int ag7240_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg); +extern int ag7240_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data); + +#define ag7240_unit2name(_unit) _unit ? "eth1" : "eth0" +#define phy_reg_read(base, addr, reg) ag7240_miiphy_read(ag7240_unit2name(base), addr, reg) +#define phy_reg_write(base, addr, reg, data) ag7240_miiphy_write(ag7240_unit2name(base), addr, reg, data) + +#endif /* ifndef _PHY_H */ diff --git a/u-boot/board/ar7240/db12x/Makefile b/u-boot/board/ar7240/db12x/Makefile new file mode 100755 index 0000000..c01ba39 --- /dev/null +++ b/u-boot/board/ar7240/db12x/Makefile @@ -0,0 +1,19 @@ +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/ar7240_pci.o ../common/ar7240_flash.o ../common/athrs17_phy.o + +SOBJS = ../common/lowlevel_init_934x.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/board/ar7240/db12x/config.mk b/u-boot/board/ar7240/db12x/config.mk new file mode 100755 index 0000000..76b95d5 --- /dev/null +++ b/u-boot/board/ar7240/db12x/config.mk @@ -0,0 +1,10 @@ +# ROM version +TEXT_BASE = 0x80010000 +BOOTSTRAP_TEXT_BASE = 0x9F000000 + +# SDRAM version +# TEXT_BASE = 0x80000000 + +# RAM version +# TEXT_BASE = 0x83FC0000 +# TEXT_BASE = 0x80100000 diff --git a/u-boot/board/ar7240/db12x/db12x.c b/u-boot/board/ar7240/db12x/db12x.c new file mode 100755 index 0000000..eb6fdf2 --- /dev/null +++ b/u-boot/board/ar7240/db12x/db12x.c @@ -0,0 +1,127 @@ +#include +#include +#include +#include +#include +#include +#include "ar7240_soc.h" + +extern int wasp_ddr_initial_config(uint32_t refresh); +extern int ar7240_ddr_find_size(void); + +#define SETBITVAL(val, pos, bit) do {ulong bitval = (bit) ? 0x1 : 0x0; (val) = ((val) & ~(0x1 << (pos))) | ( (bitval) << (pos));} while(0) + +void led_toggle(void){ + unsigned int gpio; + + gpio = ar7240_reg_rd(AR7240_GPIO_OUT); + + // SYS LED is connected to GPIO 14 + gpio ^= 1 << 14; + + ar7240_reg_wr(AR7240_GPIO_OUT, gpio); +} + +void all_led_on(void){ + unsigned int gpio; + + gpio = ar7240_reg_rd(AR7240_GPIO_OUT); + + // SYS LED (GPIO 14) and WLAN24 (GPIO 13) + SETBITVAL(gpio, 14, 0); + SETBITVAL(gpio, 13, 0); + + ar7240_reg_wr(AR7240_GPIO_OUT, gpio); +} + +void all_led_off(void){ + unsigned int gpio; + + gpio = ar7240_reg_rd(AR7240_GPIO_OUT); + + // SYS LED (GPIO 14) and WLAN24 (GPIO 13) + SETBITVAL(gpio, 14, 1); + SETBITVAL(gpio, 13, 1); + + ar7240_reg_wr(AR7240_GPIO_OUT, gpio); +} + +// get button status +int reset_button_status(void){ + // RESET BUTTON is connected to GPIO 16 + if(ar7240_reg_rd(AR7240_GPIO_IN) & (1 << 16)){ + return 0; + } else { + return 1; + } +} + +void gpio_config(void){ + /* disable the CLK_OBS on GPIO_4 and set GPIO4 as input */ + ar7240_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 4)); + ar7240_reg_rmw_clear(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK); + ar7240_reg_rmw_set(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(0x80)); + ar7240_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 4)); +} + +void ath_set_tuning_caps(void){ + typedef struct { + u_int8_t pad[0x28]; + u_int8_t params_for_tuning_caps[2]; + u_int8_t featureEnable; + } __attribute__((__packed__)) ar9300_eeprom_t; + + ar9300_eeprom_t *eep = (ar9300_eeprom_t *)WLANCAL; + uint32_t val = 0; + + /* checking feature enable bit 6 and caldata is valid */ + if((eep->featureEnable & 0x40) && (eep->pad[0x0] != 0xff)){ + /* xtal_capin -bit 17:23 and xtag_capout -bit 24:30*/ + val = (eep->params_for_tuning_caps[0] & 0x7f) << 17; + val |= (eep->params_for_tuning_caps[0] & 0x7f) << 24; + } else { + /* default when no caldata available*/ + /* checking clock in bit 4 */ + if(ar7240_reg_rd(RST_BOOTSTRAP_ADDRESS) & 0x10){ + val = (0x1020 << 17); /*default 0x2040 for 40Mhz clock*/ + } else { + val = (0x2040 << 17); /*default 0x4080 for 25Mhz clock*/ + } + } + + val |= (ar7240_reg_rd(XTAL_ADDRESS) & (((1 << 17) - 1) | (1 << 31))); + ar7240_reg_wr(XTAL_ADDRESS, val); + + //prmsg("Setting 0xb8116290 to 0x%x\n", val); + return; +} + +int wasp_mem_config(void){ + unsigned int reg32; + + wasp_ddr_initial_config(CFG_DDR_REFRESH_VAL); + + /* Take WMAC out of reset */ + reg32 = ar7240_reg_rd(AR7240_RESET); + reg32 = reg32 & ~AR7240_RESET_WMAC; + + ar7240_reg_wr_nf(AR7240_RESET, reg32); + + /* Switching regulator settings */ + ar7240_reg_wr_nf(0x18116c40, 0x633c8176); /* AR_PHY_PMU1 */ + ar7240_reg_wr_nf(0x18116c44, 0x10380000); /* AR_PHY_PMU2 */ + + //wasp_usb_initial_config(); + + gpio_config(); + + /* Needed here not to mess with Ethernet clocks */ + ath_set_tuning_caps(); + + // return memory size + return(ar7240_ddr_find_size()); +} + +long int initdram(){ + return((long int)wasp_mem_config()); +} diff --git a/u-boot/board/ar7240/db12x/u-boot-bootstrap.lds b/u-boot/board/ar7240/db12x/u-boot-bootstrap.lds new file mode 100755 index 0000000..4b680e0 --- /dev/null +++ b/u-boot/board/ar7240/db12x/u-boot-bootstrap.lds @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start_bootstrap) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + . = ALIGN(16); + _gp = .; + __got_start_bootstrap = .; + .got : { *(.got) } + __got_end_bootstrap = .; + + + .sdata : { *(.sdata) } + + uboot_end_data_bootstrap = .; + num_got_entries = (__got_end_bootstrap - __got_start_bootstrap) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end_bootstrap = .; +} diff --git a/u-boot/board/ar7240/db12x/u-boot.lds b/u-boot/board/ar7240/db12x/u-boot.lds new file mode 100755 index 0000000..8ccdf20 --- /dev/null +++ b/u-boot/board/ar7240/db12x/u-boot.lds @@ -0,0 +1,43 @@ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + . = ALIGN(16); + _gp = .; + __got_start = .; + .got : { *(.got) } + __got_end = .; + + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/u-boot/common/Makefile b/u-boot/common/Makefile new file mode 100755 index 0000000..685b153 --- /dev/null +++ b/u-boot/common/Makefile @@ -0,0 +1,79 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libcommon.a + +AOBJS = + +COBJS = main.o \ + cmd_bootm.o \ + cmd_boot.o \ + cmd_flash.o \ + cmd_mem.o \ + cmd_custom.o \ + cmd_net.o \ + cmd_nvedit.o \ + command.o \ + console.o \ + devices.o \ + dlmalloc.o \ + environment.o \ + env_common.o \ + env_nowhere.o \ + exports.o \ + flash.o \ + lists.o \ + env_flash.o + +OBJS = $(AOBJS) $(COBJS) + +CPPFLAGS += -I.. + +ifeq ($(DUAL_FIRMWAREIMAGE_SUPPORT),1) +CFLAGS += -DCONFIG_DUALIMAGE_SUPPORT +OBJS += cmd_bdr.o +endif + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +environment.o: environment.c ../tools/envcrc + $(CC) $(AFLAGS) -Wa,--no-warn \ + -DENV_CRC=$(shell ../tools/envcrc) \ + -c -o $@ environment.c + +../tools/envcrc: + $(MAKE) -C ../tools + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/common/cmd_boot.c b/u-boot/common/cmd_boot.c new file mode 100755 index 0000000..ff1e64a --- /dev/null +++ b/u-boot/common/cmd_boot.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Misc boot support + */ +#include +#include +#include + +#if defined(CONFIG_I386) || defined(CONFIG_MIPS) +DECLARE_GLOBAL_DATA_PTR; +#endif + +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +U_BOOT_CMD(reset, 1, 0, do_reset, "perform RESET of the CPU\n", NULL); diff --git a/u-boot/common/cmd_bootm.c b/u-boot/common/cmd_bootm.c new file mode 100755 index 0000000..757f2f8 --- /dev/null +++ b/u-boot/common/cmd_bootm.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Boot support + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* cmd_boot.c */ +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* net.c */ +extern void eth_halt(void); + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) +#include +#endif + +/* + * Continue booting an OS image; caller already has: + * - copied image header to global variable `header' + * - checked header magic number, checksums (both header & image), + * - verified image architecture (PPC) and type (KERNEL or MULTI), + * - loaded (first part of) image to header load address, + * - disabled interrupts. + */ +extern void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +#ifdef CONFIG_SILENT_CONSOLE +static void fixup_silent_linux(void); +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IMI) +static int image_info(unsigned long addr); +#endif + +image_header_t header; +ulong load_addr = CFG_LOAD_ADDR; /* default load address */ + +#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) +void fake_image_header(image_header_t *hdr, tplink_image_header_t *tpl_hdr){ + memset(hdr, 0, sizeof(image_header_t)); + + /* Build new header */ + hdr->ih_magic = htonl(IH_MAGIC); + hdr->ih_hcrc = 0; + hdr->ih_time = 0; + hdr->ih_size = htonl(tpl_hdr->kernelLen); + hdr->ih_load = htonl(tpl_hdr->kernelTextAddr); + hdr->ih_ep = htonl(tpl_hdr->kernelEntryPoint); + hdr->ih_dcrc = 0; + hdr->ih_os = IH_OS_LINUX; + hdr->ih_arch = IH_CPU_MIPS; + hdr->ih_type = IH_TYPE_KERNEL; + hdr->ih_comp = IH_COMP_LZMA; + + strncpy((char *)hdr->ih_name, (char *)tpl_hdr->signiture_1, IH_NMLEN); +} +#endif /* if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) */ + +int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + ulong addr, data, len; + uint unc_len = CFG_BOOTM_LEN; + int i; + image_header_t *hdr = &header; +#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + tplink_image_header_t *fileTag; +#endif + + if(argc < 2){ + addr = load_addr; + } else { + addr = simple_strtoul(argv[1], NULL, 16); + } + + printf("Booting image at: 0x%08lX\n", addr); + +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + memmove(&header, (char *)addr, sizeof(image_header_t)); + print_image_hdr(hdr); + + data = addr + sizeof(image_header_t); +#else + fileTag = (tplink_image_header_t *)addr; + print_image_hdr(fileTag); + + fake_image_header(hdr, fileTag); + + data = addr + TAG_LEN; +#endif + + len = ntohl(hdr->ih_size); + + /* + * We have reached the point of no return: we are going to + * overwrite all exception vector code, so we cannot easily + * recover from any failures any more... + */ +#ifdef CONFIG_NETCONSOLE + /* + * Stop the ethernet stack if NetConsole could have + * left it up + */ + eth_halt(); +#endif + +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) + /* + * Flush everything, restore caches for linux + */ + //mips_cache_flush(); + //mips_icache_flush_ix(); + + /* XXX - this causes problems when booting from flash */ + /* dcache_disable(); */ +#endif + + /* case IH_COMP_LZMA:*/ + puts("Uncompressing kernel image... "); + + i = lzma_inflate((unsigned char *)data, len, (unsigned char*)ntohl(hdr->ih_load), (int *)&unc_len); + + if(i != LZMA_RESULT_OK){ + printf("## Error: LZMA error num: %d\n", i); + return(-1); + } + + puts("OK!\n"); + +#ifdef CONFIG_SILENT_CONSOLE + fixup_silent_linux(); +#endif + + do_bootm_linux(cmdtp, flag, argc, argv); + +#ifdef DEBUG + puts("\n## Error: control returned to monitor - resetting...\n"); + do_reset(cmdtp, flag, argc, argv); +#endif + + return(1); +} + +U_BOOT_CMD(bootm, 2, 1, do_bootm, "boot application image from memory\n", "[addr]\n" +"\t- boot application image stored in memory at address 'addr'\n"); + +#ifdef CONFIG_SILENT_CONSOLE +static void fixup_silent_linux(){ + char buf[256], *start, *end; + char *cmdline = getenv("bootargs"); + + /* Only fix cmdline when requested */ + if(!(gd->flags & GD_FLG_SILENT)){ + return; + } + +#ifdef DEBUG + printf("before silent fix-up: %s\n", cmdline); +#endif + + if(cmdline){ + if((start = strstr(cmdline, "console=")) != NULL){ + end = strchr(start, ' '); + strncpy(buf, cmdline, (start - cmdline + 8)); + if(end){ + strcpy(buf + (start - cmdline + 8), end); + } else { + buf[start - cmdline + 8] = '\0'; + } + } else { + strcpy(buf, cmdline); + strcat(buf, " console="); + } + } else { + strcpy(buf, "console="); + } + + setenv("bootargs", buf); + debug("after silent fix-up: %s\n", buf); +} +#endif /* CONFIG_SILENT_CONSOLE */ + +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) +static void print_type(image_header_t *hdr){ + char *os, *arch, *type, *comp; + + switch(hdr->ih_os){ + case IH_OS_INVALID: + os = "Invalid OS"; + break; + case IH_OS_NETBSD: + os = "NetBSD"; + break; + case IH_OS_LINUX: + os = "Linux"; + break; + case IH_OS_VXWORKS: + os = "VxWorks"; + break; + case IH_OS_QNX: + os = "QNX"; + break; + case IH_OS_U_BOOT: + os = "U-Boot"; + break; + case IH_OS_RTEMS: + os = "RTEMS"; + break; + default: + os = "Unknown OS"; + break; + } + + switch(hdr->ih_arch){ + case IH_CPU_INVALID: + arch = "Invalid CPU"; + break; + case IH_CPU_ALPHA: + arch = "Alpha"; + break; + case IH_CPU_ARM: + arch = "ARM"; + break; + case IH_CPU_I386: + arch = "Intel x86"; + break; + case IH_CPU_IA64: + arch = "IA64"; + break; + case IH_CPU_MIPS: + arch = "MIPS"; + break; + case IH_CPU_MIPS64: + arch = "MIPS 64 Bit"; + break; + case IH_CPU_PPC: + arch = "PowerPC"; + break; + case IH_CPU_S390: + arch = "IBM S390"; + break; + case IH_CPU_SH: + arch = "SuperH"; + break; + case IH_CPU_SPARC: + arch = "SPARC"; + break; + case IH_CPU_SPARC64: + arch = "SPARC 64 Bit"; + break; + case IH_CPU_M68K: + arch = "M68K"; + break; + case IH_CPU_MICROBLAZE: + arch = "Microblaze"; + break; + case IH_CPU_NIOS: + arch = "Nios"; + break; + case IH_CPU_NIOS2: + arch = "Nios-II"; + break; + default: + arch = "Unknown Architecture"; + break; + } + + switch(hdr->ih_type){ + case IH_TYPE_INVALID: + type = "Invalid Image"; + break; + case IH_TYPE_STANDALONE: + type = "Standalone Program"; + break; + case IH_TYPE_KERNEL: + type = "Kernel Image"; + break; + case IH_TYPE_RAMDISK: + type = "RAMDisk Image"; + break; + case IH_TYPE_MULTI: + type = "Multi-File Image"; + break; + case IH_TYPE_FIRMWARE: + type = "Firmware"; + break; + case IH_TYPE_SCRIPT: + type = "Script"; + break; + default: + type = "Unknown Image"; + break; + } + + switch(hdr->ih_comp){ + case IH_COMP_NONE: + comp = "uncompressed"; + break; + case IH_COMP_GZIP: + comp = "gzip compressed"; + break; + case IH_COMP_BZIP2: + comp = "bzip2 compressed"; + break; + case IH_COMP_LZMA: + comp = "lzma compressed"; + break; + default: + comp = "unknown compression"; + break; + } + + printf("%s %s %s (%s)", arch, os, type, comp); +} + +void print_image_hdr(image_header_t *hdr){ +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) + time_t timestamp = (time_t)ntohl(hdr->ih_time); + struct rtc_time tm; +#endif + + printf("\n Image name: %.*s\n", IH_NMLEN, hdr->ih_name); + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) + to_tm(timestamp, &tm); + printf(" Created: %4d-%02d-%02d %2d:%02d:%02d UTC\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); +#endif /* CFG_CMD_DATE, CONFIG_TIMESTAMP */ + + puts(" Image type: "); + print_type(hdr); + + printf("\n Data size: %d Bytes = ", ntohl(hdr->ih_size)); + print_size(ntohl(hdr->ih_size), "\n"); + + printf(" Load address: %08X\n Entry point: %08X\n", ntohl(hdr->ih_load), ntohl(hdr->ih_ep)); + + if(hdr->ih_type == IH_TYPE_MULTI){ + int i; + ulong len; + ulong *len_ptr = (ulong *)((ulong)hdr + sizeof(image_header_t)); + + puts(" Contents:\n"); + + for(i = 0; (len = ntohl(*len_ptr)); ++i, ++len_ptr){ + printf(" Image %d: %8ld Bytes = ", i, len); + print_size(len, "\n"); + } + } + + puts("\n"); +} +#else +void print_image_hdr(tplink_image_header_t *hdr){ + printf("\n Image name: %.*s %.*s\n", SIG_LEN, hdr->signiture_1, SIG_LEN_2, hdr->signiture_2); + puts(" Image type: MIPS Linux Kernel Image (lzma compressed)\n"); + printf(" Data size: %d Bytes = ", ntohl(hdr->kernelLen)); + print_size(ntohl(hdr->kernelLen), "\n"); + printf(" Load address: 0x%08X\n Entry point: 0x%08X\n\n", ntohl(hdr->kernelTextAddr), ntohl(hdr->kernelEntryPoint)); +} +#endif /* defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) */ + +#if (CONFIG_COMMANDS & CFG_CMD_IMI) +int do_iminfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + ulong addr; + int rcode = 0; + + if (argc == 2){ + addr = simple_strtoul(argv[1], NULL, 16); + return image_info(addr); + } else { +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + return(rcode); +} + +static int image_info(ulong addr){ + ulong data, len, checksum; + image_header_t *hdr = &header; + + printf("\nChecking image at 0x%08lX...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ + memmove(&header, (char *)addr, sizeof(image_header_t)); + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if(crc32(0, (uchar *)data, len) != checksum){ + puts("## Error: bad header checksum!\n"); + return 1; + } + + /* for multi-file images we need the data part, too */ + print_image_hdr((image_header_t *)addr); + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + puts(" Verifying checksum... "); + + if(crc32(0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)){ + puts("bad data CRC!\n"); + return(1); + } + + puts("OK!\n\n"); + + return(0); +} + +U_BOOT_CMD(iminfo, 2, 1, do_iminfo, "print firmware header\n", "address\n" + "\t- print header information for firmware image startting at address 'address'\n" +); + +#endif /* CFG_CMD_IMI */ diff --git a/u-boot/common/cmd_custom.c b/u-boot/common/cmd_custom.c new file mode 100755 index 0000000..20189bb --- /dev/null +++ b/u-boot/common/cmd_custom.c @@ -0,0 +1,214 @@ +/* + * (C) Copyright 2013 + * Piotr Dymacz (pepe2k), Real Time Systems, piotr@realtimesystems.pl, pepe2k@gmail.com + * Custom commands for TP-Link U-Boot 1.1.4 modification. + * + * See file CREDITS for list of people who contributed to U-Boot project. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#if defined(OFFSET_MAC_ADDRESS) +/* + * Show MAC address(es) + */ +int do_print_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + char buffer[6]; +#ifdef OFFSET_MAC_ADDRESS2 + char buffer2[6]; +#endif + +#ifdef OFFSET_MAC_ADDRESS2 + // get MAC1 and MAC2 addresses from flash and print them + memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6); + memcpy(buffer2, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS2), 6); + + puts("Current MAC addresses stored in flash:\n"); + printf("MAC1 at 0x%X: %02X:%02X:%02X:%02X:%02X:%02X\n", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS, + buffer[0] & 0xFF, buffer[1] & 0xFF, buffer[2] & 0xFF, buffer[3] & 0xFF, buffer[4] & 0xFF, buffer[5] & 0xFF); + + printf("MAC2 at 0x%X: %02X:%02X:%02X:%02X:%02X:%02X\n\n", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS2, + buffer2[0] & 0xFF, buffer2[1] & 0xFF, buffer2[2] & 0xFF, buffer2[3] & 0xFF, buffer2[4] & 0xFF, buffer2[5] & 0xFF); +#else + // get MAC address from flash and print it + memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6); + + printf("Current MAC address stored in flash at offset 0x%X: ", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS); + printf("%02X:%02X:%02X:%02X:%02X:%02X\n\n", buffer[0] & 0xFF, buffer[1] & 0xFF, buffer[2] & 0xFF, buffer[3] & 0xFF, buffer[4] & 0xFF, buffer[5] & 0xFF); +#endif + + return(0); +} + +U_BOOT_CMD(printmac, 1, 1, do_print_mac, "print MAC address(es) stored in flash\n", NULL); + +/* + * Change MAC address(es) + */ +int do_set_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + unsigned char *data_pointer; + char buf[128]; + int i = 0, j = 0; + + // allow only 2 arg (command name + mac), second argument length should be 17 (xx:xx:xx:xx:xx:xx) + if(argc != 2 || strlen(argv[1]) != 17){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + // count ':' + for(i = 0; i< 17; i++){ + if(argv[1][i] == ':'){ + j++; + } + } + + if(j != 5){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + // backup block with MAC address from flash in RAM + data_pointer = (unsigned char *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS; + + if(!data_pointer){ + printf("## Error: couldn't allocate RAM for data block backup!\n"); + return(1); + } + + memcpy((void *)data_pointer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), OFFSET_MAC_DATA_BLOCK_LENGTH); + + // store new MAC address in RAM + for(i = 0; i < 6; i++){ + data_pointer[OFFSET_MAC_ADDRESS + i] = simple_strtoul((char *)(argv[1] + i*3), NULL, 16); + } + + // now we can erase flash and write data from RAM + sprintf(buf, + "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", + CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK, + OFFSET_MAC_DATA_BLOCK_LENGTH, + WEBFAILSAFE_UPLOAD_RAM_ADDRESS, + CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK, + OFFSET_MAC_DATA_BLOCK_LENGTH); + + printf("Executing: %s\n\n", buf); + + return(run_command(buf, 0)); +} + +U_BOOT_CMD(setmac, 2, 0, do_set_mac, "save new MAC address in flash\n", "xx:xx:xx:xx:xx:xx\n\t- change MAC address stored in flash (xx - value in hex format)\n"); + +#endif /* if defined(OFFSET_MAC_ADDRESS) */ + +#if defined(OFFSET_ROUTER_MODEL) +/* + * Show TP-Link router model + */ +int do_print_model(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + unsigned char buffer[8]; + + // get router model from flash and print it + memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_ROUTER_MODEL), 8); + + printf("Router model stored in flash at offset 0x%X: ", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_ROUTER_MODEL); + printf("%02X%02X%02X%02X%02X%02X%02X%02X\n\n", buffer[0] & 0xFF, buffer[1] & 0xFF, buffer[2] & 0xFF, buffer[3] & 0xFF, buffer[4] & 0xFF, buffer[5] & 0xFF, buffer[6] & 0xFF, buffer[7] & 0xFF); + + return(0); +} + +U_BOOT_CMD(printmodel, 1, 1, do_print_model, "print router model stored in flash\n", NULL); + +#endif /* if defined(OFFSET_ROUTER_MODEL) */ + +#if defined(OFFSET_PIN_NUMBER) +/* + * Show pin number + */ +int do_print_pin(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + unsigned char buffer[9]; + + // get pin number from flash and print it + memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_PIN_NUMBER), 8); + buffer[8] = 0; + + printf("Router pin number stored in flash at offset 0x%X: ", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_PIN_NUMBER); + printf("%s\n\n", buffer); + + return(0); +} + +U_BOOT_CMD(printpin, 1, 1, do_print_pin, "print WPS pin stored in flash\n", NULL); + +#endif /* if defined(OFFSET_PIN_NUMBER) */ + +#if defined(CONFIG_NETCONSOLE) +/* + * Start NetConsole + */ +int do_start_nc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + return(run_command("setenv stdin nc;setenv stdout nc;setenv stderr nc;version;", 0)); +} + +U_BOOT_CMD(startnc, 1, 0, do_start_nc, "start net console\n", NULL); + +/* + * Start Serial Console + */ +int do_start_sc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + return(run_command("setenv stdin serial;setenv stdout serial;setenv stderr serial;version;", 0)); +} + +U_BOOT_CMD(startsc, 1, 0, do_start_sc, "start serial console\n", NULL); + +#endif /* if defined(CONFIG_NETCONSOLE) */ + +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) +/* + * Erase environment sector + */ +int do_erase_env(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + char buf[64]; + + sprintf(buf, + "erase 0x%lX +0x%lX", + CFG_ENV_ADDR, + CFG_ENV_SIZE); + + printf("Executing: %s\n\n", buf); + + return(run_command(buf, 0)); +} + +U_BOOT_CMD(eraseenv, 1, 1, do_erase_env, "erase environment sector in flash\n", NULL); +#endif /* if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) */ diff --git a/u-boot/common/cmd_flash.c b/u-boot/common/cmd_flash.c new file mode 100755 index 0000000..29dbaf0 --- /dev/null +++ b/u-boot/common/cmd_flash.c @@ -0,0 +1,594 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * FLASH support + */ +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +/* + * The user interface starts numbering for Flash banks with 1 + * for historical reasons. + */ + +/* + * this routine looks for an abbreviated flash range specification. + * the syntax is B:SF[-SL], where B is the bank number, SF is the first + * sector to erase, and SL is the last sector to erase (defaults to SF). + * bank numbers start at 1 to be consistent with other specs, sector numbers + * start at zero. + * + * returns: 1 - correct spec; *pinfo, *psf and *psl are + * set appropriately + * 0 - doesn't look like an abbreviated spec + * -1 - looks like an abbreviated spec, but got + * a parsing error, a number out of range, + * or an invalid flash bank. + */ +static int abbrev_spec(char *str, flash_info_t ** pinfo, int *psf, int *psl){ + flash_info_t *fp; + int bank, first, last; + char *p, *ep; + + if((p = strchr(str, ':')) == NULL){ + return(0); + } + + *p++ = '\0'; + + bank = simple_strtoul(str, &ep, 10); + + if(ep == str || *ep != '\0' || bank < 1 || bank > CFG_MAX_FLASH_BANKS || (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN){ + return(-1); + } + + str = p; + + if((p = strchr(str, '-')) != NULL){ + *p++ = '\0'; + } + + first = simple_strtoul(str, &ep, 10); + + if(ep == str || *ep != '\0' || first >= fp->sector_count){ + return(-1); + } + + if(p != NULL){ + last = simple_strtoul(p, &ep, 10); + + if(ep == p || *ep != '\0' || last < first || last >= fp->sector_count){ + return(-1); + } + } else { + last = first; + } + + *pinfo = fp; + *psf = first; + *psl = last; + + return(1); +} + +/* + * This function computes the start and end addresses for both + * erase and protect commands. The range of the addresses on which + * either of the commands is to operate can be given in two forms: + * 1. start end - operate on <'start', 'end') + * 2. start +length - operate on <'start', start + length) + * If the second form is used and the end address doesn't fall on the + * sector boundary, than it will be adjusted to the next sector boundary. + * If it isn't in the flash, the function will fail (return -1). + * Input: + * arg1, arg2: address specification (i.e. both command arguments) + * Output: + * addr_first, addr_last: computed address range + * Return: + * 1: success + * -1: failure (bad format, bad address). + */ +static int addr_spec(char *arg1, char *arg2, ulong *addr_first, ulong *addr_last){ + char len_used = 0; /* indicates if the "start +length" form used */ + char *ep; + + *addr_first = simple_strtoul(arg1, &ep, 16); + + if(ep == arg1 || *ep != '\0'){ + return(-1); + } + + if(arg2 && *arg2 == '+'){ + len_used = 1; + ++arg2; + } + + *addr_last = simple_strtoul(arg2, &ep, 16); + + if(ep == arg2 || *ep != '\0'){ + return(-1); + } + + if(len_used){ + char found = 0; + ulong bank; + + /* + * *addr_last has the length, compute correct *addr_last + * XXX watch out for the integer overflow! Right now it is + * checked for in both the callers. + */ + *addr_last = *addr_first + *addr_last - 1; + + /* + * It may happen that *addr_last doesn't fall on the sector + * boundary. We want to round such an address to the next + * sector boundary, so that the commands don't fail later on. + */ + + /* find the end addr of the sector where the *addr_last is */ + for(bank = 0; bank < CFG_MAX_FLASH_BANKS && !found; ++bank){ + int i; + flash_info_t *info = &flash_info[bank]; + + for(i = 0; i < info->sector_count && !found; ++i){ + /* get the end address of the sector */ + ulong sector_end_addr; + + if(i == info->sector_count - 1){ + sector_end_addr = info->start[0] + info->size - 1; + } else { + sector_end_addr = info->start[i + 1] - 1; + } + + if(*addr_last <= sector_end_addr && *addr_last >= info->start[i]){ + /* sector found */ + found = 1; + + /* adjust *addr_last if necessary */ + if(*addr_last < sector_end_addr){ + *addr_last = sector_end_addr; + } + } + } /* sector */ + } /* bank */ + + if(!found){ + /* error, addres not in flash */ + printf("## Error: end address (0x%08lx) not in flash!\n", *addr_last); + return(-1); + } + + } /* "start +length" from used */ + + return(1); +} + +static int flash_fill_sect_ranges(ulong addr_first, ulong addr_last, int *s_first, int *s_last, int *s_count){ + flash_info_t *info; + ulong bank; + int rcode = 0; + + *s_count = 0; + + for(bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank){ + s_first[bank] = -1; /* first sector to erase */ + s_last[bank] = -1; /* last sector to erase */ + } + + for(bank = 0, info = &flash_info[0]; (bank < CFG_MAX_FLASH_BANKS) && (addr_first <= addr_last); ++bank, ++info){ + ulong b_end; + int sect; + short s_end; + + if(info->flash_id == FLASH_UNKNOWN){ + continue; + } + + b_end = info->start[0] + info->size - 1; /* bank end addr */ + s_end = info->sector_count - 1; /* last sector */ + + for(sect = 0; sect < info->sector_count; ++sect){ + ulong end; /* last address in current sect */ + + end = (sect == s_end) ? b_end : info->start[sect + 1] - 1; + + if(addr_first > end){ + continue; + } + + if(addr_last < info->start[sect]){ + continue; + } + + if(addr_first == info->start[sect]){ + s_first[bank] = sect; + } + + if(addr_last == end){ + s_last[bank] = sect; + } + } + + if(s_first[bank] >= 0){ + if(s_last[bank] < 0){ + if(addr_last > b_end){ + s_last[bank] = s_end; + } else { + puts("## Error: end address not on sector boundary\n"); + rcode = 1; + break; + } + } + + if(s_last[bank] < s_first[bank]){ + puts("## Error: end sector precedes start sector\n"); + rcode = 1; + break; + } + + sect = s_last[bank]; + addr_first = (sect == s_end) ? b_end + 1 : info->start[sect + 1]; + (*s_count) += s_last[bank] - s_first[bank] + 1; + } else if(addr_first >= info->start[0] && addr_first < b_end){ + puts("## Error: start address not on sector boundary\n"); + rcode = 1; + break; + } else if(s_last[bank] >= 0){ + puts("## Error: cannot span across banks when they are mapped in reverse order\n"); + rcode = 1; + break; + } + } + + return(rcode); +} + +int do_flerase(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + flash_info_t *info; + ulong bank, addr_first, addr_last; + int n, sect_first, sect_last; + int rcode = 0; + + if(argc < 2){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + // erase whole flash? + if(strcmp(argv[1], "all") == 0){ + for(bank = 1; bank <= CFG_MAX_FLASH_BANKS; ++bank){ + printf("Erase flash bank #%ld ", bank); + info = &flash_info[bank - 1]; + rcode = flash_erase(info, 0, info->sector_count - 1); + } + return(rcode); + } + + if((n = abbrev_spec(argv[1], &info, §_first, §_last)) != 0){ + if(n < 0){ + puts("## Error: bad sector spec\n"); + return(1); + } + printf("Erase flash sectors %d-%d in bank #%d ", sect_first, sect_last, (info - flash_info) + 1); + rcode = flash_erase(info, sect_first, sect_last); + return(rcode); + } + + if(argc != 3){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + if(strcmp(argv[1], "bank") == 0){ + bank = simple_strtoul(argv[2], NULL, 16); + + if((bank < 1) || (bank > CFG_MAX_FLASH_BANKS)){ + printf("## Error: only flash banks #1...#%d supported\n", CFG_MAX_FLASH_BANKS); + return(1); + } + + printf("Erase flash bank #%ld ", bank); + info = &flash_info[bank - 1]; + rcode = flash_erase(info, 0, info->sector_count - 1); + return(rcode); + } + + if(addr_spec(argv[1], argv[2], &addr_first, &addr_last) < 0){ + printf("## Error: bad address format\n"); + return(1); + } + + if(addr_first >= addr_last){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + rcode = flash_sect_erase(addr_first, addr_last); + return(rcode); +} + +int flash_sect_erase(ulong addr_first, ulong addr_last){ + flash_info_t *info; + ulong bank; + int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS]; + int erased = 0; + int planned; + int rcode = 0; + + rcode = flash_fill_sect_ranges(addr_first, addr_last, s_first, s_last, &planned); + + if(planned && (rcode == 0)){ + for(bank = 0, info = &flash_info[0]; (bank < CFG_MAX_FLASH_BANKS) && (rcode == 0); ++bank, ++info){ + if(s_first[bank] >= 0){ + erased += s_last[bank] - s_first[bank] + 1; + printf("Erase flash from 0x%08lX to 0x%08lX in bank #%ld\n", info->start[s_first[bank]], (s_last[bank] == info->sector_count - 1) ? info->start[0] + info->size - 1 : info->start[s_last[bank] + 1] - 1, bank + 1); + rcode = flash_erase(info, s_first[bank], s_last[bank]); + } + } + printf("Erased sectors: %d\n\n", erased); + } else if(rcode == 0){ + puts("## Error: start and/or end address not on sector boundary\n"); + rcode = 1; + } + return(rcode); +} + +#ifndef COMPRESSED_UBOOT +#if 0 // we don't need do_protect cmd +int do_protect(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + flash_info_t *info; + ulong bank, addr_first, addr_last; + int i, p, n, sect_first, sect_last; + int rcode = 0; + + if(argc < 3){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + if(strcmp(argv[1], "off") == 0){ + p = 0; + } else if(strcmp(argv[1], "on") == 0){ + p = 1; + } else { +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + if(strcmp(argv[2], "all") == 0){ + for(bank=1; bank <= CFG_MAX_FLASH_BANKS; ++bank){ + info = &flash_info[bank-1]; + + if(info->flash_id == FLASH_UNKNOWN){ + continue; + } + + printf("%sProtecting flash bank #%ld\n", p ? "" : "Un-", bank); + + for(i = 0; i < info->sector_count; ++i){ + info->protect[i] = p; + } + } + + return(rcode); + } + + if((n = abbrev_spec(argv[2], &info, §_first, §_last)) != 0){ + if(n < 0){ + puts("## Error: bad sector spec\n"); + return(1); + } + + printf("%sProtecting flash sectors: %d-%d in bank #%d\n", p ? "" : "Un-", sect_first, sect_last, (info-flash_info)+1); + + for(i = sect_first; i <= sect_last; i++){ + info->protect[i] = p; + } + + return(rcode); + } + + if(argc != 4){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + if(strcmp(argv[2], "bank") == 0){ + bank = simple_strtoul(argv[3], NULL, 16); + + if((bank < 1) || (bank > CFG_MAX_FLASH_BANKS)){ + printf("## Error: only flash banks #1...#%d supported\n", CFG_MAX_FLASH_BANKS); + return(1); + } + + printf("%sProtecting flash bank #%ld\n", p ? "" : "Un-", bank); + info = &flash_info[bank-1]; + + if(info->flash_id == FLASH_UNKNOWN){ + puts("## Error: missing or unknown flash type\n"); + return(1); + } + + for(i=0; isector_count; ++i){ + info->protect[i] = p; + } + + return(rcode); + } + + if(addr_spec(argv[2], argv[3], &addr_first, &addr_last) < 0){ + printf("## Error: bad address format\n"); + return(1); + } + + if(addr_first >= addr_last){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + rcode = flash_sect_protect(p, addr_first, addr_last); + return(rcode); +} +#endif /* we don't need do_protect cmd */ + +int flash_sect_protect(int p, ulong addr_first, ulong addr_last){ + flash_info_t *info; + ulong bank; + int s_first[CFG_MAX_FLASH_BANKS], s_last[CFG_MAX_FLASH_BANKS]; + int protected, i; + int planned; + int rcode; + + rcode = flash_fill_sect_ranges( addr_first, addr_last, s_first, s_last, &planned ); + + protected = 0; + + if(planned && (rcode == 0)){ + for(bank=0,info=&flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info){ + if(info->flash_id == FLASH_UNKNOWN){ + continue; + } + + if(s_first[bank] >= 0 && s_first[bank] <= s_last[bank]){ + //debug("%sProtecting sectors %d..%d in bank %ld\n", p ? "" : "Un-", s_first[bank], s_last[bank], bank+1); + protected += s_last[bank] - s_first[bank] + 1; + + for(i=s_first[bank]; i<=s_last[bank]; ++i){ + info->protect[i] = p; + } + } + } + //debug("%sProtected %d sectors\n", p ? "" : "Un-", protected); + } else if(rcode == 0){ + puts("## Error: start and/or end address not on sector boundary\n"); + rcode = 1; + } + + return(rcode); +} +#endif /* ifndef COMPRESSED_UBOOT */ + +/**************************************************/ + +U_BOOT_CMD(erase, 3, 1, do_flerase, "erase FLASH memory\n", + "start end\n" + "\t- erase FLASH from addr 'start' to addr 'end'\n" + "erase start +len\n" + "\t- erase FLASH from addr 'start' to the end of sect w/addr 'start'+'len'-1\n" + "erase N:SF[-SL]\n" + "\t- erase sectors SF-SL in FLASH bank #N\n" + "erase bank N\n" + "\t- erase FLASH bank #N\n" + "erase all\n" + "\t- erase all FLASH banks\n"); + +#ifndef COMPRESSED_UBOOT +#if 0 // we don't need do_protect cmd +U_BOOT_CMD(protect, 4, 1, do_protect, "enable or disable FLASH write protection\n", + "start end\n" + "\t- protect FLASH from addr 'start' to addr 'end'\n" + "protect start +len\n" + "\t- protect FLASH from addr 'start' to end of sect w/addr 'start'+'len'-1\n" + "protect on N:SF[-SL]\n" + "\t- protect sectors SF-SL in FLASH bank #N\n" + "protect on bank N\n" + "\t- protect FLASH bank #N\n" + "protect on all\n" + "\t- protect all FLASH banks\n" + "protect off start end\n" + "\t- make FLASH from addr 'start' to addr 'end' writable\n" + "protect off start +len\n" + "\t- make FLASH from addr 'start' to end of sect w/addr 'start'+'len'-1 writable\n" + "protect off N:SF[-SL]\n" + "\t- make sectors SF-SL writable in FLASH bank #N\n" + "protect off bank N\n" + "\t- make FLASH bank #N writable\n" + "protect off all\n" + "\t- make all FLASH banks writable\n" +); +#endif /* we don't need do_protect cmd */ +#endif /* ifndef COMPRESSED_UBOOT */ + +#endif /* CFG_CMD_FLASH */ diff --git a/u-boot/common/cmd_mem.c b/u-boot/common/cmd_mem.c new file mode 100755 index 0000000..487b3bb --- /dev/null +++ b/u-boot/common/cmd_mem.c @@ -0,0 +1,715 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Memory Functions + * + * Copied from FADS ROM, Dan Malek (dmalek@jlc.net) + */ + +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_MMC) +#include +#endif + +#if (CONFIG_COMMANDS & (CFG_CMD_MEMORY | \ + CFG_CMD_ITEST | \ + CFG_CMD_PCI | \ + CMD_CMD_PORTIO) ) +/* + * Check for a size specification .b, .w or .l. + */ +int cmd_get_data_size(char* arg, int default_size){ + int len = strlen(arg); + + if(len > 2 && arg[len - 2] == '.'){ + switch(arg[len - 1]){ + case 'b': + return(1); + case 'w': + return(2); + case 'l': + return(4); + case 's': + return(-2); + default: + return(-1); + } + } + + return(default_size); +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_MEMORY) + +static int mod_mem(cmd_tbl_t *, int, int, int, char *[]); + +/* + * Display values from last command. + * Memory modify remembered values are different from display memory. + */ +uint dp_last_addr, dp_last_size; +uint dp_last_length = 0x40; +uint mm_last_addr, mm_last_size; + +/* + * Memory Display + * + * Syntax: + * md{.b, .w, .l} {addr} {len} + */ +#define DISP_LINE_LEN 16 +int do_mem_md(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + ulong addr, length; + ulong i, nbytes, linebytes; + u_char *cp; + int size; + int rc = 0; + + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + addr = dp_last_addr; + size = dp_last_size; + length = dp_last_length; + + if(argc < 2){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + if((flag & CMD_FLAG_REPEAT) == 0){ + /* + * New command specified. Check for a size specification. + * Defaults to long if no or incorrect specification. + */ + if((size = cmd_get_data_size(argv[0], 4)) < 0){ + return(1); + } + + /* + * Address is specified since argc > 1 + */ + addr = simple_strtoul(argv[1], NULL, 16); + + /* + * If another parameter, it is the length to display. + * Length is the number of objects, not number of bytes. + */ + if(argc > 2){ + length = simple_strtoul(argv[2], NULL, 16); + } + } + + /* + * Print the lines. + * + * We buffer all read data, so we can make sure data is read only + * once, and all accesses are with the specified bus width. + */ + nbytes = length * size; + + do { + char linebuf[DISP_LINE_LEN]; + uint *uip = (uint *)linebuf; + ushort *usp = (ushort *)linebuf; + u_char *ucp = (u_char *)linebuf; + + printf("%08lX:", addr); + + linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; + + for(i = 0; i < linebytes; i += size){ + if(size == 4){ + printf(" %08X", (*uip++ = *((uint *)addr))); + } else if(size == 2){ + printf(" %04X", (*usp++ = *((ushort *)addr))); + } else { + printf(" %02X", (*ucp++ = *((u_char *)addr))); + } + addr += size; + } + + puts(" "); + cp = (u_char *)linebuf; + + for(i = 0; i < linebytes; i++){ + if((*cp < 0x20) || (*cp > 0x7e)){ + putc('.'); + } else { + printf("%c", *cp); + } + cp++; + } + + putc('\n'); + nbytes -= linebytes; + + if(ctrlc()){ + rc = 1; + break; + } + + } while(nbytes > 0); + + dp_last_addr = addr; + dp_last_length = length; + dp_last_size = size; + + return(rc); +} + +int do_mem_mm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + return(mod_mem(cmdtp, 1, flag, argc, argv)); +} +int do_mem_nm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + return(mod_mem(cmdtp, 0, flag, argc, argv)); +} + +int do_mem_mw(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + ulong addr, writeval, count; + int size; + + if((argc < 3) || (argc > 4)){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + /* + * Check for size specification. + */ + if((size = cmd_get_data_size(argv[0], 4)) < 1){ + return(1); + } + + /* + * Address is specified since argc > 1 + */ + addr = simple_strtoul(argv[1], NULL, 16); + + /* + * Get the value to write. + */ + writeval = simple_strtoul(argv[2], NULL, 16); + + /* Count ? */ + if(argc == 4){ + count = simple_strtoul(argv[3], NULL, 16); + } else { + count = 1; + } + + while(count-- > 0){ + if(size == 4){ + *((ulong *)addr) = (ulong)writeval; + } else if(size == 2){ + *((ushort *)addr) = (ushort)writeval; + } else { + *((u_char *)addr) = (u_char)writeval; + } + addr += size; + } + + return(0); +} + +int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + ulong addr, dest, count; + int size; + + if(argc != 4){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + /* + * Check for size specification. + */ + if((size = cmd_get_data_size(argv[0], 4)) < 0){ + return(1); + } + + addr = simple_strtoul(argv[1], NULL, 16); + dest = simple_strtoul(argv[2], NULL, 16); + count = simple_strtoul(argv[3], NULL, 16); + + if(count == 0){ + puts("## Error: zero length?\n"); + return(1); + } + +#ifndef CFG_NO_FLASH + /* check if we are copying to Flash */ + if(addr2info(dest) != NULL){ + int rc; + + puts("Copying to flash...\n"); + + rc = flash_write((char *)addr, dest, count * size); + + if(rc != 0){ + flash_perror(rc); + return(1); + } + + puts("Done!\n\n"); + return(0); + } +#endif + + while(count-- > 0){ + if(size == 4){ + *((ulong *)dest) = *((ulong *)addr); + } else if(size == 2){ + *((ushort *)dest) = *((ushort *)addr); + } else { + *((u_char *)dest) = *((u_char *)addr); + } + addr += size; + dest += size; + } + + return(0); +} + +/* + * Perform a memory test. A more complete alternative test can be + * configured using CFG_ALT_MEMTEST. The complete test loops until + * interrupted by ctrl-c or by a failure of one of the sub-tests. + */ +int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + vu_long *addr, *start, *end; + ulong val; + ulong readback; + +#if defined(CFG_ALT_MEMTEST) + vu_long addr_mask; + vu_long offset; + vu_long test_offset; + vu_long pattern; + vu_long temp; + vu_long anti_pattern; + vu_long num_words; +#if defined(CFG_MEMTEST_SCRATCH) + vu_long *dummy = (vu_long*)CFG_MEMTEST_SCRATCH; +#else + vu_long *dummy = NULL; +#endif + int j; + int iterations = 1; + + static const ulong bitpattern[] = { + 0x00000001, /* single bit */ + 0x00000003, /* two adjacent bits */ + 0x00000007, /* three adjacent bits */ + 0x0000000F, /* four adjacent bits */ + 0x00000005, /* two non-adjacent bits */ + 0x00000015, /* three non-adjacent bits */ + 0x00000055, /* four non-adjacent bits */ + 0xaaaaaaaa, /* alternating 1/0 */ + }; +#else + ulong incr; + ulong pattern; + int rcode = 0; +#endif + + if(argc > 1){ + start = (ulong *)simple_strtoul(argv[1], NULL, 16); + } else { + start = (ulong *)CFG_MEMTEST_START; + } + + if(argc > 2){ + end = (ulong *)simple_strtoul(argv[2], NULL, 16); + } else { + end = (ulong *)(CFG_MEMTEST_END); + } + + if(argc > 3){ + pattern = (ulong)simple_strtoul(argv[3], NULL, 16); + } else { + pattern = 0; + } + +#if defined(CFG_ALT_MEMTEST) + printf("Testing RAM 0x%08X...0x%08X:\n", (uint)start, (uint)end); + + for(;;){ + if(ctrlc()){ + putc('\n'); + return(1); + } + + printf("Iteration: %6d\r", iterations); + + iterations++; + + /* + * Data line test: write a pattern to the first + * location, write the 1's complement to a 'parking' + * address (changes the state of the data bus so a + * floating bus doen't give a false OK), and then + * read the value back. Note that we read it back + * into a variable because the next time we read it, + * it might be right (been there, tough to explain to + * the quality guys why it prints a failure when the + * "is" and "should be" are obviously the same in the + * error message). + * + * Rather than exhaustively testing, we test some + * patterns by shifting '1' bits through a field of + * '0's and '0' bits through a field of '1's (i.e. + * pattern and ~pattern). + */ + addr = start; + + for(j = 0; j < sizeof(bitpattern)/sizeof(bitpattern[0]); j++){ + val = bitpattern[j]; + + for(; val != 0; val <<= 1){ + *addr = val; + *dummy = ~val; /* clear the test data off of the bus */ + readback = *addr; + + if(readback != val){ + printf("## Error (data line): expected 0x%08lX, found 0x%08lX\n", val, readback); + } + + *addr = ~val; + *dummy = val; + readback = *addr; + + if(readback != ~val){ + printf("## Error (data line): expected %08lX, found %08lX\n", ~val, readback); + } + } + } + + /* + * Based on code whose Original Author and Copyright + * information follows: Copyright (c) 1998 by Michael + * Barr. This software is placed into the public + * domain and may be used for any purpose. However, + * this notice must not be changed or removed and no + * warranty is either expressed or implied by its + * publication or distribution. + */ + + /* + * Address line test + * + * Description: Test the address bus wiring in a + * memory region by performing a walking + * 1's test on the relevant bits of the + * address and checking for aliasing. + * This test will find single-bit + * address failures such as stuck -high, + * stuck-low, and shorted pins. The base + * address and size of the region are + * selected by the caller. + * + * Notes: For best results, the selected base + * address should have enough LSB 0's to + * guarantee single address bit changes. + * For example, to test a 64-Kbyte + * region, select a base address on a + * 64-Kbyte boundary. Also, select the + * region size as a power-of-two if at + * all possible. + * + * Returns: 0 if the test succeeds, 1 if the test fails. + * + * ## NOTE ## Be sure to specify start and end + * addresses such that addr_mask has + * lots of bits set. For example an + * address range of 01000000 02000000 is + * bad while a range of 01000000 + * 01ffffff is perfect. + */ + addr_mask = ((ulong)end - (ulong)start)/sizeof(vu_long); + pattern = (vu_long)0xaaaaaaaa; + anti_pattern = (vu_long)0x55555555; + + /* + * Write the default pattern at each of the + * power-of-two offsets. + */ + for(offset = 1; (offset & addr_mask) != 0; offset <<= 1){ + start[offset] = pattern; + } + + /* + * Check for address bits stuck high. + */ + test_offset = 0; + start[test_offset] = anti_pattern; + + for(offset = 1; (offset & addr_mask) != 0; offset <<= 1){ + temp = start[offset]; + + if(temp != pattern){ + printf("\n## Error: address bit stuck high @ 0x%.8lX, expected 0x%.8lX, found 0x%.8lX\n", (ulong)&start[offset], pattern, temp); + return(1); + } + } + start[test_offset] = pattern; + + /* + * Check for addr bits stuck low or shorted. + */ + for(test_offset = 1; (test_offset & addr_mask) != 0; test_offset <<= 1){ + start[test_offset] = anti_pattern; + + for(offset = 1; (offset & addr_mask) != 0; offset <<= 1){ + temp = start[offset]; + + if((temp != pattern) && (offset != test_offset)){ + printf("\n## Error: address bit stuck low or shorted @ 0x%.8lX, expected 0x%.8lX, found 0x%.8lX\n", (ulong)&start[offset], pattern, temp); + return(1); + } + } + start[test_offset] = pattern; + } + + /* + * Description: Test the integrity of a physical + * memory device by performing an + * increment/decrement test over the + * entire region. In the process every + * storage bit in the device is tested + * as a zero and a one. The base address + * and the size of the region are + * selected by the caller. + * + * Returns: 0 if the test succeeds, 1 if the test fails. + */ + num_words = ((ulong)end - (ulong)start)/sizeof(vu_long) + 1; + + /* + * Fill memory with a known pattern. + */ + for(pattern = 1, offset = 0; offset < num_words; pattern++, offset++){ + start[offset] = pattern; + } + + /* + * Check each location and invert it for the second pass. + */ + for(pattern = 1, offset = 0; offset < num_words; pattern++, offset++){ + temp = start[offset]; + + if(temp != pattern){ + printf("\n## Error (read/write) @ 0x%.8lX: expected 0x%.8lX, found 0x%.8lX)\n", (ulong)&start[offset], pattern, temp); + return(1); + } + + anti_pattern = ~pattern; + start[offset] = anti_pattern; + } + + /* + * Check each location for the inverted pattern and zero it. + */ + for(pattern = 1, offset = 0; offset < num_words; pattern++, offset++){ + anti_pattern = ~pattern; + temp = start[offset]; + + if(temp != anti_pattern){ + printf("\n## Error (read/write): @ 0x%.8lX: expected 0x%.8lX, found 0x%.8lX)\n", (ulong)&start[offset], anti_pattern, temp); + return(1); + } + start[offset] = 0; + } + } + +#else /* The original, quickie test */ + incr = 1; + for(;;){ + if(ctrlc()){ + putc('\n'); + return(1); + } + + printf("\rPattern %08lX Writing...%12s\b\b\b\b\b\b\b\b\b\b", pattern, ""); + + for(addr = start, val = pattern; addr < end; addr++){ + *addr = val; + val += incr; + } + + puts("Reading..."); + + for(addr = start, val = pattern; addr < end; addr++){ + readback = *addr; + if(readback != val){ + printf("\n## Error @ 0x%08X: found %08lX, expected %08lX\n", (uint)addr, readback, val); + rcode = 1; + } + val += incr; + } + + /* + * Flip the pattern each time to make lots of zeros and + * then, the next time, lots of ones. We decrement + * the "negative" patterns and increment the "positive" + * patterns to preserve this feature. + */ + if(pattern & 0x80000000){ + pattern = -pattern; /* complement & increment */ + } else { + pattern = ~pattern; + } + incr = -incr; + } + return(rcode); +#endif +} + +/* Modify memory. + * + * Syntax: + * mm{.b, .w, .l} {addr} + * nm{.b, .w, .l} {addr} + */ +static int mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]){ + ulong addr, i; + int nbytes, size; + extern char console_buffer[]; + + if(argc != 2){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + /* We use the last specified parameters, unless new ones are + * entered. + */ + addr = mm_last_addr; + size = mm_last_size; + + if((flag & CMD_FLAG_REPEAT) == 0){ + /* New command specified. Check for a size specification. + * Defaults to long if no or incorrect specification. + */ + if((size = cmd_get_data_size(argv[0], 4)) < 0){ + return(1); + } + + /* Address is specified since argc > 1 + */ + addr = simple_strtoul(argv[1], NULL, 16); + } + + /* Print the address, followed by value. Then accept input for + * the next value. A non-converted value exits. + */ + do { + printf("%08lX:", addr); + + if(size == 4){ + printf(" %08X", *((uint *)addr)); + } else if(size == 2){ + printf(" %04X", *((ushort *)addr)); + } else{ + printf(" %02X", *((u_char *)addr)); + } + + nbytes = readline(" ? "); + if(nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')){ + /* pressed as only input, don't modify current + * location and move to next. "-" pressed will go back. + */ + if(incrflag){ + addr += nbytes ? -size : size; + } + nbytes = 1; + } else { + char *endp; + i = simple_strtoul(console_buffer, &endp, 16); + nbytes = endp - console_buffer; + if(nbytes){ + if(size == 4){ + *((uint *)addr) = i; + } else if(size == 2){ + *((ushort *)addr) = i; + } else { + *((u_char *)addr) = i; + } + if(incrflag){ + addr += size; + } + } + } + } while(nbytes); + + mm_last_addr = addr; + mm_last_size = size; + + return(0); +} + +/**************************************************/ +U_BOOT_CMD(md, 3, 1, do_mem_md, "memory display\n", "[.b, .w, .l] address [# of objects]\n\t- memory display\n"); +U_BOOT_CMD(mm, 2, 1, do_mem_mm, "memory modify (auto-incrementing)\n", "[.b, .w, .l] address\n\t- memory modify, auto increment address\n"); +U_BOOT_CMD(nm, 2, 1, do_mem_nm, "memory modify (constant address)\n", "[.b, .w, .l] address\n\t- memory modify, read and keep address\n"); +U_BOOT_CMD(mw, 4, 1, do_mem_mw, "memory write (fill)\n", "[.b, .w, .l] address value [count]\n\t- write memory\n"); +U_BOOT_CMD(mtest, 4, 1, do_mem_mtest, "simple RAM test\n", "[start [end [pattern]]]\n\t- simple RAM read/write test\n"); +U_BOOT_CMD(cp, 4, 1, do_mem_cp, "memory copy\n", "[.b, .w, .l] source target count\n\t- copy memory\n"); + +#endif /* CFG_CMD_MEMORY */ diff --git a/u-boot/common/cmd_net.c b/u-boot/common/cmd_net.c new file mode 100755 index 0000000..098abed --- /dev/null +++ b/u-boot/common/cmd_net.c @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Boot support + */ +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +extern int do_bootm(cmd_tbl_t *, int, int, char *[]); +static int netboot_common(proto_t, cmd_tbl_t *, int, char *[]); + +int do_httpd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + return NetLoopHttpd(); +} +U_BOOT_CMD(httpd, 1, 1, do_httpd, "start www server for firmware recovery\n", NULL); + +int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + return netboot_common(TFTP, cmdtp, argc, argv); +} +U_BOOT_CMD(tftpboot, 3, 1, do_tftpb, "boot image via network using TFTP protocol\n", "[loadAddress] [bootfilename]\n"); + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +int do_dhcp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + return netboot_common(DHCP, cmdtp, argc, argv); +} +U_BOOT_CMD(dhcp, 3, 1, do_dhcp, "invoke DHCP client to obtain IP/boot params\n", NULL); +#endif /* CFG_CMD_DHCP */ + +#if (CONFIG_COMMANDS & CFG_CMD_NFS) +int do_nfs(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + return netboot_common(NFS, cmdtp, argc, argv); +} +U_BOOT_CMD(nfs, 3, 1, do_nfs, "boot image via network using NFS protocol\n", "[loadAddress] [host ip addr:bootfilename]\n"); +#endif /* CFG_CMD_NFS */ + +static void netboot_update_env(void){ + char tmp[22]; + + if(NetOurGatewayIP){ + ip_to_string(NetOurGatewayIP, tmp); + setenv("gatewayip", tmp); + } + + if(NetOurSubnetMask){ + ip_to_string(NetOurSubnetMask, tmp); + setenv("netmask", tmp); + } + + if(NetOurHostName[0]){ + setenv("hostname", NetOurHostName); + } + + if(NetOurRootPath[0]){ + setenv("rootpath", NetOurRootPath); + } + + if(NetOurIP){ + ip_to_string(NetOurIP, tmp); + setenv("ipaddr", tmp); + } + + if(NetServerIP){ + ip_to_string(NetServerIP, tmp); + setenv("serverip", tmp); + } + + if(NetOurDNSIP){ + ip_to_string(NetOurDNSIP, tmp); + setenv("dnsip", tmp); + } + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) + if(NetOurDNS2IP){ + ip_to_string (NetOurDNS2IP, tmp); + setenv("dnsip2", tmp); + } +#endif + + if(NetOurNISDomain[0]){ + setenv("domain", NetOurNISDomain); + } + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) + if(NetTimeOffset){ + sprintf(tmp, "%d", NetTimeOffset); + setenv("timeoffset", tmp); + } +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) + if (NetNtpServerIP){ + ip_to_string(NetNtpServerIP, tmp); + setenv("ntpserverip", tmp); + } +#endif +} + +static int netboot_common(proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]){ + char *s; + int rcode = 0; + int size; + + /* pre-set load_addr */ + if((s = getenv("loadaddr")) != NULL){ + load_addr = simple_strtoul(s, NULL, 16); + } + + switch(argc){ + case 1: + break; + + case 2: + /* only one arg - accept two forms: + * just load address, or just boot file name. + * The latter form must be written "filename" here. + */ + if(argv[1][0] == '"'){ /* just boot filename */ + copy_filename(BootFile, argv[1], sizeof(BootFile)); + } else { /* load address */ + load_addr = simple_strtoul(argv[1], NULL, 16); + } + + break; + + case 3: + load_addr = simple_strtoul(argv[1], NULL, 16); + copy_filename(BootFile, argv[2], sizeof(BootFile)); + + break; + + default: + +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return 1; + } + + if((size = NetLoop(proto)) < 0){ + return(1); + } + + /* NetLoop ok, update environment */ + netboot_update_env(); + + /* done if no file was loaded (no errors though) */ + if(size == 0){ + return(0); + } + + /* flush cache */ + flush_cache(load_addr, size); + + /* Loading ok, check if we should attempt an auto-start */ + if(((s = getenv("autostart")) != NULL) && (strcmp(s, "yes") == 0)){ + char *local_args[2]; + local_args[0] = argv[0]; + local_args[1] = NULL; + + printf("Automatic boot of image at addr 0x%08lX ...\n", load_addr); + rcode = do_bootm(cmdtp, 0, 1, local_args); + } + +#ifdef CONFIG_AUTOSCRIPT + if(((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)){ + printf("Running autoscript at addr 0x%08lX ...\n", load_addr); + rcode = autoscript(load_addr); + } +#endif + return rcode; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PING) +int do_ping(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + + if(argc < 2){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(-1); + } + + NetPingIP = string_to_ip(argv[1]); + + if (NetPingIP == 0){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(-1); + } + + if(NetLoop(PING) < 0){ + printf("\n## Error: ping failed, host %s is not alive!\n\n", argv[1]); + return(1); + } + + printf("\nPing OK, host %s is alive!\n\n", argv[1]); + + return(0); +} + +U_BOOT_CMD(ping, 2, 1, do_ping, "send ICMP ECHO_REQUEST to network host\n", "host IP\n" + "\t- sends ping to IP 'host IP'\n"); +#endif /* CFG_CMD_PING */ + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +int do_sntp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + char *toff; + + if(argc < 2){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(-1); + } else { + NetNtpServerIP = string_to_ip(argv[1]); + if(NetNtpServerIP == 0){ + printf("## Error: bad SNTP server IP address\n"); + return(1); + } + } + + toff = getenv("timeoffset"); + + if(toff == NULL){ + NetTimeOffset = 0; + } else{ + NetTimeOffset = simple_strtol(toff, NULL, 10); + } + + if(NetLoop(SNTP) < 0){ + printf("## Error: SNTP host %s not responding\n", argv[1]); + return(1); + } + + return(0); +} + +U_BOOT_CMD(sntp, 2, 1, do_sntp, "send NTP request to NTP server\n", "ntpserverip\n" + "\t- sends NTP request to NTP server 'ntpserverip'\n"); +#endif /* CFG_CMD_SNTP */ + +#endif /* CFG_CMD_NET */ diff --git a/u-boot/common/cmd_nvedit.c b/u-boot/common/cmd_nvedit.c new file mode 100755 index 0000000..c70c608 --- /dev/null +++ b/u-boot/common/cmd_nvedit.c @@ -0,0 +1,631 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/************************************************************************** + * + * Support for persistent environment data + * + * The "environment" is stored as a list of '\0' terminated + * "name=value" strings. The end of the list is marked by a double + * '\0'. New entries are always added at the end. Deleting an entry + * shifts the remaining entries to the front. Replacing an entry is a + * combination of deleting the old value and adding the new one. + * + * The environment is preceeded by a 32 bit CRC over the data part. + * + ************************************************************************** + */ +#include +#include +#include +#include +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CFG_ENV_IS_IN_NVRAM) && \ + !defined(CFG_ENV_IS_IN_EEPROM) && \ + !defined(CFG_ENV_IS_IN_FLASH) && \ + !defined(CFG_ENV_IS_IN_DATAFLASH) && \ + !defined(CFG_ENV_IS_IN_NAND) && \ + !defined(CFG_ENV_IS_NOWHERE) + #error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE} +#endif + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +/************************************************************************ + ************************************************************************/ + +/* Function that returns a character from the environment */ +extern uchar (*env_get_char)(int); + +/* Function that returns a pointer to a value from the environment */ +/* (Only memory version supported / needed). */ +extern uchar *env_get_addr(int); + +/* Function that updates CRC of the enironment */ +extern void env_crc_update(void); + +/************************************************************************ + ************************************************************************/ + +static int envmatch(uchar *, int); + +/* + * Table with supported baudrates (defined in config_xyz.h) + */ +static const unsigned long baudrate_table[] = CFG_BAUDRATE_TABLE; +#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0])) + +/************************************************************************ + * Command interface: print one or all environment variables + */ +int do_printenv(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + int i, j, k, nxt; + int rcode = 0; + + if(argc == 1){ /* Print all env variables */ + for(i = 0; env_get_char(i) != '\0'; i = nxt + 1){ + + for(nxt = i; env_get_char(nxt) != '\0'; ++nxt); + + for(k = i; k < nxt; ++k){ + putc(env_get_char(k)); + } + + putc('\n'); + + if(ctrlc()){ + puts("\nAbort\n"); + return(1); + } + } + +#if defined(CFG_ENV_IS_IN_NVRAM) || \ + defined(CFG_ENV_IS_IN_EEPROM) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND)) + printf("\nEnvironment size: %d/%d bytes\n\n", i, ENV_SIZE); +#else + printf("\nEnvironment size: %d bytes\n\n", i); +#endif + return(0); + } + + for(i = 1; i < argc; ++i){ /* print single env variables */ + char *name = argv[i]; + + k = -1; + + for(j = 0; env_get_char(j) != '\0'; j = nxt + 1){ + + for(nxt = j; env_get_char(nxt) != '\0'; ++nxt); + + k = envmatch((uchar *)name, j); + + if(k < 0){ + continue; + } + + puts(name); + putc('='); + + while(k < nxt){ + putc(env_get_char(k++)); + } + + putc('\n'); + break; + } + if(k < 0){ + printf("## Error: \"%s\" not defined\n", name); + rcode++; + } + } + return(rcode); +} + +/************************************************************************ + * Set a new environment variable, + * or replace or delete an existing one. + * + * This function will ONLY work with a in-RAM copy of the environment + */ +int _do_setenv(int flag, int argc, char *argv[]){ + int i, len, oldval; + int console = -1; + uchar *env, *nxt = NULL; + char *name; + bd_t *bd = gd->bd; + + uchar *env_data = env_get_addr(0); + + if(!env_data){ /* need copy in RAM */ + return(1); + } + + name = argv[1]; + + /* + * search if variable with this name already exists + */ + oldval = -1; + + for(env = env_data; *env; env = nxt + 1){ + for(nxt = env; *nxt; ++nxt); + + if((oldval = envmatch((uchar *)name, env - env_data)) >= 0){ + break; + } + } + + /* + * Delete any existing definition + */ + if(oldval >= 0){ + /* Check for console redirection */ + if(strcmp(name, "stdin") == 0){ + console = stdin; + } else if(strcmp(name, "stdout") == 0){ + console = stdout; + } else if(strcmp(name, "stderr") == 0){ + console = stderr; + } + + if(console != -1){ + if(argc < 3){ /* Cannot delete it! */ + printf("## Error: can't delete \"%s\"\n", name); + return(1); + } + + /* Try assigning specified device */ + if(console_assign(console, argv[2]) < 0){ + return(1); + } + +#ifdef CONFIG_SERIAL_MULTI + if(serial_assign(argv[2]) < 0){ + return(1); + } +#endif + } + + /* + * Switch to new baudrate if new baudrate is supported + */ + if(strcmp(argv[1], "baudrate") == 0){ + int baudrate = simple_strtoul(argv[2], NULL, 10); + int i; + + for(i = 0; i < N_BAUDRATES; ++i){ + if(baudrate == baudrate_table[i]){ + break; + } + } + + if(i == N_BAUDRATES){ + printf("## Error: baudrate %d bps not supported\n", baudrate); + return(1); + } + + printf("Switch baudrate to %d bps and press ENTER...\n", baudrate); + udelay(50000); + + gd->baudrate = baudrate; + udelay(50000); + + for(;;){ + if(getc() == '\r'){ + break; + } + } + } + + if(*++nxt == '\0'){ + if(env > env_data){ + env--; + } else { + *env = '\0'; + } + } else { + for(;;){ + *env = *nxt++; + + if((*env == '\0') && (*nxt == '\0')){ + break; + } + + ++env; + } + } + *++env = '\0'; + } + +#ifdef CONFIG_NET_MULTI + if(strncmp(name, "eth", 3) == 0){ + char *end; + int num = simple_strtoul(name + 3, &end, 10); + + if(strcmp(end, "addr") == 0){ + eth_set_enetaddr(num, argv[2]); + } + } +#endif + + /* Delete only ? */ + if((argc < 3) || argv[2] == NULL){ + env_crc_update(); + return(0); + } + + /* + * Append new definition at the end + */ + for(env = env_data; *env || *(env + 1); ++env); + + if(env > env_data){ + ++env; + } + /* + * Overflow when: + * "name" + "=" + "val" +"\0\0" > ENV_SIZE - (env-env_data) + */ + len = strlen(name) + 2; + + /* add '=' for first arg, ' ' for all others */ + for(i = 2; i < argc; ++i){ + len += strlen(argv[i]) + 1; + } + + if(len > (&env_data[ENV_SIZE] - env)){ + printf("## Error: environment overflow, \"%s\" deleted\n", name); + return(1); + } + + while((*env = *name++) != '\0'){ + env++; + } + + for(i = 2; i < argc; ++i){ + char *val = argv[i]; + + *env = (i == 2) ? '=' : ' '; + while((*++env = *val++) != '\0'); + } + + /* end is marked with double '\0' */ + *++env = '\0'; + + /* Update CRC */ + env_crc_update(); + + /* + * Some variables should be updated when the corresponding + * entry in the enviornment is changed + */ + if(strcmp(argv[1], "ethaddr") == 0){ + char *s = argv[2]; /* always use only one arg */ + char *e; + + for(i = 0; i < 6; ++i){ + bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; + if(s){ + s = (*e) ? e + 1 : e; + } + } +#ifdef CONFIG_NET_MULTI + eth_set_enetaddr(0, argv[2]); +#endif + return(0); + } + + if(strcmp(argv[1], "ipaddr") == 0){ + char *s = argv[2]; /* always use only one arg */ + char *e; + unsigned long addr; + + bd->bi_ip_addr = 0; + + for(addr = 0, i = 0; i < 4; ++i){ + ulong val = s ? simple_strtoul(s, &e, 10) : 0; + addr <<= 8; + addr |= (val & 0xFF); + if(s){ + s = (*e) ? e + 1 : e; + } + } + + bd->bi_ip_addr = htonl(addr); + return(0); + } + + if(strcmp(argv[1], "loadaddr") == 0){ + load_addr = simple_strtoul(argv[2], NULL, 16); + return(0); + } + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if(strcmp(argv[1], "bootfile") == 0){ + copy_filename(BootFile, argv[2], sizeof(BootFile)); + return(0); + } +#endif /* CFG_CMD_NET */ + + return(0); +} + +void setenv(char *varname, char *varvalue){ + char *argv[4] = { "setenv", varname, varvalue, NULL }; + _do_setenv(0, 3, argv); +} + +int do_setenv(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + if(argc < 2){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + return(_do_setenv(flag, argc, argv)); +} + +/************************************************************************ + * Prompt for environment variable + */ + +#if (CONFIG_COMMANDS & CFG_CMD_ASKENV) +int do_askenv( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + extern char console_buffer[CFG_CBSIZE]; + char message[CFG_CBSIZE]; + int size = CFG_CBSIZE - 1; + int len; + char *local_args[4]; + + local_args[0] = argv[0]; + local_args[1] = argv[1]; + local_args[2] = NULL; + local_args[3] = NULL; + + if(argc < 2){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + /* Check the syntax */ + switch(argc){ + case 1: +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + + case 2: /* askenv envname */ + sprintf(message, "Please enter '%s':", argv[1]); + break; + + case 3: /* askenv envname size */ + sprintf(message, "Please enter '%s':", argv[1]); + size = simple_strtoul(argv[2], NULL, 10); + break; + + default: /* askenv envname message1 ... messagen size */ + { + int i; + int pos = 0; + + for(i = 2; i < argc - 1; i++){ + if(pos){ + message[pos++] = ' '; + } + strcpy(message+pos, argv[i]); + pos += strlen(argv[i]); + } + message[pos] = '\0'; + size = simple_strtoul(argv[argc - 1], NULL, 10); + } + break; + } + + if(size >= CFG_CBSIZE){ + size = CFG_CBSIZE - 1; + } + + if(size <= 0){ + return(1); + } + + /* prompt for input */ + len = readline(message); + + if(size < len){ + console_buffer[size] = '\0'; + } + + len = 2; + if(console_buffer[0] != '\0'){ + local_args[2] = console_buffer; + len = 3; + } + + /* Continue calling setenv code */ + return(_do_setenv(flag, len, local_args)); +} +#endif /* CFG_CMD_ASKENV */ + +/************************************************************************ + * Look up variable from environment, + * return address of storage for that variable, + * or NULL if not found + */ +char *getenv(char *name){ + int i, nxt; + + for(i = 0; env_get_char(i) != '\0'; i = nxt + 1){ + int val; + + for(nxt = i; env_get_char(nxt) != '\0'; ++nxt){ + if(nxt >= CFG_ENV_SIZE){ + return(NULL); + } + } + if((val = envmatch((uchar *)name, i)) < 0){ + continue; + } + return((char *)env_get_addr(val)); + } + + return(NULL); +} + +int getenv_r(char *name, char *buf, unsigned len){ + int i, nxt; + + for(i = 0; env_get_char(i) != '\0'; i = nxt + 1){ + int val, n; + + for(nxt = i; env_get_char(nxt) != '\0'; ++nxt){ + if(nxt >= CFG_ENV_SIZE){ + return(-1); + } + } + if((val = envmatch((uchar *)name, i)) < 0){ + continue; + } + /* found; copy out */ + n = 0; + while((len > n++) && (*buf++ = env_get_char(val++)) != '\0'); + + if(len == n){ + *buf = '\0'; + } + + return(n); + } + + return(-1); +} + +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ + (CFG_CMD_ENV|CFG_CMD_FLASH)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == \ + (CFG_CMD_ENV|CFG_CMD_NAND)) +int do_saveenv(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + extern char * env_name_spec; + + printf("Saving environment to %s...\n\n", env_name_spec); + + return(saveenv() ? 1 : 0); +} + +#endif + +/************************************************************************ + * Match a name / name=value pair + * + * s1 is either a simple 'name', or a 'name=value' pair. + * i2 is the environment index for a 'name2=value2' pair. + * If the names match, return the index for the value2, else NULL. + */ +static int envmatch(uchar *s1, int i2){ + + while(*s1 == env_get_char(i2++)){ + if(*s1++ == '='){ + return(i2); + } + } + + if(*s1 == '\0' && env_get_char(i2 - 1) == '='){ + return(i2); + } + + return(-1); +} + +/**************************************************/ +U_BOOT_CMD(printenv, CFG_MAXARGS, 1, do_printenv, "print environment variables\n", "[name]\n\t- print values of all environment variables or of one with name 'name'\n"); + +U_BOOT_CMD(setenv, CFG_MAXARGS, 0, do_setenv, "set environment variables\n", + "name value ...\n" + "\t- set environment variable 'name' to 'value ...'\n" + "setenv name\n" + "\t- delete environment variable 'name'\n"); + +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ + (CFG_CMD_ENV|CFG_CMD_FLASH)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == \ + (CFG_CMD_ENV|CFG_CMD_NAND)) +U_BOOT_CMD(saveenv, 1, 0, do_saveenv, "save environment variables to FLASH\n", NULL); + +#endif /* CFG_CMD_ENV */ + +#if (CONFIG_COMMANDS & CFG_CMD_ASKENV) + +U_BOOT_CMD( + askenv, CFG_MAXARGS, 1, do_askenv, + "get environment variables from stdin\n", + "name [message] [size]\n" + " - get environment variable 'name' from stdin (max 'size' chars)\n" + "askenv name\n" + " - get environment variable 'name' from stdin\n" + "askenv name size\n" + " - get environment variable 'name' from stdin (max 'size' chars)\n" + "askenv name [message] size\n" + " - display 'message' string and get environment variable 'name'" + "from stdin (max 'size' chars)\n" +); +#endif /* CFG_CMD_ASKENV */ + +#if (CONFIG_COMMANDS & CFG_CMD_RUN) +int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +U_BOOT_CMD(run, CFG_MAXARGS, 1, do_run, "run commands in an environment variable\n", "var [...]\n\t- run the commands in the environment variable(s) 'var'\n"); +#endif /* CFG_CMD_RUN */ diff --git a/u-boot/common/command.c b/u-boot/common/command.c new file mode 100755 index 0000000..d96b3a5 --- /dev/null +++ b/u-boot/common/command.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Command Processor Table + */ + +#include +#include + +int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + extern char version_string[]; + printf("%s\n\n", version_string); + + return(0); +} + +U_BOOT_CMD(version, 1, 1, do_version, "print U-Boot version\n", NULL); + +#if (CONFIG_COMMANDS & CFG_CMD_ECHO) +int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ + int i, putnl = 1; + + for(i = 1; i < argc; i++){ + char *p = argv[i], c; + + if(i > 1){ + putc(' '); + } + + while((c = *p++) != '\0'){ + if(c == '\\' && *p == 'c'){ + putnl = 0; + p++; + } else { + putc(c); + } + } + } + + if(putnl){ + putc('\n'); + } + + return(0); +} +U_BOOT_CMD(echo, CFG_MAXARGS, 1, do_echo, "echo args to console\n", "[args..]\n" "\t- echo args to console; \\c suppresses newline\n"); +#endif /* CFG_CMD_ECHO */ + +/* + * Use puts() instead of printf() to avoid printf buffer overflow + * for long help messages + */ +int do_help(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + int i; + int rcode = 0; + + if(argc == 1){ /*show list of commands */ + + int cmd_items = &__u_boot_cmd_end - &__u_boot_cmd_start; /* pointer arith! */ + cmd_tbl_t *cmd_array[cmd_items]; + int i, j, swaps, max_len = 0; + + /* Make array of commands from .uboot_cmd section */ + cmdtp = &__u_boot_cmd_start; + + for(i = 0; i < cmd_items; i++){ + cmd_array[i] = cmdtp++; + } + + /* Sort command list (trivial bubble sort) */ + for(i = cmd_items - 1; i > 0; --i){ + swaps = 0; + for(j = 0; j < i; ++j){ + + const char *name = cmd_array[j]->name; + + if(strlen(name) >= max_len){ + max_len = strlen(name); + } + + if(strcmp(cmd_array[j]->name, cmd_array[j + 1]->name) > 0){ + cmd_tbl_t *tmp; + tmp = cmd_array[j]; + cmd_array[j] = cmd_array[j + 1]; + cmd_array[j + 1] = tmp; + ++swaps; + } + } + + if(!swaps){ + break; + } + } + + max_len++; + + /* print short help (usage) */ + for(i = 0; i < cmd_items; i++){ + const char *usage = cmd_array[i]->usage; + const char *name = cmd_array[i]->name; + + /* allow user abort */ + if(ctrlc()){ + return(1); + } + + if(usage == NULL){ + continue; + } + /* print aligned command name and usage */ + printf("%-*s - ", max_len, name); + puts(usage); + } + + printf("\n"); + + return(0); + } + /* + * command help (long version) + */ + for(i = 1; i < argc; ++i){ + if((cmdtp = find_cmd(argv[i])) != NULL){ +#ifdef CFG_LONGHELP + /* found - print (long) help info */ + puts(cmdtp->name); + putc(' '); + + if(cmdtp->help){ + puts(cmdtp->help); + } else { + puts("- there is no help for this command\n"); + rcode = 1; + } + + putc('\n'); +#else /* no long help available */ + if(cmdtp->usage){ + puts(cmdtp->usage); + } +#endif /* CFG_LONGHELP */ + } else { + printf("Unknown command '%s' - try 'help' without arguments\n\n", argv[i]); + rcode = 1; + } + } + + return(rcode); +} + +U_BOOT_CMD(help, CFG_MAXARGS, 1, do_help, "print embedded help\n", + "[command ...]\n" + "\t- show help information (for 'command')\n" + "\twithout arguments, it prints a short usage message for available commands.\n"); + +/* This do not ust the U_BOOT_CMD macro as ? can't be used in symbol names */ +#ifdef CFG_LONGHELP +cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {"?", CFG_MAXARGS, 1, do_help, "alias for 'help'\n", NULL}; +#else +cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {"?", CFG_MAXARGS, 1, do_help, "alias for 'help'\n"}; +#endif /* CFG_LONGHELP */ + +/*************************************************************************** + * find command table entry for a command + */ +cmd_tbl_t *find_cmd(const char *cmd){ + cmd_tbl_t *cmdtp; + cmd_tbl_t *cmdtp_temp = &__u_boot_cmd_start; /*Init value */ + const char *p; + int len; + int n_found = 0; + + /* + * Some commands allow length modifiers (like "cp.b"); + * compare command name only until first dot. + */ + len = ((p = strchr(cmd, '.')) == NULL) ? strlen(cmd) : (p - cmd); + + for(cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++){ + if(strncmp(cmd, cmdtp->name, len) == 0){ + if(len == strlen(cmdtp->name)){ + return(cmdtp); /* full match */ + } + + cmdtp_temp = cmdtp; /* abbreviated command ? */ + n_found++; + } + } + if(n_found == 1){ /* exactly one match */ + return(cmdtp_temp); + } + + return(NULL); /* not found or ambiguous command */ +} diff --git a/u-boot/common/console.c b/u-boot/common/console.c new file mode 100755 index 0000000..8d0f720 --- /dev/null +++ b/u-boot/common/console.c @@ -0,0 +1,507 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CFG_CONSOLE_IS_IN_ENV +/* + * if overwrite_console returns 1, the stdin, stderr and stdout + * are switched to the serial port, else the settings in the + * environment are used + */ +#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console(void); +#define OVERWRITE_CONSOLE overwrite_console() +#else +#define OVERWRITE_CONSOLE 0 +#endif /* CFG_CONSOLE_OVERWRITE_ROUTINE */ + +#endif /* CFG_CONSOLE_IS_IN_ENV */ + +static int console_setfile(int file, device_t * dev){ + int error = 0; + + if(dev == NULL){ + return(-1); + } + + switch(file){ + case stdin: + case stdout: + case stderr: + /* Start new device */ + if(dev->start){ + error = dev->start(); + /* If it's not started dont use it */ + if(error < 0){ + break; + } + } + + /* Assign the new device (leaving the existing one started) */ + stdio_devices[file] = dev; + + /* + * Update monitor functions + * (to use the console stuff by other applications) + */ + switch(file){ + case stdin: + gd->jt[XF_getc] = dev->getc; + gd->jt[XF_tstc] = dev->tstc; + break; + case stdout: + gd->jt[XF_putc] = dev->putc; + gd->jt[XF_puts] = dev->puts; + gd->jt[XF_printf] = printf; + break; + } + break; + + default: /* Invalid file ID */ + error = -1; + } + return(error); +} + +/** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/ + +void serial_printf(const char *fmt, ...){ + va_list args; + //uint i; + char printbuffer[CFG_PBSIZE]; + + va_start(args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + //i = vsprintf(printbuffer, fmt, args); + vsprintf(printbuffer, fmt, args); + va_end(args); + + serial_puts(printbuffer); +} + +int fgetc(int file){ + if(file < MAX_FILES){ + return(stdio_devices[file]->getc()); + } + + return(-1); +} + +int ftstc(int file){ + if(file < MAX_FILES){ + return(stdio_devices[file]->tstc()); + } + + return(-1); +} + +void fputc(int file, const char c){ + if(file < MAX_FILES){ + stdio_devices[file]->putc(c); + } +} + +void fputs(int file, const char *s){ + if(file < MAX_FILES){ + stdio_devices[file]->puts(s); + } +} + +void fprintf(int file, const char *fmt, ...){ + va_list args; + //uint i; + char printbuffer[CFG_PBSIZE]; + + va_start(args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + //i = vsprintf(printbuffer, fmt, args); + vsprintf(printbuffer, fmt, args); + va_end(args); + + /* Send to desired file */ + fputs(file, printbuffer); +} + +/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/ + +int getc(void){ + if(gd->flags & GD_FLG_DEVINIT){ + /* Get from the standard input */ + return(fgetc(stdin)); + } + + /* Send directly to the handler */ + return(serial_getc()); +} + +int tstc(void){ + if(gd->flags & GD_FLG_DEVINIT){ + /* Test the standard input */ + return(ftstc(stdin)); + } + + /* Send directly to the handler */ + return(serial_tstc()); +} + +void putc(const char c){ +#ifdef CONFIG_SILENT_CONSOLE + if(gd->flags & GD_FLG_SILENT){ + return; + } +#endif + + if(gd->flags & GD_FLG_DEVINIT){ + /* Send to the standard output */ + fputc(stdout, c); + } else { + /* Send directly to the handler */ + serial_putc(c); + } +} + +void puts(const char *s){ +#ifdef CONFIG_SILENT_CONSOLE + if(gd->flags & GD_FLG_SILENT){ + return; + } +#endif + + if(gd->flags & GD_FLG_DEVINIT){ + /* Send to the standard output */ + fputs(stdout, s); + } else { + /* Send directly to the handler */ + serial_puts(s); + } +} + +void printf(const char *fmt, ...){ + va_list args; + //uint i; + char printbuffer[CFG_PBSIZE]; + + va_start(args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + //i = vsprintf(printbuffer, fmt, args); + vsprintf(printbuffer, fmt, args); + va_end(args); + + /* Print the string */ + puts(printbuffer); +} +#if 0 +void vprintf(const char *fmt, va_list args){ + //uint i; + char printbuffer[CFG_PBSIZE]; + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + //i = vsprintf(printbuffer, fmt, args); + vsprintf(printbuffer, fmt, args); + + /* Print the string */ + puts(printbuffer); +} +#endif +/* test if ctrl-c was pressed */ +static int ctrlc_disabled = 0; /* see disable_ctrl() */ +static int ctrlc_was_pressed = 0; +int ctrlc(void){ + if(!ctrlc_disabled && gd->have_console){ + if(tstc()){ + switch(getc()){ + case 0x03: /* ^C - Control C */ + ctrlc_was_pressed = 1; + return(1); + default: + break; + } + } + } + return(0); +} + +/* pass 1 to disable ctrlc() checking, 0 to enable. + * returns previous state + */ +int disable_ctrlc(int disable){ + int prev = ctrlc_disabled; /* save previous state */ + + ctrlc_disabled = disable; + return(prev); +} + +int had_ctrlc(void){ + return(ctrlc_was_pressed); +} + +void clear_ctrlc(void){ + ctrlc_was_pressed = 0; +} + +#if 0 +inline void dbg(const char *fmt, ...){ +} +#endif + +/** U-Boot INIT FUNCTIONS *************************************************/ + +int console_assign(int file, char *devname){ + int flag, i; + + /* Check for valid file */ + switch(file){ + case stdin: + flag = DEV_FLAGS_INPUT; + break; + case stdout: + case stderr: + flag = DEV_FLAGS_OUTPUT; + break; + default: + return(-1); + } + + /* Check for valid device name */ + + for(i = 1; i <= ListNumItems(devlist); i++){ + device_t *dev = ListGetPtrToItem(devlist, i); + + if(strcmp(devname, dev->name) == 0){ + if(dev->flags & flag){ + return(console_setfile(file, dev)); + } + + return(-1); + } + } + + return(-1); +} + +/* Called before relocation - use serial functions */ +int console_init_f(void){ + gd->have_console = 1; + +#ifdef CONFIG_SILENT_CONSOLE + if(getenv("silent") != NULL){ + gd->flags |= GD_FLG_SILENT; + } +#endif + + return(0); +} + +#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SILENT_CONSOLE) +/* search a device */ +device_t *search_device(int flags, char *name){ + int i, items; + device_t *dev = NULL; + + items = ListNumItems(devlist); + + if(name == NULL){ + return(dev); + } + + for(i = 1; i <= items; i++){ + dev = ListGetPtrToItem(devlist, i); + if((dev->flags & flags) && (strcmp(name, dev->name) == 0)){ + break; + } + } + return(dev); +} +#endif /* CFG_CONSOLE_IS_IN_ENV || CONFIG_SILENT_CONSOLE */ + +#ifdef CFG_CONSOLE_IS_IN_ENV +/* Called after the relocation - use desired console functions */ +int console_init_r(void){ + char *stdinname, *stdoutname, *stderrname; + device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL; +#ifdef CFG_CONSOLE_ENV_OVERWRITE + int i; +#endif /* CFG_CONSOLE_ENV_OVERWRITE */ + + /* set default handlers at first */ + gd->jt[XF_getc] = serial_getc; + gd->jt[XF_tstc] = serial_tstc; + gd->jt[XF_putc] = serial_putc; + gd->jt[XF_puts] = serial_puts; + gd->jt[XF_printf] = serial_printf; + + /* stdin stdout and stderr are in environment */ + /* scan for it */ + stdinname = getenv("stdin"); + stdoutname = getenv("stdout"); + stderrname = getenv("stderr"); + + if(OVERWRITE_CONSOLE == 0){ /* if not overwritten by config switch */ + inputdev = search_device(DEV_FLAGS_INPUT, stdinname); + outputdev = search_device(DEV_FLAGS_OUTPUT, stdoutname); + errdev = search_device(DEV_FLAGS_OUTPUT, stderrname); + } + /* if the devices are overwritten or not found, use default device */ + if(inputdev == NULL){ + inputdev = search_device(DEV_FLAGS_INPUT, "serial"); + } + if(outputdev == NULL){ + outputdev = search_device(DEV_FLAGS_OUTPUT, "serial"); + } + if(errdev == NULL){ + errdev = search_device(DEV_FLAGS_OUTPUT, "serial"); + } + /* Initializes output console first */ + if(outputdev != NULL){ + console_setfile(stdout, outputdev); + } + if(errdev != NULL){ + console_setfile(stderr, errdev); + } + if(inputdev != NULL){ + console_setfile(stdin, inputdev); + } + + gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */ + +#ifndef CFG_CONSOLE_INFO_QUIET + /* Print information */ + puts("In: "); + if(stdio_devices[stdin] == NULL){ + puts("No input devices available!\n"); + } else { + printf("%s\n", stdio_devices[stdin]->name); + } + + puts("Out: "); + if(stdio_devices[stdout] == NULL){ + puts("No output devices available!\n"); + } else { + printf("%s\n", stdio_devices[stdout]->name); + } + + puts("Err: "); + if(stdio_devices[stderr] == NULL){ + puts("No error devices available!\n"); + } else { + printf("%s\n", stdio_devices[stderr]->name); + } +#endif /* CFG_CONSOLE_INFO_QUIET */ + +#ifdef CFG_CONSOLE_ENV_OVERWRITE + /* set the environment variables (will overwrite previous env settings) */ + for(i = 0; i < 3; i++){ + setenv(stdio_names[i], stdio_devices[i]->name); + } +#endif /* CFG_CONSOLE_ENV_OVERWRITE */ + return(0); +} + +#else /* CFG_CONSOLE_IS_IN_ENV */ + +/* Called after the relocation - use desired console functions */ +int console_init_r(void){ + device_t *inputdev = NULL, *outputdev = NULL; + int i, items = ListNumItems(devlist); + +#ifdef CONFIG_SILENT_CONSOLE + /* Suppress all output if "silent" mode requested */ + if(gd->flags & GD_FLG_SILENT){ + outputdev = search_device(DEV_FLAGS_OUTPUT, "nulldev"); + } +#endif + + /* Scan devices looking for input and output devices */ + for(i = 1; (i <= items) && ((inputdev == NULL) || (outputdev == NULL)); i++){ + device_t *dev = ListGetPtrToItem(devlist, i); + + if((dev->flags & DEV_FLAGS_INPUT) && (inputdev == NULL)){ + inputdev = dev; + } + if((dev->flags & DEV_FLAGS_OUTPUT) && (outputdev == NULL)){ + outputdev = dev; + } + } + + /* Initializes output console first */ + if(outputdev != NULL){ + console_setfile(stdout, outputdev); + console_setfile(stderr, outputdev); + } + + /* Initializes input console */ + if(inputdev != NULL){ + console_setfile(stdin, inputdev); + } + + gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */ + +#ifndef CFG_CONSOLE_INFO_QUIET + /* Print information */ + puts("In: "); + if(stdio_devices[stdin] == NULL){ + puts("No input devices available!\n"); + } else { + printf("%s\n", stdio_devices[stdin]->name); + } + + puts("Out: "); + if(stdio_devices[stdout] == NULL){ + puts("No output devices available!\n"); + } else { + printf("%s\n", stdio_devices[stdout]->name); + } + + puts("Err: "); + if(stdio_devices[stderr] == NULL){ + puts("No error devices available!\n"); + } else { + printf("%s\n", stdio_devices[stderr]->name); + } +#endif /* CFG_CONSOLE_INFO_QUIET */ + + /* Setting environment variables */ + for(i = 0; i < 3; i++){ + setenv(stdio_names[i], stdio_devices[i]->name); + } + + return(0); +} + +#endif /* CFG_CONSOLE_IS_IN_ENV */ diff --git a/u-boot/common/devices.c b/u-boot/common/devices.c new file mode 100755 index 0000000..c167072 --- /dev/null +++ b/u-boot/common/devices.c @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +list_t devlist = 0; +device_t *stdio_devices[] = {NULL, NULL, NULL}; +char *stdio_names[MAX_FILES] = {"stdin", "stdout", "stderr"}; + +/************************************************************************** + * SYSTEM DRIVERS + ************************************************************************** + */ +static void drv_system_init(void){ + device_t dev; + + memset(&dev, 0, sizeof(dev)); + + strcpy(dev.name, "serial"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + + dev.putc = serial_putc; + dev.puts = serial_puts; + dev.getc = serial_getc; + dev.tstc = serial_tstc; + + device_register(&dev); +} + +/************************************************************************** + * DEVICES + ************************************************************************** + */ +int device_register(device_t * dev){ + ListInsertItem(devlist, dev, LIST_END); + return(0); +} + +/* + * deregister the device "devname". + * returns 0 if success, -1 if device is assigned and 1 if devname not found + */ +#ifdef CFG_DEVICE_DEREGISTER +int device_deregister(char *devname){ + int i,l,dev_index; + device_t *dev = NULL; + char temp_names[3][8]; + + dev_index=-1; + + for(i=1; i<=ListNumItems(devlist); i++){ + dev = ListGetPtrToItem(devlist, i); + + if(strcmp(dev->name,devname)==0){ + dev_index=i; + break; + } + } + + if(dev_index<0){ /* device not found */ + return(0); + } + + /* get stdio devices (ListRemoveItem changes the dev list) */ + for(l=0; l< MAX_FILES; l++){ + if(stdio_devices[l] == dev){ + /* Device is assigned -> report error */ + return(-1); + } + memcpy(&temp_names[l][0], stdio_devices[l]->name, sizeof(stdio_devices[l]->name)); + } + + ListRemoveItem(devlist,NULL,dev_index); + + /* reassign Device list */ + for(i=1; i<=ListNumItems(devlist); i++){ + dev = ListGetPtrToItem(devlist, i); + + for(l=0; l< MAX_FILES; l++){ + if(strcmp(dev->name,temp_names[l])==0){ + stdio_devices[l] = dev; + } + } + } + + return(0); +} +#endif /* CFG_DEVICE_DEREGISTER */ + +int devices_init(void){ + ulong relocation_offset = gd->reloc_off; + int i; + + /* relocate device name pointers */ + for(i = 0; i < (sizeof(stdio_names) / sizeof(char *)); ++i){ + stdio_names[i] = (char *)(((ulong)stdio_names[i]) + relocation_offset); + } + + /* Initialize the list */ + devlist = ListCreate(sizeof(device_t)); + + if(devlist == NULL){ + eputs("Cannot initialize the list of devices!\n"); + return(-1); + } + + drv_system_init(); + +#ifdef CONFIG_NETCONSOLE + drv_nc_init(); +#endif + + return(0); +} + +int devices_done(void){ + ListDispose(devlist); + + return(0); +} diff --git a/u-boot/common/dlmalloc.c b/u-boot/common/dlmalloc.c new file mode 100755 index 0000000..20c2069 --- /dev/null +++ b/u-boot/common/dlmalloc.c @@ -0,0 +1,3302 @@ +#if 0 /* Moved to malloc.h */ +/* ---------- To make a malloc.h, start cutting here ------------ */ + +/* + A version of malloc/free/realloc written by Doug Lea and released to the + public domain. Send questions/comments/complaints/performance data + to dl@cs.oswego.edu + +* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) + + Note: There may be an updated version of this malloc obtainable at + ftp://g.oswego.edu/pub/misc/malloc.c + Check before installing! + +* Why use this malloc? + + This is not the fastest, most space-conserving, most portable, or + most tunable malloc ever written. However it is among the fastest + while also being among the most space-conserving, portable and tunable. + Consistent balance across these factors results in a good general-purpose + allocator. For a high-level description, see + http://g.oswego.edu/dl/html/malloc.html + +* Synopsis of public routines + + (Much fuller descriptions are contained in the program documentation below.) + + malloc(size_t n); + Return a pointer to a newly allocated chunk of at least n bytes, or null + if no space is available. + free(Void_t* p); + Release the chunk of memory pointed to by p, or no effect if p is null. + realloc(Void_t* p, size_t n); + Return a pointer to a chunk of size n that contains the same data + as does chunk p up to the minimum of (n, p's size) bytes, or null + if no space is available. The returned pointer may or may not be + the same as p. If p is null, equivalent to malloc. Unless the + #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + memalign(size_t alignment, size_t n); + Return a pointer to a newly allocated chunk of n bytes, aligned + in accord with the alignment argument, which must be a power of + two. + valloc(size_t n); + Equivalent to memalign(pagesize, n), where pagesize is the page + size of the system (or as near to this as can be figured out from + all the includes/defines below.) + pvalloc(size_t n); + Equivalent to valloc(minimum-page-that-holds(n)), that is, + round up n to nearest pagesize. + calloc(size_t unit, size_t quantity); + Returns a pointer to quantity * unit bytes, with all locations + set to zero. + cfree(Void_t* p); + Equivalent to free(p). + malloc_trim(size_t pad); + Release all but pad bytes of freed top-most memory back + to the system. Return 1 if successful, else 0. + malloc_usable_size(Void_t* p); + Report the number usable allocated bytes associated with allocated + chunk p. This may or may not report more bytes than were requested, + due to alignment and minimum size constraints. + malloc_stats(); + Prints brief summary statistics. + mallinfo() + Returns (by copy) a struct containing various summary statistics. + mallopt(int parameter_number, int parameter_value) + Changes one of the tunable parameters described below. Returns + 1 if successful in changing the parameter, else 0. + +* Vital statistics: + + Alignment: 8-byte + 8 byte alignment is currently hardwired into the design. This + seems to suffice for all current machines and C compilers. + + Assumed pointer representation: 4 or 8 bytes + Code for 8-byte pointers is untested by me but has worked + reliably by Wolfram Gloger, who contributed most of the + changes supporting this. + + Assumed size_t representation: 4 or 8 bytes + Note that size_t is allowed to be 4 bytes even if pointers are 8. + + Minimum overhead per allocated chunk: 4 or 8 bytes + Each malloced chunk has a hidden overhead of 4 bytes holding size + and status information. + + Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead) + 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) + + When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte + ptrs but 4 byte size) or 24 (for 8/8) additional bytes are + needed; 4 (8) for a trailing size field + and 8 (16) bytes for free list pointers. Thus, the minimum + allocatable size is 16/24/32 bytes. + + Even a request for zero bytes (i.e., malloc(0)) returns a + pointer to something of the minimum allocatable size. + + Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes + 8-byte size_t: 2^63 - 16 bytes + + It is assumed that (possibly signed) size_t bit values suffice to + represent chunk sizes. `Possibly signed' is due to the fact + that `size_t' may be defined on a system as either a signed or + an unsigned type. To be conservative, values that would appear + as negative numbers are avoided. + Requests for sizes with a negative sign bit when the request + size is treaded as a long will return null. + + Maximum overhead wastage per allocated chunk: normally 15 bytes + + Alignnment demands, plus the minimum allocatable size restriction + make the normal worst-case wastage 15 bytes (i.e., up to 15 + more bytes will be allocated than were requested in malloc), with + two exceptions: + 1. Because requests for zero bytes allocate non-zero space, + the worst case wastage for a request of zero bytes is 24 bytes. + 2. For requests >= mmap_threshold that are serviced via + mmap(), the worst case wastage is 8 bytes plus the remainder + from a system page (the minimal mmap unit); typically 4096 bytes. + +* Limitations + + Here are some features that are NOT currently supported + + * No user-definable hooks for callbacks and the like. + * No automated mechanism for fully checking that all accesses + to malloced memory stay within their bounds. + * No support for compaction. + +* Synopsis of compile-time options: + + People have reported using previous versions of this malloc on all + versions of Unix, sometimes by tweaking some of the defines + below. It has been tested most extensively on Solaris and + Linux. It is also reported to work on WIN32 platforms. + People have also reported adapting this malloc for use in + stand-alone embedded systems. + + The implementation is in straight, hand-tuned ANSI C. Among other + consequences, it uses a lot of macros. Because of this, to be at + all usable, this code should be compiled using an optimizing compiler + (for example gcc -O2) that can simplify expressions and control + paths. + + __STD_C (default: derived from C compiler defines) + Nonzero if using ANSI-standard C compiler, a C++ compiler, or + a C compiler sufficiently close to ANSI to get away with it. + DEBUG (default: NOT defined) + Define to enable debugging. Adds fairly extensive assertion-based + checking to help track down memory errors, but noticeably slows down + execution. + REALLOC_ZERO_BYTES_FREES (default: NOT defined) + Define this if you think that realloc(p, 0) should be equivalent + to free(p). Otherwise, since malloc returns a unique pointer for + malloc(0), so does realloc(p, 0). + HAVE_MEMCPY (default: defined) + Define if you are not otherwise using ANSI STD C, but still + have memcpy and memset in your C library and want to use them. + Otherwise, simple internal versions are supplied. + USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise) + Define as 1 if you want the C library versions of memset and + memcpy called in realloc and calloc (otherwise macro versions are used). + At least on some platforms, the simple macro versions usually + outperform libc versions. + HAVE_MMAP (default: defined as 1) + Define to non-zero to optionally make malloc() use mmap() to + allocate very large blocks. + HAVE_MREMAP (default: defined as 0 unless Linux libc set) + Define to non-zero to optionally make realloc() use mremap() to + reallocate very large blocks. + malloc_getpagesize (default: derived from system #includes) + Either a constant or routine call returning the system page size. + HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined) + Optionally define if you are on a system with a /usr/include/malloc.h + that declares struct mallinfo. It is not at all necessary to + define this even if you do, but will ensure consistency. + INTERNAL_SIZE_T (default: size_t) + Define to a 32-bit type (probably `unsigned int') if you are on a + 64-bit machine, yet do not want or need to allow malloc requests of + greater than 2^31 to be handled. This saves space, especially for + very small chunks. + INTERNAL_LINUX_C_LIB (default: NOT defined) + Defined only when compiled as part of Linux libc. + Also note that there is some odd internal name-mangling via defines + (for example, internally, `malloc' is named `mALLOc') needed + when compiling in this case. These look funny but don't otherwise + affect anything. + WIN32 (default: undefined) + Define this on MS win (95, nt) platforms to compile in sbrk emulation. + LACKS_UNISTD_H (default: undefined if not WIN32) + Define this if your system does not have a . + LACKS_SYS_PARAM_H (default: undefined if not WIN32) + Define this if your system does not have a . + MORECORE (default: sbrk) + The name of the routine to call to obtain more memory from the system. + MORECORE_FAILURE (default: -1) + The value returned upon failure of MORECORE. + MORECORE_CLEARS (default 1) + True (1) if the routine mapped to MORECORE zeroes out memory (which + holds for sbrk). + DEFAULT_TRIM_THRESHOLD + DEFAULT_TOP_PAD + DEFAULT_MMAP_THRESHOLD + DEFAULT_MMAP_MAX + Default values of tunable parameters (described in detail below) + controlling interaction with host system routines (sbrk, mmap, etc). + These values may also be changed dynamically via mallopt(). The + preset defaults are those that give best performance for typical + programs/systems. + USE_DL_PREFIX (default: undefined) + Prefix all public routines with the string 'dl'. Useful to + quickly avoid procedure declaration conflicts and linker symbol + conflicts with existing memory allocation routines. + + +*/ + + + + +/* Preliminaries */ + +#ifndef __STD_C +#ifdef __STDC__ +#define __STD_C 1 +#else +#if __cplusplus +#define __STD_C 1 +#else +#define __STD_C 0 +#endif /*__cplusplus*/ +#endif /*__STDC__*/ +#endif /*__STD_C*/ + +#ifndef Void_t +#if (__STD_C || defined(WIN32)) +#define Void_t void +#else +#define Void_t char +#endif +#endif /*Void_t*/ + +#if __STD_C +#include /* for size_t */ +#else +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#include /* needed for malloc_stats */ + + +/* + Compile-time options +*/ + + +/* + Debugging: + + Because freed chunks may be overwritten with link fields, this + malloc will often die when freed memory is overwritten by user + programs. This can be very effective (albeit in an annoying way) + in helping track down dangling pointers. + + If you compile with -DDEBUG, a number of assertion checks are + enabled that will catch more memory errors. You probably won't be + able to make much sense of the actual assertion errors, but they + should help you locate incorrectly overwritten memory. The + checking is fairly extensive, and will slow down execution + noticeably. Calling malloc_stats or mallinfo with DEBUG set will + attempt to check every non-mmapped allocated and free chunk in the + course of computing the summmaries. (By nature, mmapped regions + cannot be checked very much automatically.) + + Setting DEBUG may also be helpful if you are trying to modify + this code. The assertions in the check routines spell out in more + detail the assumptions and invariants underlying the algorithms. + +*/ + +#ifdef DEBUG +#include +#else +#define assert(x) ((void)0) +#endif + + +/* + INTERNAL_SIZE_T is the word-size used for internal bookkeeping + of chunk sizes. On a 64-bit machine, you can reduce malloc + overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' + at the expense of not being able to handle requests greater than + 2^31. This limitation is hardly ever a concern; you are encouraged + to set this. However, the default version is the same as size_t. +*/ + +#ifndef INTERNAL_SIZE_T +#define INTERNAL_SIZE_T size_t +#endif + +/* + REALLOC_ZERO_BYTES_FREES should be set if a call to + realloc with zero bytes should be the same as a call to free. + Some people think it should. Otherwise, since this malloc + returns a unique pointer for malloc(0), so does realloc(p, 0). +*/ + + +/* #define REALLOC_ZERO_BYTES_FREES */ + + +/* + WIN32 causes an emulation of sbrk to be compiled in + mmap-based options are not currently supported in WIN32. +*/ + +/* #define WIN32 */ +#ifdef WIN32 +#define MORECORE wsbrk +#define HAVE_MMAP 0 + +#define LACKS_UNISTD_H +#define LACKS_SYS_PARAM_H + +/* + Include 'windows.h' to get the necessary declarations for the + Microsoft Visual C++ data structures and routines used in the 'sbrk' + emulation. + + Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft + Visual C++ header files are included. +*/ +#define WIN32_LEAN_AND_MEAN +#include +#endif + + +/* + HAVE_MEMCPY should be defined if you are not otherwise using + ANSI STD C, but still have memcpy and memset in your C library + and want to use them in calloc and realloc. Otherwise simple + macro versions are defined here. + + USE_MEMCPY should be defined as 1 if you actually want to + have memset and memcpy called. People report that the macro + versions are often enough faster than libc versions on many + systems that it is better to use them. + +*/ + +#define HAVE_MEMCPY + +#ifndef USE_MEMCPY +#ifdef HAVE_MEMCPY +#define USE_MEMCPY 1 +#else +#define USE_MEMCPY 0 +#endif +#endif + +#if (__STD_C || defined(HAVE_MEMCPY)) + +#if __STD_C +void* memset(void*, int, size_t); +void* memcpy(void*, const void*, size_t); +#else +#ifdef WIN32 +/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */ +/* 'windows.h' */ +#else +Void_t* memset(); +Void_t* memcpy(); +#endif +#endif +#endif + +#if USE_MEMCPY + +/* The following macros are only invoked with (2n+1)-multiples of + INTERNAL_SIZE_T units, with a positive integer n. This is exploited + for fast inline execution when n is small. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T mzsz = (nbytes); \ + if(mzsz <= 9*sizeof(mzsz)) { \ + INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \ + if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; }}} \ + *mz++ = 0; \ + *mz++ = 0; \ + *mz = 0; \ + } else memset((charp), 0, mzsz); \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T mcsz = (nbytes); \ + if(mcsz <= 9*sizeof(mcsz)) { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \ + if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; }}} \ + *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + *mcdst = *mcsrc ; \ + } else memcpy(dest, src, mcsz); \ +} while(0) + +#else /* !USE_MEMCPY */ + +/* Use Duff's device for good zeroing/copying performance. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mzp++ = 0; \ + case 7: *mzp++ = 0; \ + case 6: *mzp++ = 0; \ + case 5: *mzp++ = 0; \ + case 4: *mzp++ = 0; \ + case 3: *mzp++ = 0; \ + case 2: *mzp++ = 0; \ + case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mcdst++ = *mcsrc++; \ + case 7: *mcdst++ = *mcsrc++; \ + case 6: *mcdst++ = *mcsrc++; \ + case 5: *mcdst++ = *mcsrc++; \ + case 4: *mcdst++ = *mcsrc++; \ + case 3: *mcdst++ = *mcsrc++; \ + case 2: *mcdst++ = *mcsrc++; \ + case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#endif + + +/* + Define HAVE_MMAP to optionally make malloc() use mmap() to + allocate very large blocks. These will be returned to the + operating system immediately after a free(). +*/ + +#ifndef HAVE_MMAP +#define HAVE_MMAP 1 +#endif + +/* + Define HAVE_MREMAP to make realloc() use mremap() to re-allocate + large blocks. This is currently only possible on Linux with + kernel versions newer than 1.3.77. +*/ + +#ifndef HAVE_MREMAP +#ifdef INTERNAL_LINUX_C_LIB +#define HAVE_MREMAP 1 +#else +#define HAVE_MREMAP 0 +#endif +#endif + +#if HAVE_MMAP + +#include +#include +#include + +#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON) +#define MAP_ANONYMOUS MAP_ANON +#endif + +#endif /* HAVE_MMAP */ + +/* + Access to system page size. To the extent possible, this malloc + manages memory from the system in page-size units. + + The following mechanics for getpagesize were adapted from + bsd/gnu getpagesize.h +*/ + +#ifndef LACKS_UNISTD_H +# include +#endif + +#ifndef malloc_getpagesize +# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */ +# ifndef _SC_PAGE_SIZE +# define _SC_PAGE_SIZE _SC_PAGESIZE +# endif +# endif +# ifdef _SC_PAGE_SIZE +# define malloc_getpagesize sysconf(_SC_PAGE_SIZE) +# else +# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE) + extern size_t getpagesize(); +# define malloc_getpagesize getpagesize() +# else +# ifdef WIN32 +# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */ +# else +# ifndef LACKS_SYS_PARAM_H +# include +# endif +# ifdef EXEC_PAGESIZE +# define malloc_getpagesize EXEC_PAGESIZE +# else +# ifdef NBPG +# ifndef CLSIZE +# define malloc_getpagesize NBPG +# else +# define malloc_getpagesize (NBPG * CLSIZE) +# endif +# else +# ifdef NBPC +# define malloc_getpagesize NBPC +# else +# ifdef PAGESIZE +# define malloc_getpagesize PAGESIZE +# else +# define malloc_getpagesize (4096) /* just guess */ +# endif +# endif +# endif +# endif +# endif +# endif +# endif +#endif + + +/* + + This version of malloc supports the standard SVID/XPG mallinfo + routine that returns a struct containing the same kind of + information you can get from malloc_stats. It should work on + any SVID/XPG compliant system that has a /usr/include/malloc.h + defining struct mallinfo. (If you'd like to install such a thing + yourself, cut out the preliminary declarations as described above + and below and save them in a malloc.h file. But there's no + compelling reason to bother to do this.) + + The main declaration needed is the mallinfo struct that is returned + (by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a + bunch of fields, most of which are not even meaningful in this + version of malloc. Some of these fields are are instead filled by + mallinfo() with other numbers that might possibly be of interest. + + HAVE_USR_INCLUDE_MALLOC_H should be set if you have a + /usr/include/malloc.h file that includes a declaration of struct + mallinfo. If so, it is included; else an SVID2/XPG2 compliant + version is declared below. These must be precisely the same for + mallinfo() to work. + +*/ + +/* #define HAVE_USR_INCLUDE_MALLOC_H */ + +#if HAVE_USR_INCLUDE_MALLOC_H +#include "/usr/include/malloc.h" +#else + +/* SVID2/XPG mallinfo structure */ + +struct mallinfo { + int arena; /* total space allocated from system */ + int ordblks; /* number of non-inuse chunks */ + int smblks; /* unused -- always zero */ + int hblks; /* number of mmapped regions */ + int hblkhd; /* total space in mmapped regions */ + int usmblks; /* unused -- always zero */ + int fsmblks; /* unused -- always zero */ + int uordblks; /* total allocated space */ + int fordblks; /* total non-inuse space */ + int keepcost; /* top-most, releasable (via malloc_trim) space */ +}; + +/* SVID2/XPG mallopt options */ + +#define M_MXFAST 1 /* UNUSED in this malloc */ +#define M_NLBLKS 2 /* UNUSED in this malloc */ +#define M_GRAIN 3 /* UNUSED in this malloc */ +#define M_KEEP 4 /* UNUSED in this malloc */ + +#endif + +/* mallopt options that actually do something */ + +#define M_TRIM_THRESHOLD -1 +#define M_TOP_PAD -2 +#define M_MMAP_THRESHOLD -3 +#define M_MMAP_MAX -4 + + +#ifndef DEFAULT_TRIM_THRESHOLD +#define DEFAULT_TRIM_THRESHOLD (128 * 1024) +#endif + +/* + M_TRIM_THRESHOLD is the maximum amount of unused top-most memory + to keep before releasing via malloc_trim in free(). + + Automatic trimming is mainly useful in long-lived programs. + Because trimming via sbrk can be slow on some systems, and can + sometimes be wasteful (in cases where programs immediately + afterward allocate more large chunks) the value should be high + enough so that your overall system performance would improve by + releasing. + + The trim threshold and the mmap control parameters (see below) + can be traded off with one another. Trimming and mmapping are + two different ways of releasing unused memory back to the + system. Between these two, it is often possible to keep + system-level demands of a long-lived program down to a bare + minimum. For example, in one test suite of sessions measuring + the XF86 X server on Linux, using a trim threshold of 128K and a + mmap threshold of 192K led to near-minimal long term resource + consumption. + + If you are using this malloc in a long-lived program, it should + pay to experiment with these values. As a rough guide, you + might set to a value close to the average size of a process + (program) running on your system. Releasing this much memory + would allow such a process to run in memory. Generally, it's + worth it to tune for trimming rather tham memory mapping when a + program undergoes phases where several large chunks are + allocated and released in ways that can reuse each other's + storage, perhaps mixed with phases where there are no such + chunks at all. And in well-behaved long-lived programs, + controlling release of large blocks via trimming versus mapping + is usually faster. + + However, in most programs, these parameters serve mainly as + protection against the system-level effects of carrying around + massive amounts of unneeded memory. Since frequent calls to + sbrk, mmap, and munmap otherwise degrade performance, the default + parameters are set to relatively high values that serve only as + safeguards. + + The default trim value is high enough to cause trimming only in + fairly extreme (by current memory consumption standards) cases. + It must be greater than page size to have any useful effect. To + disable trimming completely, you can set to (unsigned long)(-1); + + +*/ + + +#ifndef DEFAULT_TOP_PAD +#define DEFAULT_TOP_PAD (0) +#endif + +/* + M_TOP_PAD is the amount of extra `padding' space to allocate or + retain whenever sbrk is called. It is used in two ways internally: + + * When sbrk is called to extend the top of the arena to satisfy + a new malloc request, this much padding is added to the sbrk + request. + + * When malloc_trim is called automatically from free(), + it is used as the `pad' argument. + + In both cases, the actual amount of padding is rounded + so that the end of the arena is always a system page boundary. + + The main reason for using padding is to avoid calling sbrk so + often. Having even a small pad greatly reduces the likelihood + that nearly every malloc request during program start-up (or + after trimming) will invoke sbrk, which needlessly wastes + time. + + Automatic rounding-up to page-size units is normally sufficient + to avoid measurable overhead, so the default is 0. However, in + systems where sbrk is relatively slow, it can pay to increase + this value, at the expense of carrying around more memory than + the program needs. + +*/ + + +#ifndef DEFAULT_MMAP_THRESHOLD +#define DEFAULT_MMAP_THRESHOLD (128 * 1024) +#endif + +/* + + M_MMAP_THRESHOLD is the request size threshold for using mmap() + to service a request. Requests of at least this size that cannot + be allocated using already-existing space will be serviced via mmap. + (If enough normal freed space already exists it is used instead.) + + Using mmap segregates relatively large chunks of memory so that + they can be individually obtained and released from the host + system. A request serviced through mmap is never reused by any + other request (at least not directly; the system may just so + happen to remap successive requests to the same locations). + + Segregating space in this way has the benefit that mmapped space + can ALWAYS be individually released back to the system, which + helps keep the system level memory demands of a long-lived + program low. Mapped memory can never become `locked' between + other chunks, as can happen with normally allocated chunks, which + menas that even trimming via malloc_trim would not release them. + + However, it has the disadvantages that: + + 1. The space cannot be reclaimed, consolidated, and then + used to service later requests, as happens with normal chunks. + 2. It can lead to more wastage because of mmap page alignment + requirements + 3. It causes malloc performance to be more dependent on host + system memory management support routines which may vary in + implementation quality and may impose arbitrary + limitations. Generally, servicing a request via normal + malloc steps is faster than going through a system's mmap. + + All together, these considerations should lead you to use mmap + only for relatively large requests. + + +*/ + + +#ifndef DEFAULT_MMAP_MAX +#if HAVE_MMAP +#define DEFAULT_MMAP_MAX (64) +#else +#define DEFAULT_MMAP_MAX (0) +#endif +#endif + +/* + M_MMAP_MAX is the maximum number of requests to simultaneously + service using mmap. This parameter exists because: + + 1. Some systems have a limited number of internal tables for + use by mmap. + 2. In most systems, overreliance on mmap can degrade overall + performance. + 3. If a program allocates many large regions, it is probably + better off using normal sbrk-based allocation routines that + can reclaim and reallocate normal heap memory. Using a + small value allows transition into this mode after the + first few allocations. + + Setting to 0 disables all use of mmap. If HAVE_MMAP is not set, + the default value is 0, and attempts to set it to non-zero values + in mallopt will fail. +*/ + + +/* + USE_DL_PREFIX will prefix all public routines with the string 'dl'. + Useful to quickly avoid procedure declaration conflicts and linker + symbol conflicts with existing memory allocation routines. + +*/ + +/* #define USE_DL_PREFIX */ + + +/* + + Special defines for linux libc + + Except when compiled using these special defines for Linux libc + using weak aliases, this malloc is NOT designed to work in + multithreaded applications. No semaphores or other concurrency + control are provided to ensure that multiple malloc or free calls + don't run at the same time, which could be disasterous. A single + semaphore could be used across malloc, realloc, and free (which is + essentially the effect of the linux weak alias approach). It would + be hard to obtain finer granularity. + +*/ + + +#ifdef INTERNAL_LINUX_C_LIB + +#if __STD_C + +Void_t * __default_morecore_init (ptrdiff_t); +Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init; + +#else + +Void_t * __default_morecore_init (); +Void_t *(*__morecore)() = __default_morecore_init; + +#endif + +#define MORECORE (*__morecore) +#define MORECORE_FAILURE 0 +#define MORECORE_CLEARS 1 + +#else /* INTERNAL_LINUX_C_LIB */ + +#if __STD_C +extern Void_t* sbrk(ptrdiff_t); +#else +extern Void_t* sbrk(); +#endif + +#ifndef MORECORE +#define MORECORE sbrk +#endif + +#ifndef MORECORE_FAILURE +#define MORECORE_FAILURE -1 +#endif + +#ifndef MORECORE_CLEARS +#define MORECORE_CLEARS 1 +#endif + +#endif /* INTERNAL_LINUX_C_LIB */ + +#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__) + +#define cALLOc __libc_calloc +#define fREe __libc_free +#define mALLOc __libc_malloc +#define mEMALIGn __libc_memalign +#define rEALLOc __libc_realloc +#define vALLOc __libc_valloc +#define pvALLOc __libc_pvalloc +#define mALLINFo __libc_mallinfo +#define mALLOPt __libc_mallopt + +#pragma weak calloc = __libc_calloc +#pragma weak free = __libc_free +#pragma weak cfree = __libc_free +#pragma weak malloc = __libc_malloc +#pragma weak memalign = __libc_memalign +#pragma weak realloc = __libc_realloc +#pragma weak valloc = __libc_valloc +#pragma weak pvalloc = __libc_pvalloc +#pragma weak mallinfo = __libc_mallinfo +#pragma weak mallopt = __libc_mallopt + +#else + +#ifdef USE_DL_PREFIX +#define cALLOc dlcalloc +#define fREe dlfree +#define mALLOc dlmalloc +#define mEMALIGn dlmemalign +#define rEALLOc dlrealloc +#define vALLOc dlvalloc +#define pvALLOc dlpvalloc +#define mALLINFo dlmallinfo +#define mALLOPt dlmallopt +#else /* USE_DL_PREFIX */ +#define cALLOc calloc +#define fREe free +#define mALLOc malloc +#define mEMALIGn memalign +#define rEALLOc realloc +#define vALLOc valloc +#define pvALLOc pvalloc +#define mALLINFo mallinfo +#define mALLOPt mallopt +#endif /* USE_DL_PREFIX */ + +#endif + +/* Public routines */ + +#if __STD_C + +Void_t* mALLOc(size_t); +void fREe(Void_t*); +Void_t* rEALLOc(Void_t*, size_t); +Void_t* mEMALIGn(size_t, size_t); +Void_t* vALLOc(size_t); +Void_t* pvALLOc(size_t); +Void_t* cALLOc(size_t, size_t); +void cfree(Void_t*); +int malloc_trim(size_t); +size_t malloc_usable_size(Void_t*); +void malloc_stats(); +int mALLOPt(int, int); +struct mallinfo mALLINFo(void); +#else +Void_t* mALLOc(); +void fREe(); +Void_t* rEALLOc(); +Void_t* mEMALIGn(); +Void_t* vALLOc(); +Void_t* pvALLOc(); +Void_t* cALLOc(); +void cfree(); +int malloc_trim(); +size_t malloc_usable_size(); +void malloc_stats(); +int mALLOPt(); +struct mallinfo mALLINFo(); +#endif + + +#ifdef __cplusplus +}; /* end of extern "C" */ +#endif + +/* ---------- To make a malloc.h, end cutting here ------------ */ +#else /* Moved to malloc.h */ + +#include +#if 0 +#if __STD_C +static void malloc_update_mallinfo (void); +void malloc_stats (void); +#else +static void malloc_update_mallinfo (); +void malloc_stats(); +#endif +#endif /* 0 */ + +#endif /* 0 */ /* Moved to malloc.h */ +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + Emulation of sbrk for WIN32 + All code within the ifdef WIN32 is untested by me. + + Thanks to Martin Fong and others for supplying this. +*/ + + +#ifdef WIN32 + +#define AlignPage(add) (((add) + (malloc_getpagesize-1)) & \ +~(malloc_getpagesize-1)) +#define AlignPage64K(add) (((add) + (0x10000 - 1)) & ~(0x10000 - 1)) + +/* resrve 64MB to insure large contiguous space */ +#define RESERVED_SIZE (1024*1024*64) +#define NEXT_SIZE (2048*1024) +#define TOP_MEMORY ((unsigned long)2*1024*1024*1024) + +struct GmListElement; +typedef struct GmListElement GmListElement; + +struct GmListElement +{ + GmListElement* next; + void* base; +}; + +static GmListElement* head = 0; +static unsigned int gNextAddress = 0; +static unsigned int gAddressBase = 0; +static unsigned int gAllocatedSize = 0; + +static +GmListElement* makeGmListElement (void* bas) +{ + GmListElement* this; + this = (GmListElement*)(void*)LocalAlloc (0, sizeof (GmListElement)); + assert (this); + if (this) + { + this->base = bas; + this->next = head; + head = this; + } + return this; +} + +void gcleanup () +{ + BOOL rval; + assert ( (head == NULL) || (head->base == (void*)gAddressBase)); + if (gAddressBase && (gNextAddress - gAddressBase)) + { + rval = VirtualFree ((void*)gAddressBase, + gNextAddress - gAddressBase, + MEM_DECOMMIT); + assert (rval); + } + while (head) + { + GmListElement* next = head->next; + rval = VirtualFree (head->base, 0, MEM_RELEASE); + assert (rval); + LocalFree (head); + head = next; + } +} + +static +void* findRegion (void* start_address, unsigned long size) +{ + MEMORY_BASIC_INFORMATION info; + if (size >= TOP_MEMORY) return NULL; + + while ((unsigned long)start_address + size < TOP_MEMORY) + { + VirtualQuery (start_address, &info, sizeof (info)); + if ((info.State == MEM_FREE) && (info.RegionSize >= size)) + return start_address; + else + { + /* Requested region is not available so see if the */ + /* next region is available. Set 'start_address' */ + /* to the next region and call 'VirtualQuery()' */ + /* again. */ + + start_address = (char*)info.BaseAddress + info.RegionSize; + + /* Make sure we start looking for the next region */ + /* on the *next* 64K boundary. Otherwise, even if */ + /* the new region is free according to */ + /* 'VirtualQuery()', the subsequent call to */ + /* 'VirtualAlloc()' (which follows the call to */ + /* this routine in 'wsbrk()') will round *down* */ + /* the requested address to a 64K boundary which */ + /* we already know is an address in the */ + /* unavailable region. Thus, the subsequent call */ + /* to 'VirtualAlloc()' will fail and bring us back */ + /* here, causing us to go into an infinite loop. */ + + start_address = + (void *) AlignPage64K((unsigned long) start_address); + } + } + return NULL; + +} + + +void* wsbrk (long size) +{ + void* tmp; + if (size > 0) + { + if (gAddressBase == 0) + { + gAllocatedSize = max (RESERVED_SIZE, AlignPage (size)); + gNextAddress = gAddressBase = + (unsigned int)VirtualAlloc (NULL, gAllocatedSize, + MEM_RESERVE, PAGE_NOACCESS); + } else if (AlignPage (gNextAddress + size) > (gAddressBase + +gAllocatedSize)) + { + long new_size = max (NEXT_SIZE, AlignPage (size)); + void* new_address = (void*)(gAddressBase+gAllocatedSize); + do + { + new_address = findRegion (new_address, new_size); + + if (new_address == 0) + return (void*)-1; + + gAddressBase = gNextAddress = + (unsigned int)VirtualAlloc (new_address, new_size, + MEM_RESERVE, PAGE_NOACCESS); + /* repeat in case of race condition */ + /* The region that we found has been snagged */ + /* by another thread */ + } + while (gAddressBase == 0); + + assert (new_address == (void*)gAddressBase); + + gAllocatedSize = new_size; + + if (!makeGmListElement ((void*)gAddressBase)) + return (void*)-1; + } + if ((size + gNextAddress) > AlignPage (gNextAddress)) + { + void* res; + res = VirtualAlloc ((void*)AlignPage (gNextAddress), + (size + gNextAddress - + AlignPage (gNextAddress)), + MEM_COMMIT, PAGE_READWRITE); + if (res == 0) + return (void*)-1; + } + tmp = (void*)gNextAddress; + gNextAddress = (unsigned int)tmp + size; + return tmp; + } + else if (size < 0) + { + unsigned int alignedGoal = AlignPage (gNextAddress + size); + /* Trim by releasing the virtual memory */ + if (alignedGoal >= gAddressBase) + { + VirtualFree ((void*)alignedGoal, gNextAddress - alignedGoal, + MEM_DECOMMIT); + gNextAddress = gNextAddress + size; + return (void*)gNextAddress; + } + else + { + VirtualFree ((void*)gAddressBase, gNextAddress - gAddressBase, + MEM_DECOMMIT); + gNextAddress = gAddressBase; + return (void*)-1; + } + } + else + { + return (void*)gNextAddress; + } +} + +#endif + + + +/* + Type declarations +*/ + + +struct malloc_chunk +{ + INTERNAL_SIZE_T prev_size; /* Size of previous chunk (if free). */ + INTERNAL_SIZE_T size; /* Size in bytes, including overhead. */ + struct malloc_chunk* fd; /* double links -- used only if free. */ + struct malloc_chunk* bk; +}; + +typedef struct malloc_chunk* mchunkptr; + +/* + + malloc_chunk details: + + (The following includes lightly edited explanations by Colin Plumb.) + + Chunks of memory are maintained using a `boundary tag' method as + described in e.g., Knuth or Standish. (See the paper by Paul + Wilson ftp://ftp.cs.utexas.edu/pub/garbage/allocsrv.ps for a + survey of such techniques.) Sizes of free chunks are stored both + in the front of each chunk and at the end. This makes + consolidating fragmented chunks into bigger chunks very fast. The + size fields also hold bits representing whether chunks are free or + in use. + + An allocated chunk looks like this: + + + chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of previous chunk, if allocated | | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of chunk, in bytes |P| + mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | User data starts here... . + . . + . (malloc_usable_space() bytes) . + . | +nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of chunk | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + + Where "chunk" is the front of the chunk for the purpose of most of + the malloc code, but "mem" is the pointer that is returned to the + user. "Nextchunk" is the beginning of the next contiguous chunk. + + Chunks always begin on even word boundries, so the mem portion + (which is returned to the user) is also on an even word boundary, and + thus double-word aligned. + + Free chunks are stored in circular doubly-linked lists, and look like this: + + chunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Size of previous chunk | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + `head:' | Size of chunk, in bytes |P| + mem-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Forward pointer to next chunk in list | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Back pointer to previous chunk in list | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Unused space (may be 0 bytes long) . + . . + . | +nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + `foot:' | Size of chunk, in bytes | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + The P (PREV_INUSE) bit, stored in the unused low-order bit of the + chunk size (which is always a multiple of two words), is an in-use + bit for the *previous* chunk. If that bit is *clear*, then the + word before the current chunk size contains the previous chunk + size, and can be used to find the front of the previous chunk. + (The very first chunk allocated always has this bit set, + preventing access to non-existent (or non-owned) memory.) + + Note that the `foot' of the current chunk is actually represented + as the prev_size of the NEXT chunk. (This makes it easier to + deal with alignments etc). + + The two exceptions to all this are + + 1. The special chunk `top', which doesn't bother using the + trailing size field since there is no + next contiguous chunk that would have to index off it. (After + initialization, `top' is forced to always exist. If it would + become less than MINSIZE bytes long, it is replenished via + malloc_extend_top.) + + 2. Chunks allocated via mmap, which have the second-lowest-order + bit (IS_MMAPPED) set in their size fields. Because they are + never merged or traversed from any other chunk, they have no + foot size or inuse information. + + Available chunks are kept in any of several places (all declared below): + + * `av': An array of chunks serving as bin headers for consolidated + chunks. Each bin is doubly linked. The bins are approximately + proportionally (log) spaced. There are a lot of these bins + (128). This may look excessive, but works very well in + practice. All procedures maintain the invariant that no + consolidated chunk physically borders another one. Chunks in + bins are kept in size order, with ties going to the + approximately least recently used chunk. + + The chunks in each bin are maintained in decreasing sorted order by + size. This is irrelevant for the small bins, which all contain + the same-sized chunks, but facilitates best-fit allocation for + larger chunks. (These lists are just sequential. Keeping them in + order almost never requires enough traversal to warrant using + fancier ordered data structures.) Chunks of the same size are + linked with the most recently freed at the front, and allocations + are taken from the back. This results in LRU or FIFO allocation + order, which tends to give each chunk an equal opportunity to be + consolidated with adjacent freed chunks, resulting in larger free + chunks and less fragmentation. + + * `top': The top-most available chunk (i.e., the one bordering the + end of available memory) is treated specially. It is never + included in any bin, is used only if no other chunk is + available, and is released back to the system if it is very + large (see M_TRIM_THRESHOLD). + + * `last_remainder': A bin holding only the remainder of the + most recently split (non-top) chunk. This bin is checked + before other non-fitting chunks, so as to provide better + locality for runs of sequentially allocated chunks. + + * Implicitly, through the host system's memory mapping tables. + If supported, requests greater than a threshold are usually + serviced via calls to mmap, and then later released via munmap. + +*/ + +/* sizes, alignments */ + +#define SIZE_SZ (sizeof(INTERNAL_SIZE_T)) +#define MALLOC_ALIGNMENT (SIZE_SZ + SIZE_SZ) +#define MALLOC_ALIGN_MASK (MALLOC_ALIGNMENT - 1) +#define MINSIZE (sizeof(struct malloc_chunk)) + +/* conversion from malloc headers to user pointers, and back */ + +#define chunk2mem(p) ((Void_t*)((char*)(p) + 2*SIZE_SZ)) +#define mem2chunk(mem) ((mchunkptr)((char*)(mem) - 2*SIZE_SZ)) + +/* pad request bytes into a usable size */ + +#define request2size(req) \ + (((long)((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \ + (long)(MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \ + (((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) & ~(MALLOC_ALIGN_MASK))) + +/* Check if m has acceptable alignment */ + +#define aligned_OK(m) (((unsigned long)((m)) & (MALLOC_ALIGN_MASK)) == 0) + + + + +/* + Physical chunk operations +*/ + + +/* size field is or'ed with PREV_INUSE when previous adjacent chunk in use */ + +#define PREV_INUSE 0x1 + +/* size field is or'ed with IS_MMAPPED if the chunk was obtained with mmap() */ + +#define IS_MMAPPED 0x2 + +/* Bits to mask off when extracting size */ + +#define SIZE_BITS (PREV_INUSE|IS_MMAPPED) + + +/* Ptr to next physical malloc_chunk. */ + +#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~PREV_INUSE) )) + +/* Ptr to previous physical malloc_chunk */ + +#define prev_chunk(p)\ + ((mchunkptr)( ((char*)(p)) - ((p)->prev_size) )) + + +/* Treat space at ptr + offset as a chunk */ + +#define chunk_at_offset(p, s) ((mchunkptr)(((char*)(p)) + (s))) + + + + +/* + Dealing with use bits +*/ + +/* extract p's inuse bit */ + +#define inuse(p)\ +((((mchunkptr)(((char*)(p))+((p)->size & ~PREV_INUSE)))->size) & PREV_INUSE) + +/* extract inuse bit of previous chunk */ + +#define prev_inuse(p) ((p)->size & PREV_INUSE) + +/* check for mmap()'ed chunk */ + +#define chunk_is_mmapped(p) ((p)->size & IS_MMAPPED) + +/* set/clear chunk as in use without otherwise disturbing */ + +#define set_inuse(p)\ +((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size |= PREV_INUSE + +#define clear_inuse(p)\ +((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size &= ~(PREV_INUSE) + +/* check/set/clear inuse bits in known places */ + +#define inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size & PREV_INUSE) + +#define set_inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size |= PREV_INUSE) + +#define clear_inuse_bit_at_offset(p, s)\ + (((mchunkptr)(((char*)(p)) + (s)))->size &= ~(PREV_INUSE)) + + + + +/* + Dealing with size fields +*/ + +/* Get size, ignoring use bits */ + +#define chunksize(p) ((p)->size & ~(SIZE_BITS)) + +/* Set size at head, without disturbing its use bit */ + +#define set_head_size(p, s) ((p)->size = (((p)->size & PREV_INUSE) | (s))) + +/* Set size/use ignoring previous bits in header */ + +#define set_head(p, s) ((p)->size = (s)) + +/* Set size at footer (only when chunk is not in use) */ + +#define set_foot(p, s) (((mchunkptr)((char*)(p) + (s)))->prev_size = (s)) + + + + + +/* + Bins + + The bins, `av_' are an array of pairs of pointers serving as the + heads of (initially empty) doubly-linked lists of chunks, laid out + in a way so that each pair can be treated as if it were in a + malloc_chunk. (This way, the fd/bk offsets for linking bin heads + and chunks are the same). + + Bins for sizes < 512 bytes contain chunks of all the same size, spaced + 8 bytes apart. Larger bins are approximately logarithmically + spaced. (See the table below.) The `av_' array is never mentioned + directly in the code, but instead via bin access macros. + + Bin layout: + + 64 bins of size 8 + 32 bins of size 64 + 16 bins of size 512 + 8 bins of size 4096 + 4 bins of size 32768 + 2 bins of size 262144 + 1 bin of size what's left + + There is actually a little bit of slop in the numbers in bin_index + for the sake of speed. This makes no difference elsewhere. + + The special chunks `top' and `last_remainder' get their own bins, + (this is implemented via yet more trickery with the av_ array), + although `top' is never properly linked to its bin since it is + always handled specially. + +*/ + +#define NAV 128 /* number of bins */ + +typedef struct malloc_chunk* mbinptr; + +/* access macros */ + +#define bin_at(i) ((mbinptr)((char*)&(av_[2*(i) + 2]) - 2*SIZE_SZ)) +#define next_bin(b) ((mbinptr)((char*)(b) + 2 * sizeof(mbinptr))) +#define prev_bin(b) ((mbinptr)((char*)(b) - 2 * sizeof(mbinptr))) + +/* + The first 2 bins are never indexed. The corresponding av_ cells are instead + used for bookkeeping. This is not to save space, but to simplify + indexing, maintain locality, and avoid some initialization tests. +*/ + +#define top (bin_at(0)->fd) /* The topmost chunk */ +#define last_remainder (bin_at(1)) /* remainder from last split */ + + +/* + Because top initially points to its own bin with initial + zero size, thus forcing extension on the first malloc request, + we avoid having any special code in malloc to check whether + it even exists yet. But we still need to in malloc_extend_top. +*/ + +#define initial_top ((mchunkptr)(bin_at(0))) + +/* Helper macro to initialize bins */ + +#define IAV(i) bin_at(i), bin_at(i) + +static mbinptr av_[NAV * 2 + 2] = { + 0, 0, + IAV(0), IAV(1), IAV(2), IAV(3), IAV(4), IAV(5), IAV(6), IAV(7), + IAV(8), IAV(9), IAV(10), IAV(11), IAV(12), IAV(13), IAV(14), IAV(15), + IAV(16), IAV(17), IAV(18), IAV(19), IAV(20), IAV(21), IAV(22), IAV(23), + IAV(24), IAV(25), IAV(26), IAV(27), IAV(28), IAV(29), IAV(30), IAV(31), + IAV(32), IAV(33), IAV(34), IAV(35), IAV(36), IAV(37), IAV(38), IAV(39), + IAV(40), IAV(41), IAV(42), IAV(43), IAV(44), IAV(45), IAV(46), IAV(47), + IAV(48), IAV(49), IAV(50), IAV(51), IAV(52), IAV(53), IAV(54), IAV(55), + IAV(56), IAV(57), IAV(58), IAV(59), IAV(60), IAV(61), IAV(62), IAV(63), + IAV(64), IAV(65), IAV(66), IAV(67), IAV(68), IAV(69), IAV(70), IAV(71), + IAV(72), IAV(73), IAV(74), IAV(75), IAV(76), IAV(77), IAV(78), IAV(79), + IAV(80), IAV(81), IAV(82), IAV(83), IAV(84), IAV(85), IAV(86), IAV(87), + IAV(88), IAV(89), IAV(90), IAV(91), IAV(92), IAV(93), IAV(94), IAV(95), + IAV(96), IAV(97), IAV(98), IAV(99), IAV(100), IAV(101), IAV(102), IAV(103), + IAV(104), IAV(105), IAV(106), IAV(107), IAV(108), IAV(109), IAV(110), IAV(111), + IAV(112), IAV(113), IAV(114), IAV(115), IAV(116), IAV(117), IAV(118), IAV(119), + IAV(120), IAV(121), IAV(122), IAV(123), IAV(124), IAV(125), IAV(126), IAV(127) +}; + +void malloc_bin_reloc (void) +{ + unsigned long *p = (unsigned long *)(&av_[2]); + int i; + for (i=2; i<(sizeof(av_)/sizeof(mbinptr)); ++i) { + *p++ += gd->reloc_off; + } +} + + +/* field-extraction macros */ + +#define first(b) ((b)->fd) +#define last(b) ((b)->bk) + +/* + Indexing into bins +*/ + +#define bin_index(sz) \ +(((((unsigned long)(sz)) >> 9) == 0) ? (((unsigned long)(sz)) >> 3): \ + ((((unsigned long)(sz)) >> 9) <= 4) ? 56 + (((unsigned long)(sz)) >> 6): \ + ((((unsigned long)(sz)) >> 9) <= 20) ? 91 + (((unsigned long)(sz)) >> 9): \ + ((((unsigned long)(sz)) >> 9) <= 84) ? 110 + (((unsigned long)(sz)) >> 12): \ + ((((unsigned long)(sz)) >> 9) <= 340) ? 119 + (((unsigned long)(sz)) >> 15): \ + ((((unsigned long)(sz)) >> 9) <= 1364) ? 124 + (((unsigned long)(sz)) >> 18): \ + 126) +/* + bins for chunks < 512 are all spaced 8 bytes apart, and hold + identically sized chunks. This is exploited in malloc. +*/ + +#define MAX_SMALLBIN 63 +#define MAX_SMALLBIN_SIZE 512 +#define SMALLBIN_WIDTH 8 + +#define smallbin_index(sz) (((unsigned long)(sz)) >> 3) + +/* + Requests are `small' if both the corresponding and the next bin are small +*/ + +#define is_small_request(nb) (nb < MAX_SMALLBIN_SIZE - SMALLBIN_WIDTH) + + + +/* + To help compensate for the large number of bins, a one-level index + structure is used for bin-by-bin searching. `binblocks' is a + one-word bitvector recording whether groups of BINBLOCKWIDTH bins + have any (possibly) non-empty bins, so they can be skipped over + all at once during during traversals. The bits are NOT always + cleared as soon as all bins in a block are empty, but instead only + when all are noticed to be empty during traversal in malloc. +*/ + +#define BINBLOCKWIDTH 4 /* bins per block */ + +#define binblocks (bin_at(0)->size) /* bitvector of nonempty blocks */ + +/* bin<->block macros */ + +#define idx2binblock(ix) ((unsigned)1 << (ix / BINBLOCKWIDTH)) +#define mark_binblock(ii) (binblocks |= idx2binblock(ii)) +#define clear_binblock(ii) (binblocks &= ~(idx2binblock(ii))) + + + + + +/* Other static bookkeeping data */ + +/* variables holding tunable values */ + +static unsigned long trim_threshold = DEFAULT_TRIM_THRESHOLD; +static unsigned long top_pad = DEFAULT_TOP_PAD; +static unsigned int n_mmaps_max = DEFAULT_MMAP_MAX; +static unsigned long mmap_threshold = DEFAULT_MMAP_THRESHOLD; + +/* The first value returned from sbrk */ +static char* sbrk_base = (char*)(-1); + +/* The maximum memory obtained from system via sbrk */ +static unsigned long max_sbrked_mem = 0; + +/* The maximum via either sbrk or mmap */ +static unsigned long max_total_mem = 0; + +/* internal working copy of mallinfo */ +static struct mallinfo current_mallinfo = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + +/* The total memory obtained from system via sbrk */ +#define sbrked_mem (current_mallinfo.arena) + +/* Tracking mmaps */ + +#if 0 +static unsigned int n_mmaps = 0; +#endif /* 0 */ +static unsigned long mmapped_mem = 0; +#if HAVE_MMAP +static unsigned int max_n_mmaps = 0; +static unsigned long max_mmapped_mem = 0; +#endif + + + +/* + Debugging support +*/ + +#ifdef DEBUG + + +/* + These routines make a number of assertions about the states + of data structures that should be true at all times. If any + are not true, it's very likely that a user program has somehow + trashed memory. (It's also possible that there is a coding error + in malloc. In which case, please report it!) +*/ + +#if __STD_C +static void do_check_chunk(mchunkptr p) +#else +static void do_check_chunk(p) mchunkptr p; +#endif +{ +#if 0 /* causes warnings because assert() is off */ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; +#endif /* 0 */ + + /* No checkable chunk is mmapped */ + assert(!chunk_is_mmapped(p)); + + /* Check for legal address ... */ + assert((char*)p >= sbrk_base); + if (p != top) + assert((char*)p + sz <= (char*)top); + else + assert((char*)p + sz <= sbrk_base + sbrked_mem); + +} + + +#if __STD_C +static void do_check_free_chunk(mchunkptr p) +#else +static void do_check_free_chunk(p) mchunkptr p; +#endif +{ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; +#if 0 /* causes warnings because assert() is off */ + mchunkptr next = chunk_at_offset(p, sz); +#endif /* 0 */ + + do_check_chunk(p); + + /* Check whether it claims to be free ... */ + assert(!inuse(p)); + + /* Unless a special marker, must have OK fields */ + if ((long)sz >= (long)MINSIZE) + { + assert((sz & MALLOC_ALIGN_MASK) == 0); + assert(aligned_OK(chunk2mem(p))); + /* ... matching footer field */ + assert(next->prev_size == sz); + /* ... and is fully consolidated */ + assert(prev_inuse(p)); + assert (next == top || inuse(next)); + + /* ... and has minimally sane links */ + assert(p->fd->bk == p); + assert(p->bk->fd == p); + } + else /* markers are always of size SIZE_SZ */ + assert(sz == SIZE_SZ); +} + +#if __STD_C +static void do_check_inuse_chunk(mchunkptr p) +#else +static void do_check_inuse_chunk(p) mchunkptr p; +#endif +{ + mchunkptr next = next_chunk(p); + do_check_chunk(p); + + /* Check whether it claims to be in use ... */ + assert(inuse(p)); + + /* ... and is surrounded by OK chunks. + Since more things can be checked with free chunks than inuse ones, + if an inuse chunk borders them and debug is on, it's worth doing them. + */ + if (!prev_inuse(p)) + { + mchunkptr prv = prev_chunk(p); + assert(next_chunk(prv) == p); + do_check_free_chunk(prv); + } + if (next == top) + { + assert(prev_inuse(next)); + assert(chunksize(next) >= MINSIZE); + } + else if (!inuse(next)) + do_check_free_chunk(next); + +} + +#if __STD_C +static void do_check_malloced_chunk(mchunkptr p, INTERNAL_SIZE_T s) +#else +static void do_check_malloced_chunk(p, s) mchunkptr p; INTERNAL_SIZE_T s; +#endif +{ +#if 0 /* causes warnings because assert() is off */ + INTERNAL_SIZE_T sz = p->size & ~PREV_INUSE; + long room = sz - s; +#endif /* 0 */ + + do_check_inuse_chunk(p); + + /* Legal size ... */ + assert((long)sz >= (long)MINSIZE); + assert((sz & MALLOC_ALIGN_MASK) == 0); + assert(room >= 0); + assert(room < (long)MINSIZE); + + /* ... and alignment */ + assert(aligned_OK(chunk2mem(p))); + + + /* ... and was allocated at front of an available chunk */ + assert(prev_inuse(p)); + +} + + +#define check_free_chunk(P) do_check_free_chunk(P) +#define check_inuse_chunk(P) do_check_inuse_chunk(P) +#define check_chunk(P) do_check_chunk(P) +#define check_malloced_chunk(P,N) do_check_malloced_chunk(P,N) +#else +#define check_free_chunk(P) +#define check_inuse_chunk(P) +#define check_chunk(P) +#define check_malloced_chunk(P,N) +#endif + + + +/* + Macro-based internal utilities +*/ + + +/* + Linking chunks in bin lists. + Call these only with variables, not arbitrary expressions, as arguments. +*/ + +/* + Place chunk p of size s in its bin, in size order, + putting it ahead of others of same size. +*/ + + +#define frontlink(P, S, IDX, BK, FD) \ +{ \ + if (S < MAX_SMALLBIN_SIZE) \ + { \ + IDX = smallbin_index(S); \ + mark_binblock(IDX); \ + BK = bin_at(IDX); \ + FD = BK->fd; \ + P->bk = BK; \ + P->fd = FD; \ + FD->bk = BK->fd = P; \ + } \ + else \ + { \ + IDX = bin_index(S); \ + BK = bin_at(IDX); \ + FD = BK->fd; \ + if (FD == BK) mark_binblock(IDX); \ + else \ + { \ + while (FD != BK && S < chunksize(FD)) FD = FD->fd; \ + BK = FD->bk; \ + } \ + P->bk = BK; \ + P->fd = FD; \ + FD->bk = BK->fd = P; \ + } \ +} + + +/* take a chunk off a list */ + +#define unlink(P, BK, FD) \ +{ \ + BK = P->bk; \ + FD = P->fd; \ + FD->bk = BK; \ + BK->fd = FD; \ +} \ + +/* Place p as the last remainder */ + +#define link_last_remainder(P) \ +{ \ + last_remainder->fd = last_remainder->bk = P; \ + P->fd = P->bk = last_remainder; \ +} + +/* Clear the last_remainder bin */ + +#define clear_last_remainder \ + (last_remainder->fd = last_remainder->bk = last_remainder) + + + + + +/* Routines dealing with mmap(). */ + +#if HAVE_MMAP + +#if __STD_C +static mchunkptr mmap_chunk(size_t size) +#else +static mchunkptr mmap_chunk(size) size_t size; +#endif +{ + size_t page_mask = malloc_getpagesize - 1; + mchunkptr p; + +#ifndef MAP_ANONYMOUS + static int fd = -1; +#endif + + if(n_mmaps >= n_mmaps_max) return 0; /* too many regions */ + + /* For mmapped chunks, the overhead is one SIZE_SZ unit larger, because + * there is no following chunk whose prev_size field could be used. + */ + size = (size + SIZE_SZ + page_mask) & ~page_mask; + +#ifdef MAP_ANONYMOUS + p = (mchunkptr)mmap(0, size, PROT_READ|PROT_WRITE, + MAP_PRIVATE|MAP_ANONYMOUS, -1, 0); +#else /* !MAP_ANONYMOUS */ + if (fd < 0) + { + fd = open("/dev/zero", O_RDWR); + if(fd < 0) return 0; + } + p = (mchunkptr)mmap(0, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0); +#endif + + if(p == (mchunkptr)-1) return 0; + + n_mmaps++; + if (n_mmaps > max_n_mmaps) max_n_mmaps = n_mmaps; + + /* We demand that eight bytes into a page must be 8-byte aligned. */ + assert(aligned_OK(chunk2mem(p))); + + /* The offset to the start of the mmapped region is stored + * in the prev_size field of the chunk; normally it is zero, + * but that can be changed in memalign(). + */ + p->prev_size = 0; + set_head(p, size|IS_MMAPPED); + + mmapped_mem += size; + if ((unsigned long)mmapped_mem > (unsigned long)max_mmapped_mem) + max_mmapped_mem = mmapped_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + return p; +} + +#if __STD_C +static void munmap_chunk(mchunkptr p) +#else +static void munmap_chunk(p) mchunkptr p; +#endif +{ + INTERNAL_SIZE_T size = chunksize(p); + int ret; + + assert (chunk_is_mmapped(p)); + assert(! ((char*)p >= sbrk_base && (char*)p < sbrk_base + sbrked_mem)); + assert((n_mmaps > 0)); + assert(((p->prev_size + size) & (malloc_getpagesize-1)) == 0); + + n_mmaps--; + mmapped_mem -= (size + p->prev_size); + + ret = munmap((char *)p - p->prev_size, size + p->prev_size); + + /* munmap returns non-zero on failure */ + assert(ret == 0); +} + +#if HAVE_MREMAP + +#if __STD_C +static mchunkptr mremap_chunk(mchunkptr p, size_t new_size) +#else +static mchunkptr mremap_chunk(p, new_size) mchunkptr p; size_t new_size; +#endif +{ + size_t page_mask = malloc_getpagesize - 1; + INTERNAL_SIZE_T offset = p->prev_size; + INTERNAL_SIZE_T size = chunksize(p); + char *cp; + + assert (chunk_is_mmapped(p)); + assert(! ((char*)p >= sbrk_base && (char*)p < sbrk_base + sbrked_mem)); + assert((n_mmaps > 0)); + assert(((size + offset) & (malloc_getpagesize-1)) == 0); + + /* Note the extra SIZE_SZ overhead as in mmap_chunk(). */ + new_size = (new_size + offset + SIZE_SZ + page_mask) & ~page_mask; + + cp = (char *)mremap((char *)p - offset, size + offset, new_size, 1); + + if (cp == (char *)-1) return 0; + + p = (mchunkptr)(cp + offset); + + assert(aligned_OK(chunk2mem(p))); + + assert((p->prev_size == offset)); + set_head(p, (new_size - offset)|IS_MMAPPED); + + mmapped_mem -= size + offset; + mmapped_mem += new_size; + if ((unsigned long)mmapped_mem > (unsigned long)max_mmapped_mem) + max_mmapped_mem = mmapped_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + return p; +} + +#endif /* HAVE_MREMAP */ + +#endif /* HAVE_MMAP */ + + + + +/* + Extend the top-most chunk by obtaining memory from system. + Main interface to sbrk (but see also malloc_trim). +*/ + +#if __STD_C +static void malloc_extend_top(INTERNAL_SIZE_T nb) +#else +static void malloc_extend_top(nb) INTERNAL_SIZE_T nb; +#endif +{ + char* brk; /* return value from sbrk */ + INTERNAL_SIZE_T front_misalign; /* unusable bytes at front of sbrked space */ + INTERNAL_SIZE_T correction; /* bytes for 2nd sbrk call */ + char* new_brk; /* return of 2nd sbrk call */ + INTERNAL_SIZE_T top_size; /* new size of top chunk */ + + mchunkptr old_top = top; /* Record state of old top */ + INTERNAL_SIZE_T old_top_size = chunksize(old_top); + char* old_end = (char*)(chunk_at_offset(old_top, old_top_size)); + + /* Pad request with top_pad plus minimal overhead */ + + INTERNAL_SIZE_T sbrk_size = nb + top_pad + MINSIZE; + unsigned long pagesz = malloc_getpagesize; + + /* If not the first time through, round to preserve page boundary */ + /* Otherwise, we need to correct to a page size below anyway. */ + /* (We also correct below if an intervening foreign sbrk call.) */ + + if (sbrk_base != (char*)(-1)) + sbrk_size = (sbrk_size + (pagesz - 1)) & ~(pagesz - 1); + + brk = (char*)(MORECORE (sbrk_size)); + + /* Fail if sbrk failed or if a foreign sbrk call killed our space */ + if (brk == (char*)(MORECORE_FAILURE) || + (brk < old_end && old_top != initial_top)) + return; + + sbrked_mem += sbrk_size; + + if (brk == old_end) /* can just add bytes to current top */ + { + top_size = sbrk_size + old_top_size; + set_head(top, top_size | PREV_INUSE); + } + else + { + if (sbrk_base == (char*)(-1)) /* First time through. Record base */ + sbrk_base = brk; + else /* Someone else called sbrk(). Count those bytes as sbrked_mem. */ + sbrked_mem += brk - (char*)old_end; + + /* Guarantee alignment of first new chunk made from this space */ + front_misalign = (unsigned long)chunk2mem(brk) & MALLOC_ALIGN_MASK; + if (front_misalign > 0) + { + correction = (MALLOC_ALIGNMENT) - front_misalign; + brk += correction; + } + else + correction = 0; + + /* Guarantee the next brk will be at a page boundary */ + + correction += ((((unsigned long)(brk + sbrk_size))+(pagesz-1)) & + ~(pagesz - 1)) - ((unsigned long)(brk + sbrk_size)); + + /* Allocate correction */ + new_brk = (char*)(MORECORE (correction)); + if (new_brk == (char*)(MORECORE_FAILURE)) return; + + sbrked_mem += correction; + + top = (mchunkptr)brk; + top_size = new_brk - brk + correction; + set_head(top, top_size | PREV_INUSE); + + if (old_top != initial_top) + { + + /* There must have been an intervening foreign sbrk call. */ + /* A double fencepost is necessary to prevent consolidation */ + + /* If not enough space to do this, then user did something very wrong */ + if (old_top_size < MINSIZE) + { + set_head(top, PREV_INUSE); /* will force null return from malloc */ + return; + } + + /* Also keep size a multiple of MALLOC_ALIGNMENT */ + old_top_size = (old_top_size - 3*SIZE_SZ) & ~MALLOC_ALIGN_MASK; + set_head_size(old_top, old_top_size); + chunk_at_offset(old_top, old_top_size )->size = + SIZE_SZ|PREV_INUSE; + chunk_at_offset(old_top, old_top_size + SIZE_SZ)->size = + SIZE_SZ|PREV_INUSE; + /* If possible, release the rest. */ + if (old_top_size >= MINSIZE) + fREe(chunk2mem(old_top)); + } + } + + if ((unsigned long)sbrked_mem > (unsigned long)max_sbrked_mem) + max_sbrked_mem = sbrked_mem; + if ((unsigned long)(mmapped_mem + sbrked_mem) > (unsigned long)max_total_mem) + max_total_mem = mmapped_mem + sbrked_mem; + + /* We always land on a page boundary */ + assert(((unsigned long)((char*)top + top_size) & (pagesz - 1)) == 0); +} + + + + +/* Main public routines */ + + +/* + Malloc Algorthim: + + The requested size is first converted into a usable form, `nb'. + This currently means to add 4 bytes overhead plus possibly more to + obtain 8-byte alignment and/or to obtain a size of at least + MINSIZE (currently 16 bytes), the smallest allocatable size. + (All fits are considered `exact' if they are within MINSIZE bytes.) + + From there, the first successful of the following steps is taken: + + 1. The bin corresponding to the request size is scanned, and if + a chunk of exactly the right size is found, it is taken. + + 2. The most recently remaindered chunk is used if it is big + enough. This is a form of (roving) first fit, used only in + the absence of exact fits. Runs of consecutive requests use + the remainder of the chunk used for the previous such request + whenever possible. This limited use of a first-fit style + allocation strategy tends to give contiguous chunks + coextensive lifetimes, which improves locality and can reduce + fragmentation in the long run. + + 3. Other bins are scanned in increasing size order, using a + chunk big enough to fulfill the request, and splitting off + any remainder. This search is strictly by best-fit; i.e., + the smallest (with ties going to approximately the least + recently used) chunk that fits is selected. + + 4. If large enough, the chunk bordering the end of memory + (`top') is split off. (This use of `top' is in accord with + the best-fit search rule. In effect, `top' is treated as + larger (and thus less well fitting) than any other available + chunk since it can be extended to be as large as necessary + (up to system limitations). + + 5. If the request size meets the mmap threshold and the + system supports mmap, and there are few enough currently + allocated mmapped regions, and a call to mmap succeeds, + the request is allocated via direct memory mapping. + + 6. Otherwise, the top of memory is extended by + obtaining more space from the system (normally using sbrk, + but definable to anything else via the MORECORE macro). + Memory is gathered from the system (in system page-sized + units) in a way that allows chunks obtained across different + sbrk calls to be consolidated, but does not require + contiguous memory. Thus, it should be safe to intersperse + mallocs with other sbrk calls. + + + All allocations are made from the the `lowest' part of any found + chunk. (The implementation invariant is that prev_inuse is + always true of any allocated chunk; i.e., that each allocated + chunk borders either a previously allocated and still in-use chunk, + or the base of its memory arena.) + +*/ + +#if __STD_C +Void_t* mALLOc(size_t bytes) +#else +Void_t* mALLOc(bytes) size_t bytes; +#endif +{ + mchunkptr victim; /* inspected/selected chunk */ + INTERNAL_SIZE_T victim_size; /* its size */ + int idx; /* index for bin traversal */ + mbinptr bin; /* associated bin */ + mchunkptr remainder; /* remainder from a split */ + long remainder_size; /* its size */ + int remainder_index; /* its bin index */ + unsigned long block; /* block traverser bit */ + int startidx; /* first bin of a traversed block */ + mchunkptr fwd; /* misc temp for linking */ + mchunkptr bck; /* misc temp for linking */ + mbinptr q; /* misc temp */ + + INTERNAL_SIZE_T nb; + + if ((long)bytes < 0) return 0; + + nb = request2size(bytes); /* padded request size; */ + + /* Check for exact match in a bin */ + + if (is_small_request(nb)) /* Faster version for small requests */ + { + idx = smallbin_index(nb); + + /* No traversal or size check necessary for small bins. */ + + q = bin_at(idx); + victim = last(q); + + /* Also scan the next one, since it would have a remainder < MINSIZE */ + if (victim == q) + { + q = next_bin(q); + victim = last(q); + } + if (victim != q) + { + victim_size = chunksize(victim); + unlink(victim, bck, fwd); + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + idx += 2; /* Set for bin scan below. We've already scanned 2 bins. */ + + } + else + { + idx = bin_index(nb); + bin = bin_at(idx); + + for (victim = last(bin); victim != bin; victim = victim->bk) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* too big */ + { + --idx; /* adjust to rescan below after checking last remainder */ + break; + } + + else if (remainder_size >= 0) /* exact fit */ + { + unlink(victim, bck, fwd); + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + } + + ++idx; + + } + + /* Try to use the last split-off remainder */ + + if ( (victim = last_remainder->fd) != last_remainder) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* re-split */ + { + remainder = chunk_at_offset(victim, nb); + set_head(victim, nb | PREV_INUSE); + link_last_remainder(remainder); + set_head(remainder, remainder_size | PREV_INUSE); + set_foot(remainder, remainder_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + clear_last_remainder; + + if (remainder_size >= 0) /* exhaust */ + { + set_inuse_bit_at_offset(victim, victim_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + /* Else place in bin */ + + frontlink(victim, victim_size, remainder_index, bck, fwd); + } + + /* + If there are any possibly nonempty big-enough blocks, + search for best fitting chunk by scanning bins in blockwidth units. + */ + + if ( (block = idx2binblock(idx)) <= binblocks) + { + + /* Get to the first marked block */ + + if ( (block & binblocks) == 0) + { + /* force to an even block boundary */ + idx = (idx & ~(BINBLOCKWIDTH - 1)) + BINBLOCKWIDTH; + block <<= 1; + while ((block & binblocks) == 0) + { + idx += BINBLOCKWIDTH; + block <<= 1; + } + } + + /* For each possibly nonempty block ... */ + for (;;) + { + startidx = idx; /* (track incomplete blocks) */ + q = bin = bin_at(idx); + + /* For each bin in this block ... */ + do + { + /* Find and use first big enough chunk ... */ + + for (victim = last(bin); victim != bin; victim = victim->bk) + { + victim_size = chunksize(victim); + remainder_size = victim_size - nb; + + if (remainder_size >= (long)MINSIZE) /* split */ + { + remainder = chunk_at_offset(victim, nb); + set_head(victim, nb | PREV_INUSE); + unlink(victim, bck, fwd); + link_last_remainder(remainder); + set_head(remainder, remainder_size | PREV_INUSE); + set_foot(remainder, remainder_size); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + else if (remainder_size >= 0) /* take */ + { + set_inuse_bit_at_offset(victim, victim_size); + unlink(victim, bck, fwd); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + } + + } + + bin = next_bin(bin); + + } while ((++idx & (BINBLOCKWIDTH - 1)) != 0); + + /* Clear out the block bit. */ + + do /* Possibly backtrack to try to clear a partial block */ + { + if ((startidx & (BINBLOCKWIDTH - 1)) == 0) + { + binblocks &= ~block; + break; + } + --startidx; + q = prev_bin(q); + } while (first(q) == q); + + /* Get to the next possibly nonempty block */ + + if ( (block <<= 1) <= binblocks && (block != 0) ) + { + while ((block & binblocks) == 0) + { + idx += BINBLOCKWIDTH; + block <<= 1; + } + } + else + break; + } + } + + + /* Try to use top chunk */ + + /* Require that there be a remainder, ensuring top always exists */ + if ( (remainder_size = chunksize(top) - nb) < (long)MINSIZE) + { + +#if HAVE_MMAP + /* If big and would otherwise need to extend, try to use mmap instead */ + if ((unsigned long)nb >= (unsigned long)mmap_threshold && + (victim = mmap_chunk(nb)) != 0) + return chunk2mem(victim); +#endif + + /* Try to extend */ + malloc_extend_top(nb); + if ( (remainder_size = chunksize(top) - nb) < (long)MINSIZE) + return 0; /* propagate failure */ + } + + victim = top; + set_head(victim, nb | PREV_INUSE); + top = chunk_at_offset(victim, nb); + set_head(top, remainder_size | PREV_INUSE); + check_malloced_chunk(victim, nb); + return chunk2mem(victim); + +} + + + + +/* + + free() algorithm : + + cases: + + 1. free(0) has no effect. + + 2. If the chunk was allocated via mmap, it is release via munmap(). + + 3. If a returned chunk borders the current high end of memory, + it is consolidated into the top, and if the total unused + topmost memory exceeds the trim threshold, malloc_trim is + called. + + 4. Other chunks are consolidated as they arrive, and + placed in corresponding bins. (This includes the case of + consolidating with the current `last_remainder'). + +*/ + + +#if __STD_C +void fREe(Void_t* mem) +#else +void fREe(mem) Void_t* mem; +#endif +{ + mchunkptr p; /* chunk corresponding to mem */ + INTERNAL_SIZE_T hd; /* its head field */ + INTERNAL_SIZE_T sz; /* its size */ + int idx; /* its bin index */ + mchunkptr next; /* next contiguous chunk */ + INTERNAL_SIZE_T nextsz; /* its size */ + INTERNAL_SIZE_T prevsz; /* size of previous contiguous chunk */ + mchunkptr bck; /* misc temp for linking */ + mchunkptr fwd; /* misc temp for linking */ + int islr; /* track whether merging with last_remainder */ + + if (mem == 0) /* free(0) has no effect */ + return; + + p = mem2chunk(mem); + hd = p->size; + +#if HAVE_MMAP + if (hd & IS_MMAPPED) /* release mmapped memory. */ + { + munmap_chunk(p); + return; + } +#endif + + check_inuse_chunk(p); + + sz = hd & ~PREV_INUSE; + next = chunk_at_offset(p, sz); + nextsz = chunksize(next); + + if (next == top) /* merge with top */ + { + sz += nextsz; + + if (!(hd & PREV_INUSE)) /* consolidate backward */ + { + prevsz = p->prev_size; + p = chunk_at_offset(p, -((long) prevsz)); + sz += prevsz; + unlink(p, bck, fwd); + } + + set_head(p, sz | PREV_INUSE); + top = p; + if ((unsigned long)(sz) >= (unsigned long)trim_threshold) + malloc_trim(top_pad); + return; + } + + set_head(next, nextsz); /* clear inuse bit */ + + islr = 0; + + if (!(hd & PREV_INUSE)) /* consolidate backward */ + { + prevsz = p->prev_size; + p = chunk_at_offset(p, -((long) prevsz)); + sz += prevsz; + + if (p->fd == last_remainder) /* keep as last_remainder */ + islr = 1; + else + unlink(p, bck, fwd); + } + + if (!(inuse_bit_at_offset(next, nextsz))) /* consolidate forward */ + { + sz += nextsz; + + if (!islr && next->fd == last_remainder) /* re-insert last_remainder */ + { + islr = 1; + link_last_remainder(p); + } + else + unlink(next, bck, fwd); + } + + + set_head(p, sz | PREV_INUSE); + set_foot(p, sz); + if (!islr) + frontlink(p, sz, idx, bck, fwd); +} + + + + + +/* + + Realloc algorithm: + + Chunks that were obtained via mmap cannot be extended or shrunk + unless HAVE_MREMAP is defined, in which case mremap is used. + Otherwise, if their reallocation is for additional space, they are + copied. If for less, they are just left alone. + + Otherwise, if the reallocation is for additional space, and the + chunk can be extended, it is, else a malloc-copy-free sequence is + taken. There are several different ways that a chunk could be + extended. All are tried: + + * Extending forward into following adjacent free chunk. + * Shifting backwards, joining preceding adjacent space + * Both shifting backwards and extending forward. + * Extending into newly sbrked space + + Unless the #define REALLOC_ZERO_BYTES_FREES is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + + If the reallocation is for less space, and the new request is for + a `small' (<512 bytes) size, then the newly unused space is lopped + off and freed. + + The old unix realloc convention of allowing the last-free'd chunk + to be used as an argument to realloc is no longer supported. + I don't know of any programs still relying on this feature, + and allowing it would also allow too many other incorrect + usages of realloc to be sensible. + + +*/ + + +#if __STD_C +Void_t* rEALLOc(Void_t* oldmem, size_t bytes) +#else +Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t bytes; +#endif +{ + INTERNAL_SIZE_T nb; /* padded request size */ + + mchunkptr oldp; /* chunk corresponding to oldmem */ + INTERNAL_SIZE_T oldsize; /* its size */ + + mchunkptr newp; /* chunk to return */ + INTERNAL_SIZE_T newsize; /* its size */ + Void_t* newmem; /* corresponding user mem */ + + mchunkptr next; /* next contiguous chunk after oldp */ + INTERNAL_SIZE_T nextsize; /* its size */ + + mchunkptr prev; /* previous contiguous chunk before oldp */ + INTERNAL_SIZE_T prevsize; /* its size */ + + mchunkptr remainder; /* holds split off extra space from newp */ + INTERNAL_SIZE_T remainder_size; /* its size */ + + mchunkptr bck; /* misc temp for linking */ + mchunkptr fwd; /* misc temp for linking */ + +#ifdef REALLOC_ZERO_BYTES_FREES + if (bytes == 0) { fREe(oldmem); return 0; } +#endif + + if ((long)bytes < 0) return 0; + + /* realloc of null is supposed to be same as malloc */ + if (oldmem == 0) return mALLOc(bytes); + + newp = oldp = mem2chunk(oldmem); + newsize = oldsize = chunksize(oldp); + + + nb = request2size(bytes); + +#if HAVE_MMAP + if (chunk_is_mmapped(oldp)) + { +#if HAVE_MREMAP + newp = mremap_chunk(oldp, nb); + if(newp) return chunk2mem(newp); +#endif + /* Note the extra SIZE_SZ overhead. */ + if(oldsize - SIZE_SZ >= nb) return oldmem; /* do nothing */ + /* Must alloc, copy, free. */ + newmem = mALLOc(bytes); + if (newmem == 0) return 0; /* propagate failure */ + MALLOC_COPY(newmem, oldmem, oldsize - 2*SIZE_SZ); + munmap_chunk(oldp); + return newmem; + } +#endif + + check_inuse_chunk(oldp); + + if ((long)(oldsize) < (long)(nb)) + { + + /* Try expanding forward */ + + next = chunk_at_offset(oldp, oldsize); + if (next == top || !inuse(next)) + { + nextsize = chunksize(next); + + /* Forward into top only if a remainder */ + if (next == top) + { + if ((long)(nextsize + newsize) >= (long)(nb + MINSIZE)) + { + newsize += nextsize; + top = chunk_at_offset(oldp, nb); + set_head(top, (newsize - nb) | PREV_INUSE); + set_head_size(oldp, nb); + return chunk2mem(oldp); + } + } + + /* Forward into next chunk */ + else if (((long)(nextsize + newsize) >= (long)(nb))) + { + unlink(next, bck, fwd); + newsize += nextsize; + goto split; + } + } + else + { + next = 0; + nextsize = 0; + } + + /* Try shifting backwards. */ + + if (!prev_inuse(oldp)) + { + prev = prev_chunk(oldp); + prevsize = chunksize(prev); + + /* try forward + backward first to save a later consolidation */ + + if (next != 0) + { + /* into top */ + if (next == top) + { + if ((long)(nextsize + prevsize + newsize) >= (long)(nb + MINSIZE)) + { + unlink(prev, bck, fwd); + newp = prev; + newsize += prevsize + nextsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + top = chunk_at_offset(newp, nb); + set_head(top, (newsize - nb) | PREV_INUSE); + set_head_size(newp, nb); + return newmem; + } + } + + /* into next chunk */ + else if (((long)(nextsize + prevsize + newsize) >= (long)(nb))) + { + unlink(next, bck, fwd); + unlink(prev, bck, fwd); + newp = prev; + newsize += nextsize + prevsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + goto split; + } + } + + /* backward only */ + if (prev != 0 && (long)(prevsize + newsize) >= (long)nb) + { + unlink(prev, bck, fwd); + newp = prev; + newsize += prevsize; + newmem = chunk2mem(newp); + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + goto split; + } + } + + /* Must allocate */ + + newmem = mALLOc (bytes); + + if (newmem == 0) /* propagate failure */ + return 0; + + /* Avoid copy if newp is next chunk after oldp. */ + /* (This can only happen when new chunk is sbrk'ed.) */ + + if ( (newp = mem2chunk(newmem)) == next_chunk(oldp)) + { + newsize += chunksize(newp); + newp = oldp; + goto split; + } + + /* Otherwise copy, free, and exit */ + MALLOC_COPY(newmem, oldmem, oldsize - SIZE_SZ); + fREe(oldmem); + return newmem; + } + + + split: /* split off extra room in old or expanded chunk */ + + if (newsize - nb >= MINSIZE) /* split off remainder */ + { + remainder = chunk_at_offset(newp, nb); + remainder_size = newsize - nb; + set_head_size(newp, nb); + set_head(remainder, remainder_size | PREV_INUSE); + set_inuse_bit_at_offset(remainder, remainder_size); + fREe(chunk2mem(remainder)); /* let free() deal with it */ + } + else + { + set_head_size(newp, newsize); + set_inuse_bit_at_offset(newp, newsize); + } + + check_inuse_chunk(newp); + return chunk2mem(newp); +} + + + + +/* + + memalign algorithm: + + memalign requests more than enough space from malloc, finds a spot + within that chunk that meets the alignment request, and then + possibly frees the leading and trailing space. + + The alignment argument must be a power of two. This property is not + checked by memalign, so misuse may result in random runtime errors. + + 8-byte alignment is guaranteed by normal malloc calls, so don't + bother calling memalign with an argument of 8 or less. + + Overreliance on memalign is a sure way to fragment space. + +*/ + + +#if __STD_C +Void_t* mEMALIGn(size_t alignment, size_t bytes) +#else +Void_t* mEMALIGn(alignment, bytes) size_t alignment; size_t bytes; +#endif +{ + INTERNAL_SIZE_T nb; /* padded request size */ + char* m; /* memory returned by malloc call */ + mchunkptr p; /* corresponding chunk */ + char* brk; /* alignment point within p */ + mchunkptr newp; /* chunk to return */ + INTERNAL_SIZE_T newsize; /* its size */ + INTERNAL_SIZE_T leadsize; /* leading space befor alignment point */ + mchunkptr remainder; /* spare room at end to split off */ + long remainder_size; /* its size */ + + if ((long)bytes < 0) return 0; + + /* If need less alignment than we give anyway, just relay to malloc */ + + if (alignment <= MALLOC_ALIGNMENT) return mALLOc(bytes); + + /* Otherwise, ensure that it is at least a minimum chunk size */ + + if (alignment < MINSIZE) alignment = MINSIZE; + + /* Call malloc with worst case padding to hit alignment. */ + + nb = request2size(bytes); + m = (char*)(mALLOc(nb + alignment + MINSIZE)); + + if (m == 0) return 0; /* propagate failure */ + + p = mem2chunk(m); + + if ((((unsigned long)(m)) % alignment) == 0) /* aligned */ + { +#if HAVE_MMAP + if(chunk_is_mmapped(p)) + return chunk2mem(p); /* nothing more to do */ +#endif + } + else /* misaligned */ + { + /* + Find an aligned spot inside chunk. + Since we need to give back leading space in a chunk of at + least MINSIZE, if the first calculation places us at + a spot with less than MINSIZE leader, we can move to the + next aligned spot -- we've allocated enough total room so that + this is always possible. + */ + + brk = (char*)mem2chunk(((unsigned long)(m + alignment - 1)) & -((signed) alignment)); + if ((long)(brk - (char*)(p)) < MINSIZE) brk = brk + alignment; + + newp = (mchunkptr)brk; + leadsize = brk - (char*)(p); + newsize = chunksize(p) - leadsize; + +#if HAVE_MMAP + if(chunk_is_mmapped(p)) + { + newp->prev_size = p->prev_size + leadsize; + set_head(newp, newsize|IS_MMAPPED); + return chunk2mem(newp); + } +#endif + + /* give back leader, use the rest */ + + set_head(newp, newsize | PREV_INUSE); + set_inuse_bit_at_offset(newp, newsize); + set_head_size(p, leadsize); + fREe(chunk2mem(p)); + p = newp; + + assert (newsize >= nb && (((unsigned long)(chunk2mem(p))) % alignment) == 0); + } + + /* Also give back spare room at the end */ + + remainder_size = chunksize(p) - nb; + + if (remainder_size >= (long)MINSIZE) + { + remainder = chunk_at_offset(p, nb); + set_head(remainder, remainder_size | PREV_INUSE); + set_head_size(p, nb); + fREe(chunk2mem(remainder)); + } + + check_inuse_chunk(p); + return chunk2mem(p); + +} + + + + +/* + valloc just invokes memalign with alignment argument equal + to the page size of the system (or as near to this as can + be figured out from all the includes/defines above.) +*/ + +#if __STD_C +Void_t* vALLOc(size_t bytes) +#else +Void_t* vALLOc(bytes) size_t bytes; +#endif +{ + return mEMALIGn (malloc_getpagesize, bytes); +} + +/* + pvalloc just invokes valloc for the nearest pagesize + that will accommodate request +*/ + + +#if __STD_C +Void_t* pvALLOc(size_t bytes) +#else +Void_t* pvALLOc(bytes) size_t bytes; +#endif +{ + size_t pagesize = malloc_getpagesize; + return mEMALIGn (pagesize, (bytes + pagesize - 1) & ~(pagesize - 1)); +} + +/* + + calloc calls malloc, then zeroes out the allocated chunk. + +*/ + +#if __STD_C +Void_t* cALLOc(size_t n, size_t elem_size) +#else +Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; +#endif +{ + mchunkptr p; + INTERNAL_SIZE_T csz; + + INTERNAL_SIZE_T sz = n * elem_size; + + + /* check if expand_top called, in which case don't need to clear */ +#if MORECORE_CLEARS + mchunkptr oldtop = top; + INTERNAL_SIZE_T oldtopsize = chunksize(top); +#endif + Void_t* mem = mALLOc (sz); + + if ((long)n < 0) return 0; + + if (mem == 0) + return 0; + else + { + p = mem2chunk(mem); + + /* Two optional cases in which clearing not necessary */ + + +#if HAVE_MMAP + if (chunk_is_mmapped(p)) return mem; +#endif + + csz = chunksize(p); + +#if MORECORE_CLEARS + if (p == oldtop && csz > oldtopsize) + { + /* clear only the bytes from non-freshly-sbrked memory */ + csz = oldtopsize; + } +#endif + + MALLOC_ZERO(mem, csz - SIZE_SZ); + return mem; + } +} + +/* + + cfree just calls free. It is needed/defined on some systems + that pair it with calloc, presumably for odd historical reasons. + +*/ + +#if !defined(INTERNAL_LINUX_C_LIB) || !defined(__ELF__) +#if __STD_C +void cfree(Void_t *mem) +#else +void cfree(mem) Void_t *mem; +#endif +{ + fREe(mem); +} +#endif + + + +/* + + Malloc_trim gives memory back to the system (via negative + arguments to sbrk) if there is unused memory at the `high' end of + the malloc pool. You can call this after freeing large blocks of + memory to potentially reduce the system-level memory requirements + of a program. However, it cannot guarantee to reduce memory. Under + some allocation patterns, some large free blocks of memory will be + locked between two used chunks, so they cannot be given back to + the system. + + The `pad' argument to malloc_trim represents the amount of free + trailing space to leave untrimmed. If this argument is zero, + only the minimum amount of memory to maintain internal data + structures will be left (one page or less). Non-zero arguments + can be supplied to maintain enough trailing space to service + future expected allocations without having to re-obtain memory + from the system. + + Malloc_trim returns 1 if it actually released any memory, else 0. + +*/ + +#if __STD_C +int malloc_trim(size_t pad) +#else +int malloc_trim(pad) size_t pad; +#endif +{ + long top_size; /* Amount of top-most memory */ + long extra; /* Amount to release */ + char* current_brk; /* address returned by pre-check sbrk call */ + char* new_brk; /* address returned by negative sbrk call */ + + unsigned long pagesz = malloc_getpagesize; + + top_size = chunksize(top); + extra = ((top_size - pad - MINSIZE + (pagesz-1)) / pagesz - 1) * pagesz; + + if (extra < (long)pagesz) /* Not enough memory to release */ + return 0; + + else + { + /* Test to make sure no one else called sbrk */ + current_brk = (char*)(MORECORE (0)); + if (current_brk != (char*)(top) + top_size) + return 0; /* Apparently we don't own memory; must fail */ + + else + { + new_brk = (char*)(MORECORE (-extra)); + + if (new_brk == (char*)(MORECORE_FAILURE)) /* sbrk failed? */ + { + /* Try to figure out what we have */ + current_brk = (char*)(MORECORE (0)); + top_size = current_brk - (char*)top; + if (top_size >= (long)MINSIZE) /* if not, we are very very dead! */ + { + sbrked_mem = current_brk - sbrk_base; + set_head(top, top_size | PREV_INUSE); + } + check_chunk(top); + return 0; + } + + else + { + /* Success. Adjust top accordingly. */ + set_head(top, (top_size - extra) | PREV_INUSE); + sbrked_mem -= extra; + check_chunk(top); + return 1; + } + } + } +} + + + +/* + malloc_usable_size: + + This routine tells you how many bytes you can actually use in an + allocated chunk, which may be more than you requested (although + often not). You can use this many bytes without worrying about + overwriting other allocated objects. Not a particularly great + programming practice, but still sometimes useful. + +*/ + +#if __STD_C +size_t malloc_usable_size(Void_t* mem) +#else +size_t malloc_usable_size(mem) Void_t* mem; +#endif +{ + mchunkptr p; + if (mem == 0) + return 0; + else + { + p = mem2chunk(mem); + if(!chunk_is_mmapped(p)) + { + if (!inuse(p)) return 0; + check_inuse_chunk(p); + return chunksize(p) - SIZE_SZ; + } + return chunksize(p) - 2*SIZE_SZ; + } +} + + + + +/* Utility to update current_mallinfo for malloc_stats and mallinfo() */ + +#if 0 +static void malloc_update_mallinfo() +{ + int i; + mbinptr b; + mchunkptr p; +#ifdef DEBUG + mchunkptr q; +#endif + + INTERNAL_SIZE_T avail = chunksize(top); + int navail = ((long)(avail) >= (long)MINSIZE)? 1 : 0; + + for (i = 1; i < NAV; ++i) + { + b = bin_at(i); + for (p = last(b); p != b; p = p->bk) + { +#ifdef DEBUG + check_free_chunk(p); + for (q = next_chunk(p); + q < top && inuse(q) && (long)(chunksize(q)) >= (long)MINSIZE; + q = next_chunk(q)) + check_inuse_chunk(q); +#endif + avail += chunksize(p); + navail++; + } + } + + current_mallinfo.ordblks = navail; + current_mallinfo.uordblks = sbrked_mem - avail; + current_mallinfo.fordblks = avail; + current_mallinfo.hblks = n_mmaps; + current_mallinfo.hblkhd = mmapped_mem; + current_mallinfo.keepcost = chunksize(top); + +} +#endif /* 0 */ + + + +/* + + malloc_stats: + + Prints on the amount of space obtain from the system (both + via sbrk and mmap), the maximum amount (which may be more than + current if malloc_trim and/or munmap got called), the maximum + number of simultaneous mmap regions used, and the current number + of bytes allocated via malloc (or realloc, etc) but not yet + freed. (Note that this is the number of bytes allocated, not the + number requested. It will be larger than the number requested + because of alignment and bookkeeping overhead.) + +*/ + +#if 0 +void malloc_stats() +{ + malloc_update_mallinfo(); + printf("max system bytes = %10u\n", + (unsigned int)(max_total_mem)); + printf("system bytes = %10u\n", + (unsigned int)(sbrked_mem + mmapped_mem)); + printf("in use bytes = %10u\n", + (unsigned int)(current_mallinfo.uordblks + mmapped_mem)); +#if HAVE_MMAP + printf("max mmap regions = %10u\n", + (unsigned int)max_n_mmaps); +#endif +} +#endif /* 0 */ + +/* + mallinfo returns a copy of updated current mallinfo. +*/ + +#if 0 +struct mallinfo mALLINFo() +{ + malloc_update_mallinfo(); + return current_mallinfo; +} +#endif /* 0 */ + + + + +/* + mallopt: + + mallopt is the general SVID/XPG interface to tunable parameters. + The format is to provide a (parameter-number, parameter-value) pair. + mallopt then sets the corresponding parameter to the argument + value if it can (i.e., so long as the value is meaningful), + and returns 1 if successful else 0. + + See descriptions of tunable parameters above. + +*/ + +#if __STD_C +int mALLOPt(int param_number, int value) +#else +int mALLOPt(param_number, value) int param_number; int value; +#endif +{ + switch(param_number) + { + case M_TRIM_THRESHOLD: + trim_threshold = value; return 1; + case M_TOP_PAD: + top_pad = value; return 1; + case M_MMAP_THRESHOLD: + mmap_threshold = value; return 1; + case M_MMAP_MAX: +#if HAVE_MMAP + n_mmaps_max = value; return 1; +#else + if (value != 0) return 0; else n_mmaps_max = value; return 1; +#endif + + default: + return 0; + } +} + +/* + +History: + + V2.6.6 Sun Dec 5 07:42:19 1999 Doug Lea (dl at gee) + * return null for negative arguments + * Added Several WIN32 cleanups from Martin C. Fong + * Add 'LACKS_SYS_PARAM_H' for those systems without 'sys/param.h' + (e.g. WIN32 platforms) + * Cleanup up header file inclusion for WIN32 platforms + * Cleanup code to avoid Microsoft Visual C++ compiler complaints + * Add 'USE_DL_PREFIX' to quickly allow co-existence with existing + memory allocation routines + * Set 'malloc_getpagesize' for WIN32 platforms (needs more work) + * Use 'assert' rather than 'ASSERT' in WIN32 code to conform to + usage of 'assert' in non-WIN32 code + * Improve WIN32 'sbrk()' emulation's 'findRegion()' routine to + avoid infinite loop + * Always call 'fREe()' rather than 'free()' + + V2.6.5 Wed Jun 17 15:57:31 1998 Doug Lea (dl at gee) + * Fixed ordering problem with boundary-stamping + + V2.6.3 Sun May 19 08:17:58 1996 Doug Lea (dl at gee) + * Added pvalloc, as recommended by H.J. Liu + * Added 64bit pointer support mainly from Wolfram Gloger + * Added anonymously donated WIN32 sbrk emulation + * Malloc, calloc, getpagesize: add optimizations from Raymond Nijssen + * malloc_extend_top: fix mask error that caused wastage after + foreign sbrks + * Add linux mremap support code from HJ Liu + + V2.6.2 Tue Dec 5 06:52:55 1995 Doug Lea (dl at gee) + * Integrated most documentation with the code. + * Add support for mmap, with help from + Wolfram Gloger (Gloger@lrz.uni-muenchen.de). + * Use last_remainder in more cases. + * Pack bins using idea from colin@nyx10.cs.du.edu + * Use ordered bins instead of best-fit threshhold + * Eliminate block-local decls to simplify tracing and debugging. + * Support another case of realloc via move into top + * Fix error occuring when initial sbrk_base not word-aligned. + * Rely on page size for units instead of SBRK_UNIT to + avoid surprises about sbrk alignment conventions. + * Add mallinfo, mallopt. Thanks to Raymond Nijssen + (raymond@es.ele.tue.nl) for the suggestion. + * Add `pad' argument to malloc_trim and top_pad mallopt parameter. + * More precautions for cases where other routines call sbrk, + courtesy of Wolfram Gloger (Gloger@lrz.uni-muenchen.de). + * Added macros etc., allowing use in linux libc from + H.J. Lu (hjl@gnu.ai.mit.edu) + * Inverted this history list + + V2.6.1 Sat Dec 2 14:10:57 1995 Doug Lea (dl at gee) + * Re-tuned and fixed to behave more nicely with V2.6.0 changes. + * Removed all preallocation code since under current scheme + the work required to undo bad preallocations exceeds + the work saved in good cases for most test programs. + * No longer use return list or unconsolidated bins since + no scheme using them consistently outperforms those that don't + given above changes. + * Use best fit for very large chunks to prevent some worst-cases. + * Added some support for debugging + + V2.6.0 Sat Nov 4 07:05:23 1995 Doug Lea (dl at gee) + * Removed footers when chunks are in use. Thanks to + Paul Wilson (wilson@cs.texas.edu) for the suggestion. + + V2.5.4 Wed Nov 1 07:54:51 1995 Doug Lea (dl at gee) + * Added malloc_trim, with help from Wolfram Gloger + (wmglo@Dent.MED.Uni-Muenchen.DE). + + V2.5.3 Tue Apr 26 10:16:01 1994 Doug Lea (dl at g) + + V2.5.2 Tue Apr 5 16:20:40 1994 Doug Lea (dl at g) + * realloc: try to expand in both directions + * malloc: swap order of clean-bin strategy; + * realloc: only conditionally expand backwards + * Try not to scavenge used bins + * Use bin counts as a guide to preallocation + * Occasionally bin return list chunks in first scan + * Add a few optimizations from colin@nyx10.cs.du.edu + + V2.5.1 Sat Aug 14 15:40:43 1993 Doug Lea (dl at g) + * faster bin computation & slightly different binning + * merged all consolidations to one part of malloc proper + (eliminating old malloc_find_space & malloc_clean_bin) + * Scan 2 returns chunks (not just 1) + * Propagate failure in realloc if malloc returns 0 + * Add stuff to allow compilation on non-ANSI compilers + from kpv@research.att.com + + V2.5 Sat Aug 7 07:41:59 1993 Doug Lea (dl at g.oswego.edu) + * removed potential for odd address access in prev_chunk + * removed dependency on getpagesize.h + * misc cosmetics and a bit more internal documentation + * anticosmetics: mangled names in macros to evade debugger strangeness + * tested on sparc, hp-700, dec-mips, rs6000 + with gcc & native cc (hp, dec only) allowing + Detlefs & Zorn comparison study (in SIGPLAN Notices.) + + Trial version Fri Aug 28 13:14:29 1992 Doug Lea (dl at g.oswego.edu) + * Based loosely on libg++-1.2X malloc. (It retains some of the overall + structure of old version, but most details differ.) + +*/ diff --git a/u-boot/common/env_common.c b/u-boot/common/env_common.c new file mode 100755 index 0000000..d6d9ead --- /dev/null +++ b/u-boot/common/env_common.c @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#undef DEBUG_ENV + +#ifdef DEBUG_ENV + #define DEBUGF(fmt,args...) printf(fmt ,##args) +#else + #define DEBUGF(fmt,args...) +#endif + +extern env_t *env_ptr; + +extern void env_relocate_spec(void); +extern uchar env_get_char_spec(int); + +static uchar env_get_char_init(int index); +uchar (*env_get_char)(int) = env_get_char_init; + +/************************************************************************ + * Default settings to be used when no valid environment is found + */ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +uchar default_environment[] = { +#ifdef CONFIG_BOOTARGS + "bootargs=" CONFIG_BOOTARGS "\0" +#endif +#ifdef CONFIG_BOOTCOMMAND + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#ifdef CONFIG_RAMBOOTCOMMAND + "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" +#endif +#ifdef CONFIG_NFSBOOTCOMMAND + "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0" +#endif +#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) + "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" +#endif +#ifdef CONFIG_LOADS_ECHO + "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0" +#endif +#ifdef CONFIG_ETHADDR + "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0" +#endif +#ifdef CONFIG_ETH1ADDR + "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0" +#endif +#ifdef CONFIG_ETH2ADDR + "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0" +#endif +#ifdef CONFIG_ETH3ADDR + "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0" +#endif +#ifdef CONFIG_IPADDR + "ipaddr=" MK_STR(CONFIG_IPADDR) "\0" +#endif +#ifdef CONFIG_SERVERIP + "serverip=" MK_STR(CONFIG_SERVERIP) "\0" +#endif +#ifdef CFG_AUTOLOAD + "autoload=" CFG_AUTOLOAD "\0" +#endif +#ifdef CONFIG_ROOTPATH + "rootpath=" MK_STR(CONFIG_ROOTPATH) "\0" +#endif +#ifdef CONFIG_GATEWAYIP + "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0" +#endif +#ifdef CONFIG_NETMASK + "netmask=" MK_STR(CONFIG_NETMASK) "\0" +#endif +#ifdef CONFIG_HOSTNAME + "hostname=" MK_STR(CONFIG_HOSTNAME) "\0" +#endif +#ifdef CONFIG_BOOTFILE + "bootfile=" MK_STR(CONFIG_BOOTFILE) "\0" +#endif +#ifdef CONFIG_LOADADDR + "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0" +#endif +#ifdef CONFIG_CLOCKS_IN_MHZ + "clocks_in_mhz=1\0" +#endif +#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0" +#endif +#ifdef CONFIG_NETCONSOLE_PORT + "ncport=" MK_STR(CONFIG_NETCONSOLE_PORT) "\0" +#endif +#ifdef CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS +#endif + "\0" }; + +#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ +int default_environment_size = sizeof(default_environment); +#endif + +void env_crc_update(void){ + env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); +} + +static uchar env_get_char_init(int index){ + uchar c; + + /* if crc was bad, use the default environment */ + if(gd->env_valid){ + c = env_get_char_spec(index); + } else { + c = default_environment[index]; + } + + return(c); +} + +uchar env_get_char_memory(int index){ + if(gd->env_valid){ + return(*((uchar *)(gd->env_addr + index))); + } else { + return(default_environment[index]); + } +} + +uchar *env_get_addr(int index){ + if(gd->env_valid){ + return(((uchar *)(gd->env_addr + index))); + } else { + return(&default_environment[index]); + } +} + +void env_relocate(void){ + DEBUGF("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__, gd->reloc_off); + +#if defined(ENV_IS_EMBEDDED) + /* + * The environment buffer is embedded with the text segment, + * just relocate the environment pointer + */ + env_ptr = (env_t *)((ulong)env_ptr + gd->reloc_off); + DEBUGF("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); +#else + /* + * We must allocate a buffer for the environment + */ + env_ptr = (env_t *)malloc(CFG_ENV_SIZE); + DEBUGF("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); +#endif + + /* + * After relocation to RAM, we can always use the "memory" functions + */ + env_get_char = env_get_char_memory; + + if(gd->env_valid == 0){ +#if defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */ + //puts("Using default environment\n\n"); +#else + puts("** Warning: bad env CRC, using default,\n" + " use 'saveenv' to save it in flash\n\n"); +#endif + + if(sizeof(default_environment) > ENV_SIZE){ + puts("## Error: default environment is too large\n"); + return; + } + + memset(env_ptr, 0, sizeof(env_t)); + memcpy(env_ptr->data, default_environment, sizeof(default_environment)); +#ifdef CFG_REDUNDAND_ENVIRONMENT + env_ptr->flags = 0xFF; +#endif + env_crc_update(); + gd->env_valid = 1; + } else { + env_relocate_spec(); + } + gd->env_addr = (ulong)&(env_ptr->data); +} diff --git a/u-boot/common/env_flash.c b/u-boot/common/env_flash.c new file mode 100644 index 0000000..b8d8e39 --- /dev/null +++ b/u-boot/common/env_flash.c @@ -0,0 +1,360 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include + +#if defined(CFG_ENV_IS_IN_FLASH) /* Environment is in Flash */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if ((CONFIG_COMMANDS & (CFG_CMD_ENV | CFG_CMD_FLASH)) == (CFG_CMD_ENV | CFG_CMD_FLASH)) + #define CMD_SAVEENV +#elif defined(CFG_ENV_ADDR_REDUND) + #error Cannot use CFG_ENV_ADDR_REDUND without CFG_CMD_ENV & CFG_CMD_FLASH +#endif + +#if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND < CFG_ENV_SIZE) + #error CFG_ENV_SIZE_REDUND should not be less then CFG_ENV_SIZE +#endif + +#ifdef CONFIG_INFERNO + #ifdef CFG_ENV_ADDR_REDUND + #error CFG_ENV_ADDR_REDUND is not implemented for CONFIG_INFERNO + #endif +#endif + +char *env_name_spec = "flash"; + +#ifdef ENV_IS_EMBEDDED + +extern uchar environment[]; +env_t *env_ptr = (env_t *)(&environment[0]); + +#ifdef CMD_SAVEENV +/* static env_t *flash_addr = (env_t *)(&environment[0]);-broken on ARM-wd-*/ +static env_t *flash_addr = (env_t *)CFG_ENV_ADDR; +#endif + +#else /* ! ENV_IS_EMBEDDED */ + +env_t *env_ptr = (env_t *)CFG_ENV_ADDR; + +#ifdef CMD_SAVEENV +static env_t *flash_addr = (env_t *)CFG_ENV_ADDR; +#endif + +#endif /* ENV_IS_EMBEDDED */ + +#ifdef CFG_ENV_ADDR_REDUND +static env_t *flash_addr_new = (env_t *)CFG_ENV_ADDR_REDUND; + +/* CFG_ENV_ADDR is supposed to be on sector boundary */ +static ulong end_addr = CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1; +static ulong end_addr_new = CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1; + +#define ACTIVE_FLAG 1 +#define OBSOLETE_FLAG 0 +#endif /* CFG_ENV_ADDR_REDUND */ + +extern uchar default_environment[]; +extern int default_environment_size; + +uchar env_get_char_spec(int index){ + return(*((uchar *)(gd->env_addr + index))); +} + +#ifdef CFG_ENV_ADDR_REDUND + +int env_init(void){ + int crc1_ok = 0, crc2_ok = 0; + + uchar flag1 = flash_addr->flags; + uchar flag2 = flash_addr_new->flags; + + ulong addr_default = (ulong)&default_environment[0]; + ulong addr1 = (ulong)&(flash_addr->data); + ulong addr2 = (ulong)&(flash_addr_new->data); + + crc1_ok = (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc); + crc2_ok = (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc); + + if(crc1_ok && !crc2_ok){ + gd->env_addr = addr1; + gd->env_valid = 1; + } else if(!crc1_ok && crc2_ok){ + gd->env_addr = addr2; + gd->env_valid = 1; + } else if(!crc1_ok && !crc2_ok){ + gd->env_addr = addr_default; + gd->env_valid = 0; + } else if(flag1 == ACTIVE_FLAG && flag2 == OBSOLETE_FLAG){ + gd->env_addr = addr1; + gd->env_valid = 1; + } else if(flag1 == OBSOLETE_FLAG && flag2 == ACTIVE_FLAG){ + gd->env_addr = addr2; + gd->env_valid = 1; + } else if(flag1 == flag2){ + gd->env_addr = addr1; + gd->env_valid = 2; + } else if(flag1 == 0xFF){ + gd->env_addr = addr1; + gd->env_valid = 2; + } else if(flag2 == 0xFF){ + gd->env_addr = addr2; + gd->env_valid = 2; + } + + return(0); +} + +#ifdef CMD_SAVEENV +int saveenv(void){ + char *saved_data = NULL; + int rc = 1; + char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG; +#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE + ulong up_data = 0; +#endif + + //debug("Protect off %08lX ... %08lX\n", (ulong)flash_addr, end_addr); + + if(flash_sect_protect(0, (ulong)flash_addr, end_addr)){ + goto Done; + } + + //debug("Protect off %08lX ... %08lX\n", (ulong)flash_addr_new, end_addr_new); + + if(flash_sect_protect(0, (ulong)flash_addr_new, end_addr_new)){ + goto Done; + } + +#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE + up_data = (end_addr_new + 1 - ((long)flash_addr_new + CFG_ENV_SIZE)); + //debug ("Data to save 0x%x\n", up_data); + + if(up_data){ + if((saved_data = malloc(up_data)) == NULL){ + printf("## Error: unable to save the rest of sector (%ld)\n", up_data); + goto Done; + } + + memcpy(saved_data, (void *)((long)flash_addr_new + CFG_ENV_SIZE), up_data); + //debug("Data (start 0x%x, len 0x%x) saved at 0x%x\n", (long)flash_addr_new + CFG_ENV_SIZE, up_data, saved_data); + } +#endif + //debug("Erasing Flash..."); + //debug(" %08lX ... %08lX ...", (ulong)flash_addr_new, end_addr_new); + + if(flash_sect_erase((ulong)flash_addr_new, end_addr_new)){ + goto Done; + } + + //debug("Writing to Flash... "); + //debug(" %08lX ... %08lX ...", (ulong)&(flash_addr_new->data), sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data)); + + if((rc = flash_write((char *)env_ptr->data, (ulong)&(flash_addr_new->data), sizeof(env_ptr->data))) || + (rc = flash_write((char *)&(env_ptr->crc), (ulong)&(flash_addr_new->crc), sizeof(env_ptr->crc))) || + (rc = flash_write(&flag, (ulong)&(flash_addr->flags), sizeof(flash_addr->flags))) || + (rc = flash_write(&new_flag, (ulong)&(flash_addr_new->flags), sizeof(flash_addr_new->flags)))){ + flash_perror(rc); + goto Done; + } + + //debug("done\n"); + +#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE + if(up_data){ /* restore the rest of sector */ + //debug("Restoring the rest of data to 0x%x len 0x%x\n", (long)flash_addr_new + CFG_ENV_SIZE, up_data); + if(flash_write(saved_data, (long)flash_addr_new + CFG_ENV_SIZE, up_data)){ + flash_perror(rc); + goto Done; + } + } +#endif + env_t * etmp = flash_addr; + ulong ltmp = end_addr; + + flash_addr = flash_addr_new; + flash_addr_new = etmp; + + end_addr = end_addr_new; + end_addr_new = ltmp; + + rc = 0; + +Done: + + if(saved_data){ + free(saved_data); + } + + /* try to re-protect */ + (void)flash_sect_protect(1, (ulong)flash_addr, end_addr); + (void)flash_sect_protect(1, (ulong)flash_addr_new, end_addr_new); + + return(rc); +} +#endif /* CMD_SAVEENV */ + +#else /* ! CFG_ENV_ADDR_REDUND */ +int env_init(void){ + if(crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc){ + gd->env_addr = (ulong)&(env_ptr->data); + gd->env_valid = 1; + + return(0); + } + + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 0; + + return(0); +} + +#ifdef CMD_SAVEENV +int saveenv(void){ + int len, rc; + ulong end_addr, flash_sect_addr; +#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) + ulong flash_offset; + uchar env_buffer[CFG_ENV_SECT_SIZE]; +#else + uchar *env_buffer = (uchar *)env_ptr; +#endif /* CFG_ENV_SECT_SIZE */ + int rcode = 0; + +#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) + + flash_offset = ((ulong)flash_addr) & (CFG_ENV_SECT_SIZE-1); + flash_sect_addr = ((ulong)flash_addr) & ~(CFG_ENV_SECT_SIZE-1); + + //debug("copy old content: sect_addr: %08lX env_addr: %08lX offset: %08lX\n", flash_sect_addr, (ulong)flash_addr, flash_offset); + + /* copy old contents to temporary buffer */ + memcpy(env_buffer, (void *)flash_sect_addr, CFG_ENV_SECT_SIZE); + + /* copy current environment to temporary buffer */ + memcpy((uchar *)((unsigned long)env_buffer + flash_offset), env_ptr, CFG_ENV_SIZE); + + len = CFG_ENV_SECT_SIZE; +#else + flash_sect_addr = (ulong)flash_addr; + len = CFG_ENV_SIZE; +#endif /* CFG_ENV_SECT_SIZE */ + +#ifndef CONFIG_INFERNO + end_addr = flash_sect_addr + len - 1; +#else + /* this is the last sector, and the size is hardcoded here */ + /* otherwise we will get stack problems on loading 128 KB environment */ + end_addr = flash_sect_addr + 0x20000 - 1; +#endif + + //debug("Protect off %08lX ... %08lX\n", (ulong)flash_sect_addr, end_addr); + + if(flash_sect_protect(0, flash_sect_addr, end_addr)){ + return(1); + } + + //debug("Erasing Flash..."); + + if(flash_sect_erase(flash_sect_addr, end_addr)){ + return(1); + } + + //debug("Writing to Flash... "); + + rc = flash_write((char *)env_buffer, flash_sect_addr, len); + + if(rc != 0){ + flash_perror(rc); + rcode = 1; + } else { + //debug("done\n"); + } + + /* try to re-protect */ + (void)flash_sect_protect(1, flash_sect_addr, end_addr); + + return(rcode); +} + +#endif /* CMD_SAVEENV */ + +#endif /* CFG_ENV_ADDR_REDUND */ + +void env_relocate_spec(void){ +#if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_ADDR_REDUND) + #ifdef CFG_ENV_ADDR_REDUND + if(gd->env_addr != (ulong)&(flash_addr->data)){ + env_t * etmp = flash_addr; + ulong ltmp = end_addr; + + flash_addr = flash_addr_new; + flash_addr_new = etmp; + + end_addr = end_addr_new; + end_addr_new = ltmp; + } + + if(flash_addr_new->flags != OBSOLETE_FLAG && crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc){ + char flag = OBSOLETE_FLAG; + + gd->env_valid = 2; + + flash_sect_protect(0, (ulong)flash_addr_new, end_addr_new); + flash_write(&flag, (ulong)&(flash_addr_new->flags), sizeof(flash_addr_new->flags)); + flash_sect_protect(1, (ulong)flash_addr_new, end_addr_new); + } + + if(flash_addr->flags != ACTIVE_FLAG && (flash_addr->flags & ACTIVE_FLAG) == ACTIVE_FLAG){ + char flag = ACTIVE_FLAG; + + gd->env_valid = 2; + + flash_sect_protect(0, (ulong)flash_addr, end_addr); + flash_write(&flag, (ulong)&(flash_addr->flags), sizeof(flash_addr->flags)); + flash_sect_protect(1, (ulong)flash_addr, end_addr); + } + + if(gd->env_valid == 2){ + puts("** Warning: some problems detected reading environment, recovered successfully\n"); + } + #endif /* CFG_ENV_ADDR_REDUND */ + + memcpy(env_ptr, (void*)flash_addr, CFG_ENV_SIZE); + +#endif /* ! ENV_IS_EMBEDDED || CFG_ENV_ADDR_REDUND */ +} + +#endif /* CFG_ENV_IS_IN_FLASH */ diff --git a/u-boot/common/env_nowhere.c b/u-boot/common/env_nowhere.c new file mode 100755 index 0000000..c5fbb68 --- /dev/null +++ b/u-boot/common/env_nowhere.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CFG_ENV_IS_NOWHERE) /* Environment is nowhere */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +env_t *env_ptr = NULL; + +extern uchar default_environment[]; +extern int default_environment_size; + +void env_relocate_spec(void){ +} + +uchar env_get_char_spec(int index){ + return(*((uchar *) (gd->env_addr + index))); +} + +/************************************************************************ + * Initialize Environment use + * + * We are still running from ROM, so data use is limited + */ +int env_init(void){ + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 0; + + return(0); +} + +#endif /* CFG_ENV_IS_NOWHERE) */ diff --git a/u-boot/common/environment.c b/u-boot/common/environment.c new file mode 100755 index 0000000..b8b8a8e --- /dev/null +++ b/u-boot/common/environment.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ /* Dirty trick to get only #defines */ +#endif +#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */ +#include +#undef __ASSEMBLY__ +#include + +/* + * Handle HOSTS that have prepended + * crap on symbol names, not TARGETS. + */ +#if defined(__APPLE__) +/* Leading underscore on symbols */ +# define SYM_CHAR "_" +#else /* No leading character on symbols */ +# define SYM_CHAR +#endif + +/* + * Generate embedded environment table + * inside U-Boot image, if needed. + */ +#if defined(ENV_IS_EMBEDDED) +/* + * Only put the environment in it's own section when we are building + * U-Boot proper. The host based program "tools/envcrc" does not need + * a seperate section. Note that ENV_CRC is only defined when building + * U-Boot itself. + */ +#if (defined(CONFIG_CMI) || \ + defined(CONFIG_FADS) || \ + defined(CONFIG_HYMOD) || \ + defined(CONFIG_ICU862) || \ + defined(CONFIG_R360MPI) || \ + defined(CONFIG_TQM8xxL) || \ + defined(CONFIG_RRVISION) || \ + defined(CONFIG_TRAB) || \ + defined(CONFIG_PPCHAMELEONEVB) ) && \ + defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */ + + /* XXX - This only works with GNU C */ + #define __PPCENV__ __attribute__ ((section(".ppcenv"))) + #define __PPCTEXT__ __attribute__ ((section(".text"))) + +#elif defined(USE_HOSTCC) /* Native for 'tools/envcrc' */ + + #define __PPCENV__ /*XXX DO_NOT_DEL_THIS_COMMENT*/ + #define __PPCTEXT__ /*XXX DO_NOT_DEL_THIS_COMMENT*/ + +#else /* Environment is embedded in U-Boot's .text section */ + + /* XXX - This only works with GNU C */ + #define __PPCENV__ __attribute__ ((section(".text"))) + #define __PPCTEXT__ __attribute__ ((section(".text"))) + +#endif + +/* + * Macros to generate global absolutes. + */ +#define GEN_SYMNAME(str) SYM_CHAR #str +#define GEN_VALUE(str) #str +#define GEN_ABS(name, value) \ + asm (".globl " GEN_SYMNAME(name)); \ + asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) + +/* + * Macros to transform values + * into environment strings. + */ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +/* + * Check to see if we are building with a + * computed CRC. Otherwise define it as ~0. + */ +#if !defined(ENV_CRC) +# define ENV_CRC ~0 +#endif + +env_t environment __PPCENV__ = { + ENV_CRC, /* CRC Sum */ +#ifdef CFG_REDUNDAND_ENVIRONMENT + 1, /* Flags: valid */ +#endif + { +#if defined(CONFIG_BOOTARGS) + "bootargs=" CONFIG_BOOTARGS "\0" +#endif +#if defined(CONFIG_BOOTCOMMAND) + "bootcmd=" CONFIG_BOOTCOMMAND "\0" +#endif +#if defined(CONFIG_RAMBOOTCOMMAND) + "ramboot=" CONFIG_RAMBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_NFSBOOTCOMMAND) + "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0" +#endif +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0" +#endif +#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) + "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" +#endif +#ifdef CONFIG_LOADS_ECHO + "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0" +#endif +#ifdef CONFIG_ETHADDR + "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0" +#endif +#ifdef CONFIG_ETH1ADDR + "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0" +#endif +#ifdef CONFIG_ETH2ADDR + "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0" +#endif +#ifdef CONFIG_ETH3ADDR + "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0" +#endif +#ifdef CONFIG_ETHPRIME + "ethprime=" CONFIG_ETHPRIME "\0" +#endif +#ifdef CONFIG_IPADDR + "ipaddr=" MK_STR(CONFIG_IPADDR) "\0" +#endif +#ifdef CONFIG_SERVERIP + "serverip=" MK_STR(CONFIG_SERVERIP) "\0" +#endif +#ifdef CFG_AUTOLOAD + "autoload=" CFG_AUTOLOAD "\0" +#endif +#ifdef CONFIG_ROOTPATH + "rootpath=" MK_STR(CONFIG_ROOTPATH) "\0" +#endif +#ifdef CONFIG_GATEWAYIP + "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0" +#endif +#ifdef CONFIG_NETMASK + "netmask=" MK_STR(CONFIG_NETMASK) "\0" +#endif +#ifdef CONFIG_HOSTNAME + "hostname=" MK_STR(CONFIG_HOSTNAME) "\0" +#endif +#ifdef CONFIG_BOOTFILE + "bootfile=" MK_STR(CONFIG_BOOTFILE) "\0" +#endif +#ifdef CONFIG_LOADADDR + "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0" +#endif +#ifdef CONFIG_NETCONSOLE_PORT + "ncport=" MK_STR(CONFIG_NETCONSOLE_PORT) "\0" +#endif +#ifdef CONFIG_CLOCKS_IN_MHZ + "clocks_in_mhz=" "1" "\0" +#endif +#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) + "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0" +#endif +#ifdef CONFIG_EXTRA_ENV_SETTINGS + CONFIG_EXTRA_ENV_SETTINGS +#endif + "\0" /* Term. env_t.data with 2 NULs */ + } +}; +#ifdef CFG_ENV_ADDR_REDUND +env_t redundand_environment __PPCENV__ = { + 0, /* CRC Sum: invalid */ + 0, /* Flags: invalid */ + { + "\0" + } +}; +#endif /* CFG_ENV_ADDR_REDUND */ + +/* + * These will end up in the .text section + * if the environment strings are embedded + * in the image. When this is used for + * tools/envcrc, they are placed in the + * .data/.sdata section. + * + */ +unsigned long env_size __PPCTEXT__ = sizeof(env_t); + +/* + * Add in absolutes. + */ +GEN_ABS(env_offset, CFG_ENV_OFFSET); + +#endif /* ENV_IS_EMBEDDED */ diff --git a/u-boot/common/exports.c b/u-boot/common/exports.c new file mode 100755 index 0000000..1461826 --- /dev/null +++ b/u-boot/common/exports.c @@ -0,0 +1,27 @@ +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void dummy(void){ +} + +unsigned long get_version(void){ + return(XF_VERSION); +} + +void jumptable_init(void){ + int i; + + gd->jt = (void **)malloc(XF_MAX * sizeof(void *)); + + for(i = 0; i < XF_MAX; i++){ + gd->jt[i] = (void *)dummy; + } + + gd->jt[XF_get_version] = (void *)get_version; + gd->jt[XF_malloc] = (void *)malloc; + gd->jt[XF_free] = (void *)free; + gd->jt[XF_get_timer] = (void *)get_timer; + gd->jt[XF_udelay] = (void *)udelay; +} diff --git a/u-boot/common/flash.c b/u-boot/common/flash.c new file mode 100755 index 0000000..6c3e130 --- /dev/null +++ b/u-boot/common/flash.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +#if !defined(CFG_NO_FLASH) + +extern flash_info_t flash_info[]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +flash_info_t * addr2info(ulong addr){ + flash_info_t *info; + int i; + + for(i = 0, info = &flash_info[0]; i < CFG_MAX_FLASH_BANKS; ++i, ++info){ + /* WARNING - The '- 1' is needed if the flash + * is at the end of the address space, since + * info->start[0] + info->size wraps back to 0. + * Please don't change this unless you understand this. + */ + if(info->flash_id != FLASH_UNKNOWN && addr >= info->start[0] && addr <= info->start[0] + info->size - 1){ + return(info); + } + } + return(NULL); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + * Make sure all target addresses are within Flash bounds, + * and no protected sectors are hit. + * Returns: + * ERR_OK 0 - OK + * ERR_TIMOUT 1 - write timeout + * ERR_NOT_ERASED 2 - Flash not erased + * ERR_PROTECTED 4 - target range includes protected sectors + * ERR_INVAL 8 - target address not in Flash memory + * ERR_ALIGN 16 - target address not aligned on boundary + * (only some targets require alignment) + */ +int flash_write(char *src, ulong addr, ulong cnt){ + int i; + ulong end = addr + cnt - 1; + flash_info_t *info_first = addr2info(addr); + flash_info_t *info_last = addr2info(end); + flash_info_t *info; + + if(cnt == 0){ + return(ERR_OK); + } + + if(!info_first || !info_last){ + return(ERR_INVAL); + } + + for(info = info_first; info <= info_last; ++info){ + ulong b_end = info->start[0] + info->size; /* bank end addr */ + short s_end = info->sector_count - 1; + for(i = 0; i < info->sector_count; ++i){ + ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; + + if((end >= info->start[i]) && (addr < e_addr) && (info->protect[i] != 0)){ + return(ERR_PROTECTED); + } + } + } + + /* finally write data to flash */ + for(info = info_first; info <= info_last && cnt > 0; ++info){ + ulong len; + + len = info->start[0] + info->size - addr; + if(len > cnt){ + len = cnt; + } + if((i = write_buff(info, (uchar *)src, addr, len)) != 0){ + return(i); + } + cnt -= len; + addr += len; + src += len; + } + return(ERR_OK); +} + +/*----------------------------------------------------------------------- + */ + +void flash_perror(int err){ + switch(err){ + case ERR_OK: + break; + case ERR_TIMOUT: + puts("## Error: timeout writing to flash\n"); + break; + case ERR_NOT_ERASED: + puts("## Error: flash not erased\n"); + break; + case ERR_PROTECTED: + puts("## Error: can't write to protected sectors\n"); + break; + case ERR_INVAL: + puts("## Error: outside available flash\n"); + break; + case ERR_ALIGN: + puts("## Error: start and/or end address not on sector boundary\n"); + break; + case ERR_UNKNOWN_FLASH_VENDOR: + puts("## Error: unknown vendor of flash\n"); + break; + case ERR_UNKNOWN_FLASH_TYPE: + puts("## Error: unknown type of flash\n"); + break; + case ERR_PROG_ERROR: + puts("## Error: general flash programming error\n"); + break; + default: + printf("## Error: %s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err); + break; + } +} + +/*----------------------------------------------------------------------- + */ +#endif /* !CFG_NO_FLASH */ diff --git a/u-boot/common/lists.c b/u-boot/common/lists.c new file mode 100755 index 0000000..3973277 --- /dev/null +++ b/u-boot/common/lists.c @@ -0,0 +1,734 @@ +#include +#include +#include + +#define MAX(a,b) (((a)>(b)) ? (a) : (b)) +#define MIN(a,b) (((a)<(b)) ? (a) : (b)) +#define CAT4CHARS(a,b,c,d) ((a<<24) | (b<<16) | (c<<8) | d) + +/* increase list size by 10% every time it is full */ +#define kDefaultAllocationPercentIncrease 10 + +/* always increase list size by 4 items when it is full */ +#define kDefaultAllocationminNumItemsIncrease 4 + +/* + * how many items to expand the list by when it becomes full + * = current listSize (in items) + (hiword percent of list size) + loword + */ +#define NUMITEMSPERALLOC(list) MAX(((*list)->listSize * \ + ((*list)->percentIncrease + 100)) / 100, \ + (*list)->minNumItemsIncrease ) + +#define ITEMPTR(list,item) &(((char *)&(*list)->itemList)[(*(list))->itemSize * (item)]) + +#define LIST_SIGNATURE CAT4CHARS('L', 'I', 'S', 'T'); + +#define calloc(size,num) malloc(size*num) + +/********************************************************************/ + +Handle NewHandle (unsigned int numBytes) +{ + void *memPtr; + HandleRecord *hanPtr; + + memPtr = calloc (numBytes, 1); + hanPtr = (HandleRecord *) calloc (sizeof (HandleRecord), 1); + if (hanPtr && (memPtr || numBytes == 0)) { + hanPtr->ptr = memPtr; + hanPtr->size = numBytes; + return (Handle) hanPtr; + } else { + free (memPtr); + free (hanPtr); + return NULL; + } +} +/********************************************************************/ + +void DisposeHandle (Handle handle) +{ + if (handle) { + free (*handle); + free ((void *) handle); + } +} +/********************************************************************/ + +unsigned int GetHandleSize (Handle handle) +{ + return ((HandleRecord *) handle)->size; +} +/********************************************************************/ + +int SetHandleSize (Handle handle, unsigned int newSize) +{ + HandleRecord *hanRecPtr = (HandleRecord *) handle; + void *newPtr, *oldPtr; + unsigned int oldSize; + + + oldPtr = hanRecPtr->ptr; + oldSize = hanRecPtr->size; + + if (oldSize == newSize) + return 1; + + if (oldPtr == NULL) { + newPtr = malloc (newSize); + } else { + newPtr = realloc (oldPtr, newSize); + } + if (newPtr || (newSize == 0)) { + hanRecPtr->ptr = newPtr; + hanRecPtr->size = newSize; + if (newSize > oldSize) + memset ((char *) newPtr + oldSize, 0, newSize - oldSize); + return 1; + } else + return 0; +} + +#ifdef CFG_ALL_LIST_FUNCTIONS + +/* Used to compare list elements by their raw data contents */ +static int ListMemBlockCmp (void *a, void *b, int size) +{ + return memcmp (a, b, size); +} + +/***************************************************************************/ + +/* + * Binary search numElements of size elementSize in array for a match + * to the. item. Return the index of the element that matches + * (0 - numElements - 1). If no match is found return the -i-1 where + * i is the index (0 - numElements) where the item should be placed. + * (*theCmp)(a,b) should return <0 if a0 if a>b. + * + * This function is like the C-Library function bsearch() except that + * this function returns the index where the item should be placed if + * it is not found. + */ +int BinSearch ( void *array, int numElements, int elementSize, + void *itemPtr, CompareFunction compareFunction) +{ + int low, high, mid, cmp; + void *arrayItemPtr; + + for (low = 0, high = numElements - 1, mid = 0, cmp = -1; low <= high;) { + mid = (low + high) >> 1; + + arrayItemPtr = (void *) (((char *) array) + (mid * elementSize)); + cmp = compareFunction + ? compareFunction (itemPtr, arrayItemPtr) + : ListMemBlockCmp (itemPtr, arrayItemPtr, elementSize); + if (cmp == 0) { + return mid; + } else if (cmp < 0) { + high = mid - 1; + } else { + low = mid + 1; + } + } + if (cmp > 0) + mid++; + + return -mid - 1; +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/*******************************************************************************/ + +/* + * If numNewItems == 0 then expand the list by the number of items + * indicated by its allocation policy. + * If numNewItems > 0 then expand the list by exactly the number of + * items indicated. + * If numNewItems < 0 then expand the list by the absolute value of + * numNewItems plus the number of items indicated by its allocation + * policy. + * Returns 1 for success, 0 if out of memory +*/ +static int ExpandListSpace (list_t list, int numNewItems) +{ + if (numNewItems == 0) { + numNewItems = NUMITEMSPERALLOC (list); + } else if (numNewItems < 0) { + numNewItems = (-numNewItems) + NUMITEMSPERALLOC (list); + } + + if (SetHandleSize ((Handle) list, + sizeof (ListStruct) + + ((*list)->listSize + + numNewItems) * (*list)->itemSize)) { + (*list)->listSize += numNewItems; + return 1; + } else { + return 0; + } +} + +/*******************************/ + +#ifdef CFG_ALL_LIST_FUNCTIONS + +/* + * This function reallocate the list, minus any currently unused + * portion of its allotted memory. + */ +void ListCompact (list_t list) +{ + + if (!SetHandleSize ((Handle) list, + sizeof (ListStruct) + + (*list)->numItems * (*list)->itemSize)) { + return; + } + + (*list)->listSize = (*list)->numItems; +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/*******************************/ + +list_t ListCreate (int elementSize) +{ + list_t list; + + list = (list_t) (NewHandle (sizeof (ListStruct))); /* create empty list */ + if (list) { + (*list)->signature = LIST_SIGNATURE; + (*list)->numItems = 0; + (*list)->listSize = 0; + (*list)->itemSize = elementSize; + (*list)->percentIncrease = kDefaultAllocationPercentIncrease; + (*list)->minNumItemsIncrease = + kDefaultAllocationminNumItemsIncrease; + } + + return list; +} + +/*******************************/ +#if 0 +void ListSetAllocationPolicy (list_t list, int minItemsPerAlloc, + int percentIncreasePerAlloc) +{ + (*list)->percentIncrease = percentIncreasePerAlloc; + (*list)->minNumItemsIncrease = minItemsPerAlloc; +} +#endif +/*******************************/ + +void ListDispose (list_t list) +{ + DisposeHandle ((Handle) list); +} +/*******************************/ + +#ifdef CFG_ALL_LIST_FUNCTIONS + +void ListDisposePtrList (list_t list) +{ + int index; + int numItems; + + if (list) { + numItems = ListNumItems (list); + + for (index = 1; index <= numItems; index++) + free (*(void **) ListGetPtrToItem (list, index)); + + ListDispose (list); + } +} + +/*******************************/ + +/* + * keeps memory, resets the number of items to 0 + */ +void ListClear (list_t list) +{ + if (!list) + return; + (*list)->numItems = 0; +} + +/*******************************/ + +/* + * copy is only as large as necessary + */ +list_t ListCopy (list_t originalList) +{ + list_t tempList = NULL; + int numItems; + + if (!originalList) + return NULL; + + tempList = ListCreate ((*originalList)->itemSize); + if (tempList) { + numItems = ListNumItems (originalList); + + if (!SetHandleSize ((Handle) tempList, + sizeof (ListStruct) + + numItems * (*tempList)->itemSize)) { + ListDispose (tempList); + return NULL; + } + + (*tempList)->numItems = (*originalList)->numItems; + (*tempList)->listSize = (*originalList)->numItems; + (*tempList)->itemSize = (*originalList)->itemSize; + (*tempList)->percentIncrease = (*originalList)->percentIncrease; + (*tempList)->minNumItemsIncrease = + (*originalList)->minNumItemsIncrease; + + memcpy (ITEMPTR (tempList, 0), ITEMPTR (originalList, 0), + numItems * (*tempList)->itemSize); + } + + return tempList; +} + +/********************************/ + +/* + * list1 = list1 + list2 + */ +int ListAppend (list_t list1, list_t list2) +{ + int numItemsL1, numItemsL2; + + if (!list2) + return 1; + + if (!list1) + return 0; + if ((*list1)->itemSize != (*list2)->itemSize) + return 0; + + numItemsL1 = ListNumItems (list1); + numItemsL2 = ListNumItems (list2); + + if (numItemsL2 == 0) + return 1; + + if (!SetHandleSize ((Handle) list1, + sizeof (ListStruct) + (numItemsL1 + numItemsL2) * + (*list1)->itemSize)) { + return 0; + } + + (*list1)->numItems = numItemsL1 + numItemsL2; + (*list1)->listSize = numItemsL1 + numItemsL2; + + memmove (ITEMPTR (list1, numItemsL1), + ITEMPTR (list2, 0), + numItemsL2 * (*list2)->itemSize); + + return 1; +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/*******************************/ + +/* + * returns 1 if the item is inserted, returns 0 if out of memory or + * bad arguments were passed. + */ +int ListInsertItem (list_t list, void *ptrToItem, int itemPosition) +{ + return ListInsertItems (list, ptrToItem, itemPosition, 1); +} + +/*******************************/ + +int ListInsertItems (list_t list, void *ptrToItems, int firstItemPosition, + int numItemsToInsert) +{ + int numItems = (*list)->numItems; + + if (firstItemPosition == numItems + 1) + firstItemPosition = LIST_END; + else if (firstItemPosition > numItems) + return 0; + + if ((*list)->numItems >= (*list)->listSize) { + if (!ExpandListSpace (list, -numItemsToInsert)) + return 0; + } + + if (firstItemPosition == LIST_START) { + if (numItems == 0) { + /* special case for empty list */ + firstItemPosition = LIST_END; + } else { + firstItemPosition = 1; + } + } + + if (firstItemPosition == LIST_END) { /* add at the end of the list */ + if (ptrToItems) + memcpy (ITEMPTR (list, numItems), ptrToItems, + (*list)->itemSize * numItemsToInsert); + else + memset (ITEMPTR (list, numItems), 0, + (*list)->itemSize * numItemsToInsert); + + (*list)->numItems += numItemsToInsert; + } else { /* move part of list up to make room for new item */ + memmove (ITEMPTR (list, firstItemPosition - 1 + numItemsToInsert), + ITEMPTR (list, firstItemPosition - 1), + (numItems + 1 - firstItemPosition) * (*list)->itemSize); + + if (ptrToItems) + memmove (ITEMPTR (list, firstItemPosition - 1), ptrToItems, + (*list)->itemSize * numItemsToInsert); + else + memset (ITEMPTR (list, firstItemPosition - 1), 0, + (*list)->itemSize * numItemsToInsert); + + (*list)->numItems += numItemsToInsert; + } + + return 1; +} + +#ifdef CFG_ALL_LIST_FUNCTIONS + +/*******************************/ + +int ListEqual (list_t list1, list_t list2) +{ + if (list1 == list2) + return 1; + + if (list1 == NULL || list2 == NULL) + return 0; + + if ((*list1)->itemSize == (*list1)->itemSize) { + if ((*list1)->numItems == (*list2)->numItems) { + return (memcmp (ITEMPTR (list1, 0), ITEMPTR (list2, 0), + (*list1)->itemSize * (*list1)->numItems) == 0); + } + } + + return 0; +} + +/*******************************/ + +/* + * The item pointed to by ptrToItem is copied over the current item + * at itemPosition + */ +void ListReplaceItem (list_t list, void *ptrToItem, int itemPosition) +{ + ListReplaceItems (list, ptrToItem, itemPosition, 1); +} + +/*******************************/ + +/* + * The item pointed to by ptrToItems is copied over the current item + * at itemPosition + */ +void ListReplaceItems ( list_t list, void *ptrToItems, + int firstItemPosition, int numItemsToReplace) +{ + + if (firstItemPosition == LIST_END) + firstItemPosition = (*list)->numItems; + else if (firstItemPosition == LIST_START) + firstItemPosition = 1; + + memmove (ITEMPTR (list, firstItemPosition - 1), ptrToItems, + (*list)->itemSize * numItemsToReplace); +} + +/*******************************/ + +void ListGetItem (list_t list, void *itemDestination, int itemPosition) +{ + ListGetItems (list, itemDestination, itemPosition, 1); +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/*******************************/ + +#if defined(CFG_ALL_LIST_FUNCTIONS) || defined(CFG_DEVICE_DEREGISTER) + +void ListRemoveItem (list_t list, void *itemDestination, int itemPosition) +{ + ListRemoveItems (list, itemDestination, itemPosition, 1); +} + +/*******************************/ + +void ListRemoveItems (list_t list, void *itemsDestination, + int firstItemPosition, int numItemsToRemove) +{ + int firstItemAfterChunk, numToMove; + + if (firstItemPosition == LIST_START) + firstItemPosition = 1; + else if (firstItemPosition == LIST_END) + firstItemPosition = (*list)->numItems; + + if (itemsDestination != NULL) + memcpy (itemsDestination, ITEMPTR (list, firstItemPosition - 1), + (*list)->itemSize * numItemsToRemove); + + firstItemAfterChunk = firstItemPosition + numItemsToRemove; + numToMove = (*list)->numItems - (firstItemAfterChunk - 1); + + if (numToMove > 0) { + /* + * move part of list down to cover hole left by removed item + */ + memmove (ITEMPTR (list, firstItemPosition - 1), + ITEMPTR (list, firstItemAfterChunk - 1), + (*list)->itemSize * numToMove); + } + + (*list)->numItems -= numItemsToRemove; +} +#endif /* CFG_ALL_LIST_FUNCTIONS || CFG_DEVICE_DEREGISTER */ + +/*******************************/ +#if 0 +void ListGetItems (list_t list, void *itemsDestination, + int firstItemPosition, int numItemsToGet) +{ + + if (firstItemPosition == LIST_START) + firstItemPosition = 1; + else if (firstItemPosition == LIST_END) + firstItemPosition = (*list)->numItems; + + memcpy (itemsDestination, + ITEMPTR (list, firstItemPosition - 1), + (*list)->itemSize * numItemsToGet); +} +#endif +/*******************************/ + +/* + * Returns a pointer to the item at itemPosition. returns null if an + * errors occurred. + */ +void *ListGetPtrToItem (list_t list, int itemPosition) +{ + if (itemPosition == LIST_START) + itemPosition = 1; + else if (itemPosition == LIST_END) + itemPosition = (*list)->numItems; + + return ITEMPTR (list, itemPosition - 1); +} + +/*******************************/ +#if 0 +/* + * returns a pointer the lists data (abstraction violation for + * optimization) + */ +void *ListGetDataPtr (list_t list) +{ + return &((*list)->itemList[0]); +} +#endif +/********************************/ + +#ifdef CFG_ALL_LIST_FUNCTIONS + +int ListApplyToEach (list_t list, int ascending, + ListApplicationFunc funcToApply, + void *callbackData) +{ + int result = 0, index; + + if (!list || !funcToApply) + goto Error; + + if (ascending) { + for (index = 1; index <= ListNumItems (list); index++) { + result = funcToApply (index, + ListGetPtrToItem (list, index), + callbackData); + if (result < 0) + goto Error; + } + } else { + for (index = ListNumItems (list); + index > 0 && index <= ListNumItems (list); + index--) { + result = funcToApply (index, + ListGetPtrToItem (list, index), + callbackData); + if (result < 0) + goto Error; + } + } + +Error: + return result; +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ + +/********************************/ +#if 0 +int ListGetItemSize (list_t list) +{ + return (*list)->itemSize; +} +#endif +/********************************/ + +int ListNumItems (list_t list) +{ + return (*list)->numItems; +} + +/*******************************/ + +#ifdef CFG_ALL_LIST_FUNCTIONS + +void ListRemoveDuplicates (list_t list, CompareFunction compareFunction) +{ + int numItems, index, startIndexForFind, duplicatesIndex; + + numItems = ListNumItems (list); + + for (index = 1; index < numItems; index++) { + startIndexForFind = index + 1; + while (startIndexForFind <= numItems) { + duplicatesIndex = + ListFindItem (list, + ListGetPtrToItem (list, index), + startIndexForFind, + compareFunction); + if (duplicatesIndex > 0) { + ListRemoveItem (list, NULL, duplicatesIndex); + numItems--; + startIndexForFind = duplicatesIndex; + } else { + break; + } + } + } +} + +/*******************************/ + + +/*******************************/ + +int ListFindItem (list_t list, void *ptrToItem, int startingPosition, + CompareFunction compareFunction) +{ + int numItems, size, index, cmp; + void *listItemPtr; + + if ((numItems = (*list)->numItems) == 0) + return 0; + + size = (*list)->itemSize; + + if (startingPosition == LIST_START) + startingPosition = 1; + else if (startingPosition == LIST_END) + startingPosition = numItems; + + for (index = startingPosition; index <= numItems; index++) { + listItemPtr = ITEMPTR (list, index - 1); + cmp = compareFunction + ? compareFunction (ptrToItem, listItemPtr) + : ListMemBlockCmp (ptrToItem, listItemPtr, size); + if (cmp == 0) + return index; + } + + return 0; +} + +/*******************************/ + +int ShortCompare (void *a, void *b) +{ + if (*(short *) a < *(short *) b) + return -1; + if (*(short *) a > *(short *) b) + return 1; + return 0; +} + +/*******************************/ + +int IntCompare (void *a, void *b) +{ + if (*(int *) a < *(int *) b) + return -1; + if (*(int *) a > *(int *) b) + return 1; + return 0; +} + +/*******************************/ + +int CStringCompare (void *a, void *b) +{ + return strcmp (*(char **) a, *(char **) b); +} + +/*******************************/ + + +int ListBinSearch (list_t list, void *ptrToItem, + CompareFunction compareFunction) +{ + int index; + + index = BinSearch (ITEMPTR (list, 0), + (int) (*list)->numItems, + (int) (*list)->itemSize, ptrToItem, + compareFunction); + + if (index >= 0) + index++; /* lists start from 1 */ + else + index = 0; /* item not found */ + + return index; +} + +/**************************************************************************/ + +/* + * Reserves memory for numItems in the list. If it succeeds then + * numItems items can be inserted without possibility of an out of + * memory error (useful to simplify error recovery in complex + * functions). Returns 1 if success, 0 if out of memory. + */ +int ListPreAllocate (list_t list, int numItems) +{ + if ((*list)->listSize - (*list)->numItems < numItems) { + return ExpandListSpace (list, + numItems - ((*list)->listSize - + (*list)->numItems)); + } else { + return 1; /* enough items are already pre-allocated */ + } +} + +#endif /* CFG_ALL_LIST_FUNCTIONS */ diff --git a/u-boot/common/main.c b/u-boot/common/main.c new file mode 100755 index 0000000..47de5a9 --- /dev/null +++ b/u-boot/common/main.c @@ -0,0 +1,652 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include +#include + +#ifdef CONFIG_SILENT_CONSOLE +DECLARE_GLOBAL_DATA_PTR; +#endif + +extern int reset_button_status(void); +extern void all_led_on(void); +extern void all_led_off(void); +extern int NetLoopHttpd(void); + +#define MAX_DELAY_STOP_STR 32 + +static char *delete_char(char *buffer, char *p, int *colp, int *np, int plen); +static int parse_line(char *, char *[]); +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) +static int abortboot(int); +#endif + +char console_buffer[CFG_CBSIZE]; /* console I/O buffer */ +static char erase_seq[] = "\b \b"; /* erase sequence */ +static char tab_seq[] = " "; /* used to expand TABs */ + +/*************************************************************************** + * Watch for 'delay' seconds for autoboot stop or autoboot delay string. + * returns: 0 - no key string, allow autoboot + * 1 - got key string, abort + */ +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) +static __inline__ int abortboot(int bootdelay){ + int abort = 0; + +#ifdef CONFIG_SILENT_CONSOLE + if(gd->flags & GD_FLG_SILENT){ + /* Restore serial console */ + console_assign(stdout, "serial"); + console_assign(stderr, "serial"); + } +#endif + +#ifdef CONFIG_MENUPROMPT + printf(CONFIG_MENUPROMPT, bootdelay); +#else + printf("Hit any key to stop autoboot: %d ", bootdelay); +#endif + + while((bootdelay > 0) && (!abort)){ + int i; + + --bootdelay; + + /* delay 100 * 10ms */ + for(i = 0; !abort && i < 100; ++i){ + + /* we got a key press */ + if(tstc()){ + /* don't auto boot */ + abort = 1; + /* no more delay */ + bootdelay = 0; + /* consume input */ + (void) getc(); + break; + } + udelay(10000); + } + + printf("\b\b%d ", bootdelay); + } + + printf("\n\n"); + +#ifdef CONFIG_SILENT_CONSOLE + if(abort){ + /* permanently enable normal console output */ + gd->flags &= ~(GD_FLG_SILENT); + } else if(gd->flags & GD_FLG_SILENT){ + /* Restore silent console */ + console_assign(stdout, "nulldev"); + console_assign(stderr, "nulldev"); + } +#endif + + return(abort); +} +#endif /* CONFIG_BOOTDELAY >= 0 */ + +/****************************************************************************/ + +void main_loop(void){ + static char lastcommand[CFG_CBSIZE] = { 0, }; + int len; + int rc = 1; + int flag; + int counter = 0; + +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + char *s; + int bootdelay; + + // get boot delay (seconds) + s = getenv("bootdelay"); + bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; + + // get boot command + s = getenv("bootcmd"); + +#if !defined(CONFIG_BOOTCOMMAND) +#error "CONFIG_BOOTCOMMAND not defined!" +#endif + + if(!s){ + setenv("bootcmd", CONFIG_BOOTCOMMAND); + } + + s = getenv("bootcmd"); + + // are we going to run web failsafe mode, U-Boot console, U-Boot netconsole or just boot command? + if(reset_button_status()){ + + // wait 0,5s + milisecdelay(500); + + printf("Press reset button for at least:\n- %d sec. to run web failsafe mode\n- %d sec. to run U-Boot console\n- %d sec. to run U-Boot netconsole\n\n", + CONFIG_DELAY_TO_AUTORUN_HTTPD, + CONFIG_DELAY_TO_AUTORUN_CONSOLE, + CONFIG_DELAY_TO_AUTORUN_NETCONSOLE); + + printf("Reset button is pressed for: %2d ", counter); + + while(reset_button_status()){ + + // LED ON and wait 0,15s + all_led_on(); + milisecdelay(150); + + // LED OFF and wait 0,85s + all_led_off(); + milisecdelay(850); + + counter++; + + // how long the button is pressed? + printf("\b\b\b%2d ", counter); + + if(!reset_button_status()){ + break; + } + + if(counter >= CONFIG_MAX_BUTTON_PRESSING){ + break; + } + } + + all_led_off(); + + if(counter > 0){ + + // run web failsafe mode + if(counter >= CONFIG_DELAY_TO_AUTORUN_HTTPD && counter < CONFIG_DELAY_TO_AUTORUN_CONSOLE){ + printf("\n\nButton was pressed for %d sec...\nHTTP server is starting for firmware update...\n\n", counter); + NetLoopHttpd(); + bootdelay = -1; + } else if(counter >= CONFIG_DELAY_TO_AUTORUN_CONSOLE && counter < CONFIG_DELAY_TO_AUTORUN_NETCONSOLE){ + printf("\n\nButton was pressed for %d sec...\nStarting U-Boot console...\n\n", counter); + bootdelay = -1; + } else if(counter >= CONFIG_DELAY_TO_AUTORUN_NETCONSOLE){ + printf("\n\nButton was pressed for %d sec...\nStarting U-Boot netconsole...\n\n", counter); + bootdelay = -1; + run_command("startnc", 0); + } else { + printf("\n\n## Error: button wasn't pressed long enough!\nContinuing normal boot...\n\n"); + } + + } else { + printf("\n\n## Error: button wasn't pressed long enough!\nContinuing normal boot...\n\n"); + } + + } + + if(bootdelay >= 0 && s && !abortboot(bootdelay)){ + + // try to boot + run_command(s, 0); + + // something goes wrong! + printf("\n## Error: failed to execute 'bootcmd'!\nHTTP server is starting for firmware update...\n\n"); + NetLoopHttpd(); + } +#endif /* CONFIG_BOOTDELAY */ + + /* + * Main Loop for Monitor Command Processing + */ + for(;;){ + len = readline(CFG_PROMPT); + + flag = 0; /* assume no special flags for now */ + if(len > 0){ + strcpy(lastcommand, console_buffer); + } else if(len == 0){ + flag |= CMD_FLAG_REPEAT; + } + + if(len == -1){ + puts("\n"); + } else { + rc = run_command(lastcommand, flag); + } + + if(rc <= 0){ + /* invalid command or not repeatable, forget it */ + lastcommand[0] = 0; + } + } +} + +/****************************************************************************/ + +/* + * Prompt for input and read a line. + * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0, + * time out when time goes past endtime (timebase time in ticks). + * Return: number of read characters + * -1 if break + * -2 if timed out + */ +int readline(const char * const prompt){ + char *p = console_buffer; + int n = 0; /* buffer index */ + int plen = 0; /* prompt length */ + int col; /* output column cnt */ + char c; + + /* print prompt */ + if(prompt){ + plen = strlen(prompt); + puts(prompt); + } + col = plen; + + for(;;){ + c = getc(); + + /* + * Special character handling + */ + switch(c){ + case '\r': /* Enter */ + case '\n': + *p = '\0'; + puts("\r\n"); + return(p - console_buffer); + + case '\0': /* nul */ + continue; + + case 0x03: /* ^C - break */ + console_buffer[0] = '\0'; /* discard input */ + return(-1); + + case 0x15: /* ^U - erase line */ + while(col > plen){ + puts(erase_seq); + --col; + } + p = console_buffer; + n = 0; + continue; + + case 0x17: /* ^W - erase word */ + p = delete_char(console_buffer, p, &col, &n, plen); + while((n > 0) && (*p != ' ')){ + p = delete_char(console_buffer, p, &col, &n, plen); + } + continue; + + case 0x08: /* ^H - backspace */ + case 0x7F: /* DEL - backspace */ + p = delete_char(console_buffer, p, &col, &n, plen); + continue; + + default: + /* + * Must be a normal character then + */ + if(n < CFG_CBSIZE - 2){ + if(c == '\t'){ /* expand TABs */ + puts(tab_seq + (col & 07)); + col += 8 - (col & 07); + } else { + ++col; /* echo input */ + putc(c); + } + *p++ = c; + ++n; + } else { /* Buffer full */ + putc('\a'); + } + } + } +} + +/****************************************************************************/ + +static char * delete_char(char *buffer, char *p, int *colp, int *np, int plen){ + char *s; + + if(*np == 0){ + return(p); + } + + if(*(--p) == '\t'){ /* will retype the whole line */ + while(*colp > plen){ + puts(erase_seq); + (*colp)--; + } + for(s = buffer; s < p; ++s){ + if(*s == '\t'){ + puts(tab_seq + ((*colp) & 07)); + *colp += 8 - ((*colp) & 07); + } else { + ++(*colp); + putc(*s); + } + } + } else { + puts(erase_seq); + (*colp)--; + } + (*np)--; + return(p); +} + +/****************************************************************************/ + +int parse_line(char *line, char *argv[]){ + int nargs = 0; + + while(nargs < CFG_MAXARGS){ + + /* skip any white space */ + while((*line == ' ') || (*line == '\t')){ + ++line; + } + + if(*line == '\0'){ /* end of line, no more args */ + argv[nargs] = NULL; + return(nargs); + } + + argv[nargs++] = line; /* begin of argument string */ + + /* find end of string */ + while(*line && (*line != ' ') && (*line != '\t')){ + ++line; + } + + if(*line == '\0'){ /* end of line, no more args */ + argv[nargs] = NULL; + return(nargs); + } + + *line++ = '\0'; /* terminate current arg */ + } + + printf("## Error: too many args (max. %d)\n", CFG_MAXARGS); + + return(nargs); +} + +/****************************************************************************/ + +static void process_macros(const char *input, char *output){ + char c, prev; + const char *varname_start = NULL; + int inputcnt = strlen(input); + int outputcnt = CFG_CBSIZE; + int state = 0; /* 0 = waiting for '$' */ + /* 1 = waiting for '(' or '{' */ + /* 2 = waiting for ')' or '}' */ + /* 3 = waiting for ''' */ + + prev = '\0'; /* previous character */ + + while(inputcnt && outputcnt){ + c = *input++; + inputcnt--; + + if(state != 3){ + /* remove one level of escape characters */ + if((c == '\\') && (prev != '\\')){ + if(inputcnt-- == 0){ + break; + } + + prev = c; + c = *input++; + } + } + + switch(state){ + case 0: /* Waiting for (unescaped) $ */ + if((c == '\'') && (prev != '\\')){ + state = 3; + break; + } + if((c == '$') && (prev != '\\')){ + state++; + } else { + *(output++) = c; + outputcnt--; + } + break; + case 1: /* Waiting for ( */ + if(c == '(' || c == '{'){ + state++; + varname_start = input; + } else { + state = 0; + *(output++) = '$'; + outputcnt--; + + if(outputcnt){ + *(output++) = c; + outputcnt--; + } + } + break; + case 2: /* Waiting for ) */ + if(c == ')' || c == '}'){ + int i; + char envname[CFG_CBSIZE], *envval; + int envcnt = input - varname_start - 1; /* Varname # of chars */ + + /* Get the varname */ + for(i = 0; i < envcnt; i++){ + envname[i] = varname_start[i]; + } + envname[i] = 0; + + /* Get its value */ + envval = getenv(envname); + + /* Copy into the line if it exists */ + if(envval != NULL){ + while((*envval) && outputcnt){ + *(output++) = *(envval++); + outputcnt--; + } + } + /* Look for another '$' */ + state = 0; + } + break; + case 3: /* Waiting for ' */ + if((c == '\'') && (prev != '\\')){ + state = 0; + } else { + *(output++) = c; + outputcnt--; + } + break; + } + prev = c; + } + + if(outputcnt){ + *output = 0; + } +} + +/**************************************************************************** + * returns: + * 1 - command executed, repeatable + * 0 - command executed but not repeatable, interrupted commands are + * always considered not repeatable + * -1 - not executed (unrecognized, bootd recursion or too many args) + * (If cmd is NULL or "" or longer than CFG_CBSIZE-1 it is + * considered unrecognized) + * + * WARNING: + * + * We must create a temporary copy of the command since the command we get + * may be the result from getenv(), which returns a pointer directly to + * the environment data, which may change magicly when the command we run + * creates or modifies environment variables (like "bootp" does). + */ + +int run_command(const char *cmd, int flag){ + cmd_tbl_t *cmdtp; + char cmdbuf[CFG_CBSIZE]; /* working copy of cmd */ + char *token; /* start of token in cmdbuf */ + char *sep; /* end of token (separator) in cmdbuf */ + char finaltoken[CFG_CBSIZE]; + char *str = cmdbuf; + char *argv[CFG_MAXARGS + 1]; /* NULL terminated */ + int argc, inquotes; + int repeatable = 1; + int rc = 0; + + clear_ctrlc(); /* forget any previous Control C */ + + if(!cmd || !*cmd){ + return(-1); /* empty command */ + } + + if(strlen(cmd) >= CFG_CBSIZE){ + puts("## Error: command too long!\n"); + return(-1); + } + + strcpy(cmdbuf, cmd); + + /* Process separators and check for invalid + * repeatable commands + */ + while(*str){ + + /* + * Find separator, or string end + * Allow simple escape of ';' by writing "\;" + */ + for(inquotes = 0, sep = str; *sep; sep++){ + if((*sep == '\'') && (*(sep - 1) != '\\')){ + inquotes = !inquotes; + } + + if(!inquotes && (*sep == ';') && (sep != str) && (*(sep - 1) != '\\')){ + break; + } + } + + /* + * Limit the token to data between separators + */ + token = str; + if(*sep){ + str = sep + 1; /* start of command for next pass */ + *sep = '\0'; + } else { + str = sep; /* no more commands for next pass */ + } + + /* find macros in this token and replace them */ + process_macros(token, finaltoken); + + /* Extract arguments */ + if((argc = parse_line(finaltoken, argv)) == 0){ + rc = -1; /* no command at all */ + continue; + } + + /* Look up command in command table */ + if((cmdtp = find_cmd(argv[0])) == NULL){ + printf("## Error: unknown command '%s' - try 'help'\n\n", argv[0]); + rc = -1; /* give up after bad command */ + continue; + } + + /* found - check max args */ + if(argc > cmdtp->maxargs){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + rc = -1; + continue; + } + + /* OK - call function to do the command */ + if((cmdtp->cmd)(cmdtp, flag, argc, argv) != 0){ + rc = -1; + } + + repeatable &= cmdtp->repeatable; + + /* Did the user stop this? */ + if(had_ctrlc()){ /* if stopped then not repeatable */ + return(0); + } + } + + return(rc ? rc : repeatable); +} + +/****************************************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_RUN) +int do_run(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + int i; + + if(argc < 2){ +#ifdef CFG_LONGHELP + if(cmdtp->help != NULL){ + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->help); + } else { + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); + } +#else + printf("Usage:\n%s %s\n", cmdtp->name, cmdtp->usage); +#endif + return(1); + } + + for(i=1; i /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;) + +# +# Include the make variables (CC, etc...) +# +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +RANLIB = $(CROSS_COMPILE)RANLIB + +.depend : CC = @$(CROSS_COMPILE)gcc + +RELFLAGS= $(PLATFORM_RELFLAGS) +OPTFLAGS= -O +ifndef LDSCRIPT +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds +endif +OBJCFLAGS += --gap-fill=0xff + +LDSCRIPT_BOOTSTRAP := $(TOPDIR)/board/$(BOARDDIR)/u-boot-bootstrap.lds + +gccincdir := $(shell $(CC) -print-file-name=include) + +CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ + -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ + -I$(TOPDIR)/include \ + -fno-builtin -ffreestanding -nostdinc -isystem \ + $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) + +ifdef BUILD_TAG +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ + -DBUILD_TAG='"$(BUILD_TAG)"' +else +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes +ifeq ($(COMPRESSED_UBOOT),1) +CFLAGS += -DCOMPRESSED_UBOOT=1 +else +CFLAGS += -DCOMPRESSED_UBOOT=0 +endif + +ifeq ($(BUILD_OPTIMIZED),y) +CFLAGS += -Os -funit-at-a-time -mips32r2 -mtune=mips32r2 +endif +endif + +ifeq ($(BUILD_TYPE),jffs2) +CFLAGS += -DROOTFS=1 +else +ifeq ($(BUILD_TYPE),squashfs) +CFLAGS += -DROOTFS=2 +endif +endif + +# avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9) +# this option have to be placed behind -Wall -- that's why it is here +ifeq ($(ARCH),nios) +ifeq ($(findstring 2.9,$(shell $(CC) --version)),2.9) +CFLAGS := $(CPPFLAGS) -Wall -Wno-trigraphs +endif +endif + +ifeq ($(BUILD_TYPE),jffs2) +CFLAGS += -DROOTFS=1 +else +ifeq ($(BUILD_TYPE),squashfs) +CFLAGS += -DROOTFS=2 +endif +endif + +AFLAGS_DEBUG := -Wa,-gstabs + +AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) +ifeq ($(COMPRESSED_UBOOT),1) +AFLAGS += -DCOMPRESSED_UBOOT=1 +else +AFLAGS += -DCOMPRESSED_UBOOT=0 +endif + +LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) + +ifeq ($(COMPRESSED_UBOOT), 1) +LDFLAGS_BOOTSTRAP += -Bstatic -T $(LDSCRIPT_BOOTSTRAP) -Ttext $(BOOTSTRAP_TEXT_BASE) $(PLATFORM_LDFLAGS) +endif + +# Location of a usable BFD library, where we define "usable" as +# "built for ${HOST}, supports ${TARGET}". Sensible values are +# - When cross-compiling: the root of the cross-environment +# - Linux/ppc (native): /usr +# - NetBSD/ppc (native): you lose ... (must extract these from the +# binutils build directory, plus the native and U-Boot include +# files don't like each other) +# +# So far, this is used only by tools/gdb/Makefile. + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +BFD_ROOT_DIR = /usr/local/tools +else +ifeq ($(HOSTARCH),$(ARCH)) +# native +BFD_ROOT_DIR = /usr +else +#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 +#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 +BFD_ROOT_DIR = /opt/powerpc +endif +endif + +ifeq ($(PCI_CLOCK),PCI_66M) +CFLAGS := $(CFLAGS) -DPCI_66M +endif + +#CFLAGS += $(UBOOT_GCC_4_3_3_EXTRA_CFLAGS) -g +CFLAGS += $(UBOOT_GCC_4_3_3_EXTRA_CFLAGS) + +######################################################################### + +export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ + AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \ + MAKE +export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS + +ifeq ($(V),1) + Q = +else + Q = @ +endif + +export quiet Q V + +######################################################################### + +%.s: %.S +ifneq ($(V),1) + @echo [CPP] $(CURDIR)/$< +endif + $(Q)$(CPP) $(AFLAGS) -o $@ $(CURDIR)/$< + +%.o: %.S +ifneq ($(V),1) + @echo [CC] $(CURDIR)/$< +endif + $(Q)$(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$< + +%.o: %.c +ifneq ($(V),1) + @echo [CC] $(CURDIR)/$< +endif + $(Q)$(CC) $(CFLAGS) -c -o $@ $< + +######################################################################### diff --git a/u-boot/cpu/mips/Makefile b/u-boot/cpu/mips/Makefile new file mode 100755 index 0000000..2944b66 --- /dev/null +++ b/u-boot/cpu/mips/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +ifeq ($(COMRESSED_UBOOT),1) +START = start.o start_bootstrap.o +else +START = start.o +endif + +OBJS = cpu.o +SOBJS = cache.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/cpu/mips/ar7240/Makefile b/u-boot/cpu/mips/ar7240/Makefile new file mode 100755 index 0000000..ce36dfc --- /dev/null +++ b/u-boot/cpu/mips/ar7240/Makefile @@ -0,0 +1,37 @@ +include $(TOPDIR)/config.mk + +LIB = lib$(SOC).a + +START = +#OBJS = ar7240_serial.o ag7240.o ar7240_flash.o meminit.o + +OBJS = meminit.o + +ifeq ($(BOARD), ap121) +OBJS += hornet_serial.o +SOBJS += hornet_ddr_init.o +else +OBJS += ar7240_serial.o +endif + +ifeq ($(BOARD), db12x) +OBJS += ag934x.o +else +OBJS += ag7240.o +endif + +SOBJS += + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) $(SOBJS) $(OBJS-0) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/cpu/mips/ar7240/ag7240.c b/u-boot/cpu/mips/ar7240/ag7240.c new file mode 100755 index 0000000..6b6aefe --- /dev/null +++ b/u-boot/cpu/mips/ar7240/ag7240.c @@ -0,0 +1,707 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "ar7240_soc.h" +#include "ag7240.h" +#include "ag7240_phy.h" + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +#include +#else +#define _1000BASET 1000 +#define _100BASET 100 +#define _10BASET 10 +#endif + +#define ag7240_unit2mac(_unit) ag7240_macs[(_unit)] +#define ag7240_name2mac(name) strcmp(name,"eth0") ? ag7240_unit2mac(1) : ag7240_unit2mac(0) +#define CHECK_BIT(var,pos) ((var) & (1<<(pos))) + +uint16_t ag7240_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg); + +void ag7240_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data); + +ag7240_mac_t *ag7240_macs[CFG_AG7240_NMACS]; + +extern void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq); + +extern int athrs26_phy_setup(int unit); +extern int athrs26_phy_is_up(int unit); +extern int athrs26_phy_is_fdx(int unit); +extern int athrs26_phy_speed(int unit); +extern void athrs26_reg_init(void); +extern void athrs26_reg_init_lan(void); +extern int athrs26_mdc_check(void); + +#ifdef CONFIG_F1E_PHY +extern int athr_phy_setup(int unit); +extern int athr_phy_is_up(int unit); +extern int athr_phy_is_fdx(int unit); +extern int athr_phy_speed(int unit); +extern void athr_reg_init(void); +#endif + +static int ag7240_send(struct eth_device *dev, volatile void *packet, int length) { + int i; + + ag7240_mac_t *mac = (ag7240_mac_t *) dev->priv; + + ag7240_desc_t *f = mac->fifo_tx[mac->next_tx]; + + f->pkt_size = length; + f->res1 = 0; + f->pkt_start_addr = virt_to_phys(packet); + + ag7240_tx_give_to_dma(f); + flush_cache((u32) packet, length); + ag7240_reg_wr(mac, AG7240_DMA_TX_DESC, virt_to_phys(f)); + ag7240_reg_wr(mac, AG7240_DMA_TX_CTRL, AG7240_TXE); + + for (i = 0; i < MAX_WAIT; i++) { + udelay(10); + if (!ag7240_tx_owned_by_dma(f)) + break; + } + + if (i == MAX_WAIT) { + printf("Tx Timed out\n"); + } + + f->pkt_start_addr = 0; + f->pkt_size = 0; + + if (++mac->next_tx >= NO_OF_TX_FIFOS) { + mac->next_tx = 0; + } + + return (0); +} + +static int ag7240_recv(struct eth_device *dev) { + int length; + ag7240_desc_t *f; + ag7240_mac_t *mac; + + mac = (ag7240_mac_t *) dev->priv; + + for (;;) { + f = mac->fifo_rx[mac->next_rx]; + + if (ag7240_rx_owned_by_dma(f)) { + break; + } + + length = f->pkt_size; + + NetReceive(NetRxPackets[mac->next_rx], length - 4); + flush_cache((u32) NetRxPackets[mac->next_rx], PKTSIZE_ALIGN); + + ag7240_rx_give_to_dma(f); + + if (++mac->next_rx >= NO_OF_RX_FIFOS) { + mac->next_rx = 0; + } + } + + if (!(ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL))) { + ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(f)); + ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 1); + } + + return (0); +} + +/* + * Called in ag7240_hw_start() function + * */ +void ag7240_mii_setup(ag7240_mac_t *mac) { + u32 mgmt_cfg_val; + u32 cpu_freq, ddr_freq, ahb_freq; + u32 check_cnt; + +#ifdef CFG_ATHRS27_PHY + if (is_wasp()) { + printf("WASP ----> S27 PHY \n"); + mgmt_cfg_val = 2; + ar7240_reg_wr(0xb8050024, 0x271); // 25MHz ref clock + //ar7240_reg_wr(0xb8050024, 0x570); // 40MHz ref clock + ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + return; + } +#endif + +#ifdef CONFIG_AR7242_S16_PHY + if (is_wasp()) { + printf("WASP ----> S16 PHY *\n"); + mgmt_cfg_val = 4; + if(mac->mac_unit == 0) + ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0); + + ar7240_reg_rmw_clear(AG7240_ETH_SWITCH_CLK_SPARE, (1 << 6)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + + return; + } +#endif + +#ifdef CONFIG_F1E_PHY + if (is_wasp()) { + printf("WASP ----> F1 PHY *\n"); + mgmt_cfg_val = 6; + if(mac->mac_unit == 0) + ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0); + + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + + return; + } +#endif + + if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) { + mgmt_cfg_val = 0x2; + if (mac->mac_unit == 0) { + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + } + } else { + ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq); + + switch (ahb_freq / 1000000) { + case 150: + mgmt_cfg_val = 0x7; + break; + case 175: + mgmt_cfg_val = 0x5; + break; + case 200: + mgmt_cfg_val = 0x4; + break; + case 210: + mgmt_cfg_val = 0x9; + break; + case 220: + mgmt_cfg_val = 0x9; + break; + default: + mgmt_cfg_val = 0x7; + } + if ((is_ar7241() || is_ar7242())) { + + /* External MII mode */ + if (mac->mac_unit == 0 && is_ar7242()) { + mgmt_cfg_val = 0x6; + ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + } + /* Virian */ + mgmt_cfg_val = 0x4; + ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + printf("Virian MDC CFG Value ==> %x\n", mgmt_cfg_val); + + } else if (is_ar933x()) { + //GE0 receives Rx/Tx clock, and use S26 phy + ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE); + mgmt_cfg_val = 0xF; + if (mac->mac_unit == 1) { + check_cnt = 0; + while (check_cnt++ < 10) { + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); +#ifdef CFG_ATHRS26_PHY + if (athrs26_mdc_check() == 0) { + break; + } +#endif + } + if (check_cnt == 11) { + printf("%s: MDC check failed\n", __func__); + } + } + } else { /* Python 1.0 & 1.1 */ + if (mac->mac_unit == 0) { + check_cnt = 0; + while (check_cnt++ < 10) { + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); +#ifdef CFG_ATHRS26_PHY + if (athrs26_mdc_check() == 0) { + break; + } +#endif + } + if (check_cnt == 11) { + printf("%s: MDC check failed\n", __func__); + } + } + } + + } +} + +static void ag7240_hw_start(ag7240_mac_t *mac) { + + if (mac->mac_unit) { + ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN)); + ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_1000)); + } else { + ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN)); + ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_10_100)); + } + + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_0, 0x1f00); + ag7240_mii_setup(mac); + + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_1, 0x10ffff); + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_2, 0xAAA0555); + + ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_4, 0x3ffff); + + // TODO: check this register + /* + * When enable the web failsafe mode in uboot,you can't drop the broadcast + * frames now,the PC first will tx a ARP request packet, it's a broadcast packet. + */ + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x66b82); + /* + * Setting Drop CRC Errors, Pause Frames, Length Error frames + * and Multi/Broad cast frames. + */ + //ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x7eccf); + + + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_3, 0x1f00140); + //printf("cfg1:\t%#x\ncfg2:\t%#x\n", ag7240_reg_rd(mac, AG7240_MAC_CFG1), ag7240_reg_rd(mac, AG7240_MAC_CFG2)); +} + +static int ag7240_check_link(ag7240_mac_t *mac) { + int link = 0, duplex = 0, speed = 0; + char *s; + + s = getenv("stdin"); + + ag7240_phy_link(mac->mac_unit, &link); + ag7240_phy_duplex(mac->mac_unit, &duplex); + ag7240_phy_speed(mac->mac_unit, &speed); + + mac->link = link; + + if (!mac->link) { + if((s != NULL) && (strcmp(s, "nc") != 0)){ + printf("Link down: %s\n", mac->dev->name); + } + return 0; + } + + switch (speed) { + case _1000BASET: + ag7240_set_mac_if(mac, 1); + ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19)); + if (is_ar7242() && (mac->mac_unit == 0)) { + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1c000000); + } +#ifdef CONFIG_F1E_PHY + if (is_wasp() && (mac->mac_unit == 0)) { + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0e000000); + } +#else + if (is_wasp() && (mac->mac_unit == 0)) { + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x06000000); + } +#endif + break; + + case _100BASET: + ag7240_set_mac_if(mac, 0); + ag7240_set_mac_speed(mac, 1); + ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19)); + if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0)){ + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0101); + } + break; + + case _10BASET: + ag7240_set_mac_if(mac, 0); + ag7240_set_mac_speed(mac, 0); + ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19)); + if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0)){ + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1616); + } + break; + + default: + if((s != NULL) && (strcmp(s, "nc") != 0)){ + printf("## Error: invalid speed detected\n"); + } + return 0; + } + + if (mac->link && (duplex == mac->duplex) && (speed == mac->speed)){ + return 1; + } + + mac->duplex = duplex; + mac->speed = speed; + + if((s != NULL) && (strcmp(s, "nc") != 0)){ + printf("Ethernet mode (duplex/speed): %d/%d Mbps\n", duplex, speed); + } + + ag7240_set_mac_duplex(mac, duplex); + + return 1; +} + +/* + * For every command we re-setup the ring and start with clean h/w rx state + */ +static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd) { + + int i; + ag7240_desc_t *fr; + ag7240_mac_t *mac = (ag7240_mac_t*)dev->priv; + + if (!ag7240_check_link(mac)){ + return 0; + } + + mac->next_rx = 0; + + for (i = 0; i < NO_OF_RX_FIFOS; i++) { + fr = mac->fifo_rx[i]; + fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]); + flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN); + ag7240_rx_give_to_dma(fr); + } + + ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0])); + ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, AG7240_RXE); + /* rx start */ + + if (!is_ar933x()){ + // TODO: do we need this? + udelay(1000 * 1000); + } + + return 1; + +} + +static int ag7240_alloc_fifo(int ndesc, ag7240_desc_t ** fifo) { + int i; + u32 size; + uchar *p = NULL; + + size = sizeof(ag7240_desc_t) * ndesc; + size += CFG_CACHELINE_SIZE - 1; + + if ((p = malloc(size)) == NULL) { + printf("Cant allocate fifos\n"); + return -1; + } + + p = (uchar *) (((u32) p + CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1)); + p = UNCACHED_SDRAM(p); + + for (i = 0; i < ndesc; i++) + fifo[i] = (ag7240_desc_t *) p + i; + + return 0; +} + +static int ag7240_setup_fifos(ag7240_mac_t *mac) { + int i; + + if (ag7240_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx)) + return 1; + + for (i = 0; i < NO_OF_TX_FIFOS; i++) { + mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ? virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]); + ag7240_tx_own(mac->fifo_tx[i]); + } + + if (ag7240_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx)) + return 1; + + for (i = 0; i < NO_OF_RX_FIFOS; i++) { + mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ? virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]); + } + + return (1); +} + +static void ag7240_halt(struct eth_device *dev) { + ag7240_mac_t *mac = (ag7240_mac_t *) dev->priv; + ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 0); + while (ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL)) + ; +} + +/* + * Get MAC address stored in flash + */ +static void ag7240_get_ethaddr(struct eth_device *dev) { + unsigned char *mac = dev->enetaddr; + unsigned char buffer[6]; + +#ifdef OFFSET_MAC_ADDRESS + // get MAC address from flash and check it + memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6); + + // check LSBit and second LCBit in MSByte of vendor part -> both of them should be 0 + if(CHECK_BIT((buffer[0] & 0xFF), 0) == 0 && CHECK_BIT((buffer[0] & 0xFF), 1) == 0){ + mac[0] = (buffer[0] & 0xFF); + mac[1] = (buffer[1] & 0xFF); + mac[2] = (buffer[2] & 0xFF); + mac[3] = (buffer[3] & 0xFF); + mac[4] = (buffer[4] & 0xFF); + mac[5] = (buffer[5] & 0xFF); + } else { + // 00-03-7F (Atheros Communications, Inc.) + mac[0] = 0x00; + mac[1] = 0x03; + mac[2] = 0x7f; + mac[3] = 0x09; + mac[4] = 0x0b; + mac[5] = 0xad; + + printf("## Error: MAC address stored in flash is invalid!\nUsing fixed address!\n"); + } +#else + // 00-03-7F (Atheros Communications, Inc.) + mac[0] = 0x00; + mac[1] = 0x03; + mac[2] = 0x7f; + mac[3] = 0x09; + mac[4] = 0x0b; + mac[5] = 0xad; + printf("## Error: Using fixed MAC address!\n"); +#endif +} + +int ag7240_enet_initialize(bd_t * bis) { + struct eth_device *dev[CFG_AG7240_NMACS]; + u32 mask, mac_h, mac_l; + int i; + + //printf("ag7240_enet_initialize...\n"); + + // TODO check this register! + ar7240_reg_wr(HORNET_BOOTSTRAP_STATUS, ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & ~HORNET_BOOTSTRAP_MDIO_SLAVE_MASK); + + if (is_ar933x()) { + u32 rd = 0x0; + + /* + * To get s26 out of reset, we have to... + * bit0~bit3: has to be deasserted + * bit4: has to be asserted + */ + rd = ar7240_reg_rd(AR7240_S26_CLK_CTRL_OFFSET) & ~(0x1f); + rd |= 0x10; + ar7240_reg_wr(AR7240_S26_CLK_CTRL_OFFSET, rd); + + if (ar7240_reg_rd(AR7240_RESET) != 0) { + ar7240_reg_wr(AR7240_RESET, 0); + } + } + + for (i = 0; i < CFG_AG7240_NMACS; i++) { + + if ((dev[i] = (struct eth_device *) malloc(sizeof(struct eth_device))) == NULL) { + puts("malloc failed\n"); + return 0; + } + + if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof(ag7240_mac_t))) == NULL) { + puts("malloc failed\n"); + return 0; + } + + memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i])); + memset(dev[i], 0, sizeof(dev[i])); + + sprintf(dev[i]->name, "eth%d", i); + ag7240_get_ethaddr(dev[i]); + + ag7240_macs[i]->mac_unit = i; + ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE; + ag7240_macs[i]->dev = dev[i]; + + dev[i]->iobase = 0; + dev[i]->init = ag7240_clean_rx; + dev[i]->halt = ag7240_halt; + dev[i]->send = ag7240_send; + dev[i]->recv = ag7240_recv; + dev[i]->priv = (void *) ag7240_macs[i]; + } + + for (i = 0; i < CFG_AG7240_NMACS; i++) { + + eth_register(dev[i]); + +#if(CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write); +#endif + + ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST); + + if (!i) { + mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY); + + if (is_ar7241() || is_ar7242() || is_wasp()){ + mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO; + } + + ar7240_reg_rmw_set(AR7240_RESET, mask); + + if (!is_ar933x()){ + udelay(1000 * 100); + } + + ar7240_reg_rmw_clear(AR7240_RESET, mask); + + if (!is_ar933x()){ + udelay(1000 * 100); + } + + if (!is_ar933x()){ + udelay(10 * 1000); + } + } + + ag7240_hw_start(ag7240_macs[i]); + + ag7240_setup_fifos(ag7240_macs[i]); + + if (!is_ar933x()){ + udelay(100 * 1000); + } + + //unsigned char *mac = dev[i]->enetaddr; + //printf("\nInterface %s MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff); + + mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]); + mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0); + + ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l); + ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h); + + /* if using header for register configuration, we have to */ + /* configure s26 register after frame transmission is enabled */ + + if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */ +#ifdef CONFIG_AR7242_S16_PHY + if (is_ar7242() || is_wasp()) { + athrs16_reg_init(); + } else +#endif + { +#ifdef CFG_ATHRS26_PHY + //printf("s26 reg init \n"); + athrs26_reg_init(); +#endif +#ifdef CFG_ATHRS27_PHY + //printf("s27 reg init \n"); + athrs27_reg_init(); +#endif +#ifdef CONFIG_F1E_PHY + //printf("F1Phy reg init \n"); + athr_reg_init(); +#endif + } + } else { +#ifdef CFG_ATHRS26_PHY + //printf("athrs26_reg_init_lan\n"); + athrs26_reg_init_lan(); +#endif +#ifdef CFG_ATHRS27_PHY + //printf("s27 reg init lan \n"); + athrs27_reg_init_lan(); +#endif + } + + //printf("ag7240_phy_setup\n"); + //udelay(100*1000); + + ag7240_phy_setup(ag7240_macs[i]->mac_unit); + //printf("Interface %s is up\n", dev[i]->name); + } + + return 1; +} + +/* Modified by lsz for reduceing CMD_MII, but ag7240 need this 090306 */ +uint16_t ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg) { + ag7240_mac_t *mac = ag7240_name2mac(devname); + uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val; + volatile int rddata; + uint16_t ii = 0xFFFF; + + /* + * Check for previous transactions are complete. Added to avoid + * race condition while running at higher frequencies. + */ + do { + udelay(5); + rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; + } while (rddata && --ii); + + if (ii == 0) + printf("ERROR:%s:%d transaction failed\n", __func__, __LINE__); + + ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0); + ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr); + ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ); + + do { + udelay(5); + rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; + } while (rddata && --ii); + + if (ii == 0) + printf("ERROR! Leave ag7240_miiphy_read without polling correct status!\n"); + + val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS); + ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0); + + return val; +} + +void ag7240_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data) { + ag7240_mac_t *mac = ag7240_name2mac(devname); + uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg; + volatile int rddata; + uint16_t ii = 0xFFFF; + + /* + * Check for previous transactions are complete. Added to avoid + * race condition while running at higher frequencies. + */ + do { + udelay(5); + rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; + } while (rddata && --ii); + + if (ii == 0) + printf("ERROR:%s:%d transaction failed\n", __func__, __LINE__); + + ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr); + ag7240_reg_wr(mac, AG7240_MII_MGMT_CTRL, data); + + do { + rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; + } while (rddata && --ii); + + if (ii == 0) + printf("ERROR! Leave ag7240_miiphy_write without polling correct status!\n"); +} diff --git a/u-boot/cpu/mips/ar7240/ag7240.h b/u-boot/cpu/mips/ar7240/ag7240.h new file mode 100755 index 0000000..d0c6c6f --- /dev/null +++ b/u-boot/cpu/mips/ar7240/ag7240.h @@ -0,0 +1,233 @@ +#ifndef _AG7240_H +#define _AG7240_H + +#include + +/* + * h/w descriptor + */ +typedef struct { + uint32_t pkt_start_addr; + + uint32_t is_empty : 1; + uint32_t res1 : 10; + uint32_t ftpp_override : 5; + uint32_t res2 : 4; + uint32_t pkt_size : 12; + + uint32_t next_desc ; +}ag7240_desc_t; + +#define NO_OF_TX_FIFOS 8 +#define NO_OF_RX_FIFOS 8 + +typedef struct { + ag7240_desc_t *fifo_tx[NO_OF_TX_FIFOS]; + ag7240_desc_t *fifo_rx[NO_OF_RX_FIFOS]; + struct eth_device *dev; + u32 next_tx; + u32 next_rx; + u32 link; + u32 duplex; + u32 speed; + u32 mac_unit; + u32 mac_base; + +}ag7240_mac_t; + +#define ag7240_reg_wr(_mac, _x, _y) ar7240_reg_wr(((_x) + _mac->mac_base), (_y)) +#define ag7240_reg_rd(_mac, _x) ar7240_reg_rd(((_x) + _mac->mac_base)) + +#define ag7240_reg_rmw_set(_mac, _x, _y) ar7240_reg_rmw_set(((_x) + _mac->mac_base ), (_y)) +#define ag7240_reg_rmw_clear(_mac, _x, _y) ar7240_reg_rmw_clear(((_x) + _mac->mac_base), (_y)) + +#define _1000BASET 1000 +#define _100BASET 100 +#define _10BASET 10 + +/* + * spd is _1000BASET, _100BASET etc. defined in include/miiphy.h + */ +#define mii_reg(_mac) (AR7240_MII0_CTRL + ((_mac)->mac_unit * 4)) +#define mii_if(_mac) (((_mac)->mac_unit == 0) ? mii0_if : mii1_if) + +#define ag7240_set_mii_ctrl_speed(_mac, _spd) do { \ + ar7240_reg_rmw_clear(mii_reg(_mac), (3 << 4)); \ + ar7240_reg_rmw_set(mii_reg(_mac), ((_spd) << 4)); \ +}while(0); + +#if defined (CFG_MII0_GMII) +#define ag7240_get_mii_if() 0 +#elif defined (CFG_MII0_MII) +#define ag7240_get_mii_if() 0 +#elif defined (CFG_MII0_RGMII) +#define ag7240_get_mii_if() 0 +#elif defined (CFG_MII0_RMII) +#define ag7240_get_mii_if() 0 +#endif + +#define MAX_WAIT 1000 + +/* + * Config/Mac Register definitions + */ +#define AG7240_MAC_CFG1 0x00 +#define AG7240_MAC_CFG2 0x04 +#define AG7240_MAC_IFCTL 0x38 + +/* + * fifo control registers + */ +#define AG7240_MAC_FIFO_CFG_0 0x48 +#define AG7240_MAC_FIFO_CFG_1 0x4c +#define AG7240_MAC_FIFO_CFG_2 0x50 +#define AG7240_MAC_FIFO_CFG_3 0x54 +#define AG7240_MAC_FIFO_CFG_4 0x58 + +#define AG7240_MAC_FIFO_CFG_5 0x5c +#define AG7240_BYTE_PER_CLK_EN (1 << 19) + +#define AG7240_MAC_FIFO_RAM_0 0x60 +#define AG7240_MAC_FIFO_RAM_1 0x64 +#define AG7240_MAC_FIFO_RAM_2 0x68 +#define AG7240_MAC_FIFO_RAM_3 0x6c +#define AG7240_MAC_FIFO_RAM_4 0x70 +#define AG7240_MAC_FIFO_RAM_5 0x74 +#define AG7240_MAC_FIFO_RAM_6 0x78 +#define AG7240_MAC_FIFO_RAM_7 0x7c + +/* + * fields + */ +#define AG7240_MAC_CFG1_SOFT_RST (1 << 31) +#define AG7240_MAC_CFG1_RX_RST (1 << 19) +#define AG7240_MAC_CFG1_TX_RST (1 << 18) +#define AG7240_MAC_CFG1_LOOPBACK (1 << 8) +#define AG7240_MAC_CFG1_RX_EN (1 << 2) +#define AG7240_MAC_CFG1_TX_EN (1 << 0) + +#define AG7240_MAC_CFG2_FDX (1 << 0) +#define AG7240_MAC_CFG2_PAD_CRC_EN (1 << 2) +#define AG7240_MAC_CFG2_LEN_CHECK (1 << 4) +#define AG7240_MAC_CFG2_HUGE_FRAME_EN (1 << 5) +#define AG7240_MAC_CFG2_IF_1000 (1 << 9) +#define AG7240_MAC_CFG2_IF_10_100 (1 << 8) + +#define AG7240_MAC_IFCTL_SPEED (1 << 16) + +/* + * DMA (tx/rx) register defines + */ +#define AG7240_DMA_TX_CTRL 0x180 +#define AG7240_DMA_TX_DESC 0x184 +#define AG7240_DMA_TX_STATUS 0x188 +#define AG7240_DMA_RX_CTRL 0x18c +#define AG7240_DMA_RX_DESC 0x190 +#define AG7240_DMA_RX_STATUS 0x194 +#define AG7240_DMA_INTR_MASK 0x198 +#define AG7240_DMA_INTR 0x19c + +/* + * tx/rx ctrl and status bits + */ +#define AG7240_TXE (1 << 0) +#define AG7240_TX_STATUS_PKTCNT_SHIFT 16 +#define AG7240_TX_STATUS_PKT_SENT 0x1 +#define AG7240_TX_STATUS_URN 0x2 +#define AG7240_TX_STATUS_BUS_ERROR 0x8 + +#define AG7240_RXE (1 << 0) + +#define AG7240_RX_STATUS_PKTCNT_MASK 0xff0000 +#define AG7240_RX_STATUS_PKT_RCVD (1 << 0) +#define AG7240_RX_STATUS_OVF (1 << 2) +#define AG7240_RX_STATUS_BUS_ERROR (1 << 3) + +/* + * Int and int mask + */ +#define AG7240_INTR_TX (1 << 0) +#define AG7240_INTR_TX_URN (1 << 1) +#define AG7240_INTR_TX_BUS_ERROR (1 << 3) +#define AG7240_INTR_RX (1 << 4) +#define AG7240_INTR_RX_OVF (1 << 6) +#define AG7240_INTR_RX_BUS_ERROR (1 << 7) + +/* + * MII registers + */ +#define AG7240_MAC_MII_MGMT_CFG 0x20 +#define AG7240_MGMT_CFG_CLK_DIV_20 0x07 + +#define AG7240_MII_MGMT_CMD 0x24 +#define AG7240_MGMT_CMD_READ 0x1 + +#define AG7240_MII_MGMT_ADDRESS 0x28 +#define AG7240_ADDR_SHIFT 8 + +#define AG7240_MII_MGMT_CTRL 0x2c +#define AG7240_MII_MGMT_STATUS 0x30 + +#define AG7240_MII_MGMT_IND 0x34 +#define AG7240_MGMT_IND_BUSY (1 << 0) +#define AG7240_MGMT_IND_INVALID (1 << 2) + +#define AG7240_GE_MAC_ADDR1 0x40 +#define AG7240_GE_MAC_ADDR2 0x44 + +/* + * Ethernet config registers + */ +#define AG7240_ETH_CFG 0x18070000 +#define AG7240_ETH_CFG_RGMII_GE0 (1<<0) +#define AG7240_ETH_CFG_MII_GE0 (1<<1) +#define AG7240_ETH_CFG_GMII_GE0 (1<<2) +#define AG7240_ETH_CFG_MII_GE0_MASTER (1<<3) +#define AG7240_ETH_CFG_MII_GE0_SLAVE (1<<4) +#define AG7240_ETH_CFG_GE0_ERR_EN (1<<5) +#define AG7240_ETH_CFG_SW_ONLY_MODE (1<<6) +#define AG7240_ETH_CFG_SW_PHY_SWAP (1<<7) +#define AG7240_ETH_CFG_SW_PHY_ADDR_SWAP (1<<8) +#define AG7240_ETH_SWITCH_CLK_SPARE 0x18050024 + + +/* + * * ownership of descriptors between DMA and cpu + * */ +#define ag7240_rx_owned_by_dma(_ds) ((_ds)->is_empty == 1) +#define ag7240_rx_give_to_dma(_ds) ((_ds)->is_empty = 1) +#define ag7240_tx_owned_by_dma(_ds) ((_ds)->is_empty == 0) +#define ag7240_tx_give_to_dma(_ds) ((_ds)->is_empty = 0) +#define ag7240_tx_own(_ds) ((_ds)->is_empty = 1) + +/* + * link settings + */ +#define ag7240_set_mac_duplex(_mac, _fdx) do { \ + if ((_fdx)) \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_FDX) \ + else \ + ag7240_reg_rmw_clear(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_FDX) \ +}while(0) + +#define ag7240_set_mac_if(_mac, _isXGMII) do { \ + ag7240_reg_rmw_clear(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_IF_1000| \ + AG7240_MAC_CFG2_IF_10_100); \ + if ((_isXGMII)) { \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_IF_1000) \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_FIFO_CFG_5, AG7240_BYTE_PER_CLK_EN);\ + } \ + else { \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_IF_10_100)\ + ag7240_reg_rmw_clear(_mac, AG7240_MAC_FIFO_CFG_5, AG7240_BYTE_PER_CLK_EN);\ + } \ +}while(0) + +#define ag7240_set_mac_speed(_mac, _is100) do { \ + if ((_is100)) \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_IFCTL, AG7240_MAC_IFCTL_SPEED) \ + else \ + ag7240_reg_rmw_clear(_mac, AG7240_MAC_IFCTL, AG7240_MAC_IFCTL_SPEED)\ +}while(0) + +#endif diff --git a/u-boot/cpu/mips/ar7240/ag7240_phy.h b/u-boot/cpu/mips/ar7240/ag7240_phy.h new file mode 100755 index 0000000..985c363 --- /dev/null +++ b/u-boot/cpu/mips/ar7240/ag7240_phy.h @@ -0,0 +1,70 @@ +#ifndef _AG7240_PHY_H +#define _AG7240_PHY_H + +extern int athrs16_phy_is_up(int unit); +extern int athrs16_phy_is_fdx(int unit); +extern int athrs16_phy_speed(int unit); +extern int athrs16_phy_setup(int unit); + +extern int athrs26_phy_is_up(int unit); +extern int athrs26_phy_speed(int unit); +extern int athrs26_phy_setup(int unit); +extern int athrs26_phy_is_fdx(int unit); + +static inline void ag7240_phy_setup(int unit) { +#ifdef CONFIG_AR7242_S16_PHY + if ((is_ar7242() || is_wasp()) && (unit==0)) { + athrs16_phy_setup(unit); + } else +#endif + { + athrs26_phy_setup(unit); +#ifdef CONFIG_F1E_PHY + athr_phy_setup(unit); +#endif + } +} + +static inline void ag7240_phy_link(int unit, int *link) { +#ifdef CONFIG_AR7242_S16_PHY + if ((is_ar7242() || is_wasp()) && (unit==0)) { + *link = athrs16_phy_is_up(unit); + } else +#endif + { + *link = athrs26_phy_is_up(unit); +#ifdef CONFIG_F1E_PHY + *link = athr_phy_is_up(unit); +#endif + } +} + +static inline void ag7240_phy_duplex(int unit, int *duplex) { +#ifdef CONFIG_AR7242_S16_PHY + if ((is_ar7242() || is_wasp()) && (unit==0)) { + *duplex = athrs16_phy_is_fdx(unit); + } else +#endif + { + *duplex = athrs26_phy_is_fdx(unit); +#ifdef CONFIG_F1E_PHY + *duplex = athr_phy_is_fdx(unit); +#endif + } +} + +static inline void ag7240_phy_speed(int unit, int *speed) { +#ifdef CONFIG_AR7242_S16_PHY + if ((is_ar7242() || is_wasp()) && (unit==0)) { + *speed = athrs16_phy_speed(unit); + } else +#endif + { + *speed = athrs26_phy_speed(unit); +#ifdef CONFIG_F1E_PHY + *speed = athr_phy_speed(unit); +#endif + } +} + +#endif /*_AG7240_PHY_H*/ diff --git a/u-boot/cpu/mips/ar7240/ag934x.c b/u-boot/cpu/mips/ar7240/ag934x.c new file mode 100755 index 0000000..14b8c1c --- /dev/null +++ b/u-boot/cpu/mips/ar7240/ag934x.c @@ -0,0 +1,762 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "ar7240_soc.h" +#include "ag934x.h" +#include "ag934x_phy.h" + +#define _1000BASET 1000 +#define _100BASET 100 +#define _10BASET 10 + +#define ag7240_unit2mac(_unit) ag7240_macs[(_unit)] +#define ag7240_name2mac(name) strcmp(name,"eth0") ? ag7240_unit2mac(1) : ag7240_unit2mac(0) +#define CHECK_BIT(var,pos) ((var) & (1<<(pos))) + +uint16_t ag7240_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg); +void ag7240_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data); +ag7240_mac_t *ag7240_macs[CFG_AG7240_NMACS]; +extern void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq); + +#ifdef CFG_ATHRS26_PHY +extern int athrs26_phy_setup(int unit); +extern int athrs26_phy_is_up(int unit); +extern int athrs26_phy_is_fdx(int unit); +extern int athrs26_phy_speed(int unit); +extern void athrs26_reg_init(void); +extern void athrs26_reg_init_lan(void); +extern int athrs26_mdc_check(void); +#endif + +#ifdef CONFIG_ATHRS17_PHY +extern void athrs17_reg_init(void); +#endif + +#ifdef CFG_ATHRS27_PHY +extern int athrs27_phy_setup(int unit); +extern int athrs27_phy_is_up(int unit); +extern int athrs27_phy_is_fdx(int unit); +extern int athrs27_phy_speed(int unit); +extern void athrs27_reg_init(void); +extern void athrs27_reg_init_lan(void); +extern int athrs27_mdc_check(void); +#endif + +#if defined(CONFIG_F1E_PHY) || defined(CONFIG_F2E_PHY) +extern int athr_phy_setup(int unit); +extern int athr_phy_is_up(int unit); +extern int athr_phy_is_fdx(int unit); +extern int athr_phy_speed(int unit); +extern void athr_reg_init(void); +#endif + +#ifdef CONFIG_VIR_PHY +extern int athr_vir_phy_setup(int unit); +extern int athr_vir_phy_is_up(int unit); +extern int athr_vir_phy_is_fdx(int unit); +extern int athr_vir_phy_speed(int unit); +extern void athr_vir_reg_init(void); +#endif + + +static int ag7240_send(struct eth_device *dev, volatile void *packet, int length){ + int i; + + ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv; + + ag7240_desc_t *f = mac->fifo_tx[mac->next_tx]; + + f->pkt_size = length; + f->res1 = 0; + f->pkt_start_addr = virt_to_phys(packet); + + ag7240_tx_give_to_dma(f); + flush_cache((u32)packet, length); + ag7240_reg_wr(mac, AG7240_DMA_TX_DESC, virt_to_phys(f)); + ag7240_reg_wr(mac, AG7240_DMA_TX_CTRL, AG7240_TXE); + + for(i = 0; i < MAX_WAIT; i++){ + udelay(10); + if(!ag7240_tx_owned_by_dma(f)){ + break; + } + } + + f->pkt_start_addr = 0; + f->pkt_size = 0; + + if(++mac->next_tx >= NO_OF_TX_FIFOS){ + mac->next_tx = 0; + } + + return(0); +} + +static int ag7240_recv(struct eth_device *dev){ + int length; + ag7240_desc_t *f; + ag7240_mac_t *mac; + + mac = (ag7240_mac_t *)dev->priv; + + for(;;){ + f = mac->fifo_rx[mac->next_rx]; + if(ag7240_rx_owned_by_dma(f)){ + break; + } + + length = f->pkt_size; + + NetReceive(NetRxPackets[mac->next_rx] , length - 4); + flush_cache((u32)NetRxPackets[mac->next_rx] , PKTSIZE_ALIGN); + + ag7240_rx_give_to_dma(f); + + if(++mac->next_rx >= NO_OF_RX_FIFOS) + mac->next_rx = 0; + } + + if(!(ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL))){ + ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(f)); + ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 1); + } + + return(0); +} + +/* + * Called in ag7240_hw_start() function + */ +void ag7240_mii_setup(ag7240_mac_t *mac){ + u32 mgmt_cfg_val; + u32 cpu_freq,ddr_freq,ahb_freq; + u32 check_cnt; + + if((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0){ +#ifndef CFG_DUAL_PHY_SUPPORT + ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x271); +#endif + } else { + ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x570); + } + +#if defined(CONFIG_AR7242_S16_PHY) || defined(CONFIG_ATHRS17_PHY) + if(is_wasp() && mac->mac_unit == 0){ +#ifdef CONFIG_AR7242_S16_PHY + //printf("WASP ----> S16 PHY *\n"); +#else + //printf("WASP ----> S17 PHY *\n"); +#endif + mgmt_cfg_val = 4; + + if(mac->mac_unit == 0){ + ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0); + } + + udelay(1000); + + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + + return; + } +#endif + +#ifdef CFG_ATHRS27_PHY + if(is_wasp()){ + //printf("WASP ----> S27 PHY \n"); + mgmt_cfg_val = 2; + ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + return; + } +#endif + +#ifdef CONFIG_F2E_PHY + if(is_wasp()){ + //printf("WASP ----> F2 PHY *\n"); + mgmt_cfg_val = 6; + ar7240_reg_wr(AG7240_ETH_CFG, (AG7240_ETH_CFG_RMII_MASTER_MODE | AG7240_ETH_CFG_RMII_GE0 | AG7240_ETH_CFG_RMII_HISPD_GE0)); + + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + + return; + } +#endif + +#if defined(CONFIG_F1E_PHY) || defined(CONFIG_VIR_PHY) + if(is_wasp()){ +#ifdef CONFIG_VIR_PHY + //printf("WASP ----> VIR PHY *\n"); +#else + //printf("WASP ----> F1 PHY *\n"); +#endif + if(mac->mac_unit == 0){ + ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0); + } + + mgmt_cfg_val = 6; + + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + + return; + } +#endif + + if((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2){ + mgmt_cfg_val = 0x2; + + if(mac->mac_unit == 0){ + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + } + } else { + ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq); + + // TODO: ?? + switch(ahb_freq/1000000){ + case 150: + mgmt_cfg_val = 0x7; + break; + case 175: + mgmt_cfg_val = 0x5; + break; + case 200: + mgmt_cfg_val = 0x4; + break; + case 210: + mgmt_cfg_val = 0x9; + break; + case 220: + mgmt_cfg_val = 0x9; + break; + default: + mgmt_cfg_val = 0x7; + } + + if((is_ar7241() || is_ar7242())){ + /* External MII mode */ + if(mac->mac_unit == 0 && is_ar7242()){ + mgmt_cfg_val = 0x6; + ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + } + + /* Virian */ + mgmt_cfg_val = 0x4; + ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); + //printf("Virian MDC CFG Value ==> %x\n",mgmt_cfg_val); + } else if(is_ar933x()){ + //GE0 receives Rx/Tx clock, and use S26 phy + ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE); + mgmt_cfg_val = 0xF; + + if(mac->mac_unit == 1){ + check_cnt = 0; + while(check_cnt++ < 10){ + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); +#ifdef CFG_ATHRS26_PHY + if(athrs26_mdc_check() == 0){ + break; + } +#endif + } + + //if(check_cnt == 11) + //printf("%s: MDC check failed\n", __func__); + } + } else { /* Python 1.0 & 1.1 */ + if(mac->mac_unit == 0){ + check_cnt = 0; + + while(check_cnt++ < 10){ + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val); +#ifdef CFG_ATHRS26_PHY + if(athrs26_mdc_check() == 0){ + break; + } +#endif + } + + //if(check_cnt == 11) + //printf("%s: MDC check failed\n", __func__); + } + } + } +} + +static void ag7240_hw_start(ag7240_mac_t *mac){ + + if(mac->mac_unit){ + ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN)); + ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_1000)); + } else { + ag7240_reg_wr(mac, AG7240_MAC_CFG1, (AG7240_MAC_CFG1_RX_EN | AG7240_MAC_CFG1_TX_EN)); + ag7240_reg_rmw_set(mac, AG7240_MAC_CFG2, (AG7240_MAC_CFG2_PAD_CRC_EN | AG7240_MAC_CFG2_LEN_CHECK | AG7240_MAC_CFG2_IF_10_100)); + } + + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_0, 0x1f00); + ag7240_mii_setup(mac); + + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_1, 0x10ffff); + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_2, 0xAAA0555); + + ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_4, 0x3ffff); + + // TODO: check this register + /* + * When enable the web failsafe mode in uboot,you can't drop the broadcast + * frames now,the PC first will tx a ARP request packet, it's a broadcast packet. + */ + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x66b82); + /* + * Setting Drop CRC Errors, Pause Frames,Length Error frames + * and Multi/Broad cast frames. + */ + //ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_5, 0x7eccf); + + ag7240_reg_wr(mac, AG7240_MAC_FIFO_CFG_3, 0x1f00140); + //printf(": cfg1 %#x cfg2 %#x\n", ag7240_reg_rd(mac, AG7240_MAC_CFG1), ag7240_reg_rd(mac, AG7240_MAC_CFG2)); +} + +static int ag7240_check_link(ag7240_mac_t *mac){ + int link = 0, duplex = 0, speed = 0; + char *s; + + s = getenv("stdin"); + + ag7240_phy_link(mac->mac_unit, &link); + ag7240_phy_duplex(mac->mac_unit, &duplex); + ag7240_phy_speed(mac->mac_unit, &speed); + + mac->link = link; + + if(!mac->link){ + if((s != NULL) && (strcmp(s, "nc") != 0)){ + printf("Link down: %s\n", mac->dev->name); + } + return(0); + } + + switch(speed){ + case _1000BASET: + ag7240_set_mac_if(mac, 1); + ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19)); + + if(is_ar7242() && (mac->mac_unit == 0)){ + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1c000000); + } +#ifdef CONFIG_F1E_PHY + if(is_wasp() && (mac->mac_unit == 0)){ + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0e000000); + } +#elif CONFIG_VIR_PHY + if(is_wasp() && (mac->mac_unit == 0)){ + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x82000000); + ar7240_reg_wr(AG7240_ETH_CFG, 0x000c0001); + } +#else + if(is_wasp() && (mac->mac_unit == 0) && !is_f2e()){ + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x06000000); + } +#endif + if(is_wasp() && mac->mac_unit == 0 && is_f1e() ){ + ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RXD_DELAY); + ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RDV_DELAY); + } + break; + + case _100BASET: + ag7240_set_mac_if(mac, 0); + ag7240_set_mac_speed(mac, 1); + ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19)); + + if((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e()){ + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0101); + } + + if(is_wasp() && mac->mac_unit == 0 && is_f1e()){ + ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RXD_DELAY); + ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RDV_DELAY); + } + break; + + case _10BASET: + ag7240_set_mac_if(mac, 0); + ag7240_set_mac_speed(mac, 0); + ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19)); + + if((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e()){ + ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1616); + } + + if(is_wasp() && mac->mac_unit == 0 && is_f1e()){ + ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY); + ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY); + } + + if(is_f2e()){ + ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RMII_HISPD_GE0); + } + break; + + default: + if((s != NULL) && (strcmp(s, "nc") != 0)){ + printf("## Error: invalid speed detected\n"); + } + return(0); + } + + if(mac->link && (duplex == mac->duplex) && (speed == mac->speed)){ + return(1); + } + + mac->duplex = duplex; + mac->speed = speed; + + if((s != NULL) && (strcmp(s, "nc") != 0)){ + printf("Ethernet mode (duplex/speed): %d/%d Mbps\n", duplex, speed); + } + + ag7240_set_mac_duplex(mac, duplex); + + return(1); +} + +/* + * For every command we re-setup the ring and start with clean h/w rx state + */ +static int ag7240_clean_rx(struct eth_device *dev, bd_t * bd){ + int i; + ag7240_desc_t *fr; + ag7240_mac_t *mac = (ag7240_mac_t*)dev->priv; + + if(!ag7240_check_link(mac)){ + return(0); + } + + mac->next_rx = 0; + + for(i = 0; i < NO_OF_RX_FIFOS; i++){ + fr = mac->fifo_rx[i]; + fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]); + flush_cache((u32)NetRxPackets[i], PKTSIZE_ALIGN); + ag7240_rx_give_to_dma(fr); + } + + ag7240_reg_wr(mac, AG7240_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0])); + ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, AG7240_RXE); /* rx start */ + + udelay(1000 * 1000); + return(1); +} + +static int ag7240_alloc_fifo(int ndesc, ag7240_desc_t ** fifo){ + int i; + u32 size; + uchar *p = NULL; + + size = sizeof(ag7240_desc_t) * ndesc; + size += CFG_CACHELINE_SIZE - 1; + + if((p = malloc(size)) == NULL){ + printf("## Error: cant allocate fifos\n"); + return(-1); + } + + p = (uchar *)(((u32)p + CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1)); + p = UNCACHED_SDRAM(p); + + for(i = 0; i < ndesc; i++){ + fifo[i] = (ag7240_desc_t *)p + i; + } + + return(0); +} + +static int ag7240_setup_fifos(ag7240_mac_t *mac){ + int i; + + if(ag7240_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx)){ + return(1); + } + + for(i = 0; i < NO_OF_TX_FIFOS; i++){ + mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ? virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]); + ag7240_tx_own(mac->fifo_tx[i]); + } + + if(ag7240_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx)){ + return(1); + } + + for(i = 0; i < NO_OF_RX_FIFOS; i++){ + mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ? virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]); + } + + return(1); +} + +static void ag7240_halt(struct eth_device *dev){ + ag7240_mac_t *mac = (ag7240_mac_t *)dev->priv; + ag7240_reg_wr(mac, AG7240_DMA_RX_CTRL, 0); + while(ag7240_reg_rd(mac, AG7240_DMA_RX_CTRL)); +} + +/* + * Get MAC address stored in flash + */ +static void ag7240_get_ethaddr(struct eth_device *dev){ + unsigned char *mac = dev->enetaddr; + unsigned char buffer[6]; + +#ifdef OFFSET_MAC_ADDRESS + // get MAC address from flash and check it + memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6); + + // check LSBit and second LCBit in MSByte of vendor part -> both of them should be 0 + if(CHECK_BIT((buffer[0] & 0xFF), 0) == 0 && CHECK_BIT((buffer[0] & 0xFF), 1) == 0){ + mac[0] = (buffer[0] & 0xFF); + mac[1] = (buffer[1] & 0xFF); + mac[2] = (buffer[2] & 0xFF); + mac[3] = (buffer[3] & 0xFF); + mac[4] = (buffer[4] & 0xFF); + mac[5] = (buffer[5] & 0xFF); + } else { + // 00-03-7F (Atheros Communications, Inc.) + mac[0] = 0x00; + mac[1] = 0x03; + mac[2] = 0x7f; + mac[3] = 0x09; + mac[4] = 0x0b; + mac[5] = 0xad; + + printf("## Error: MAC address stored in flash is invalid!\nUsing fixed address!\n"); + } +#else + // 00-03-7F (Atheros Communications, Inc.) + mac[0] = 0x00; + mac[1] = 0x03; + mac[2] = 0x7f; + mac[3] = 0x09; + mac[4] = 0x0b; + mac[5] = 0xad; + printf("## Error: Using fixed MAC address!\n"); +#endif +} + +int ag7240_enet_initialize(bd_t * bis){ + struct eth_device *dev[CFG_AG7240_NMACS]; + u32 mask, mac_h, mac_l; + int i; + + //printf("ag934x_enet_initialize...\n"); + + /* + if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0)){ + ar7240_reg_wr(AR7240_RESET,0); + } + + if(is_ar933x()) //Turn on LED + ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8)); + */ + + for(i = 0;i < CFG_AG7240_NMACS;i++){ + if((dev[i] = (struct eth_device *)malloc(sizeof(struct eth_device))) == NULL){ + //puts("malloc failed\n"); + return(0); + } + + if((ag7240_macs[i] = (ag7240_mac_t *)malloc(sizeof(ag7240_mac_t))) == NULL){ + //puts("malloc failed\n"); + return(0); + } + + memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i])); + memset(dev[i], 0, sizeof(dev[i])); + + sprintf(dev[i]->name, "eth%d", i); + ag7240_get_ethaddr(dev[i]); + + ag7240_macs[i]->mac_unit = i; + ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ; + ag7240_macs[i]->dev = dev[i]; + + dev[i]->iobase = 0; + dev[i]->init = ag7240_clean_rx; + dev[i]->halt = ag7240_halt; + dev[i]->send = ag7240_send; + dev[i]->recv = ag7240_recv; + dev[i]->priv = (void *)ag7240_macs[i]; + } + + for(i = 0;i < CFG_AG7240_NMACS;i++){ + eth_register(dev[i]); + +#if(CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write); +#endif + + ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST); + + if(!i){ + mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY); + + if(is_ar7241() || is_ar7242() || is_wasp()){ + mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO; + } + + //printf(" wasp reset mask:%x \n",mask); + + ar7240_reg_rmw_set(AR7240_RESET, mask); + udelay(1000 * 100); + + ar7240_reg_rmw_clear(AR7240_RESET, mask); + udelay(1000 * 100); + + udelay(10 * 1000); + } + + ag7240_hw_start(ag7240_macs[i]); + ag7240_setup_fifos(ag7240_macs[i]); + + udelay(100 * 1000); + + //unsigned char *mac = dev[i]->enetaddr; + //printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff); + + mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]); + mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0); + + ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l); + ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h); + + /* if using header for register configuration, we have to */ + /* configure s26 register after frame transmission is enabled */ + if(ag7240_macs[i]->mac_unit == 0){ /* WAN Phy */ +#ifdef CONFIG_AR7242_S16_PHY + if(is_ar7242() || is_wasp()){ + athrs16_reg_init(); + } else +#endif + { +#ifdef CONFIG_ATHRS17_PHY + athrs17_reg_init(); +#endif + +#ifdef CFG_ATHRS26_PHY + athrs26_reg_init(); +#endif + +#ifdef CFG_ATHRS27_PHY + //printf("s27 reg init \n"); + athrs27_reg_init(); +#endif + +#ifdef CONFIG_F1E_PHY + //printf("F1Phy reg init \n"); + athr_reg_init(); +#endif + +#ifdef CONFIG_VIR_PHY + //printf("VIRPhy reg init \n"); + athr_vir_reg_init(); +#endif + +#ifdef CONFIG_F2E_PHY + //printf("F2Phy reg init \n"); + athr_reg_init(); +#endif + + } + } else { +#ifdef CFG_ATHRS26_PHY + athrs26_reg_init_lan(); +#endif + +#ifdef CFG_ATHRS27_PHY + //printf("s27 reg init lan \n"); + athrs27_reg_init_lan(); +#endif + } + + ag7240_phy_setup(ag7240_macs[i]->mac_unit); + //printf("%s up\n",dev[i]->name); + } + + return(1); +} + +uint16_t ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg){ + ag7240_mac_t *mac = ag7240_name2mac(devname); + uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val; + volatile int rddata; + uint16_t ii = 0xFFFF; + + /* + * Check for previous transactions are complete. Added to avoid + * race condition while running at higher frequencies. + */ + do { + udelay(5); + rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; + } while(rddata && --ii); + + //if(ii == 0) + //printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__); + + ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0); + ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr); + ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ); + + do { + udelay(5); + rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; + } while(rddata && --ii); + + //if(ii==0) + //printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n"); + + val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS); + ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0); + + return(val); +} + +void ag7240_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data){ + ag7240_mac_t *mac = ag7240_name2mac(devname); + uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg; + volatile int rddata; + uint16_t ii = 0xFFFF; + + /* + * Check for previous transactions are complete. Added to avoid + * race condition while running at higher frequencies. + */ + do { + udelay(5); + rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; + } while(rddata && --ii); + + //if(ii == 0) + //printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__); + + ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr); + ag7240_reg_wr(mac, AG7240_MII_MGMT_CTRL, data); + + do { + rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; + } while(rddata && --ii); + +} diff --git a/u-boot/cpu/mips/ar7240/ag934x.h b/u-boot/cpu/mips/ar7240/ag934x.h new file mode 100755 index 0000000..02ca337 --- /dev/null +++ b/u-boot/cpu/mips/ar7240/ag934x.h @@ -0,0 +1,242 @@ +#ifndef _AG7240_H +#define _AG7240_H + +#include + +/* + * h/w descriptor + */ +typedef struct { + uint32_t pkt_start_addr; + + uint32_t is_empty : 1; + uint32_t res1 : 10; + uint32_t ftpp_override : 5; + uint32_t res2 : 4; + uint32_t pkt_size : 12; + + uint32_t next_desc ; +}ag7240_desc_t; + +#define NO_OF_TX_FIFOS 8 +#define NO_OF_RX_FIFOS 8 + +typedef struct { + ag7240_desc_t *fifo_tx[NO_OF_TX_FIFOS]; + ag7240_desc_t *fifo_rx[NO_OF_RX_FIFOS]; + struct eth_device *dev; + u32 next_tx; + u32 next_rx; + u32 link; + u32 duplex; + u32 speed; + u32 mac_unit; + u32 mac_base; + +}ag7240_mac_t; + +#define ag7240_reg_wr(_mac, _x, _y) ar7240_reg_wr(((_x) + _mac->mac_base), (_y)) +#define ag7240_reg_rd(_mac, _x) ar7240_reg_rd(((_x) + _mac->mac_base)) + +#define ag7240_reg_rmw_set(_mac, _x, _y) \ + ar7240_reg_rmw_set(((_x) + _mac->mac_base ), (_y)) +#define ag7240_reg_rmw_clear(_mac, _x, _y) \ + ar7240_reg_rmw_clear(((_x) + _mac->mac_base), (_y)) + +#ifdef COMPRESSED_UBOOT +#define _1000BASET 1000 +#define _100BASET 100 +#define _10BASET 10 +#endif /* #ifdef COMPRESSED_UBOOT */ + +/* + * spd is _1000BASET, _100BASET etc. defined in include/miiphy.h + */ +#define mii_reg(_mac) (AR7240_MII0_CTRL + ((_mac)->mac_unit * 4)) +#define mii_if(_mac) (((_mac)->mac_unit == 0) ? mii0_if : mii1_if) + +#define ag7240_set_mii_ctrl_speed(_mac, _spd) do { \ + ar7240_reg_rmw_clear(mii_reg(_mac), (3 << 4)); \ + ar7240_reg_rmw_set(mii_reg(_mac), ((_spd) << 4)); \ +}while(0); + +#if defined (CFG_MII0_GMII) +#define ag7240_get_mii_if() 0 +#elif defined (CFG_MII0_MII) +#define ag7240_get_mii_if() 0 +#elif defined (CFG_MII0_RGMII) +#define ag7240_get_mii_if() 0 +#elif defined (CFG_MII0_RMII) +#define ag7240_get_mii_if() 0 +#endif + +#define MAX_WAIT 1000 + +/* + * Config/Mac Register definitions + */ +#define AG7240_MAC_CFG1 0x00 +#define AG7240_MAC_CFG2 0x04 +#define AG7240_MAC_IFCTL 0x38 + +/* + * fifo control registers + */ +#define AG7240_MAC_FIFO_CFG_0 0x48 +#define AG7240_MAC_FIFO_CFG_1 0x4c +#define AG7240_MAC_FIFO_CFG_2 0x50 +#define AG7240_MAC_FIFO_CFG_3 0x54 +#define AG7240_MAC_FIFO_CFG_4 0x58 + +#define AG7240_MAC_FIFO_CFG_5 0x5c +#define AG7240_BYTE_PER_CLK_EN (1 << 19) + +#define AG7240_MAC_FIFO_RAM_0 0x60 +#define AG7240_MAC_FIFO_RAM_1 0x64 +#define AG7240_MAC_FIFO_RAM_2 0x68 +#define AG7240_MAC_FIFO_RAM_3 0x6c +#define AG7240_MAC_FIFO_RAM_4 0x70 +#define AG7240_MAC_FIFO_RAM_5 0x74 +#define AG7240_MAC_FIFO_RAM_6 0x78 +#define AG7240_MAC_FIFO_RAM_7 0x7c + +/* + * fields + */ +#define AG7240_MAC_CFG1_SOFT_RST (1 << 31) +#define AG7240_MAC_CFG1_RX_RST (1 << 19) +#define AG7240_MAC_CFG1_TX_RST (1 << 18) +#define AG7240_MAC_CFG1_LOOPBACK (1 << 8) +#define AG7240_MAC_CFG1_RX_EN (1 << 2) +#define AG7240_MAC_CFG1_TX_EN (1 << 0) + +#define AG7240_MAC_CFG2_FDX (1 << 0) +#define AG7240_MAC_CFG2_PAD_CRC_EN (1 << 2) +#define AG7240_MAC_CFG2_LEN_CHECK (1 << 4) +#define AG7240_MAC_CFG2_HUGE_FRAME_EN (1 << 5) +#define AG7240_MAC_CFG2_IF_1000 (1 << 9) +#define AG7240_MAC_CFG2_IF_10_100 (1 << 8) + +#define AG7240_MAC_IFCTL_SPEED (1 << 16) + +/* + * DMA (tx/rx) register defines + */ +#define AG7240_DMA_TX_CTRL 0x180 +#define AG7240_DMA_TX_DESC 0x184 +#define AG7240_DMA_TX_STATUS 0x188 +#define AG7240_DMA_RX_CTRL 0x18c +#define AG7240_DMA_RX_DESC 0x190 +#define AG7240_DMA_RX_STATUS 0x194 +#define AG7240_DMA_INTR_MASK 0x198 +#define AG7240_DMA_INTR 0x19c + +/* + * tx/rx ctrl and status bits + */ +#define AG7240_TXE (1 << 0) +#define AG7240_TX_STATUS_PKTCNT_SHIFT 16 +#define AG7240_TX_STATUS_PKT_SENT 0x1 +#define AG7240_TX_STATUS_URN 0x2 +#define AG7240_TX_STATUS_BUS_ERROR 0x8 + +#define AG7240_RXE (1 << 0) + +#define AG7240_RX_STATUS_PKTCNT_MASK 0xff0000 +#define AG7240_RX_STATUS_PKT_RCVD (1 << 0) +#define AG7240_RX_STATUS_OVF (1 << 2) +#define AG7240_RX_STATUS_BUS_ERROR (1 << 3) + +/* + * Int and int mask + */ +#define AG7240_INTR_TX (1 << 0) +#define AG7240_INTR_TX_URN (1 << 1) +#define AG7240_INTR_TX_BUS_ERROR (1 << 3) +#define AG7240_INTR_RX (1 << 4) +#define AG7240_INTR_RX_OVF (1 << 6) +#define AG7240_INTR_RX_BUS_ERROR (1 << 7) + +/* + * MII registers + */ +#define AG7240_MAC_MII_MGMT_CFG 0x20 +#define AG7240_MGMT_CFG_CLK_DIV_20 0x07 + +#define AG7240_MII_MGMT_CMD 0x24 +#define AG7240_MGMT_CMD_READ 0x1 + +#define AG7240_MII_MGMT_ADDRESS 0x28 +#define AG7240_ADDR_SHIFT 8 + +#define AG7240_MII_MGMT_CTRL 0x2c +#define AG7240_MII_MGMT_STATUS 0x30 + +#define AG7240_MII_MGMT_IND 0x34 +#define AG7240_MGMT_IND_BUSY (1 << 0) +#define AG7240_MGMT_IND_INVALID (1 << 2) + +#define AG7240_GE_MAC_ADDR1 0x40 +#define AG7240_GE_MAC_ADDR2 0x44 + +/* + * Ethernet config registers + */ +#define AG7240_ETH_CFG 0x18070000 +#define AG7240_ETH_CFG_RGMII_GE0 (1<<0) +#define AG7240_ETH_CFG_MII_GE0 (1<<1) +#define AG7240_ETH_CFG_GMII_GE0 (1<<2) +#define AG7240_ETH_CFG_RMII_GE0 (1<<10) +#define AG7240_ETH_CFG_RMII_HISPD_GE0 (1<<11) +#define AG7240_ETH_CFG_RMII_MASTER_MODE (1<<12) +#define AG7240_ETH_CFG_MII_GE0_MASTER (1<<3) +#define AG7240_ETH_CFG_MII_GE0_SLAVE (1<<4) +#define AG7240_ETH_CFG_GE0_ERR_EN (1<<5) +#define AG7240_ETH_CFG_SW_ONLY_MODE (1<<6) +#define AG7240_ETH_CFG_SW_PHY_SWAP (1<<7) +#define AG7240_ETH_CFG_SW_PHY_ADDR_SWAP (1<<8) +#define AG7240_ETH_CFG_RXD_DELAY (1 << 14) +#define AG7240_ETH_CFG_RDV_DELAY (1 << 16) +#define AG7240_ETH_SWITCH_CLK_SPARE 0x18050024 + + +/* + * * ownership of descriptors between DMA and cpu + * */ +#define ag7240_rx_owned_by_dma(_ds) ((_ds)->is_empty == 1) +#define ag7240_rx_give_to_dma(_ds) ((_ds)->is_empty = 1) +#define ag7240_tx_owned_by_dma(_ds) ((_ds)->is_empty == 0) +#define ag7240_tx_give_to_dma(_ds) ((_ds)->is_empty = 0) +#define ag7240_tx_own(_ds) ((_ds)->is_empty = 1) + +/* + * link settings + */ +#define ag7240_set_mac_duplex(_mac, _fdx) do { \ + if ((_fdx)) \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_FDX) \ + else \ + ag7240_reg_rmw_clear(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_FDX) \ +}while(0) + +#define ag7240_set_mac_if(_mac, _isXGMII) do { \ + ag7240_reg_rmw_clear(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_IF_1000| \ + AG7240_MAC_CFG2_IF_10_100); \ + if ((_isXGMII)) { \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_IF_1000) \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_FIFO_CFG_5, AG7240_BYTE_PER_CLK_EN);\ + } \ + else { \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_CFG2, AG7240_MAC_CFG2_IF_10_100)\ + ag7240_reg_rmw_clear(_mac, AG7240_MAC_FIFO_CFG_5, AG7240_BYTE_PER_CLK_EN);\ + } \ +}while(0) + +#define ag7240_set_mac_speed(_mac, _is100) do { \ + if ((_is100)) \ + ag7240_reg_rmw_set(_mac, AG7240_MAC_IFCTL, AG7240_MAC_IFCTL_SPEED) \ + else \ + ag7240_reg_rmw_clear(_mac, AG7240_MAC_IFCTL, AG7240_MAC_IFCTL_SPEED)\ +}while(0) + +#endif diff --git a/u-boot/cpu/mips/ar7240/ag934x_phy.h b/u-boot/cpu/mips/ar7240/ag934x_phy.h new file mode 100755 index 0000000..5ae745d --- /dev/null +++ b/u-boot/cpu/mips/ar7240/ag934x_phy.h @@ -0,0 +1,117 @@ +#ifndef _AG7240_PHY_H +#define _AG7240_PHY_H + +int athrs17_phy_is_up(int unit); +int athrs17_phy_is_fdx(int unit); +int athrs17_phy_speed(int unit); +int athrs17_phy_setup(int unit); + +static inline void ag7240_phy_setup(int unit) { +#ifdef CONFIG_AR7242_S16_PHY + if ((is_ar7242() || is_wasp()) && (unit==0)) { + athrs16_phy_setup(unit); + } else +#endif +#ifdef CONFIG_ATHRS17_PHY + if (unit == 0) { + athrs17_phy_setup(unit); + } else +#endif + { +#ifdef CFG_ATHRS27_PHY + athrs27_phy_setup(unit); +#endif +#ifdef CFG_ATHRS26_PHY + athrs26_phy_setup(unit); +#endif +#if defined(CONFIG_F1E_PHY) || defined(CONFIG_F2E_PHY) + athr_phy_setup(unit); +#endif +#ifdef CONFIG_VIR_PHY + athr_vir_phy_setup(unit); +#endif + } +} + +static inline void ag7240_phy_link(int unit, int *link) { +#ifdef CONFIG_AR7242_S16_PHY + if ((is_ar7242() || is_wasp()) && (unit==0)) { + *link = athrs16_phy_is_up(unit); + } else +#endif +#ifdef CONFIG_ATHRS17_PHY + if (unit == 0) { + *link = athrs17_phy_is_up(unit); + } else +#endif + { +#ifdef CFG_ATHRS27_PHY + *link = athrs27_phy_is_up(unit); +#endif +#ifdef CFG_ATHRS26_PHY + *link = athrs26_phy_is_up(unit); +#endif +#if defined(CONFIG_F1E_PHY) || defined(CONFIG_F2E_PHY) + *link = athr_phy_is_up(unit); +#endif +#ifdef CONFIG_VIR_PHY + *link = athr_vir_phy_is_up(unit); +#endif + } +} + +static inline void ag7240_phy_duplex(int unit, int *duplex) { +#ifdef CONFIG_AR7242_S16_PHY + if ((is_ar7242() || is_wasp()) && (unit==0)) { + *duplex = athrs16_phy_is_fdx(unit); + } else +#endif +#ifdef CONFIG_ATHRS17_PHY + if (unit == 0) { + *duplex = athrs17_phy_is_fdx(unit); + } else +#endif + { +#ifdef CFG_ATHRS27_PHY + *duplex = athrs27_phy_is_fdx(unit); +#endif +#ifdef CFG_ATHRS26_PHY + *duplex = athrs26_phy_is_fdx(unit); +#endif +#if defined(CONFIG_F1E_PHY) || defined(CONFIG_F2E_PHY) + *duplex = athr_phy_is_fdx(unit); +#endif +#ifdef CONFIG_VIR_PHY + *duplex = athr_vir_phy_is_fdx(unit); +#endif + } +} + +static inline void ag7240_phy_speed(int unit, int *speed) { +#ifdef CONFIG_AR7242_S16_PHY + if ((is_ar7242() || is_wasp()) && (unit==0)) { + *speed = athrs16_phy_speed(unit); + } else +#endif +#ifdef CONFIG_ATHRS17_PHY + if (unit == 0) { + *speed = athrs17_phy_speed(unit); + } else +#endif + { +#ifdef CFG_ATHRS27_PHY + *speed = athrs27_phy_speed(unit); +#endif +#ifdef CFG_ATHRS26_PHY + *speed = athrs26_phy_speed(unit); +#endif +#if defined(CONFIG_F1E_PHY) || defined(CONFIG_F2E_PHY) + *speed = athr_phy_speed(unit); +#endif +#ifdef CONFIG_VIR_PHY + *speed = athr_vir_phy_speed(unit); +#endif + } +} + +#endif /*_AG7240_PHY_H*/ diff --git a/u-boot/cpu/mips/ar7240/ar7240_serial.c b/u-boot/cpu/mips/ar7240/ar7240_serial.c new file mode 100755 index 0000000..be91075 --- /dev/null +++ b/u-boot/cpu/mips/ar7240/ar7240_serial.c @@ -0,0 +1,126 @@ +#include +#include +#include +#include + +#define REG_OFFSET 4 + +/* === END OF CONFIG === */ + +/* register offset */ +#define OFS_RCV_BUFFER (0*REG_OFFSET) +#define OFS_TRANS_HOLD (0*REG_OFFSET) +#define OFS_SEND_BUFFER (0*REG_OFFSET) +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + +#define MY_WRITE(y, z) ((*((volatile u32*)(y))) = z) +#define UART16550_READ(y) ar7240_reg_rd((AR7240_UART_BASE+y)) +#define UART16550_WRITE(x, z) ar7240_reg_wr((AR7240_UART_BASE+x), z) + +void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq){ + u32 pll, pll_div, ref_div, ahb_div, ddr_div, freq; + + pll = ar7240_reg_rd(AR7240_CPU_PLL_CONFIG); + + pll_div = ((pll & PLL_CONFIG_PLL_DIV_MASK) >> PLL_CONFIG_PLL_DIV_SHIFT); + ref_div = ((pll & PLL_CONFIG_PLL_REF_DIV_MASK) >> PLL_CONFIG_PLL_REF_DIV_SHIFT); + ddr_div = ((pll & PLL_CONFIG_DDR_DIV_MASK) >> PLL_CONFIG_DDR_DIV_SHIFT) + 1; + ahb_div = (((pll & PLL_CONFIG_AHB_DIV_MASK) >> PLL_CONFIG_AHB_DIV_SHIFT) + 1) * 2; + + freq = pll_div * ref_div * 5000000; + + if(cpu_freq){ + *cpu_freq = freq; + } + + if(ddr_freq){ + *ddr_freq = freq/ddr_div; + } + + if(ahb_freq){ + *ahb_freq = freq/ahb_div; + } +} + +int serial_init(void){ + u32 div, val; + u32 ahb_freq, ddr_freq, cpu_freq; + +#ifdef CONFIG_WASP + val = ar7240_reg_rd(WASP_BOOTSTRAP_REG); + + if((val & WASP_REF_CLK_25) == 0){ + div = (25 * 1000000) / (16 * CONFIG_BAUDRATE); + } else { + div = (40 * 1000000) / (16 * CONFIG_BAUDRATE); + } +#else + ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq); + + div = ahb_freq/(16 * CONFIG_BAUDRATE); + + MY_WRITE(0xb8040000, 0xcff); + MY_WRITE(0xb8040008, 0x3b); + + val = ar7240_reg_rd(0xb8040028); + MY_WRITE(0xb8040028,(val | 0x8002)); + + MY_WRITE(0xb8040008, 0x2f); +#endif + + /* + * set DIAB bit + */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + UART16550_WRITE(OFS_DIVISOR_LSB, (div & 0xff)); + UART16550_WRITE(OFS_DIVISOR_MSB, ((div >> 8) & 0xff)); + + /* clear DIAB bit*/ + UART16550_WRITE(OFS_LINE_CONTROL, 0x00); + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, 0x3); + + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + return(0); +} + +int serial_tstc(void){ + return(UART16550_READ(OFS_LINE_STATUS) & 0x1); +} + +u8 serial_getc(void){ + while(!serial_tstc()); + return(UART16550_READ(OFS_RCV_BUFFER)); +} + +void serial_putc(u8 byte){ + if(byte == '\n'){ + serial_putc('\r'); + } + + while(((UART16550_READ(OFS_LINE_STATUS)) & 0x20) == 0x0); + + UART16550_WRITE(OFS_SEND_BUFFER, byte); +} + +void serial_puts(const char *s){ + while(*s){ + serial_putc(*s++); + } +} diff --git a/u-boot/cpu/mips/ar7240/hornet_ddr_init.S b/u-boot/cpu/mips/ar7240/hornet_ddr_init.S new file mode 100755 index 0000000..ba2fd9b --- /dev/null +++ b/u-boot/cpu/mips/ar7240/hornet_ddr_init.S @@ -0,0 +1,4692 @@ +/* + * Startup Code for MIPS32 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + + .globl hornet_ddr_init + .text + .align 4 + +#define set_mem(_mem, _val) \ + li t9, _mem; \ + sw _val, 0(t9); + +//============================================ +// init DDR1 parameter before rel_start +//=========================================== +hornet_ddr_init: + + //--------DDR_Config_1-------- D.S 0xB8000000 %LONG 0x7fbc8cd0 + li t8, CFG_DDR_CONFIG_VAL; + set_mem(0xB8000000,t8); + + //--------DDR_Config_2-------- D.S 0xB8000004 %LONG 0x99d0e6a8 + li t8, CFG_DDR_CONFIG2_VAL; + set_mem(0xB8000004,t8); + + // DDR1 Paramters + + //D.S 0xB8000010 %LONG 0x8 ; // precharge + li t8,0x8; + set_mem(0xB8000010,t8); + + //D.S 0xB8000008 %LONG 0x133 ; + li t8,CFG_DDR_MODE_VAL_INIT; + set_mem(0xB8000008,t8); + + //D.S 0xB8000010 %LONG 0x1 ; // Write Mode Word in DDR + li t8, 0x1; + set_mem( 0xB8000010, t8); + + //D.S 0xB800000C %LONG 0x2 ; // Enable DLL, High drive strength from DDR + li t8, 0x2; + set_mem( 0xB800000C , t8); + + //D.S 0xB8000010 %LONG 0x2 ; // Write Extended Mode Word of DDR + li t8, 0x2; + set_mem( 0xB8000010, t8); + + //D.S 0xB8000010 %LONG 0x8 ; // precharge enabled + li t8, 0x8; + set_mem( 0xB8000010, t8); + + // D.S 0xB8000008 %LONG 0x33 ; // dll out of reset CAS Latency 3 + li t8, CFG_DDR_MODE_VAL; + set_mem( 0xB8000008, t8); + + //D.S 0xB8000010 %LONG 0x1 ; // write mode word + li t8, 0x1; + set_mem( 0xB8000010, t8); + + //D.S 0xB8000014 %LONG 0x4186/0x4270 ; // Refresh control. Bit 14 is enable. Bits<13:0> Refresh time + li t8, CFG_DDR_REFRESH_VAL; + set_mem( 0xB8000014, t8); + + //D.S 0xB800001C %LONG 0x08 ; // DQS 0 Tap Control (needs tuning) + li t8, CFG_DDR_TAP0_VAL; + set_mem( 0xB800001C, t8); + + //D.S 0xB8000020 %LONG 0x09 ; // DQS 1 Tap Control (needs tuning) + li t8, CFG_DDR_TAP1_VAL; + set_mem( 0xB8000020, t8); + + //D.S 0xB8000018 %LONG 0x00ff ; // For 16-bit DDR + li t8, 0x00ff; + set_mem( 0xB8000018, t8); + + nop + jr ra + +/* + * void hornet_ddr_tap_init(void) + * + * This "function" is used to find the tap settings for the DDR + */ + .globl hornet_ddr_tap_init + .ent hornet_ddr_tap_init +hornet_ddr_tap_init: /* { */ + +#if NEW_DDR_TAP_CAL + li t1,0x80500000 + li t0,0xffffffff + + sw t0,0x0(t1) + sw t0,0x4(t1) + sw t0,0x8(t1) + sw t0,0xc(t1) + + nop + nop + +ddr_pat_init: + li t8, 0xa0002000 + li t0, 0x00 + li t1, 0x100 +write_loop_start: + andi t2, t0, 0x03 +pat_000: + li t3, 0x00 + bne t2, t3,pat_001 + li t9, 0x00000000 + sw t9, 0x0 (t8) + b pat_004 + +pat_001: + li t3, 0x01 + bne t2, t3,pat_002 + li t9, 0x0000ffff + sw t9, 0x0 (t8) + b pat_004 + +pat_002: + li t3, 0x02 + bne t2, t3,pat_003 + li t9, 0xffff0000 + sw t9, 0x0 (t8) + b pat_004 + +pat_003: + li t3, 0x03 + bne t2, t3,pat_004 + li t9, 0xffffffff + sw t9, 0x0 (t8) + +pat_004: + andi t2, t0, 0x0c + li t3, 0x00 + bne t2, t3,pat_005 + li t9, 0x00000000 + sw t9, 0x4 (t8) + b pat_008 + +pat_005: + li t3, 0x04 + bne t2, t3,pat_006 + li t9, 0x0000ffff + sw t9, 0x4 (t8) + b pat_008 + +pat_006: + li t3, 0x08 + bne t2, t3,pat_007 + li t9, 0xffff0000 + sw t9, 0x4 (t8) + b pat_008 + +pat_007: + li t3, 0x0c + bne t2, t3,pat_008 + li t9, 0xffffffff + sw t9, 0x4 (t8) + +pat_008: + andi t2, t0, 0x30 + li t3, 0x00 + bne t2, t3,pat_009 + li t9, 0x00000000 + sw t9, 0x8 (t8) + b pat_00c + +pat_009: + li t3, 0x10 + bne t2, t3,pat_00a + li t9, 0x0000ffff + sw t9, 0x8 (t8) + b pat_00c + +pat_00a: + li t3, 0x20 + bne t2, t3,pat_00b + li t9, 0xffff0000 + sw t9, 0x8 (t8) + b pat_00c + +pat_00b: + li t3, 0x30 + bne t2, t3,pat_00c + li t9, 0xffffffff + sw t9, 0x8 (t8) + +pat_00c: + andi t2, t0, 0xc0 + li t3, 0x00 + bne t2, t3,pat_00d + li t9, 0x00000000 + sw t9, 0xc (t8) + b pat_done + +pat_00d: + li t3, 0x40 + bne t2, t3,pat_00e + li t9, 0x0000ffff + sw t9, 0xc (t8) + b pat_done + +pat_00e: + li t3, 0x80 + bne t2, t3,pat_00f + li t9, 0xffff0000 + sw t9, 0xc (t8) + b pat_done + +pat_00f: + li t3, 0xc0 + bne t2, t3,pat_done + li t9, 0xffffffff + sw t9, 0xc (t8) + +pat_done: + + addiu t0, t0, 0x1 + addiu t8, t8, 0x10 + bne t0, t1, write_loop_start + + + + +###### ddr init over ######### + + li a0, 0xa0002000 + li a1, 0x80002000 ### Start address of the pattern 200 + li a2, 0x80003000 ### End Address of the pattern 220 + li t0, 0xb800001c ## Tap settings addr + lw a3, 0x0(t0) ## loading default tap value + nop + ori t0, a3, 0x0 + nop + li t1, 0x1 ## $t1=1 indicates increasing tap value, 0 = decreasing + +load_tap: + + li t7, 0x2 + #li t7, 0x200 ## No. of times read has to happen for 1 tap setting + li t8, 0xb8000000 #### Loading Tap Setting + sw t0, 0x1c(t8) + nop + sw t0, 0x20(t8) + nop + #if 0 /* Hornet doesn't have DQS2, DQS3*/ + sw t0, 0x24(t8) + nop + sw t0, 0x28(t8) + nop + #endif + +###### t0 stores current tap setting under test +###### t1 indicates increment or decrement of tap + +pat_read: + ori t2, a0, 0x0 + nop + ori t3, a1, 0x0 + nop + ori t4, a2, 0x0 + nop + +tap_addr_loop: + lw t5, 0x0(t2) + nop + lw t6, 0x0(t3) + nop + nop + + bne t5, t6, tap_fail # jump to fail if not equal + nop + nop + nop + + addiu t2, t2, 0x4 #incrementing addr + addiu t3, t3, 0x4 + nop + nop + + bne t3, t4, tap_addr_loop # compare new addr if end addr not reached + nop + + addiu t7, t7, -1 # read passed for all locations once hence decrement t7 + nop + bnez t7, pat_read # t7 = 0 represents passing of all locations for given tap + nop + nop + + bnez t1, tap_incr # increment tap if t1 = 1 + nop + nop + + bnez t0, tap_decr ## $t0=0 implies tap=0 works + nop ## so low limit=0, else decrement tap value + nop + li t8, 0x80500000 ## assigning lower limit = 0 + sw t0, 0x0(t8) + add t9, t9, t0 ##adding lower limit to upper limit (used to calc mid value) + nop + nop + + b tap_calc + nop + nop + +tap_decr: # decrement t0 by 1 and move to loading this new tap + addiu t0, t0 , -1 + nop + b load_tap + nop + nop + +tap_incr: + addiu t0, t0 , 0x1 + nop + xori v1, t0, 0x20 # limiting upper limit to 0x20 + nop + bnez v1, load_tap + nop + nop + b up_limit + nop + nop + +tap_fail: + bnez t1, up_limit # t1=0 means lower limit detected @ fail else upper limit + nop + nop + nop + addiu t0, t0, 0x1 + nop + li t8, 0x80500000 # storing lower limit + nop + sw t0, 0x0(t8) + add t9, t9, t0 # storing lower limit# adding lower limit and upper limit + nop + nop + nop + + b tap_calc + nop + nop + +up_limit: + addiu t0, t0, -1 + li t1, 0x0 ## changing to decreasing tap mode + li t8, 0x80500000 ## storing upper limit + sw t0, 0x4(t8) + ori t9, t0, 0x0 + nop + nop + nop + + ori t0, a3, 0x0 # loading default tap value + nop + b load_tap + nop + nop + +tap_calc: ## calculating mid value of the tap, storing DQS0, DQS1 in 0x80500008, 0x8050000c resp. + li t7, 0x2 + nop + div t9, t7 + nop + mfhi t6 + mflo t5 + nop + nop + add t6, t6, t5 + li t8, 0x80500000 + nop + sw t5, 0x8(t8) + nop + sw t6, 0xc(t8) + nop + nop + li t8, 0xb8000000 #### Loading Tap Setting + nop + sw t5, 0x1c(t8) + nop + sw t6, 0x20(t8) + nop + #if 0 /* Hornet doesn't have DQS2, DQS3*/ + sw t5, 0x24(t8) + nop + sw t6, 0x28(t8) + nop + #endif + nop + nop +#else /* NEW_DDR_TAP_CAL */ + li t1,0x80500000 + li t0,0xffffffff + + sw t0,0x0(t1) + sw t0,0x4(t1) + sw t0,0x8(t1) + sw t0,0xc(t1) + + nop + nop + +ddr_pat_init: + li t0, 0xa0002000 + + li t1, 0x00000000 + sw t1, 0x0(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x10(t0) + nop + + li t1, 0x00000000 + sw t1, 0x14(t0) + nop + + li t1, 0x00000000 + sw t1, 0x18(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x20(t0) + nop + + li t1, 0x00000000 + sw t1, 0x24(t0) + nop + + li t1, 0x00000000 + sw t1, 0x28(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x30(t0) + nop + + li t1, 0x00000000 + sw t1, 0x34(t0) + nop + + li t1, 0x00000000 + sw t1, 0x38(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x44(t0) + nop + + li t1, 0x00000000 + sw t1, 0x48(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x54(t0) + nop + + li t1, 0x00000000 + sw t1, 0x58(t0) + nop + + li t1, 0x00000000 + sw t1, 0x5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x64(t0) + nop + + li t1, 0x00000000 + sw t1, 0x68(t0) + nop + + li t1, 0x00000000 + sw t1, 0x6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x74(t0) + nop + + li t1, 0x00000000 + sw t1, 0x78(t0) + nop + + li t1, 0x00000000 + sw t1, 0x7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x84(t0) + nop + + li t1, 0x00000000 + sw t1, 0x88(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x94(t0) + nop + + li t1, 0x00000000 + sw t1, 0x98(t0) + nop + + li t1, 0x00000000 + sw t1, 0x9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xdc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xfc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x100(t0) + nop + + li t1, 0x00000000 + sw t1, 0x104(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x108(t0) + nop + + li t1, 0x00000000 + sw t1, 0x10c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x110(t0) + nop + + li t1, 0x00000000 + sw t1, 0x114(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x118(t0) + nop + + li t1, 0x00000000 + sw t1, 0x11c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x120(t0) + nop + + li t1, 0x00000000 + sw t1, 0x124(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x128(t0) + nop + + li t1, 0x00000000 + sw t1, 0x12c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x130(t0) + nop + + li t1, 0x00000000 + sw t1, 0x134(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x138(t0) + nop + + li t1, 0x00000000 + sw t1, 0x13c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x140(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x144(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x148(t0) + nop + + li t1, 0x00000000 + sw t1, 0x14c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x150(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x154(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x158(t0) + nop + + li t1, 0x00000000 + sw t1, 0x15c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x160(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x164(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x168(t0) + nop + + li t1, 0x00000000 + sw t1, 0x16c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x170(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x174(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x178(t0) + nop + + li t1, 0x00000000 + sw t1, 0x17c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x180(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x184(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x188(t0) + nop + + li t1, 0x00000000 + sw t1, 0x18c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x190(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x194(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x198(t0) + nop + + li t1, 0x00000000 + sw t1, 0x19c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x1a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x1a4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1a8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x1b4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1b8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1c4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1c8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1d4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1d8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x1e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1e4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1e8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1f4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1f8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x200(t0) + nop + + li t1, 0x00000000 + sw t1, 0x204(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x208(t0) + nop + + li t1, 0x00000000 + sw t1, 0x20c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x210(t0) + nop + + li t1, 0x00000000 + sw t1, 0x214(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x218(t0) + nop + + li t1, 0x00000000 + sw t1, 0x21c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x220(t0) + nop + + li t1, 0x00000000 + sw t1, 0x224(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x228(t0) + nop + + li t1, 0x00000000 + sw t1, 0x22c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x230(t0) + nop + + li t1, 0x00000000 + sw t1, 0x234(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x238(t0) + nop + + li t1, 0x00000000 + sw t1, 0x23c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x240(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x244(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x248(t0) + nop + + li t1, 0x00000000 + sw t1, 0x24c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x250(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x254(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x258(t0) + nop + + li t1, 0x00000000 + sw t1, 0x25c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x260(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x264(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x268(t0) + nop + + li t1, 0x00000000 + sw t1, 0x26c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x270(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x274(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x278(t0) + nop + + li t1, 0x00000000 + sw t1, 0x27c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x280(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x284(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x288(t0) + nop + + li t1, 0x00000000 + sw t1, 0x28c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x290(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x294(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x298(t0) + nop + + li t1, 0x00000000 + sw t1, 0x29c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2a4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2a8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2b4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2b8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2c4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2c8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x2d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2d4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2d8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2e4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2e8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2f4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2f8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x300(t0) + nop + + li t1, 0x00000000 + sw t1, 0x304(t0) + nop + + li t1, 0xffffffff + sw t1, 0x308(t0) + nop + + li t1, 0x00000000 + sw t1, 0x30c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x310(t0) + nop + + li t1, 0x00000000 + sw t1, 0x314(t0) + nop + + li t1, 0xffffffff + sw t1, 0x318(t0) + nop + + li t1, 0x00000000 + sw t1, 0x31c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x320(t0) + nop + + li t1, 0x00000000 + sw t1, 0x324(t0) + nop + + li t1, 0xffffffff + sw t1, 0x328(t0) + nop + + li t1, 0x00000000 + sw t1, 0x32c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x330(t0) + nop + + li t1, 0x00000000 + sw t1, 0x334(t0) + nop + + li t1, 0xffffffff + sw t1, 0x338(t0) + nop + + li t1, 0x00000000 + sw t1, 0x33c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x340(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x344(t0) + nop + + li t1, 0xffffffff + sw t1, 0x348(t0) + nop + + li t1, 0x00000000 + sw t1, 0x34c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x350(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x354(t0) + nop + + li t1, 0xffffffff + sw t1, 0x358(t0) + nop + + li t1, 0x00000000 + sw t1, 0x35c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x360(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x364(t0) + nop + + li t1, 0xffffffff + sw t1, 0x368(t0) + nop + + li t1, 0x00000000 + sw t1, 0x36c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x370(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x374(t0) + nop + + li t1, 0xffffffff + sw t1, 0x378(t0) + nop + + li t1, 0x00000000 + sw t1, 0x37c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x380(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x384(t0) + nop + + li t1, 0xffffffff + sw t1, 0x388(t0) + nop + + li t1, 0x00000000 + sw t1, 0x38c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x390(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x394(t0) + nop + + li t1, 0xffffffff + sw t1, 0x398(t0) + nop + + li t1, 0x00000000 + sw t1, 0x39c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x3a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x3a4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3a8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x3b4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3b8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3c4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3c8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x3d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3d4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3d8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x3e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3e4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3e8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3f4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3f8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x400(t0) + nop + + li t1, 0x00000000 + sw t1, 0x404(t0) + nop + + li t1, 0x00000000 + sw t1, 0x408(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x40c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x410(t0) + nop + + li t1, 0x00000000 + sw t1, 0x414(t0) + nop + + li t1, 0x00000000 + sw t1, 0x418(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x41c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x420(t0) + nop + + li t1, 0x00000000 + sw t1, 0x424(t0) + nop + + li t1, 0x00000000 + sw t1, 0x428(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x42c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x430(t0) + nop + + li t1, 0x00000000 + sw t1, 0x434(t0) + nop + + li t1, 0x00000000 + sw t1, 0x438(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x43c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x440(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x444(t0) + nop + + li t1, 0x00000000 + sw t1, 0x448(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x44c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x450(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x454(t0) + nop + + li t1, 0x00000000 + sw t1, 0x458(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x45c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x460(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x464(t0) + nop + + li t1, 0x00000000 + sw t1, 0x468(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x46c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x470(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x474(t0) + nop + + li t1, 0x00000000 + sw t1, 0x478(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x47c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x480(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x484(t0) + nop + + li t1, 0x00000000 + sw t1, 0x488(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x48c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x490(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x494(t0) + nop + + li t1, 0x00000000 + sw t1, 0x498(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x49c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x4a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x4a4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4a8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x4b4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4b8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4c4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4c8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4d4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4d8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x4e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4e4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4e8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4f4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4f8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x500(t0) + nop + + li t1, 0x00000000 + sw t1, 0x504(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x508(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x50c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x510(t0) + nop + + li t1, 0x00000000 + sw t1, 0x514(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x518(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x51c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x520(t0) + nop + + li t1, 0x00000000 + sw t1, 0x524(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x528(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x52c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x530(t0) + nop + + li t1, 0x00000000 + sw t1, 0x534(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x538(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x53c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x540(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x544(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x548(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x54c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x550(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x554(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x558(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x55c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x560(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x564(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x568(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x56c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x570(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x574(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x578(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x57c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x580(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x584(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x588(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x58c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x590(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x594(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x598(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x59c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x5a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x5a4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5a8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x5b4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5b8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x5c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5c4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5c8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5d4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5d8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x5e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5e4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5e8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5f4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5f8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x600(t0) + nop + + li t1, 0x00000000 + sw t1, 0x604(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x608(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x60c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x610(t0) + nop + + li t1, 0x00000000 + sw t1, 0x614(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x618(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x61c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x620(t0) + nop + + li t1, 0x00000000 + sw t1, 0x624(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x628(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x62c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x630(t0) + nop + + li t1, 0x00000000 + sw t1, 0x634(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x638(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x63c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x640(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x644(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x648(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x64c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x650(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x654(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x658(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x65c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x660(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x664(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x668(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x66c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x670(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x674(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x678(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x67c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x680(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x684(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x688(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x68c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x690(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x694(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x698(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x69c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6a4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6a8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6b4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6b8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x6c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6c4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6c8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6d4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6d8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6e4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6e8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6f4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6f8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x700(t0) + nop + + li t1, 0x00000000 + sw t1, 0x704(t0) + nop + + li t1, 0xffffffff + sw t1, 0x708(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x70c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x710(t0) + nop + + li t1, 0x00000000 + sw t1, 0x714(t0) + nop + + li t1, 0xffffffff + sw t1, 0x718(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x71c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x720(t0) + nop + + li t1, 0x00000000 + sw t1, 0x724(t0) + nop + + li t1, 0xffffffff + sw t1, 0x728(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x72c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x730(t0) + nop + + li t1, 0x00000000 + sw t1, 0x734(t0) + nop + + li t1, 0xffffffff + sw t1, 0x738(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x73c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x740(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x744(t0) + nop + + li t1, 0xffffffff + sw t1, 0x748(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x74c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x750(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x754(t0) + nop + + li t1, 0xffffffff + sw t1, 0x758(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x75c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x760(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x764(t0) + nop + + li t1, 0xffffffff + sw t1, 0x768(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x76c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x770(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x774(t0) + nop + + li t1, 0xffffffff + sw t1, 0x778(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x77c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x780(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x784(t0) + nop + + li t1, 0xffffffff + sw t1, 0x788(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x78c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x790(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x794(t0) + nop + + li t1, 0xffffffff + sw t1, 0x798(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x79c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x7a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x7a4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7a8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x7b4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7b8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x7c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7c4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7c8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7d4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7d8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x7e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7e4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7e8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7f4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7f8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x800(t0) + nop + + li t1, 0x00000000 + sw t1, 0x804(t0) + nop + + li t1, 0x00000000 + sw t1, 0x808(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x80c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x810(t0) + nop + + li t1, 0x00000000 + sw t1, 0x814(t0) + nop + + li t1, 0x00000000 + sw t1, 0x818(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x81c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x820(t0) + nop + + li t1, 0x00000000 + sw t1, 0x824(t0) + nop + + li t1, 0x00000000 + sw t1, 0x828(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x82c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x830(t0) + nop + + li t1, 0x00000000 + sw t1, 0x834(t0) + nop + + li t1, 0x00000000 + sw t1, 0x838(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x83c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x840(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x844(t0) + nop + + li t1, 0x00000000 + sw t1, 0x848(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x84c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x850(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x854(t0) + nop + + li t1, 0x00000000 + sw t1, 0x858(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x85c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x860(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x864(t0) + nop + + li t1, 0x00000000 + sw t1, 0x868(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x86c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x870(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x874(t0) + nop + + li t1, 0x00000000 + sw t1, 0x878(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x87c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x880(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x884(t0) + nop + + li t1, 0x00000000 + sw t1, 0x888(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x88c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x890(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x894(t0) + nop + + li t1, 0x00000000 + sw t1, 0x898(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x89c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8a4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8a8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8b4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8b8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8c4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8c8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x8d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8d4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8d8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8e4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8e8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8f4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8f8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x900(t0) + nop + + li t1, 0x00000000 + sw t1, 0x904(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x908(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x90c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x910(t0) + nop + + li t1, 0x00000000 + sw t1, 0x914(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x918(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x91c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x920(t0) + nop + + li t1, 0x00000000 + sw t1, 0x924(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x928(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x92c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x930(t0) + nop + + li t1, 0x00000000 + sw t1, 0x934(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x938(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x93c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x940(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x944(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x948(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x94c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x950(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x954(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x958(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x95c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x960(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x964(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x968(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x96c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x970(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x974(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x978(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x97c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x980(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x984(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x988(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x98c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x990(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x994(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x998(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x99c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9a4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9a8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9b4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9b8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x9c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9c4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9c8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9d4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9d8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9e4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9e8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9f4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9f8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa04(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa08(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa14(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa18(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa24(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa28(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xa30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa34(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa38(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa44(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa48(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa54(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa58(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa64(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa68(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xa70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa74(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa78(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa84(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa88(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa94(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa98(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaa0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaa4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaa8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xab0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xab4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xab8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xabc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xac0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xac4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xac8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xacc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xad0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xad4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xad8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xadc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xae0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xae4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xae8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xaf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xaf4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaf8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xafc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb04(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb08(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb14(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb18(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb24(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb28(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb34(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb38(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb44(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb48(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb54(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb58(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb64(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb68(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb74(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb78(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb84(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb88(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb94(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb98(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xba0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xba4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xba8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbb4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbb8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xbc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbc4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbc8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbcc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xbd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbd4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbd8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbdc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbe0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbe4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbe8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbf4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbf8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbfc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc04(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc08(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc14(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc18(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xc20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc24(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc28(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc34(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc38(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc44(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc48(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc54(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc58(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xc60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc64(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc68(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc74(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc78(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xc84(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc88(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xc94(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc98(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xca0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xca4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xca8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xcb4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcb8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcc4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcc8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xccc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xcd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcd4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcd8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcdc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xce0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xce4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xce8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcf4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcf8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcfc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd04(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd08(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd14(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd18(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xd20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd24(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd28(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd34(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd38(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd44(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd48(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd54(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd58(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xd60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd64(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd68(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd74(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd78(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xd84(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd88(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xd94(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd98(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xda0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xda4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xda8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xdb4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdb8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xdc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdc4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdc8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdcc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdd4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdd8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xddc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xde0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xde4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xde8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdf4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdf8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdfc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe04(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe08(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe14(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe18(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe24(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe28(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe34(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe38(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe44(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe48(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe54(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe58(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe64(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe68(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe74(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe78(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe84(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe88(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe94(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe98(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xea0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xea4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xea8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xeac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xeb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xeb4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xeb8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xebc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xec0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xec4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xec8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xecc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xed0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xed4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xed8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xedc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xee0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xee4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xee8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xeec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xef0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xef4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xef8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xefc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf04(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf08(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf14(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf18(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xf20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf24(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf28(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf34(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf38(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf44(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf48(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf54(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf58(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xf60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf64(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf68(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf74(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf78(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xf84(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf88(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xf94(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf98(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xfa0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xfa4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfa8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xfb4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfb8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xfc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfc4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfc8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfcc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xfd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfd4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfd8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfdc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xfe0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfe4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfe8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xff0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xff4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xff8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xffc(t0) + nop + + +//###### ddr init over ######### + + li a0, 0xa0002000 + li a1, 0x80002000 //### Start address of the pattern 200 + li a2, 0x80003000 //### End Address of the pattern 220 + li t0, 0xb800001c //## Tap settings addr + lw a3, 0x0(t0) //## loading default tap value + nop + ori t0, a3, 0x0 + nop + li t1, 0x1 //# t1=1 indicates increasing tap value, 0 = decreasing + +load_tap: + + li t7, 0x2 + #li t7, 0x200 ## No. of times read has to happen for 1 tap setting + li t8, 0xb8000000 //#### Loading Tap Setting + sw t0, 0x1c(t8) + nop + sw t0, 0x20(t8) + nop + +pat_read: + ori t2, a0, 0x0 + nop + ori t3, a1, 0x0 + nop + ori t4, a2, 0x0 + nop + +tap_addr_loop: + lw t5, 0x0(t2) + nop + lw t6, 0x0(t3) + nop + nop + + bne t5, t6, tap_fail + nop + nop + nop + + addiu t2, t2, 0x4 //#incrementing addr + addiu t3, t3, 0x4 + nop + nop + + bne t3, t4, tap_addr_loop + nop + + addiu t7, t7, -1 + nop + bnez t7, pat_read + nop + nop + + bnez t1, tap_incr + nop + nop + + bnez t0, tap_decr //# t0=0 implies tap=0 works + nop //# so low limit=0, else decrement tap value + nop + li t8, 0x80500000 + sw t0, 0x0(t8) + add t9, t9, t0 //#adding lower limit to upper limit (used to calc mid value) + nop + nop + + b tap_calc + nop + nop + +tap_decr: + addiu t0, t0 , -1 + nop + b load_tap + nop + nop + +tap_incr: + addiu t0, t0 , 0x1 + nop + xori v1, t0, 0x20 + nop + bnez v1, load_tap + nop + nop + b up_limit + nop + nop + +tap_fail: + bnez t1, up_limit + nop + nop + nop + addiu t0, t0, 0x1 + nop + li t8, 0x80500000 + nop + sw t0, 0x0(t8) + add t9, t9, t0 + nop + nop + nop + + b tap_calc + nop + nop + +up_limit: + addiu t0, t0, -1 + li t1, 0x0 //## changing to decreasing tap mode + li t8, 0x80500000 //## storing upper limit + sw t0, 0x4(t8) + ori t9, t0, 0x0 + nop + nop + nop + + ori t0, a3, 0x0 //# loading default tap value + nop + b load_tap + nop + nop + +tap_calc: //## calculating mid value of the tap, storing DQS0, DQS1 in 0x80500008, 0x8050000c resp. + li t7, 0x2 + nop + div t9, t7 + nop + mfhi t6 + mflo t5 + nop + nop + add t6, t6, t5 + li t8, 0x80500000 + nop + sw t5, 0x8(t8) + nop + sw t6, 0xc(t8) + nop + nop + li t8, 0xb8000000 //#### Loading Tap Setting + nop + sw t5, 0x1c(t8) + nop + sw t6, 0x20(t8) + nop + nop + nop +#endif /* SIMPLE_DDR_TAP_CAL */ + +end: + nop + nop + nop + jr ra + + .end hornet_ddr_tap_init +/* } */ diff --git a/u-boot/cpu/mips/ar7240/hornet_serial.c b/u-boot/cpu/mips/ar7240/hornet_serial.c new file mode 100755 index 0000000..b22a52a --- /dev/null +++ b/u-boot/cpu/mips/ar7240/hornet_serial.c @@ -0,0 +1,178 @@ +#include +#include +#include +#include + +#define uart_reg_read(x) ar7240_reg_rd( (AR7240_UART_BASE+x) ) +#define uart_reg_write(x, y) ar7240_reg_wr( (AR7240_UART_BASE+x), y) + +static int AthrUartGet(char *__ch_data) { + u32 rdata; + + rdata = uart_reg_read(UARTDATA_ADDRESS); + + if (UARTDATA_UARTRXCSR_GET(rdata)) { + *__ch_data = (char) UARTDATA_UARTTXRXDATA_GET(rdata); + rdata = UARTDATA_UARTRXCSR_SET(1); + uart_reg_write(UARTDATA_ADDRESS, rdata); + return 1; + } else { + return 0; + } +} + +static void AthrUartPut(char __ch_data) { + u32 rdata; + + do { + rdata = uart_reg_read(UARTDATA_ADDRESS); + } while (UARTDATA_UARTTXCSR_GET(rdata) == 0); + + rdata = UARTDATA_UARTTXRXDATA_SET((u32)__ch_data); + rdata |= UARTDATA_UARTTXCSR_SET(1); + + uart_reg_write(UARTDATA_ADDRESS, rdata); +} + +void ar7240_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq) { + // TODO: check the following code + u32 ref_clock_rate, pll_freq; + u32 pllreg, clockreg; + u32 nint, refdiv, outdiv; + u32 cpu_div, ahb_div, ddr_div; + + if (ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & HORNET_BOOTSTRAP_SEL_25M_40M_MASK) { + ref_clock_rate = 40 * 1000000; + } else { + ref_clock_rate = 25 * 1000000; + } + + pllreg = ar7240_reg_rd(AR7240_CPU_PLL_CONFIG); + clockreg = ar7240_reg_rd(AR7240_CPU_CLOCK_CONTROL); + + if (clockreg & HORNET_CLOCK_CONTROL_BYPASS_MASK) { + /* Bypass PLL */ + pll_freq = ref_clock_rate; + cpu_div = ahb_div = ddr_div = 1; + } else { + nint = (pllreg & HORNET_PLL_CONFIG_NINT_MASK) >> HORNET_PLL_CONFIG_NINT_SHIFT; + refdiv = (pllreg & HORNET_PLL_CONFIG_REFDIV_MASK) >> HORNET_PLL_CONFIG_REFDIV_SHIFT; + outdiv = (pllreg & HORNET_PLL_CONFIG_OUTDIV_MASK) >> HORNET_PLL_CONFIG_OUTDIV_SHIFT; + + pll_freq = (ref_clock_rate / refdiv) * nint; + + if (outdiv == 1) + pll_freq /= 2; + else if (outdiv == 2) + pll_freq /= 4; + else if (outdiv == 3) + pll_freq /= 8; + else if (outdiv == 4) + pll_freq /= 16; + else if (outdiv == 5) + pll_freq /= 32; + else if (outdiv == 6) + pll_freq /= 64; + else if (outdiv == 7) + pll_freq /= 128; + else + /* outdiv == 0 --> illegal value */ + pll_freq /= 2; + + cpu_div = (clockreg & HORNET_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_CPU_POST_DIV_SHIFT; + ddr_div = (clockreg & HORNET_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_DDR_POST_DIV_SFIFT; + ahb_div = (clockreg & HORNET_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> HORNET_CLOCK_CONTROL_AHB_POST_DIV_SFIFT; + + /* + * b00 : div by 1, b01 : div by 2, b10 : div by 3, b11 : div by 4 + */ + cpu_div++; + ddr_div++; + ahb_div++; + } + + *cpu_freq = pll_freq / cpu_div; + *ddr_freq = pll_freq / ddr_div; + *ahb_freq = pll_freq / ahb_div; +} + +int serial_init(void) { + u32 rdata; + u32 baudRateDivisor, clock_step; + u32 fcEnable = 0; + u32 ahb_freq, ddr_freq, cpu_freq; + + ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq); + + /* GPIO Configuration */ + ar7240_reg_wr(AR7240_GPIO_OE, 0xcff); + rdata = ar7240_reg_rd(AR7240_GPIO_OUT); + rdata |= 0x400; // GPIO 10 (UART_SOUT) must output 1 + ar7240_reg_wr(AR7240_GPIO_OUT, rdata); + + rdata = ar7240_reg_rd(AR7240_GPIO_FUNC); + /* GPIO_FUN, bit1/UART_EN, bit2/UART_RTS_CTS_EN, bit15(disable_s26_uart) */ + rdata |= (0x3 << 1) | (0x1 << 15); + ar7240_reg_wr(AR7240_GPIO_FUNC, rdata); + + /* Get reference clock rate, then set baud rate to 115200 */ + // TODO: check the following code + rdata = ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS); + rdata &= HORNET_BOOTSTRAP_SEL_25M_40M_MASK; + + if (rdata) { + baudRateDivisor = (40000000 / (16 * 115200)) - 1; // 40 MHz clock is taken as UART clock + } else { + baudRateDivisor = (25000000 / (16 * 115200)) - 1; // 25 MHz clock is taken as UART clock + } + + clock_step = 8192; + + rdata = UARTCLOCK_UARTCLOCKSCALE_SET(baudRateDivisor) | UARTCLOCK_UARTCLOCKSTEP_SET(clock_step); + uart_reg_write(UARTCLOCK_ADDRESS, rdata); + + /* Config Uart Controller */ + /* No interrupt */ + rdata = UARTCS_UARTDMAEN_SET(0) | UARTCS_UARTHOSTINTEN_SET(0) | UARTCS_UARTHOSTINT_SET(0) | UARTCS_UARTSERIATXREADY_SET(0) | UARTCS_UARTTXREADYORIDE_SET(~fcEnable) | UARTCS_UARTRXREADYORIDE_SET(~fcEnable) | UARTCS_UARTHOSTINTEN_SET(0); + + /* is_dte == 1 */ + rdata = rdata | UARTCS_UARTINTERFACEMODE_SET(2); + + if (fcEnable) { + rdata = rdata | UARTCS_UARTFLOWCONTROLMODE_SET(2); + } + + /* invert_fc ==0 (Inverted Flow Control) */ + //rdata = rdata | UARTCS_UARTFLOWCONTROLMODE_SET(3); + /* parityEnable == 0 */ + //rdata = rdata | UARTCS_UARTPARITYMODE_SET(2); -->Parity Odd + //rdata = rdata | UARTCS_UARTPARITYMODE_SET(3); -->Parity Even + uart_reg_write(UARTCS_ADDRESS, rdata); + + return 0; +} + +int serial_tstc(void) { + return (UARTDATA_UARTRXCSR_GET(uart_reg_read(UARTDATA_ADDRESS))); +} + +u8 serial_getc(void) { + char ch_data; + + while (!AthrUartGet(&ch_data)) + ; + + return (u8) ch_data; +} + +void serial_putc(u8 byte) { + if (byte == '\n') AthrUartPut('\r'); + + AthrUartPut((char) byte); +} + +void serial_puts(const char *s) { + while (*s) { + serial_putc(*s++); + } +} diff --git a/u-boot/cpu/mips/ar7240/meminit.c b/u-boot/cpu/mips/ar7240/meminit.c new file mode 100755 index 0000000..ed35495 --- /dev/null +++ b/u-boot/cpu/mips/ar7240/meminit.c @@ -0,0 +1,321 @@ +/* + * Memory controller config: + * Assumes that the caches are initialized. + * + * 0) Figah out the Tap controller settings. + * 1) Figure out whether the interface is 16bit or 32bit. + * 2) Size the DRAM + * + * 0) Tap controller settings + * -------------------------- + * The Table below provides all possible values of TAP controllers. We need to + * find the extreme left and extreme right of the spectrum (of max_udelay and + * min_udelay). We then program the TAP to be in the middle. + * Note for this we would need to be able to read and write memory. So, + * initially we assume that a 16bit interface, which will always work unless + * there is exactly _1_ 32 bit part...for now we assume this is not the case. + * + * The algo: + * 0) Program the controller in 16bit mode. + * 1) Start with the extreme left of the table + * 2) Write 0xa4, 0xb5, 0xc6, 0xd7 to 0, 2, 4, 6 + * 3) Read 0 - this will fetch the entire cacheline. + * 4) If the value at address 4 is good, record this table entry, goto 6 + * 5) Increment to get the next table entry. Goto 2. + * 6) Start with extreme right. Do the same as above. + * + * 1) 16bit or 32bit + * ----------------- + * 31st bit of reg 0x1800_0000 will determine the mode. By default, + * controller is set to 32-bit mode. In 32 bit mode, full data bus DQ [31:0] + * will be used to write 32 bit data. Suppose you have 16bit DDR memory + * (it will have 16bit wide data bus). If you try to write 16 bit DDR in 32 + * bit mode, you are going to miss upper 16 bits of data. Reading to that + * location will give you only lower 16 bits correctly, upper 16 bits will + * have some junk value. E.g., + * + * write to 0x0000_0000 0x12345678 + * write to 0x0000_1000 0x00000000 (just to discharge DQ[31:16] ) + * read from 0x0000_0000 + * if u see something like 0x0000_5678 (or XXXX_5678 but not equal to + * 0x12345678) - its a 16 bit interface + * + * 2) Size the DRAM + * ------------------- + * DDR wraps around. Write a pattern to 0x0000_0000. Write an address + * pattern at 4M, 8M, 16M etc. and check when 0x0000_0000 gets overwritten. + * + * + * We can use #define's for all these addresses and patterns but its easier + * to see what's going on without :) + */ +#include +#include +#include "ar7240_soc.h" + +uint8_t tap_settings[] = {0x40, 0x41, 0x10, 0x12, 0x13, 0x15, 0x1a, 0x1c, 0x1f, 0x2f, 0x3f}; +uint16_t tap_pattern[] = {0xa5, 0xb6, 0xc7, 0xd8}; + +void ar7240_ddr_tap_set(uint8_t set){ + ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL0, set); + ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL1, set); + ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL2, set); + ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL3, set); +} + +// We check for size in 16M increments +#define AR7240_DDR_SIZE_INCR (16*1024*1024) +int ar7240_ddr_find_size(void){ + uint8_t *p = (uint8_t *)KSEG1, pat = 0x77; + int i; + + *p = pat; + + for(i = 1;; i++){ + *(p + i * AR7240_DDR_SIZE_INCR) = (uint8_t)(i); + + if(*p != pat){ + break; + } + } + + return(i * AR7240_DDR_SIZE_INCR); +} + +#ifndef CONFIG_WASP +void ar7240_ddr_initial_config(uint32_t refresh){ + int ddr2 = 0; + int ddr_config; + int ddr_config2, ext_mod, ddr2_ext_mod; + int mod_val, mod_val_init; + + ddr2 = ((ar7240_reg_rd(0xb8050020) & 0x1) == 0); + + ddr_config = CFG_DDR_CONFIG_VAL; + ddr_config2 = CFG_DDR_CONFIG2_VAL; + ext_mod = CFG_DDR_EXT_MODE_VAL; + ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL; + mod_val_init = CFG_DDR_MODE_VAL_INIT; + mod_val = CFG_DDR_MODE_VAL; + + if(ddr2){ + ar7240_reg_wr_nf(0xb800008c, 0xA59); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20); + udelay(10); + } + + ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val_init); + udelay(1000); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); + udelay(10); + + if(ddr2){ + ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ddr2_ext_mod); + } else { + ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ext_mod); + } + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_REFRESH, refresh); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE, CFG_DDR_RD_DATA_THIS_CYCLE_VAL); + udelay(100); +} +#else +int wasp_ddr_initial_config(uint32_t refresh){ + int ddr_config, ddr_config2, ext_mod, mod_val, mod_val_init, cycle_val, tap_val, type; + + switch(WASP_RAM_TYPE(ar7240_reg_rd(WASP_BOOTSTRAP_REG))){ + case 0: + case 1: // SDRAM + + // XXX XXX XXX XXX XXX XXX XXX XXX XXX + // Boot strap select is not working. In some boards, + // ddr2 shows up as sdram. Hence ignoring the foll. + // break statement. + // XXX XXX XXX XXX XXX XXX XXX XXX XXX + // break; + + ddr_config = CFG_934X_SDRAM_CONFIG_VAL; + ddr_config2 = CFG_934X_SDRAM_CONFIG2_VAL; + mod_val_init = CFG_934X_SDRAM_MODE_VAL_INIT; + mod_val = CFG_934X_SDRAM_MODE_VAL; + cycle_val = CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL; + tap_val = CFG_934X_SDRAM_TAP_VAL; + + ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, 0x13b); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_DEBUG_RD_CNTL, 0x3000001f); + udelay(100); + + type = 0; + + break; + + case 2: // ddr2 + + ddr_config = CFG_934X_DDR2_CONFIG_VAL; + ddr_config2 = CFG_934X_DDR2_CONFIG2_VAL; + ext_mod = CFG_934X_DDR2_EXT_MODE_VAL; + mod_val_init = CFG_934X_DDR2_MODE_VAL_INIT; + mod_val = CFG_934X_DDR2_MODE_VAL; + cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL; + tap_val = CFG_934X_DDR2_TAP_VAL; + + ar7240_reg_wr_nf(AR7240_DDR_DDR2_CONFIG, CFG_934X_DDR2_EN_TWL_VAL); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20); + udelay(10); + + if(ar7240_reg_rd(AR7240_REV_ID) & 0xf){ + // NAND Clear + if(ar7240_reg_rd(WASP_BOOTSTRAP_REG) & (1 << 3)){ + ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, (1 << 6)); + cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32; + } else { + ar7240_reg_rmw_set(AR7240_DDR_CTL_CONFIG, (1 << 6)); + cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16; + } + } else { +#if DDR2_32BIT_SUPPORT + ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, 0); +#endif + } + udelay(10); + + type = 1; + + break; + + case 3: // ddr1 + + ddr_config = CFG_934X_DDR1_CONFIG_VAL; + ddr_config2 = CFG_934X_DDR1_CONFIG2_VAL; + ext_mod = CFG_934X_DDR1_EXT_MODE_VAL; + mod_val_init = CFG_934X_DDR1_MODE_VAL_INIT; + mod_val = CFG_934X_DDR1_MODE_VAL; + cycle_val = CFG_DDR1_RD_DATA_THIS_CYCLE_VAL; + tap_val = CFG_934X_DDR1_TAP_VAL; + + type = 2; + + break; + } + + ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val_init); + udelay(1000); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); + udelay(10); + + if(type == 1){ + //ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, CFG_934X_DDR2_EXT_MODE_VAL_INIT); + ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, CFG_934X_DDR2_MODE_VAL_INIT); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); + udelay(10); + } + + if(type != 0){ + ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ext_mod); + } + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); + udelay(10); + + ar7240_reg_wr_nf(AR7240_DDR_REFRESH, refresh); + udelay(100); + + ar7240_reg_wr(AR7240_DDR_TAP_CONTROL0, tap_val); + ar7240_reg_wr(AR7240_DDR_TAP_CONTROL1, tap_val); + + if(ar7240_reg_rd(AR7240_REV_ID) & 0xf){ + /* NAND Clear */ + if((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & (1 << 3)) && type){ + ar7240_reg_wr(AR7240_DDR_TAP_CONTROL2, tap_val); + ar7240_reg_wr(AR7240_DDR_TAP_CONTROL3, tap_val); + } + } else { +#if DDR2_32BIT_SUPPORT + if(type != 0){ + ar7240_reg_wr(AR7240_DDR_TAP_CONTROL2, tap_val); + ar7240_reg_wr(AR7240_DDR_TAP_CONTROL3, tap_val); + } +#endif + } + + ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE, cycle_val); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_BURST, 0x74444444); + udelay(100); + + ar7240_reg_wr_nf(AR7240_DDR_BURST2, 0x222); + udelay(100); + + ar7240_reg_wr_nf(AR7240_AHB_MASTER_TIMEOUT, 0xfffff); + udelay(100); + +#if (CFG_PLL_FREQ == CFG_PLL_600_500_250) || \ + (CFG_PLL_FREQ == CFG_PLL_500_500_250) + // PMU2 ddr ldo tune + ar7240_reg_rmw_set(0xb8116c44, (0x3 << 19)); + udelay(100); +#endif + + return(type); +} +#endif diff --git a/u-boot/cpu/mips/cache.S b/u-boot/cpu/mips/cache.S new file mode 100755 index 0000000..7bc9d98 --- /dev/null +++ b/u-boot/cpu/mips/cache.S @@ -0,0 +1,435 @@ +/* + * Cache-handling routined for MIPS 4K CPUs + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include + + + /* 64K is the maximum size of instruction and data caches on + * MIPS 24K. + */ +#define MIPS_MAX_CACHE_SIZE 65536 + + +/* + * cacheop macro to automate cache operations + * first some helpers... + */ +#define _mincache(size, maxsize) \ + bltu size,maxsize,9f ; \ + move size,maxsize ; \ +9: + +#define _align(minaddr, maxaddr, linesize) \ + .set noat ; \ + subu AT,linesize,1 ; \ + not AT ; \ + and minaddr,AT ; \ + addu maxaddr,-1 ; \ + and maxaddr,AT ; \ + .set at + +/* general operations */ +#define doop1(op1) \ + cache op1,0(a0) +#define doop2(op1, op2) \ + cache op1,0(a0) ; \ + nop ; \ + cache op2,0(a0) + +/* specials for cache initialisation */ +#define doop1lw(op1) \ + lw zero,0(a0) +#define doop1lw1(op1) \ + cache op1,0(a0) ; \ + lw zero,0(a0) ; \ + cache op1,0(a0) +#define doop121(op1,op2) \ + cache op1,0(a0) ; \ + nop; \ + cache op2,0(a0) ; \ + nop; \ + cache op1,0(a0) + +#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ + .set noreorder ; \ +10: doop##tag##ops ; \ + bne minaddr,maxaddr,10b ; \ + add minaddr,linesize ; \ + .set reorder + +/* finally the cache operation macros */ +#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ + blez n,11f ; \ + addu n,kva ; \ + _align(kva, n, cacheLineSize) ; \ + _oploopn(kva, n, cacheLineSize, tag, ops) ; \ +11: + +#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \ + _mincache(n, cacheSize); \ + blez n,11f ; \ + addu n,kva ; \ + _align(kva, n, cacheLineSize) ; \ + _oploopn(kva, n, cacheLineSize, tag, ops) ; \ +11: + +#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \ + vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + +#define icacheop(kva, n, cacheSize, cacheLineSize, op) \ + icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + + +.globl simple_mips_cache_reset +.ent simple_mips_cache_reset + +simple_mips_cache_reset: + li t2, CFG_ICACHE_SIZE + li t3, CFG_DCACHE_SIZE + li t4, CFG_CACHELINE_SIZE + + mtc0 zero, CP0_TAGLO +#ifdef CONFIG_WASP_SUPPORT + mtc0 zero, $29 # C0_TagHi + mtc0 zero, $28, 2 # C0_DTagLo + mtc0 zero, $29, 2 # C0_DTagHi +#endif + + li t0, K0BASE + add t2, t2, t0 + +_arai_icache_loop: + cache Index_Store_Tag_I, 0(t0) + add t0, t0, t4 + bne t0, t2, _arai_icache_loop + + li t0, K0BASE + add t3, t3, t0 +_arai_dcache_loop: + cache Index_Store_Tag_D, 0(t0) + add t0, t0, t4 + bne t0, t3, _arai_dcache_loop + + j ra + .end simple_mips_cache_reset + + +/******************************************************************************* +* +* mips_cache_reset - low level initialisation of the primary caches +* +* This routine initialises the primary caches to ensure that they +* have good parity. It must be called by the ROM before any cached locations +* are used to prevent the possibility of data with bad parity being written to +* memory. +* To initialise the instruction cache it is essential that a source of data +* with good parity is available. This routine +* will initialise an area of memory starting at location zero to be used as +* a source of parity. +* +* RETURNS: N/A +* +*/ + .globl mips_cache_reset + .ent mips_cache_reset +mips_cache_reset: + + li t2, CFG_ICACHE_SIZE + li t3, CFG_DCACHE_SIZE + li t4, CFG_CACHELINE_SIZE + move t5, t4 + + + li v0, MIPS_MAX_CACHE_SIZE + + /* Now clear that much memory starting from zero. + */ + + li a0, KSEG1 + addu a1, a0, v0 + +2: sw zero, 0(a0) + sw zero, 4(a0) + sw zero, 8(a0) + sw zero, 12(a0) + sw zero, 16(a0) + sw zero, 20(a0) + sw zero, 24(a0) + sw zero, 28(a0) + addu a0, 32 + bltu a0, a1, 2b + + /* Set invalid tag. + */ + mtc0 zero, CP0_TAGLO +#ifdef CONFIG_WASP_SUPPORT + mtc0 zero, $29 # C0_TagHi + mtc0 zero, $28, 2 # C0_DTagLo + mtc0 zero, $29, 2 # C0_DTagHi +#endif + + + /* + * The caches are probably in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */ + + /* Assume bottom of RAM will generate good parity for the cache. + */ + + li a0, K0BASE + move a2, t2 # icacheSize + move a3, t4 # icacheLineSize + move a1, a2 + icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) + + /* To support Orion/R4600, we initialise the data cache in 3 passes. + */ + + /* 1: initialise dcache tags. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + + /* 2: fill dcache. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheopn(a0,a1,a2,a3,1lw,(dummy)) + + + /* 3: clear dcache tags. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + + j ra + .end mips_cache_reset + + +/******************************************************************************* +* +* dcache_status - get cache status +* +* RETURNS: 0 - cache disabled; 1 - cache enabled +* +*/ + .globl dcache_status + .ent dcache_status +dcache_status: + + mfc0 v0, CP0_CONFIG + andi v0, v0, 1 + j ra + + .end dcache_status + +/******************************************************************************* +* +* dcache_disable - disable cache +* +* RETURNS: N/A +* +*/ + .globl dcache_disable + .ent dcache_disable +dcache_disable: + + mfc0 t0, CP0_CONFIG + li t1, -8 + and t0, t0, t1 + ori t0, t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + j ra + + .end dcache_disable + + +/******************************************************************************* +* +* mips_cache_lock - lock RAM area pointed to by a0 in cache. +* +* RETURNS: N/A +* +*/ +#define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE) + .globl mips_cache_lock + .ent mips_cache_lock +mips_cache_lock: + li a1, K0BASE - CACHE_LOCK_SIZE + addu a0, a1 + li a2, CACHE_LOCK_SIZE + li a3, CFG_CACHELINE_SIZE + move a1, a2 + icacheop(a0,a1,a2,a3,0x1d) + + j ra + .end mips_cache_lock + +/***************************************************************************** + * flushes a range in dcache + * a0 = start + * a1 = end + */ + .globl dcache_flush_range + .ent dcache_flush_range +dcache_flush_range: + move t0, a0 + li t1, CFG_CACHELINE_SIZE + move t2, a1 +cache_loop_d_flush_range: + cache Hit_Writeback_Inv_D, 0(t0) + addu t0, t1 + bne t0, t2, cache_loop_d_flush_range + nop + j ra + .end dcache_flush_range + +/**************************************************************************** + * + * mips_cache_flush_all - flushes entire I and D caches. + */ + + .globl mips_cache_flush + .ent mips_cache_flush +mips_cache_flush: + /* Flush caches... + */ + li t0, (CFG_ICACHE_SIZE) + li t1, CFG_CACHELINE_SIZE + li t2, KSEG0 + addu t3, t0, t2 + mtc0 zero, CP0_TAGLO +#ifdef CONFIG_WASP_SUPPORT + mtc0 zero, $29 # C0_TagHi + mtc0 zero, $28, 2 # C0_DTagLo + mtc0 zero, $29, 2 # C0_DTagHi +#endif +cache_loop_flush: + cache Hit_Invalidate_I, 0(t2) + addu t2, t1 + bne t2, t3, cache_loop_flush + nop + + li t0, (CFG_DCACHE_SIZE) + li t1, CFG_CACHELINE_SIZE + li t2, KSEG0 + addu t3, t0, t2 +cache_loop_d_flush: + cache Hit_Writeback_Inv_D, 0(t2) + addu t2, t1 + bne t2, t3, cache_loop_d_flush + nop + j ra + .end mips_cache_flush + +/* + * Invalidate the I-Cache. + * Note:If this is executed from cached address space, + * the cache would still have the addresses of this + * function. + */ + .globl mips_icache_flush_ix + .ent mips_icache_flush_ix + +mips_icache_flush_ix: /* Flush caches Index Invalidate */ + li t0, (CFG_ICACHE_SIZE) + li t1, CFG_CACHELINE_SIZE + li t2, KUSEG + addu t3, t0, t2 + mtc0 zero, CP0_TAGLO +#ifdef CONFIG_WASP_SUPPORT + mtc0 zero, $29 # C0_TagHi + mtc0 zero, $28, 2 # C0_DTagLo + mtc0 zero, $29, 2 # C0_DTagHi +#endif +icache_loop_flush_ix: + cache Index_Invalidate_I, 0(t2) + addu t2, t1 + bne t2, t3, icache_loop_flush_ix + nop + + j ra + .end mips_icache_flush_ix + + + +/********************************************************* + * mips_cache_lock_24k + */ + + .globl mips_cache_lock_24k + .ent mips_cache_lock_24k + +mips_cache_lock_24k: + li t0, 7936 + li t1, CFG_CACHELINE_SIZE + li t2, KSEG0 + addu t3, t0, t2 + mtc0 zero, CP0_TAGLO +#ifdef CONFIG_WASP_SUPPORT + mtc0 zero, $29 # C0_TagHi + mtc0 zero, $28, 2 # C0_DTagLo + mtc0 zero, $29, 2 # C0_DTagHi +#endif +cache_loop_lock: + + li t5, 0xfffff000 + and t4, t2, t5 + ori t4, t4, (1 << 7) + mtc0 t4, CP0_TAGLO +#ifdef CONFIG_WASP_SUPPORT + mtc0 zero, $29 # C0_TagHi + mtc0 zero, $28, 2 # C0_DTagLo + mtc0 zero, $29, 2 # C0_DTagHi +#endif + + cache Index_Load_Tag_D, 0(t2) + cache 0x1d, 0(t2) + addu t2, t1 + bne t2, t3, cache_loop_lock + nop + j ra + .end mips_cache_lock_24k + diff --git a/u-boot/cpu/mips/config.mk b/u-boot/cpu/mips/config.mk new file mode 100755 index 0000000..21728ca --- /dev/null +++ b/u-boot/cpu/mips/config.mk @@ -0,0 +1,48 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +#v=$(shell \ +mips-openwrt-linux-uclibc-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') + +v=22 +MIPSFLAGS=$(shell \ +if [ "$v" -lt "14" ]; then \ + echo "-mcpu=mips32"; \ +else \ + echo "-mips32 -march=mips32 -mtune=mips32"; \ +fi) + +ifndef ENDIANNESS +ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) +ENDIANNESS = -EL +else +ENDIANNESS = -EB +endif +endif + +#PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -g +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic +PLATFORM_CPPFLAGS += -msoft-float +PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib +MIPSFLAGS += $(ENDIANNESS) -fno-schedule-insns -fno-schedule-insns2 + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/u-boot/cpu/mips/cpu.c b/u-boot/cpu/mips/cpu.c new file mode 100755 index 0000000..9126dd6 --- /dev/null +++ b/u-boot/cpu/mips/cpu.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_AR7100) +#include +#include +#endif + +#if defined(CONFIG_AR7240) +#include +#include +#endif + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]){ +#if defined(CONFIG_AR7100) + for(;;){ + ar7100_reg_wr(AR7100_RESET, (AR7100_RESET_FULL_CHIP | AR7100_RESET_DDR)); + } +#elif defined(CONFIG_AR7240) +#ifndef COMPRESSED_UBOOT + fprintf(stdout, "\nResetting the board...\n"); + milisecdelay(500); +#endif /* #ifndef COMPRESSED_UBOOT */ + for(;;){ + #ifdef CONFIG_WASP + if(ar7240_reg_rd(AR7240_REV_ID) & 0xf){ + ar7240_reg_wr(AR7240_RESET, (AR7240_RESET_FULL_CHIP | AR7240_RESET_DDR)); + } else { + /* + * WAR for full chip reset spi vs. boot-rom selection + * bug in wasp 1.0 + */ + ar7240_reg_wr(AR7240_GPIO_OE, ar7240_reg_rd(AR7240_GPIO_OE) & (~(1 << 17))); + } + #else + ar7240_reg_wr(AR7240_RESET, (AR7240_RESET_FULL_CHIP | AR7240_RESET_DDR)); + #endif + } +#endif +#ifndef COMPRESSED_UBOOT + fprintf(stderr, "\n*** ERROR: RESET FAILED! ***\n"); +#endif /* #ifndef COMPRESSED_UBOOT */ + return(0); +} + +extern void dcache_flush_range(u32 a, u32 end); + +void flush_cache(ulong start_addr, ulong size){ + u32 end, a; + + a = start_addr & ~(CFG_CACHELINE_SIZE - 1); + size = (size + CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1); + end = a + size; + + dcache_flush_range(a, end); +} diff --git a/u-boot/cpu/mips/start.S b/u-boot/cpu/mips/start.S new file mode 100755 index 0000000..4e0c66a --- /dev/null +++ b/u-boot/cpu/mips/start.S @@ -0,0 +1,4947 @@ +/* + * Startup Code for MIPS32 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include + +#define ATH_SPI_CLOCK 0xbf000004 + +#define RVECENT(f,n) \ + b f; nop + +#define XVECENT(f,bev) \ + b f ; \ + li k0,bev + + .set noreorder +#ifdef COMPRESSED_UBOOT + .align 4 +#endif + .globl _start + .text +_start: + +#ifndef COMPRESSED_UBOOT + RVECENT(reset,0) /* U-boot entry point */ + RVECENT(reset,1) /* software reboot */ + RVECENT(romReserved,2) + RVECENT(romReserved,3) + RVECENT(romReserved,4) + RVECENT(romReserved,5) + RVECENT(romReserved,6) + RVECENT(romReserved,7) + RVECENT(romReserved,8) + RVECENT(romReserved,9) + RVECENT(romReserved,10) + RVECENT(romReserved,11) + RVECENT(romReserved,12) + RVECENT(romReserved,13) + RVECENT(romReserved,14) + RVECENT(romReserved,15) + RVECENT(romReserved,16) + RVECENT(romReserved,17) + RVECENT(romReserved,18) + RVECENT(romReserved,19) + RVECENT(romReserved,20) + RVECENT(romReserved,21) + RVECENT(romReserved,22) + RVECENT(romReserved,23) + RVECENT(romReserved,24) + RVECENT(romReserved,25) + RVECENT(romReserved,26) + RVECENT(romReserved,27) + RVECENT(romReserved,28) + RVECENT(romReserved,29) + RVECENT(romReserved,30) + RVECENT(romReserved,31) + RVECENT(romReserved,32) + RVECENT(romReserved,33) + RVECENT(romReserved,34) + RVECENT(romReserved,35) + RVECENT(romReserved,36) + RVECENT(romReserved,37) + RVECENT(romReserved,38) + RVECENT(romReserved,39) + RVECENT(romReserved,40) + RVECENT(romReserved,41) + RVECENT(romReserved,42) + RVECENT(romReserved,43) + RVECENT(romReserved,44) + RVECENT(romReserved,45) + RVECENT(romReserved,46) + RVECENT(romReserved,47) + RVECENT(romReserved,48) + RVECENT(romReserved,49) + RVECENT(romReserved,50) + RVECENT(romReserved,51) + RVECENT(romReserved,52) + RVECENT(romReserved,53) + RVECENT(romReserved,54) + RVECENT(romReserved,55) + RVECENT(romReserved,56) + RVECENT(romReserved,57) + RVECENT(romReserved,58) + RVECENT(romReserved,59) + RVECENT(romReserved,60) + RVECENT(romReserved,61) + RVECENT(romReserved,62) + RVECENT(romReserved,63) + XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */ + RVECENT(romReserved,65) + RVECENT(romReserved,66) + RVECENT(romReserved,67) + RVECENT(romReserved,68) + RVECENT(romReserved,69) + RVECENT(romReserved,70) + RVECENT(romReserved,71) + RVECENT(romReserved,72) + RVECENT(romReserved,73) + RVECENT(romReserved,74) + RVECENT(romReserved,75) + RVECENT(romReserved,76) + RVECENT(romReserved,77) + RVECENT(romReserved,78) + RVECENT(romReserved,79) + XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */ + RVECENT(romReserved,81) + RVECENT(romReserved,82) + RVECENT(romReserved,83) + RVECENT(romReserved,84) + RVECENT(romReserved,85) + RVECENT(romReserved,86) + RVECENT(romReserved,87) + RVECENT(romReserved,88) + RVECENT(romReserved,89) + RVECENT(romReserved,90) + RVECENT(romReserved,91) + RVECENT(romReserved,92) + RVECENT(romReserved,93) + RVECENT(romReserved,94) + RVECENT(romReserved,95) + XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */ + RVECENT(romReserved,97) + RVECENT(romReserved,98) + RVECENT(romReserved,99) + RVECENT(romReserved,100) + RVECENT(romReserved,101) + RVECENT(romReserved,102) + RVECENT(romReserved,103) + RVECENT(romReserved,104) + RVECENT(romReserved,105) + RVECENT(romReserved,106) + RVECENT(romReserved,107) + RVECENT(romReserved,108) + RVECENT(romReserved,109) + RVECENT(romReserved,110) + RVECENT(romReserved,111) + XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */ + RVECENT(romReserved,113) + RVECENT(romReserved,114) + RVECENT(romReserved,115) + RVECENT(romReserved,116) + RVECENT(romReserved,116) + RVECENT(romReserved,118) + RVECENT(romReserved,119) + RVECENT(romReserved,120) + RVECENT(romReserved,121) + RVECENT(romReserved,122) + RVECENT(romReserved,123) + RVECENT(romReserved,124) + RVECENT(romReserved,125) + RVECENT(romReserved,126) + RVECENT(romReserved,127) + + /* We hope there are no more reserved vectors! + * 128 * 8 == 1024 == 0x400 + * so this is address R_VEC+0x400 == 0xbfc00400 + */ + + .align 4 +reset: + /* + * Clearing CP0 registers - This is generally required for the MIPS-24k + * core used by Atheros. + */ + mtc0 zero, $0 + mtc0 zero, $1 + mtc0 zero, $2 + mtc0 zero, $3 + mtc0 zero, $4 + mtc0 zero, $5 + mtc0 zero, $6 + mtc0 zero, $7 + mtc0 zero, $8 + mtc0 zero, $9 + mtc0 zero, $10 + mtc0 zero, $11 + li t0, 0x10000004 + mtc0 t0, $12 + mtc0 zero, $13 + mtc0 zero, $14 + mtc0 zero, $15 + mtc0 zero, $16 +#if !defined(CONFIG_WASP_SUPPORT) + mtc0 zero, $17 +#endif + mtc0 zero, $18 + mtc0 zero, $19 +#if !defined(CONFIG_WASP_SUPPORT) + mtc0 zero, $20 + mtc0 zero, $21 + mtc0 zero, $22 +#endif + mtc0 zero, $23 + mtc0 zero, $24 + mtc0 zero, $25 + mtc0 zero, $26 + mtc0 zero, $27 + mtc0 zero, $28 +#ifdef CONFIG_WASP_SUPPORT + mtc0 zero, $29 # C0_TagHi + mtc0 zero, $28, 2 # C0_DTagLo + mtc0 zero, $29, 2 # C0_DTagHi +#endif + + /* + * Clear watch registers. + */ + + mtc0 zero, CP0_WATCHLO + mtc0 zero, CP0_WATCHHI + + /* STATUS register */ + mfc0 k0, CP0_STATUS + li k1, ~ST0_IE + and k0, k1 + mtc0 zero, CP0_CAUSE + mtc0 k0, CP0_STATUS + + /* CAUSE register */ + mtc0 zero, CP0_CAUSE + + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + + /* CONFIG0 register */ + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + +#endif /* #ifndef COMPRESSED_UBOOT */ + + /* Initialize GOT pointer.*/ + bal 1f + nop + .word _GLOBAL_OFFSET_TABLE_ + 1: + move gp, ra + lw t1, 0(ra) + move gp, t1 + +#ifndef COMPRESSED_UBOOT + +#if defined(CONFIG_MACH_HORNET) && defined(CONFIG_HORNET_1_1_WAR) +/**************************************************************************/ +/* + * WAR: Hornet 1.1 currently need a reset once we boot to let the resetb has + * enough time to stable, so that trigger reset at 1st boot, system team + * is investigaing the issue, will remove in short + */ + +do_reset_normal: + + li t7, 0xbd000000 + lw t8, 0(t7) // t8 : value of 0xb8050024 + li t9, 0x12345678 + sw t9, 0(t7) + bne t8, t9, do_reset // if 0xb8050024 == 0x19 , go to do_cpld + nop + b normal_path + +do_reset: + li t7, 0xb806001c // load reset register 0x1806001c + lw t8, 0(t7) + li t9, 0x1000000 // bit24, fullchip reset + or t8, t8, t9 // t8: set bit 18 + sw t8, 0(t7) + +normal_path: +#endif /* CONFIG_MACH_HORNET */ + +/**************************************************************************/ + + /* Initialize any external memory. + */ +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) || defined(CONFIG_ATHEROS) + la t9, lowlevel_init + jalr t9 + nop + nop + +#if defined(CONFIG_MACH_HORNET) + la t9, hornet_ddr_init + jalr t9 + nop + nop +#endif + + la t0, rel_start + j t0 + nop +#endif + +rel_start: + +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) || defined(CONFIG_ATHEROS) + /* REMAP_DISABLE */ + li a0, KSEG1ADDR(ATH_SPI_CLOCK) +#if defined(CONFIG_MACH_QCA955x) + li t0, 0x246 +#elif defined(CONFIG_WASP_SUPPORT) + li t0, 0x243 +#else + li t0, 0x43 +#endif + sw t0, 0(a0) +#endif + + /* Initialize caches... + */ + la t9, simple_mips_cache_reset + jalr t9 + nop + + /* ... and enable them. + */ +#if defined(CONFIG_WASP_SUPPORT) && !defined(CONFIG_ATH_NAND_BR) + li t7, KSEG1ADDR(AR7240_REV_ID) + lw t7, 0(t7) + andi t9, t7, 0xf + bne zero, t9, 1f + nop + + li t0, CONF_CM_UNCACHED + j 2f + nop +#endif + +1: li t0, CONF_CM_CACHABLE_NONCOHERENT +2: mtc0 t0, CP0_CONFIG + +#if !defined(CONFIG_AR7100) && !defined(CONFIG_AR7240) + /* Set up temporary stack. + */ + li a0, CFG_INIT_SP_OFFSET + la t9, mips_cache_lock + jalr t9 + nop +#endif + +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) + la t9, mips_cache_lock_24k + jalr t9 + nop +#endif + +#endif /* #ifndef COMPRESSED_UBOOT */ + +#ifdef CONFIG_WASP_SUPPORT + li t0, 0xbd007000 /* Setup stack in SRAM */ +#else + li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET +#endif + la sp, 0(t0) + + la t9, board_init_f + j t9 + nop + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a0 = addr_sp + * a1 = gd + * a2 = destination address + */ + .globl relocate_code + .ent relocate_code +relocate_code: + move sp, a0 /* Set new stack pointer */ + + li t0, CFG_MONITOR_BASE + la t3, in_ram + lw t2, -12(t3) /* t2 <-- uboot_end_data */ + move t1, a2 + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + */ + move t6, gp + sub gp, CFG_MONITOR_BASE + add gp, a2 /* gp now adjusted */ + sub t6, gp, t6 /* t6 <-- relocation offset */ + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ +1: + lw t3, 0(t0) + sw t3, 0(t1) + addu t0, 4 + ble t0, t2, 1b + addu t1, 4 /* delay slot */ + + /* If caches were enabled, we would have to flush them here. + */ + + /* Jump to where we've relocated ourselves. + */ + addi t0, a2, in_ram - _start + j t0 + nop + + .word uboot_end_data + .word uboot_end + .word num_got_entries + +in_ram: + /* Now we want to update GOT. + */ + lw t3, -4(t0) /* t3 <-- num_got_entries */ + addi t4, gp, 8 /* Skipping first two entries. */ + li t2, 2 +1: + lw t1, 0(t4) + beqz t1, 2f + add t1, t6 + sw t1, 0(t4) +2: + addi t2, 1 + blt t2, t3, 1b + addi t4, 4 /* delay slot */ + + /* Clear BSS. + */ + lw t1, -12(t0) /* t1 <-- uboot_end_data */ + lw t2, -8(t0) /* t2 <-- uboot_end */ + add t1, t6 /* adjust pointers */ + add t2, t6 + + sub t1, 4 +1: addi t1, 4 + bltl t1, t2, 1b + sw zero, 0(t1) /* delay slot */ + + move a0, a1 + la t9, board_init_r + j t9 + move a1, a2 /* delay slot */ + + .end relocate_code + +#if !defined(CONFIG_WASP_SUPPORT) && defined(CONFIG_AR7240) +/* + * void ar7240_ddr_tap_init(void) + * + * This "function" is used to find the tap settings for the DDR + */ + .globl ar7240_ddr_tap_init + .ent ar7240_ddr_tap_init +ar7240_ddr_tap_init: /* { */ + li t1,0x80500000 + li t0,0xffffffff + + sw t0,0x0(t1) + sw t0,0x4(t1) + sw t0,0x8(t1) + sw t0,0xc(t1) + + nop + nop + +ddr_pat_init: + li t0, 0xa0002000 + + li t1, 0x00000000 + sw t1, 0x0(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x10(t0) + nop + + li t1, 0x00000000 + sw t1, 0x14(t0) + nop + + li t1, 0x00000000 + sw t1, 0x18(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x20(t0) + nop + + li t1, 0x00000000 + sw t1, 0x24(t0) + nop + + li t1, 0x00000000 + sw t1, 0x28(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x30(t0) + nop + + li t1, 0x00000000 + sw t1, 0x34(t0) + nop + + li t1, 0x00000000 + sw t1, 0x38(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x44(t0) + nop + + li t1, 0x00000000 + sw t1, 0x48(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x54(t0) + nop + + li t1, 0x00000000 + sw t1, 0x58(t0) + nop + + li t1, 0x00000000 + sw t1, 0x5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x64(t0) + nop + + li t1, 0x00000000 + sw t1, 0x68(t0) + nop + + li t1, 0x00000000 + sw t1, 0x6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x74(t0) + nop + + li t1, 0x00000000 + sw t1, 0x78(t0) + nop + + li t1, 0x00000000 + sw t1, 0x7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x84(t0) + nop + + li t1, 0x00000000 + sw t1, 0x88(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x94(t0) + nop + + li t1, 0x00000000 + sw t1, 0x98(t0) + nop + + li t1, 0x00000000 + sw t1, 0x9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xdc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf8(t0) + nop + + li t1, 0x00000000 + sw t1, 0xfc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x100(t0) + nop + + li t1, 0x00000000 + sw t1, 0x104(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x108(t0) + nop + + li t1, 0x00000000 + sw t1, 0x10c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x110(t0) + nop + + li t1, 0x00000000 + sw t1, 0x114(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x118(t0) + nop + + li t1, 0x00000000 + sw t1, 0x11c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x120(t0) + nop + + li t1, 0x00000000 + sw t1, 0x124(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x128(t0) + nop + + li t1, 0x00000000 + sw t1, 0x12c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x130(t0) + nop + + li t1, 0x00000000 + sw t1, 0x134(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x138(t0) + nop + + li t1, 0x00000000 + sw t1, 0x13c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x140(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x144(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x148(t0) + nop + + li t1, 0x00000000 + sw t1, 0x14c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x150(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x154(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x158(t0) + nop + + li t1, 0x00000000 + sw t1, 0x15c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x160(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x164(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x168(t0) + nop + + li t1, 0x00000000 + sw t1, 0x16c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x170(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x174(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x178(t0) + nop + + li t1, 0x00000000 + sw t1, 0x17c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x180(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x184(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x188(t0) + nop + + li t1, 0x00000000 + sw t1, 0x18c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x190(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x194(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x198(t0) + nop + + li t1, 0x00000000 + sw t1, 0x19c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x1a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x1a4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1a8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x1b4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1b8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1c4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1c8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1d4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1d8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x1e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1e4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1e8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x1f4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x1f8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x1fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x200(t0) + nop + + li t1, 0x00000000 + sw t1, 0x204(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x208(t0) + nop + + li t1, 0x00000000 + sw t1, 0x20c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x210(t0) + nop + + li t1, 0x00000000 + sw t1, 0x214(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x218(t0) + nop + + li t1, 0x00000000 + sw t1, 0x21c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x220(t0) + nop + + li t1, 0x00000000 + sw t1, 0x224(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x228(t0) + nop + + li t1, 0x00000000 + sw t1, 0x22c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x230(t0) + nop + + li t1, 0x00000000 + sw t1, 0x234(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x238(t0) + nop + + li t1, 0x00000000 + sw t1, 0x23c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x240(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x244(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x248(t0) + nop + + li t1, 0x00000000 + sw t1, 0x24c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x250(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x254(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x258(t0) + nop + + li t1, 0x00000000 + sw t1, 0x25c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x260(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x264(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x268(t0) + nop + + li t1, 0x00000000 + sw t1, 0x26c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x270(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x274(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x278(t0) + nop + + li t1, 0x00000000 + sw t1, 0x27c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x280(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x284(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x288(t0) + nop + + li t1, 0x00000000 + sw t1, 0x28c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x290(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x294(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x298(t0) + nop + + li t1, 0x00000000 + sw t1, 0x29c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2a4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2a8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2b4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2b8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2c4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2c8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x2d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2d4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2d8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2e4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2e8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x2f4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x2f8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x2fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x300(t0) + nop + + li t1, 0x00000000 + sw t1, 0x304(t0) + nop + + li t1, 0xffffffff + sw t1, 0x308(t0) + nop + + li t1, 0x00000000 + sw t1, 0x30c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x310(t0) + nop + + li t1, 0x00000000 + sw t1, 0x314(t0) + nop + + li t1, 0xffffffff + sw t1, 0x318(t0) + nop + + li t1, 0x00000000 + sw t1, 0x31c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x320(t0) + nop + + li t1, 0x00000000 + sw t1, 0x324(t0) + nop + + li t1, 0xffffffff + sw t1, 0x328(t0) + nop + + li t1, 0x00000000 + sw t1, 0x32c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x330(t0) + nop + + li t1, 0x00000000 + sw t1, 0x334(t0) + nop + + li t1, 0xffffffff + sw t1, 0x338(t0) + nop + + li t1, 0x00000000 + sw t1, 0x33c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x340(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x344(t0) + nop + + li t1, 0xffffffff + sw t1, 0x348(t0) + nop + + li t1, 0x00000000 + sw t1, 0x34c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x350(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x354(t0) + nop + + li t1, 0xffffffff + sw t1, 0x358(t0) + nop + + li t1, 0x00000000 + sw t1, 0x35c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x360(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x364(t0) + nop + + li t1, 0xffffffff + sw t1, 0x368(t0) + nop + + li t1, 0x00000000 + sw t1, 0x36c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x370(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x374(t0) + nop + + li t1, 0xffffffff + sw t1, 0x378(t0) + nop + + li t1, 0x00000000 + sw t1, 0x37c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x380(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x384(t0) + nop + + li t1, 0xffffffff + sw t1, 0x388(t0) + nop + + li t1, 0x00000000 + sw t1, 0x38c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x390(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x394(t0) + nop + + li t1, 0xffffffff + sw t1, 0x398(t0) + nop + + li t1, 0x00000000 + sw t1, 0x39c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x3a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x3a4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3a8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x3b4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3b8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3c4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3c8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x3d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3d4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3d8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x3e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3e4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3e8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3f4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x3f8(t0) + nop + + li t1, 0x00000000 + sw t1, 0x3fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x400(t0) + nop + + li t1, 0x00000000 + sw t1, 0x404(t0) + nop + + li t1, 0x00000000 + sw t1, 0x408(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x40c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x410(t0) + nop + + li t1, 0x00000000 + sw t1, 0x414(t0) + nop + + li t1, 0x00000000 + sw t1, 0x418(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x41c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x420(t0) + nop + + li t1, 0x00000000 + sw t1, 0x424(t0) + nop + + li t1, 0x00000000 + sw t1, 0x428(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x42c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x430(t0) + nop + + li t1, 0x00000000 + sw t1, 0x434(t0) + nop + + li t1, 0x00000000 + sw t1, 0x438(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x43c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x440(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x444(t0) + nop + + li t1, 0x00000000 + sw t1, 0x448(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x44c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x450(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x454(t0) + nop + + li t1, 0x00000000 + sw t1, 0x458(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x45c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x460(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x464(t0) + nop + + li t1, 0x00000000 + sw t1, 0x468(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x46c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x470(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x474(t0) + nop + + li t1, 0x00000000 + sw t1, 0x478(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x47c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x480(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x484(t0) + nop + + li t1, 0x00000000 + sw t1, 0x488(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x48c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x490(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x494(t0) + nop + + li t1, 0x00000000 + sw t1, 0x498(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x49c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x4a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x4a4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4a8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x4b4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4b8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4c4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4c8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4d4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4d8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x4e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4e4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4e8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x4f4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x4f8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x4fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x500(t0) + nop + + li t1, 0x00000000 + sw t1, 0x504(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x508(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x50c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x510(t0) + nop + + li t1, 0x00000000 + sw t1, 0x514(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x518(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x51c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x520(t0) + nop + + li t1, 0x00000000 + sw t1, 0x524(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x528(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x52c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x530(t0) + nop + + li t1, 0x00000000 + sw t1, 0x534(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x538(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x53c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x540(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x544(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x548(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x54c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x550(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x554(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x558(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x55c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x560(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x564(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x568(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x56c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x570(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x574(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x578(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x57c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x580(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x584(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x588(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x58c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x590(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x594(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x598(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x59c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x5a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x5a4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5a8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x5b4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5b8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x5c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5c4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5c8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5d4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5d8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x5e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5e4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5e8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x5f4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5f8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x5fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x600(t0) + nop + + li t1, 0x00000000 + sw t1, 0x604(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x608(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x60c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x610(t0) + nop + + li t1, 0x00000000 + sw t1, 0x614(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x618(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x61c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x620(t0) + nop + + li t1, 0x00000000 + sw t1, 0x624(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x628(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x62c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x630(t0) + nop + + li t1, 0x00000000 + sw t1, 0x634(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x638(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x63c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x640(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x644(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x648(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x64c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x650(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x654(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x658(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x65c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x660(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x664(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x668(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x66c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x670(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x674(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x678(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x67c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x680(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x684(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x688(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x68c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x690(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x694(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x698(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x69c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6a4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6a8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6b4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6b8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x6c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6c4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6c8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6d4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6d8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6e4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6e8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x6f4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x6f8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x6fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x700(t0) + nop + + li t1, 0x00000000 + sw t1, 0x704(t0) + nop + + li t1, 0xffffffff + sw t1, 0x708(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x70c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x710(t0) + nop + + li t1, 0x00000000 + sw t1, 0x714(t0) + nop + + li t1, 0xffffffff + sw t1, 0x718(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x71c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x720(t0) + nop + + li t1, 0x00000000 + sw t1, 0x724(t0) + nop + + li t1, 0xffffffff + sw t1, 0x728(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x72c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x730(t0) + nop + + li t1, 0x00000000 + sw t1, 0x734(t0) + nop + + li t1, 0xffffffff + sw t1, 0x738(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x73c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x740(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x744(t0) + nop + + li t1, 0xffffffff + sw t1, 0x748(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x74c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x750(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x754(t0) + nop + + li t1, 0xffffffff + sw t1, 0x758(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x75c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x760(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x764(t0) + nop + + li t1, 0xffffffff + sw t1, 0x768(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x76c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x770(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x774(t0) + nop + + li t1, 0xffffffff + sw t1, 0x778(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x77c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x780(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x784(t0) + nop + + li t1, 0xffffffff + sw t1, 0x788(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x78c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x790(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x794(t0) + nop + + li t1, 0xffffffff + sw t1, 0x798(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x79c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x7a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x7a4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7a8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x7b4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7b8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x7c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7c4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7c8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7d4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7d8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x7e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7e4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7e8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7f4(t0) + nop + + li t1, 0xffffffff + sw t1, 0x7f8(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x7fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x800(t0) + nop + + li t1, 0x00000000 + sw t1, 0x804(t0) + nop + + li t1, 0x00000000 + sw t1, 0x808(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x80c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x810(t0) + nop + + li t1, 0x00000000 + sw t1, 0x814(t0) + nop + + li t1, 0x00000000 + sw t1, 0x818(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x81c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x820(t0) + nop + + li t1, 0x00000000 + sw t1, 0x824(t0) + nop + + li t1, 0x00000000 + sw t1, 0x828(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x82c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x830(t0) + nop + + li t1, 0x00000000 + sw t1, 0x834(t0) + nop + + li t1, 0x00000000 + sw t1, 0x838(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x83c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x840(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x844(t0) + nop + + li t1, 0x00000000 + sw t1, 0x848(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x84c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x850(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x854(t0) + nop + + li t1, 0x00000000 + sw t1, 0x858(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x85c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x860(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x864(t0) + nop + + li t1, 0x00000000 + sw t1, 0x868(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x86c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x870(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x874(t0) + nop + + li t1, 0x00000000 + sw t1, 0x878(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x87c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x880(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x884(t0) + nop + + li t1, 0x00000000 + sw t1, 0x888(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x88c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x890(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x894(t0) + nop + + li t1, 0x00000000 + sw t1, 0x898(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x89c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8a4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8a8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8b4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8b8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8c4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8c8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x8d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8d4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8d8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8e4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8e8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x8f4(t0) + nop + + li t1, 0x00000000 + sw t1, 0x8f8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x8fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x900(t0) + nop + + li t1, 0x00000000 + sw t1, 0x904(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x908(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x90c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x910(t0) + nop + + li t1, 0x00000000 + sw t1, 0x914(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x918(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x91c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x920(t0) + nop + + li t1, 0x00000000 + sw t1, 0x924(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x928(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x92c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x930(t0) + nop + + li t1, 0x00000000 + sw t1, 0x934(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x938(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x93c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x940(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x944(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x948(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x94c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x950(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x954(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x958(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x95c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x960(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x964(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x968(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x96c(t0) + nop + + li t1, 0xffffffff + sw t1, 0x970(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x974(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x978(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x97c(t0) + nop + + li t1, 0x00000000 + sw t1, 0x980(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x984(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x988(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x98c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x990(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x994(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x998(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x99c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9a0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9a4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9a8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9ac(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9b0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9b4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9b8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9bc(t0) + nop + + li t1, 0x00000000 + sw t1, 0x9c0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9c4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9c8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9cc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9d0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9d4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9d8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9dc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9e0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9e4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9e8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9ec(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9f0(t0) + nop + + li t1, 0xffffffff + sw t1, 0x9f4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0x9f8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0x9fc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa04(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa08(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa14(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa18(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa24(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa28(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xa30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa34(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa38(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa44(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa48(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa54(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa58(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa64(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa68(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xa70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa74(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa78(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xa80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa84(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa88(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xa90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa94(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa98(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xa9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaa0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaa4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaa8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xab0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xab4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xab8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xabc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xac0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xac4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xac8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xacc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xad0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xad4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xad8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xadc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xae0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xae4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xae8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xaf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xaf4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xaf8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xafc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb04(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb08(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb14(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb18(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb24(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb28(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb34(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb38(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb44(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb48(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb54(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb58(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb64(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb68(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb74(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb78(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xb80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb84(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb88(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xb90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb94(t0) + nop + + li t1, 0xffffffff + sw t1, 0xb98(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xb9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xba0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xba4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xba8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbb4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbb8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xbc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbc4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbc8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbcc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xbd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbd4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbd8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbdc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbe0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbe4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbe8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbf4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xbf8(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xbfc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc04(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc08(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc14(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc18(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xc20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc24(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc28(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc34(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc38(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc44(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc48(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc54(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc58(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xc60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc64(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc68(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc74(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc78(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xc84(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc88(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xc90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xc94(t0) + nop + + li t1, 0x00000000 + sw t1, 0xc98(t0) + nop + + li t1, 0xffffffff + sw t1, 0xc9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xca0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xca4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xca8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xcb4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcb8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcc4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcc8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xccc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xcd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcd4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcd8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcdc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xce0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xce4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xce8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcf4(t0) + nop + + li t1, 0x00000000 + sw t1, 0xcf8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xcfc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd04(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd08(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd14(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd18(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xd20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd24(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd28(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd34(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd38(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd44(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd48(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd54(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd58(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xd60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd64(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd68(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd74(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd78(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xd80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xd84(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd88(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xd94(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xd98(t0) + nop + + li t1, 0xffffffff + sw t1, 0xd9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xda0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xda4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xda8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xdb4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdb8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xdc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdc4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdc8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdcc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdd4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdd8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xddc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xde0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xde4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xde8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdf0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdf4(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xdf8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xdfc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe04(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe08(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe14(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe18(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe24(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe28(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe34(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe38(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe44(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe48(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe54(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe58(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe64(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe68(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe74(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe78(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xe80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe84(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe88(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xe90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe94(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xe98(t0) + nop + + li t1, 0xffffffff + sw t1, 0xe9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xea0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xea4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xea8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xeac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xeb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xeb4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xeb8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xebc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xec0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xec4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xec8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xecc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xed0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xed4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xed8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xedc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xee0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xee4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xee8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xeec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xef0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xef4(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xef8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xefc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf00(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf04(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf08(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf0c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf10(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf14(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf18(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf1c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xf20(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf24(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf28(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf2c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf30(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf34(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf38(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf3c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf40(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf44(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf48(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf4c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf50(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf54(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf58(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf5c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xf60(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf64(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf68(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf6c(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf70(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf74(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf78(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf7c(t0) + nop + + li t1, 0x00000000 + sw t1, 0xf80(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xf84(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf88(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf8c(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xf90(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xf94(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf98(t0) + nop + + li t1, 0xffffffff + sw t1, 0xf9c(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xfa0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xfa4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfa8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfac(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfb0(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xfb4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfb8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfbc(t0) + nop + + li t1, 0x00000000 + sw t1, 0xfc0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfc4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfc8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfcc(t0) + nop + + li t1, 0x0000ffff + sw t1, 0xfd0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfd4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfd8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfdc(t0) + nop + + li t1, 0xffff0000 + sw t1, 0xfe0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfe4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfe8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xfec(t0) + nop + + li t1, 0xffffffff + sw t1, 0xff0(t0) + nop + + li t1, 0xffffffff + sw t1, 0xff4(t0) + nop + + li t1, 0xffffffff + sw t1, 0xff8(t0) + nop + + li t1, 0xffffffff + sw t1, 0xffc(t0) + nop + + +//###### ddr init over ######### + + li a0, 0xa0002000 + li a1, 0x80002000 //### Start address of the pattern 200 + li a2, 0x80003000 //### End Address of the pattern 220 + li t0, 0xb800001c //## Tap settings addr + lw a3, 0x0(t0) //## loading default tap value + nop + ori t0, a3, 0x0 + nop + li t1, 0x1 //# t1=1 indicates increasing tap value, 0 = decreasing + +load_tap: + +# TODO: 0x2 in hornet_ddr_init.S (speed up inicialization) + #li t7, 0x200 //## No. of times read has to happen for 1 tap setting + li t7, 0x2 //## No. of times read has to happen for 1 tap setting + li t8, 0xb8000000 //#### Loading Tap Setting + sw t0, 0x1c(t8) + nop + sw t0, 0x20(t8) + nop + +pat_read: + ori t2, a0, 0x0 + nop + ori t3, a1, 0x0 + nop + ori t4, a2, 0x0 + nop + +tap_addr_loop: + lw t5, 0x0(t2) + nop + lw t6, 0x0(t3) + nop + nop + + bne t5, t6, tap_fail + nop + nop + nop + + addiu t2, t2, 0x4 //#incrementing addr + addiu t3, t3, 0x4 + nop + nop + + bne t3, t4, tap_addr_loop + nop + + addiu t7, t7, -1 + nop + bnez t7, pat_read + nop + nop + + bnez t1, tap_incr + nop + nop + + bnez t0, tap_decr //# t0=0 implies tap=0 works + nop //# so low limit=0, else decrement tap value + nop + li t8, 0x80500000 + sw t0, 0x0(t8) + add t9, t9, t0 //#adding lower limit to upper limit (used to calc mid value) + nop + nop + + b tap_calc + nop + nop + +tap_decr: + addiu t0, t0 , -1 + nop + b load_tap + nop + nop + +tap_incr: + addiu t0, t0 , 0x1 + nop + xori v1, t0, 0x20 + nop + bnez v1, load_tap + nop + nop + b up_limit + nop + nop + +tap_fail: + bnez t1, up_limit + nop + nop + nop + addiu t0, t0, 0x1 + nop + li t8, 0x80500000 + nop + sw t0, 0x0(t8) + add t9, t9, t0 + nop + nop + nop + + b tap_calc + nop + nop + +up_limit: + addiu t0, t0, -1 + li t1, 0x0 //## changing to decreasing tap mode + li t8, 0x80500000 //## storing upper limit + sw t0, 0x4(t8) + ori t9, t0, 0x0 + nop + nop + nop + + ori t0, a3, 0x0 //# loading default tap value + nop + b load_tap + nop + nop + +tap_calc: //## calculating mid value of the tap, storing DQS0, DQS1 in 0x80500008, 0x8050000c resp. + li t7, 0x2 + nop + div t9, t7 + nop + mfhi t6 + mflo t5 + nop + nop + add t6, t6, t5 + li t8, 0x80500000 + nop + sw t5, 0x8(t8) + nop + sw t6, 0xc(t8) + nop + nop + li t8, 0xb8000000 //#### Loading Tap Setting + nop + sw t5, 0x1c(t8) + nop + sw t6, 0x20(t8) + nop + nop + nop + +end: + nop + nop + nop + jr ra + + .end ar7240_ddr_tap_init + +/* } */ +#else + +/* +.globl ath_ddr_tap_cal +.type ath_ddr_tap_cal, @function + +ath_ddr_tap_cal: + + li a0, 0xbd007f00 + sw zero, 0x0(a0) // Place where the tap values are saved and used for SWEEP + sw zero, 0x4(a0) // Place where the number of passing taps are saved. + sw zero, 0x14(a0) // Place where the last pass tap value is stored + li a1, 0xaa55aa55 // Indicates that the First pass tap value is not found + sw a1, 0x10(a0) // Place where the First pass tap value is stored + nop + + li a0, 0xb8060000 // RESET_BASE_ADDRESS + lw a1, 0x1c(a0) // Reading the RST_RESET_ADDRESS + li a2, 0x08000000 // Setting the RST_RESET_RTC_RESET + or a1, a1, a2 + sw a1, 0x1c(a0) + + li a3, 0xffffffff + xor a2, a2, a3 + and a1, a1, a2 + sw a1, 0x1c(a0) // Taking the RTC out of RESET + nop + + li a0, 0xb8107000 // RTC_BASE_ADDRESS + li a1, 0x1 + sw a1, 0x0040(a0) // RTC_SYNC_RESET_ADDRESS + + li a2, 0x2 + +_poll_for_RTC_ON: + lw a1, 0x0044(a0) // RTC_SYNC_STATUS_ADDRESS + and a1, a2, a1 + bne a1, a2, _poll_for_RTC_ON + + +_CHANGE_TAPS: + + li t0, 0xbd007f00 // Read the current value of the TAP for programming + lw t1, 0x0(t0) + li t2, 0x00000000 + or t3, t1, t2 + + + li t0, 0xb8000000 // DDR_BASE_ADDRESS + + sw t3, 0x1c(t0) // TAP_CONTROL_0_ADDRESS + sw t3, 0x20(t0) // TAP_CONTROL_1_ADDRESS + sw t3, 0x24(t0) // TAP_CONTROL_2_ADDRESS + sw t3, 0x28(t0) // TAP_CONTROL_3_ADDRESS + + li t1, 0x00000010 // Running the test 8 times + sw t1, 0x0068(t0) // PERF_COMP_ADDR_1_ADDRESS + + li t1, 0xfa5de83f // 4 Row Address Bits, 4 Column Address Bits, 2 BA bits + sw t1, 0x002c(t0) // PERF_MASK_ADDR_0_ADDRESS + + li t1, 0x545fc332 + sw t1, 0x0070(t0) // PERF_COMP_AHB_GE0_1_ADDRESS + + li t1, 0xaba03ccd + sw t1, 0x0040(t0) // PERF_COMP_AHB_GE1_0_ADDRESS + + li t1, 0x545fc332 + sw t1, 0x0078(t0) // PERF_COMP_AHB_GE1_1_ADDRESS + + li t1, 0xaba03ccd + sw t1, 0x0034(t0) // PERF_MASK_AHB_GE0_0_ADDRESS + + li t1, 0x545fc332 + sw t1, 0x006c(t0) // PERF_MASK_AHB_GE0_1_ADDRESS + + li t1, 0xaba03ccd + sw t1, 0x003c(t0) // PERF_MASK_AHB_GE1_0_ADDRESS + + li t1, 0x545fc332 + sw t1, 0x0074(t0) // PERF_MASK_AHB_GE1_1_ADDRESS + + li t1, 0xaba03ccd + sw t1, 0x0038(t0) // PERF_COMP_AHB_GE0_0_ADDRESS + + li t1, 0x00000001 + sw t1, 0x011c(t0) // DDR_BIST_ADDRESS + + li t2, 0x1 +_bist_done_poll: + lw t1, 0x0120(t0) // DDR_BIST_STATUS_ADDRESS + and t1, t1, t2 + bne t1, t2, _bist_done_poll + + lw t1, 0x0120(t0) // DDR_BIST_STATUS_ADDRESS + li t4, 0x000001fe + and t2, t1, t4 + srl t2, t2, 0x1 // no. of Pass Runs + + li t5, 0x00000000 + sw t5, 0x011c(t0) //DDR_BIST_ADDRESS - Stop the DDR BIST test + + li t5, 0x0001fe00 + and t5, t5, t1 + bnez t5, _iterate_tap // This is a redundant compare but nevertheless - Comparing the FAILS + + lw t1, 0x0068(t0) // PERF_COMP_ADDR_1_ADDRESS + li t3, 0x000001fe + and t3, t3, t1 + srl t3, t3, 0x1 // No. of runs in the config register. + + bne t3, t2, _iterate_tap + +pass_tap: + li t0, 0xbd007f00 + lw t1, 0x4(t0) + addiu t1, t1, 0x1 + sw t1, 0x4(t0) + + li t0, 0xbd007f10 + lw t1, 0x0(t0) + li t2, 0xaa55aa55 + beq t1, t2, _first_pass + nop + li t0, 0xbd007f00 + lw t1, 0x0(t0) + li t0, 0xbd007f10 + sw t1, 0x4(t0) + nop + b _iterate_tap + nop + +_first_pass: + li t0, 0xbd007f00 + lw t1, 0x0(t0) + li t0, 0xbd007f10 + sw t1, 0x0(t0) + sw t1, 0x4(t0) + nop + +_iterate_tap: + + li t0, 0xbd007f00 + lw t1, 0x0(t0) + li t2, 0x1f + beq t1, t2, _STOP_TEST + nop + addiu t1, t1, 0x1 + sw t1, 0x0(t0) + nop + b _CHANGE_TAPS + +_STOP_TEST: + li t0, 0xbd007f00 + lw t1, 0x4(t0) + bnez t1, _load_center_tap + nop + li t3, 0x8 // Default Tap to be used + b _load_tap_into_reg + +_load_center_tap: + li t0, 0xbd007f10 + lw t1, 0x0(t0) + lw t2, 0x4(t0) + add t3, t1, t2 + srl t3, t3, 0x1 + li t4, 0x1f + and t3, t3, t4 + +_load_tap_into_reg: + li t0, 0xb8000000 + sw t3, 0x1c(t0) // TAP_CONTROL_0_ADDRESS + sw t3, 0x20(t0) // TAP_CONTROL_1_ADDRESS + sw t3, 0x24(t0) // TAP_CONTROL_2_ADDRESS + sw t3, 0x28(t0) // TAP_CONTROL_3_ADDRESS + + jr ra + nop +*/ + +#endif + +#ifndef COMPRESSED_UBOOT + /* Exception handlers */ +romReserved: + b romReserved + +romExcHandle: + b romExcHandle +#endif /* #ifndef COMPRESSED_UBOOT */ diff --git a/u-boot/cpu/mips/start_bootstrap.S b/u-boot/cpu/mips/start_bootstrap.S new file mode 100755 index 0000000..1e4b8a7 --- /dev/null +++ b/u-boot/cpu/mips/start_bootstrap.S @@ -0,0 +1,554 @@ +/* + * Startup Code for MIPS32 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include + +#define AR7100_SPI_CLOCK 0xbf000004 + +#ifdef CONFIG_WASP_SUPPORT + #define ATH_APB_BASE 0xB8000000 /* KSEG1ADDR(0x18000000) */ + #define ATH_GPIO_BASE ATH_APB_BASE+0x00040000 + #define ATH_GPIO_OE ATH_GPIO_BASE+0x0 + #define ATH_GPIO_OUT ATH_GPIO_BASE+0x8 + #define ATH_GPIO_OUT_FUNCTION0 ATH_GPIO_BASE+0x2c + #define ATH_GPIO_OUT_FUNCTION1 ATH_GPIO_BASE+0x30 + #define ATH_GPIO_OUT_FUNCTION2 ATH_GPIO_BASE+0x34 + #define ATH_GPIO_OUT_FUNCTION3 ATH_GPIO_BASE+0x38 + #define ATH_GPIO_OUT_FUNCTION4 ATH_GPIO_BASE+0x3c + #define ATH_GPIO_OUT_FUNCTION5 ATH_GPIO_BASE+0x40 +#endif + + +#define RVECENT(f,n) \ + b f; nop + +#define XVECENT(f,bev) \ + b f ; \ + li k0,bev + + .set noreorder + + .globl _start_bootstrap + .text +_start_bootstrap: + RVECENT(reset,0) /* U-boot entry point */ + RVECENT(reset,1) /* software reboot */ + RVECENT(romReserved,2) + RVECENT(romReserved,3) + RVECENT(romReserved,4) + RVECENT(romReserved,5) + RVECENT(romReserved,6) + RVECENT(romReserved,7) + RVECENT(romReserved,8) + RVECENT(romReserved,9) + RVECENT(romReserved,10) + RVECENT(romReserved,11) + RVECENT(romReserved,12) + RVECENT(romReserved,13) + RVECENT(romReserved,14) + RVECENT(romReserved,15) + RVECENT(romReserved,16) + RVECENT(romReserved,17) + RVECENT(romReserved,18) + RVECENT(romReserved,19) + RVECENT(romReserved,20) + RVECENT(romReserved,21) + RVECENT(romReserved,22) + RVECENT(romReserved,23) + RVECENT(romReserved,24) + RVECENT(romReserved,25) + RVECENT(romReserved,26) + RVECENT(romReserved,27) + RVECENT(romReserved,28) + RVECENT(romReserved,29) + RVECENT(romReserved,30) + RVECENT(romReserved,31) + RVECENT(romReserved,32) + RVECENT(romReserved,33) + RVECENT(romReserved,34) + RVECENT(romReserved,35) + RVECENT(romReserved,36) + RVECENT(romReserved,37) + RVECENT(romReserved,38) + RVECENT(romReserved,39) + RVECENT(romReserved,40) + RVECENT(romReserved,41) + RVECENT(romReserved,42) + RVECENT(romReserved,43) + RVECENT(romReserved,44) + RVECENT(romReserved,45) + RVECENT(romReserved,46) + RVECENT(romReserved,47) + RVECENT(romReserved,48) + RVECENT(romReserved,49) + RVECENT(romReserved,50) + RVECENT(romReserved,51) + RVECENT(romReserved,52) + RVECENT(romReserved,53) + RVECENT(romReserved,54) + RVECENT(romReserved,55) + RVECENT(romReserved,56) + RVECENT(romReserved,57) + RVECENT(romReserved,58) + RVECENT(romReserved,59) + RVECENT(romReserved,60) + RVECENT(romReserved,61) + RVECENT(romReserved,62) + RVECENT(romReserved,63) + XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */ + RVECENT(romReserved,65) + RVECENT(romReserved,66) + RVECENT(romReserved,67) + RVECENT(romReserved,68) + RVECENT(romReserved,69) + RVECENT(romReserved,70) + RVECENT(romReserved,71) + RVECENT(romReserved,72) + RVECENT(romReserved,73) + RVECENT(romReserved,74) + RVECENT(romReserved,75) + RVECENT(romReserved,76) + RVECENT(romReserved,77) + RVECENT(romReserved,78) + RVECENT(romReserved,79) + XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */ + RVECENT(romReserved,81) + RVECENT(romReserved,82) + RVECENT(romReserved,83) + RVECENT(romReserved,84) + RVECENT(romReserved,85) + RVECENT(romReserved,86) + RVECENT(romReserved,87) + RVECENT(romReserved,88) + RVECENT(romReserved,89) + RVECENT(romReserved,90) + RVECENT(romReserved,91) + RVECENT(romReserved,92) + RVECENT(romReserved,93) + RVECENT(romReserved,94) + RVECENT(romReserved,95) + XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */ + RVECENT(romReserved,97) + RVECENT(romReserved,98) + RVECENT(romReserved,99) + RVECENT(romReserved,100) + RVECENT(romReserved,101) + RVECENT(romReserved,102) + RVECENT(romReserved,103) + RVECENT(romReserved,104) + RVECENT(romReserved,105) + RVECENT(romReserved,106) + RVECENT(romReserved,107) + RVECENT(romReserved,108) + RVECENT(romReserved,109) + RVECENT(romReserved,110) + RVECENT(romReserved,111) + XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */ + RVECENT(romReserved,113) + RVECENT(romReserved,114) + RVECENT(romReserved,115) + RVECENT(romReserved,116) + RVECENT(romReserved,116) + RVECENT(romReserved,118) + RVECENT(romReserved,119) + RVECENT(romReserved,120) + RVECENT(romReserved,121) + RVECENT(romReserved,122) + RVECENT(romReserved,123) + RVECENT(romReserved,124) + RVECENT(romReserved,125) + RVECENT(romReserved,126) + RVECENT(romReserved,127) + + /* We hope there are no more reserved vectors! + * 128 * 8 == 1024 == 0x400 + * so this is address R_VEC+0x400 == 0xbfc00400 + */ + .align 4 +reset: + +#ifdef CONFIG_WASP_SUPPORT + /* GPIO Init */ + li a1, ATH_GPIO_OE + lw v1, 0(a1) + /* GPIO 11-15 as output */ + li v0, ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11)) + and v1, v1, v0 + /* save GPIO Config Value */ + sw v1, 0(a1) + lw v0, 0(a1) + + /* set gpio funtion for gpio11 */ + li a1, ATH_GPIO_OUT_FUNCTION2 + lw v1, 0(a1) + li v0, 0x00ffffff + and v1, v1, v0 + /* set v1 value to ATH_GPIO_OUT_FUNCTION2 */ + sw v1, 0(a1) + + /* set gpio funtion for gpio12~15 */ + li a1, ATH_GPIO_OUT_FUNCTION3 + lw v1, 0(a1) + li v0, 0x0 + and v1, v1, v0 + /* set v1 value to ATH_GPIO_OUT_FUNCTION3 */ + sw v1, 0(a1) + + /* turn on gpio11-15 */ + li a1, ATH_GPIO_OUT + lw v1, 0(a1) + li v0, ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11)) + and v1, v1, v0 + /* set v1 value to ATH_GPIO_OUT */ + sw v1, 0(a1) + + /* wait for a while, for leds' bootup blink*/ + li a1, 0 + li v1, 0x70000 + +1: + addi a1, a1, 1 + bne a1, v1, 1b + nop + + /* turn off gpio11-15 */ + li a1, ATH_GPIO_OUT + lw v1, 0(a1) + li v0, ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11)) + or v1, v1, v0 + /* set v1 value to ATH_GPIO_OUT */ + sw v1, 0(a1) +#endif + + /* + * Clearing CP0 registers - This is generally required for the MIPS-24k + * core used by Atheros. + */ + mtc0 zero, $0 + mtc0 zero, $1 + mtc0 zero, $2 + mtc0 zero, $3 + mtc0 zero, $4 + mtc0 zero, $5 + mtc0 zero, $6 + mtc0 zero, $7 + mtc0 zero, $8 + mtc0 zero, $9 + mtc0 zero, $10 + mtc0 zero, $11 + li t0, 0x10000004 + mtc0 t0, $12 + mtc0 zero, $13 + mtc0 zero, $14 + mtc0 zero, $15 + mtc0 zero, $16 + mtc0 zero, $17 + mtc0 zero, $18 + mtc0 zero, $19 + mtc0 zero, $20 + mtc0 zero, $21 + mtc0 zero, $22 + mtc0 zero, $23 + mtc0 zero, $24 + mtc0 zero, $25 + mtc0 zero, $26 + mtc0 zero, $27 + mtc0 zero, $28 + +#ifdef CONFIG_WASP_SUPPORT + mtc0 zero, $29 # C0_TagHi + mtc0 zero, $28, 2 # C0_DTagLo + mtc0 zero, $29, 2 # C0_DTagHi +#endif + + /* + * Clear watch registers. + */ + + mtc0 zero, CP0_WATCHLO + mtc0 zero, CP0_WATCHHI + + /* STATUS register */ + mfc0 k0, CP0_STATUS + li k1, ~ST0_IE + and k0, k1 + mtc0 zero, CP0_CAUSE + mtc0 k0, CP0_STATUS + + /* CAUSE register */ + mtc0 zero, CP0_CAUSE + + /* Init Timer */ + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + + /* CONFIG0 register */ + li t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + + + /* Initialize GOT pointer.*/ + bal 1f + nop + .word _GLOBAL_OFFSET_TABLE_ + 1: + move gp, ra + lw t1, 0(ra) + move gp, t1 + +#if defined(CONFIG_MACH_HORNET) && defined(CONFIG_HORNET_1_1_WAR) +/**************************************************************************/ +/* + * WAR: Hornet 1.1 currently need a reset once we boot to let the resetb has + * enough time to stable, so that trigger reset at 1st boot, system team + * is investigaing the issue, will remove in short + */ + +do_reset_normal: + + li t7, 0xbd000000 + lw t8, 0(t7) // t8 : value of 0xbd000000 + li t9, 0x12345678 + bne t8, t9, do_reset // if value of 0xbd000000 != 0x12345678 , go to do_reset + nop + li t9, 0xffffffff + sw t9, 0(t7) + b normal_path + nop + +do_reset: + sw t9, 0(t7) + li t7, 0xb806001c // load reset register 0x1806001c + lw t8, 0(t7) + li t9, 0x1000000 // bit24, fullchip reset + or t8, t8, t9 + sw t8, 0(t7) +do_reset_loop: + b do_reset_loop + nop + +normal_path: +#endif /* CONFIG_MACH_HORNET */ + +/**************************************************************************/ + + /* Initialize any external memory. + */ +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) + la t9, lowlevel_init + jalr t9 + nop + nop + +#if defined(CONFIG_MACH_HORNET) + la t9, hornet_ddr_init + jalr t9 + nop + nop + +#if 0 + la t9, hornet_ddr_tap_init + jalr t9 + nop +#endif + +#endif + + la t0, rel_start + j t0 + nop +#endif + +rel_start: + +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) + /* REMAP_DISABLE */ + // TODO: SPI flash clock? + li a0, AR7100_SPI_CLOCK + li t0, 0x42 // was 0x43 + sw t0, 0(a0) +#endif + +#if defined(CONFIG_AR9100) && defined(CFG_HOWL_1_2) + /* Disable remap for parallel flash */ + li t7, AR9100_FLASH_CONFIG; + lw t8, 0(t7); + li t9, 0xffbf0000; + and t8, t8, t9; + li t9, 0x22fc; + or t8, t8, t9; + li t9, 0xffcfffff; /* scale = 0 */ + and t8, t8, t9; + sw t8, 0(t7); + +#endif + + /* Initialize caches... + */ + la t9, simple_mips_cache_reset + jalr t9 + nop + + /* ... and enable them. + */ + li t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + +#if !defined(CONFIG_AR7100) && !defined(CONFIG_AR7240) + /* Set up temporary stack. + */ + li a0, CFG_INIT_SP_OFFSET + la t9, mips_cache_lock + jalr t9 + nop +#endif + +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) + la t9, mips_cache_lock_24k + jalr t9 + nop +#endif + + li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET + la sp, 0(t0) + + la t9, bootstrap_board_init_f + j t9 + nop + + +/* + * void bootstrap_relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a0 = addr_sp + * a1 = gd + * a2 = destination address + */ + .globl bootstrap_relocate_code + .ent bootstrap_relocate_code +bootstrap_relocate_code: + move sp, a0 /* Set new stack pointer */ + + li t0, BOOTSTRAP_CFG_MONITOR_BASE + la t3, in_ram + lw t2, -12(t3) /* t2 <-- uboot_end_data_bootsrap */ + + /* + * Ideally, following line is not needed. However, + * the behaviour is flaky without it. U-boot boots on + * some boards, and doesn't on some boards. Even on the + * boards it boots, it doesn't boot all the time. + * + * Adding 256k to what needs to be read in actually. + * This introduces some delay that seems to help boot. + */ + li t3, (256 << 10) + + add t2, t3 + move t1, a2 + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - BOOTSTRAP_CFG_MONITOR_BASE) + Destination Address + */ + move t6, gp + sub gp, BOOTSTRAP_CFG_MONITOR_BASE + add gp, a2 /* gp now adjusted */ + sub t6, gp, t6 /* t6 <-- relocation offset */ + + /* + * t0 = source address + * t1 = target address + * t2 = source end address + */ +1: + lw t3, 0(t0) + sw t3, 0(t1) + addu t0, 4 + ble t0, t2, 1b + addu t1, 4 /* delay slot */ + + /* If caches were enabled, we would have to flush them here. + */ + + /* Jump to where we've relocated ourselves. + */ + addi t0, a2, in_ram - _start_bootstrap + j t0 + nop + + .word uboot_end_data_bootstrap + .word uboot_end_bootstrap + .word num_got_entries + +in_ram: + /* Now we want to update GOT. + */ + lw t3, -4(t0) /* t3 <-- num_got_entries */ + addi t4, gp, 8 /* Skipping first two entries. */ + li t2, 2 +1: + lw t1, 0(t4) + beqz t1, 2f + add t1, t6 + sw t1, 0(t4) +2: + addi t2, 1 + blt t2, t3, 1b + addi t4, 4 /* delay slot */ + + /* Clear BSS. + */ + lw t1, -12(t0) /* t1 <-- uboot_end_data_bootstrap */ + lw t2, -8(t0) /* t2 <-- uboot_end_bootstrap */ + add t1, t6 /* adjust pointers */ + add t2, t6 + + sub t1, 4 +1: addi t1, 4 + bltl t1, t2, 1b + sw zero, 0(t1) /* delay slot */ + + move a0, a1 + la t9, bootstrap_board_init_r + j t9 + move a1, a2 /* delay slot */ + + .end bootstrap_relocate_code + + /* Exception handlers. + */ +romReserved: + b romReserved + +romExcHandle: + b romExcHandle diff --git a/u-boot/drivers/Makefile b/u-boot/drivers/Makefile new file mode 100755 index 0000000..0e7a71c --- /dev/null +++ b/u-boot/drivers/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libdrivers.a + +OBJS = netconsole.o \ + pci.o + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/drivers/netconsole.c b/u-boot/drivers/netconsole.c new file mode 100755 index 0000000..f24ac54 --- /dev/null +++ b/u-boot/drivers/netconsole.c @@ -0,0 +1,298 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CONFIG_NETCONSOLE +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static char input_buffer[512]; +static int input_size = 0; /* char count in input buffer */ +static int input_offset = 0; /* offset to valid chars in input buffer */ +static int input_recursion = 0; +static int output_recursion = 0; +static int net_timeout; +static uchar nc_ether[6]; /* server enet address */ +static IPaddr_t nc_ip; /* server ip */ +static short nc_port; /* source/target port */ +static const char *output_packet; /* used by first send udp */ +static int output_packet_len = 0; + +/* + * Start with a default last protocol. + * We are only interested in NETCONS or not. + */ +proto_t net_loop_last_protocol = BOOTP; + +static void nc_wait_arp_handler(uchar * pkt, unsigned dest, unsigned src, unsigned len){ + NetState = NETLOOP_SUCCESS; /* got arp reply - quit net loop */ +} + +static void nc_handler(uchar * pkt, unsigned dest, unsigned src, unsigned len){ + if(input_size){ /* got input - quit net loop */ + NetState = NETLOOP_SUCCESS; + } +} + +static void nc_timeout(void){ + NetState = NETLOOP_SUCCESS; +} + +void NcStart(void){ + if(!output_packet_len || memcmp(nc_ether, NetEtherNullAddr, 6)){ + /* going to check for input packet */ + NetSetHandler(nc_handler); + NetSetTimeout(net_timeout, nc_timeout); + } else { + /* send arp request */ + uchar *pkt; + NetSetHandler(nc_wait_arp_handler); + pkt = (uchar *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE; + memcpy(pkt, output_packet, output_packet_len); + NetSendUDPPacket(nc_ether, nc_ip, nc_port, nc_port, output_packet_len); + } +} + +int nc_input_packet(uchar * pkt, unsigned dest, unsigned src, unsigned len){ + int end, chunk; + + if(dest != nc_port || !len){ /* not for us */ + return(0); + } + + if(input_size == sizeof(input_buffer)){ /* no space */ + return(1); + } + + if(len > sizeof input_buffer - input_size){ + len = sizeof input_buffer - input_size; + } + + end = input_offset + input_size; + + if(end > sizeof input_buffer){ + end -= sizeof input_buffer; + } + + chunk = len; + + if(end + len > sizeof input_buffer){ + chunk = sizeof input_buffer - end; + memcpy(input_buffer, pkt + chunk, len - chunk); + } + + memcpy(input_buffer + end, pkt, chunk); + + input_size += len; + + return(1); +} + +static void nc_send_packet(const char *buf, int len){ + struct eth_device *eth; + int inited = 0; + uchar *pkt; + uchar *ether; + IPaddr_t ip; + + if((eth = eth_get_dev()) == NULL){ + return; + } + + if(!memcmp(nc_ether, NetEtherNullAddr, 6)){ + if(eth->state == ETH_STATE_ACTIVE){ + return; + } + + output_packet = buf; + output_packet_len = len; + NetLoop(NETCONS); /* wait for arp reply and send packet */ + output_packet_len = 0; + + return; + } + + if(eth->state != ETH_STATE_ACTIVE){ + if(eth_is_on_demand_init()){ + if(eth_init(gd->bd) < 0){ + return; + } + eth_set_last_protocol(NETCONS); + } else { + eth_init_state_only(gd->bd); + } + + inited = 1; + } + + pkt = (uchar *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE; + memcpy(pkt, buf, len); + ether = nc_ether; + ip = nc_ip; + NetSendUDPPacket(ether, ip, nc_port, nc_port, len); + + if(inited){ + if(eth_is_on_demand_init()){ + eth_halt(); + } else { + eth_halt_state_only(); + } + } +} + +int nc_start(void){ + int netmask, our_ip; + char *p; + + p = getenv("ncport"); + nc_port = p ? (short)simple_strtol(p, NULL, 10) : 6666; /* default NetConsole port */ + + if(getenv("serverip")){ + + nc_ip = getenv_IPaddr("serverip"); + + if(!nc_ip){ + return(-1); + } + + } else { + nc_ip = ~0; /* ncip is not set */ + } + + our_ip = getenv_IPaddr("ipaddr"); + netmask = getenv_IPaddr("netmask"); + + if(nc_ip == ~0 || /* 255.255.255.255 */ + ((netmask & our_ip) == (netmask & nc_ip) && /* on the same net */ + (netmask | nc_ip) == ~0)) /* broadcast to our net */{ + memset(nc_ether, 0xff, sizeof nc_ether); + } else { + memset(nc_ether, 0, sizeof nc_ether); /* force arp request */ + } + + return(0); +} + +void nc_putc(char c){ + if(output_recursion){ + return; + } + + output_recursion = 1; + + nc_send_packet(&c, 1); + + output_recursion = 0; +} + +void nc_puts(const char *s){ + int len; + + if(output_recursion){ + return; + } + + output_recursion = 1; + + if((len = strlen(s)) > 512){ + len = 512; + } + + nc_send_packet(s, len); + + output_recursion = 0; +} + +int nc_getc(void){ + uchar c; + + input_recursion = 1; + + net_timeout = 0; /* no timeout */ + while(!input_size){ + NetLoop(NETCONS); + } + + input_recursion = 0; + + c = input_buffer[input_offset++]; + + if(input_offset >= sizeof input_buffer){ + input_offset -= sizeof input_buffer; + } + + input_size--; + + return(c); +} + +int nc_tstc(void){ + struct eth_device *eth; + + if(input_recursion){ + return(0); + } + + if(input_size){ + return(1); + } + + eth = eth_get_dev(); + + if(eth && eth->state == ETH_STATE_ACTIVE){ + return(0); /* inside net loop */ + } + + input_recursion = 1; + + net_timeout = 1; + NetLoop(NETCONS); /* kind of poll */ + + input_recursion = 0; + + return(input_size != 0); +} + +int drv_nc_init(void){ + device_t dev; + int rc; + + memset(&dev, 0, sizeof(dev)); + + strcpy(dev.name, "nc"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.start = nc_start; + dev.putc = nc_putc; + dev.puts = nc_puts; + dev.getc = nc_getc; + dev.tstc = nc_tstc; + + rc = device_register(&dev); + + return((rc == 0) ? 1 : rc); +} + +#endif /* CONFIG_NETCONSOLE */ diff --git a/u-boot/drivers/pci.c b/u-boot/drivers/pci.c new file mode 100755 index 0000000..e31c332 --- /dev/null +++ b/u-boot/drivers/pci.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002, 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI routines + */ +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include + +void pci_init(void) { +#if defined(CONFIG_PCI_BOOTDELAY) + char *s; + int i; + + /* wait "pcidelay" ms (if defined)... */ + s = getenv ("pcidelay"); + + if (s) { + int val = simple_strtoul(s, NULL, 10); + + for (i = 0; i < val; i++){ + udelay (1000); + } + } +#endif /* CONFIG_PCI_BOOTDELAY */ + + /* now call board specific pci_init()... */ + pci_init_board(); +} + +#endif /* CONFIG_PCI */ diff --git a/u-boot/httpd/Makefile b/u-boot/httpd/Makefile new file mode 100755 index 0000000..738f67c --- /dev/null +++ b/u-boot/httpd/Makefile @@ -0,0 +1,30 @@ +# +# Makefile for http stuff +# + +#include $(TOPDIR)/config.mk + +CFLAGS += -I../include -I../httpd + +LIB = libhttpd.a + +OBJS += uip.o uip_arch.o uip_arp.o httpd.o fs.o + +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + + +#%.o: +# $(CC) $(CFLAGS) -c $(<:.o=.c) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### + diff --git a/u-boot/httpd/fs.c b/u-boot/httpd/fs.c new file mode 100755 index 0000000..87e394b --- /dev/null +++ b/u-boot/httpd/fs.c @@ -0,0 +1,154 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server read-only file system code. + * \author Adam Dunkels + * + * A simple read-only filesystem. + */ + +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fs.c,v 1.7.2.3 2003/10/07 13:22:27 adam Exp $ + */ + +#include "uip.h" +#include "httpd.h" +#include "fs.h" +#include "fsdata.h" + +#include "fsdata.c" + +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +static u16_t count[FS_NUMFILES]; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + +/*-----------------------------------------------------------------------------------*/ +static u8_t +fs_strcmp(const char *str1, const char *str2) +{ + u8_t i; + i = 0; + loop: + + if(str2[i] == 0 || + str1[i] == '\r' || + str1[i] == '\n') { + return 0; + } + + if(str1[i] != str2[i]) { + return 1; + } + + + ++i; + goto loop; +} +/*-----------------------------------------------------------------------------------*/ +int +fs_open(const char *name, struct fs_file *file) +{ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t i = 0; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + struct fsdata_file_noconst *f; + + for(f = (struct fsdata_file_noconst *)FS_ROOT; + f != NULL; + f = (struct fsdata_file_noconst *)f->next) { + + if(fs_strcmp(name, f->name) == 0) { + file->data = f->data; + file->len = f->len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + ++count[i]; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + return 1; + } +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + ++i; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + + } + return 0; +} +/*-----------------------------------------------------------------------------------*/ +void +fs_init(void) +{ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t i; + for(i = 0; i < FS_NUMFILES; i++) { + count[i] = 0; + } +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +} +/*-----------------------------------------------------------------------------------*/ +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +u16_t fs_count +(char *name) +{ + struct fsdata_file_noconst *f; + u16_t i; + + i = 0; + for(f = (struct fsdata_file_noconst *)FS_ROOT; + f != NULL; + f = (struct fsdata_file_noconst *)f->next) { + + if(fs_strcmp(name, f->name) == 0) { + return count[i]; + } + ++i; + } + return 0; +} +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +/*-----------------------------------------------------------------------------------*/ diff --git a/u-boot/httpd/fs.h b/u-boot/httpd/fs.h new file mode 100755 index 0000000..2d9693b --- /dev/null +++ b/u-boot/httpd/fs.h @@ -0,0 +1,80 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server read-only file system header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $ + */ +#ifndef __FS_H__ +#define __FS_H__ + +#include "uip.h" + +/** + * An open file in the read-only file system. + */ +struct fs_file { + char *data; /**< The actual file data. */ + int len; /**< The length of the file data. */ +}; + +/** + * Open a file in the read-only file system. + * + * \param name The name of the file. + * + * \param file The file pointer, which must be allocated by caller and + * will be filled in by the function. + */ +int fs_open(const char *name, struct fs_file *file); + +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 +u16_t fs_count(char *name); +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ + +/** + * Initialize the read-only file system. + */ +void fs_init(void); + +#endif /* __FS_H__ */ diff --git a/u-boot/httpd/fsdata.c b/u-boot/httpd/fsdata.c new file mode 100755 index 0000000..dd307cf --- /dev/null +++ b/u-boot/httpd/fsdata.c @@ -0,0 +1,671 @@ +static const char data_fail_html[] = { +0x48, 0x54, 0x54, 0x50, 0x2F, 0x31, 0x2E, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4F, 0x4B, /* HTTP/1.0 200 OK */ +0x0D, 0x0A, /* CR LF */ +0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3A, 0x20, 0x75, 0x49, 0x50, 0x2F, 0x30, 0x2E, 0x39, /* Server: uIP/0.9 */ +0x0D, 0x0A, /* CR LF */ +0x43, 0x6F, 0x6E, 0x74, 0x65, 0x6E, 0x74, 0x2D, 0x74, 0x79, 0x70, 0x65, 0x3A, 0x20, 0x74, 0x65, /* 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0x64, 0x64, 0x7B, 0x6D, 0x61, 0x72, 0x67, +0x69, 0x6E, 0x2D, 0x72, 0x69, 0x67, 0x68, 0x74, 0x3A, 0x33, 0x30, 0x70, 0x78, 0x7D, 0 }; + +const struct fsdata_file file_fail_html[] = {{ + NULL, + "/fail.html", + data_fail_html, + (int) sizeof(data_fail_html) - 1 +}}; + +const struct fsdata_file file_flashing_html[] = {{ + file_fail_html, + "/flashing.html", + data_flashing_html, + (int) sizeof(data_flashing_html) - 1 +}}; + +const struct fsdata_file file_uboot_html[] = {{ + file_flashing_html, + "/uboot.html", + data_uboot_html, + (int) sizeof(data_uboot_html) - 1 +}}; + +const struct fsdata_file file_art_html[] = {{ + file_uboot_html, + "/art.html", + data_art_html, + (int) sizeof(data_art_html) - 1 +}}; + +const struct fsdata_file file_index_html[] = {{ + file_art_html, + "/index.html", + data_index_html, + (int) sizeof(data_index_html) - 1 +}}; + +const struct fsdata_file file_404_html[] = {{ + file_index_html, + "/404.html", + data_404_html, + (int) sizeof(data_404_html) - 1 +}}; + +const struct fsdata_file file_style_css[] = {{ + file_404_html, + "/style.css", + data_style_css, + (int) sizeof(data_style_css) - 1 +}}; + +#define FS_ROOT file_style_css +#define FS_NUMFILES 7 diff --git a/u-boot/httpd/fsdata.h b/u-boot/httpd/fsdata.h new file mode 100755 index 0000000..e525f4e --- /dev/null +++ b/u-boot/httpd/fsdata.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * $Id: fsdata.h,v 1.4.2.1 2003/10/04 22:54:06 adam Exp $ + */ +#ifndef __FSDATA_H__ +#define __FSDATA_H__ + +#include "uipopt.h" + +struct fsdata_file { + const struct fsdata_file *next; + const char *name; + const char *data; + const int len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t count; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +}; + +struct fsdata_file_noconst { + struct fsdata_file *next; + char *name; + char *data; + int len; +#ifdef FS_STATISTICS +#if FS_STATISTICS == 1 + u16_t count; +#endif /* FS_STATISTICS */ +#endif /* FS_STATISTICS */ +}; + +#endif /* __FSDATA_H__ */ diff --git a/u-boot/httpd/httpd.c b/u-boot/httpd/httpd.c new file mode 100755 index 0000000..7d3d803 --- /dev/null +++ b/u-boot/httpd/httpd.c @@ -0,0 +1,590 @@ +#include "uip.h" +#include "httpd.h" +#include "fs.h" +#include "fsdata.h" + +#define STATE_NONE 0 // empty state (waiting for request...) +#define STATE_FILE_REQUEST 1 // remote host sent GET request +#define STATE_UPLOAD_REQUEST 2 // remote host sent POST request + +// ASCII characters +#define ISO_G 0x47 // GET +#define ISO_E 0x45 +#define ISO_T 0x54 +#define ISO_P 0x50 // POST +#define ISO_O 0x4f +#define ISO_S 0x53 +#define ISO_T 0x54 +#define ISO_slash 0x2f // control and other characters +#define ISO_space 0x20 +#define ISO_nl 0x0a +#define ISO_cr 0x0d +#define ISO_tab 0x09 + +// we use this so that we can do without the ctype library +#define is_digit(c) ((c) >= '0' && (c) <= '9') + +// debug +//#define DEBUG_UIP + +// html files +extern const struct fsdata_file file_index_html; +extern const struct fsdata_file file_404_html; +extern const struct fsdata_file file_flashing_html; +extern const struct fsdata_file file_fail_html; + +extern int webfailsafe_ready_for_upgrade; +extern int webfailsafe_upgrade_type; +extern ulong NetBootFileXferSize; +extern unsigned char *webfailsafe_data_pointer; + +extern flash_info_t flash_info[]; + +// http app state +struct httpd_state *hs; + +static int webfailsafe_post_done = 0; +static int webfailsafe_upload_failed = 0; +static int data_start_found = 0; + +static unsigned char post_packet_counter = 0; + +// 0x0D -> CR 0x0A -> LF +static char eol[3] = { 0x0d, 0x0a, 0x00 }; +static char eol2[5] = { 0x0d, 0x0a, 0x0d, 0x0a, 0x00 }; + +static char *boundary_value; + +// str to int +static int atoi(const char *s){ + int i = 0; + + while(is_digit(*s)){ + i = i * 10 + *(s++) - '0'; + } + + return(i); +} + +// print downloading progress +static void httpd_download_progress(void){ + if(post_packet_counter == 39){ + puts("\n "); + post_packet_counter = 0; + } + + puts("#"); + post_packet_counter++; +} + +// http server init +void httpd_init(void){ + fs_init(); + uip_listen(HTONS(80)); +} + +// reset app state +static void httpd_state_reset(void){ + hs->state = STATE_NONE; + hs->count = 0; + hs->dataptr = 0; + hs->upload = 0; + hs->upload_total = 0; + + data_start_found = 0; + post_packet_counter = 0; + + if(boundary_value){ + free(boundary_value); + } +} + +// find and get first chunk of data +static int httpd_findandstore_firstchunk(void){ + char *start = NULL; + char *end = NULL; + flash_info_t *info = &flash_info[0]; + + if(!boundary_value){ + return(0); + } + + // chek if we have data in packet + start = (char *)strstr((char *)uip_appdata, (char *)boundary_value); + + if(start){ + + // ok, we have data in this packet! + // find upgrade type + + end = (char *)strstr((char *)start, "name=\"firmware\""); + + if(end){ + + printf("Upgrade type: firmware\n"); + webfailsafe_upgrade_type = WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE; + + } else { + + end = (char *)strstr((char *)start, "name=\"uboot\""); + + if(end){ + + webfailsafe_upgrade_type = WEBFAILSAFE_UPGRADE_TYPE_UBOOT; + printf("Upgrade type: U-Boot\n"); + + } else { + + end = (char *)strstr((char *)start, "name=\"art\""); + + if(end){ + + printf("Upgrade type: ART\n"); + webfailsafe_upgrade_type = WEBFAILSAFE_UPGRADE_TYPE_ART; + + // check if have known flash type + if(info->flash_id == FLASH_CUSTOM){ + printf("## Error: unknown flash type, can't update ART!\n"); + webfailsafe_upload_failed = 1; + } + + } else { + + printf("## Error: input name not found!\n"); + return(0); + + } + + } + + } + + end = NULL; + + // find start position of the data! + end = (char *)strstr((char *)start, eol2); + + if(end){ + + if((end - (char *)uip_appdata) < uip_len){ + + // move pointer over CR LF CR LF + end += 4; + + // how much data we expect? + // last part (magic value 6): [CR][LF](boundary length)[-][-][CR][LF] + hs->upload_total = hs->upload_total - (int)(end - start) - strlen(boundary_value) - 6; + + printf("Upload file size: %d bytes\n", hs->upload_total); + + // We need to check if file which we are going to download + // has correct size (for every type of upgrade) + + // U-Boot + if((webfailsafe_upgrade_type == WEBFAILSAFE_UPGRADE_TYPE_UBOOT) && (hs->upload_total != WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES)){ + + printf("## Error: wrong file size, should be: %d bytes!\n", WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES); + webfailsafe_upload_failed = 1; + + // ART + } else if((webfailsafe_upgrade_type == WEBFAILSAFE_UPGRADE_TYPE_ART) && (hs->upload_total != WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES)){ + + printf("## Error: wrong file size, should be: %d bytes!\n", WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES); + webfailsafe_upload_failed = 1; + + // firmware can't exceed: (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES) + } else if(hs->upload_total > (info->size - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)){ + + printf("## Error: file too big!\n"); + webfailsafe_upload_failed = 1; + + } + + printf("Loading: "); + + // how much data we are storing now? + hs->upload = (unsigned int)(uip_len - (end - (char *)uip_appdata)); + + memcpy((void *)webfailsafe_data_pointer, (void *)end, hs->upload); + webfailsafe_data_pointer += hs->upload; + + httpd_download_progress(); + + return(1); + + } + + } else { + printf("## Error: couldn't find start of data!\n"); + } + + } + + return(0); +} + +// called for http server app +void httpd_appcall(void){ + struct fs_file fsfile; + unsigned int i; + + switch(uip_conn->lport){ + + case HTONS(80): + + // app state + hs = (struct httpd_state *)(uip_conn->appstate); + + // closed connection + if(uip_closed()){ + httpd_state_reset(); + uip_close(); + return; + } + + // aborted connection or time out occured + if(uip_aborted() || uip_timedout()){ + httpd_state_reset(); + uip_abort(); + return; + } + + // if we are pooled + if(uip_poll()){ + if(hs->count++ >= 100){ + httpd_state_reset(); + uip_abort(); + } + return; + } + + // new connection + if(uip_connected()){ + httpd_state_reset(); + return; + } + + // new data in STATE_NONE + if(uip_newdata() && hs->state == STATE_NONE){ + + // GET or POST request? + if(uip_appdata[0] == ISO_G && uip_appdata[1] == ISO_E && uip_appdata[2] == ISO_T && (uip_appdata[3] == ISO_space || uip_appdata[3] == ISO_tab)){ + hs->state = STATE_FILE_REQUEST; + } else if(uip_appdata[0] == ISO_P && uip_appdata[1] == ISO_O && uip_appdata[2] == ISO_S && uip_appdata[3] == ISO_T && (uip_appdata[4] == ISO_space || uip_appdata[4] == ISO_tab)){ + hs->state = STATE_UPLOAD_REQUEST; + } + + // anything else -> abort the connection! + if(hs->state == STATE_NONE){ + httpd_state_reset(); + uip_abort(); + return; + } + + // get file or firmware upload? + if(hs->state == STATE_FILE_REQUEST){ + + // we are looking for GET file name + for(i = 4; i < 30; i++){ + if(uip_appdata[i] == ISO_space || uip_appdata[i] == ISO_cr || uip_appdata[i] == ISO_nl || uip_appdata[i] == ISO_tab){ + uip_appdata[i] = 0; + i = 0; + break; + } + } + + if(i != 0){ + printf("## Error: request file name too long!\n"); + httpd_state_reset(); + uip_abort(); + return; + } + + printf("Request for: "); + printf("%s\n", &uip_appdata[4]); + + // request for / + if(uip_appdata[4] == ISO_slash && uip_appdata[5] == 0){ + fs_open(file_index_html.name, &fsfile); + } else { + // check if we have requested file + if(!fs_open((const char *)&uip_appdata[4], &fsfile)){ + printf("## Error: file not found!\n"); + fs_open(file_404_html.name, &fsfile); + } + } + + hs->state = STATE_FILE_REQUEST; + hs->dataptr = (u8_t *)fsfile.data; + hs->upload = fsfile.len; + + // send first (and maybe the last) chunk of data + uip_send(hs->dataptr, (hs->upload > uip_mss() ? uip_mss() : hs->upload)); + return; + + } else if(hs->state == STATE_UPLOAD_REQUEST){ + + char *start = NULL; + char *end = NULL; + + // end bufor data with NULL + uip_appdata[uip_len] = '\0'; + + /* + * We got first packet with POST request + * + * Some browsers don't include first chunk of data in the first + * POST request packet (like Google Chrome, IE and Safari)! + * So we must now find two values: + * - Content-Length + * - boundary + * Headers with these values can be in any order! + * If we don't find these values in first packet, connection will be aborted! + * + */ + + // Content-Length pos + start = (char *)strstr((char*)uip_appdata, "Content-Length:"); + + if(start){ + + start += sizeof("Content-Length:"); + + // find end of the line with "Content-Length:" + end = (char *)strstr(start, eol); + + if(end){ + + hs->upload_total = atoi(start); +#ifdef DEBUG_UIP + printf("Expecting %d bytes in body request message\n", hs->upload_total); +#endif + + } else { + printf("## Error: couldn't find \"Content-Length\"!\n"); + httpd_state_reset(); + uip_abort(); + return; + } + + } else { + printf("## Error: couldn't find \"Content-Length\"!\n"); + httpd_state_reset(); + uip_abort(); + return; + } + + // we don't support very small files (< 10 KB) + if(hs->upload_total < 10240){ + printf("## Error: request for upload < 10 KB data!\n"); + httpd_state_reset(); + uip_abort(); + return; + } + + // boundary value + start = NULL; + end = NULL; + + start = (char *)strstr((char *)uip_appdata, "boundary="); + + if(start){ + + // move pointer over "boundary=" + start += 9; + + // find end of line with boundary value + end = (char *)strstr((char *)start, eol); + + if(end){ + + // malloc space for boundary value + '--' and '\0' + boundary_value = (char*)malloc(end - start + 3); + + if(boundary_value){ + + memcpy(&boundary_value[2], start, end - start); + + // add -- at the begin and 0 at the end + boundary_value[0] = '-'; + boundary_value[1] = '-'; + boundary_value[end - start + 2] = 0; + +#ifdef DEBUG_UIP + printf("Found boundary value: \"%s\"\n", boundary_value); +#endif + + } else { + printf("## Error: couldn't allocate memory for boundary!\n"); + httpd_state_reset(); + uip_abort(); + return; + } + + } else { + printf("## Error: couldn't find boundary!\n"); + httpd_state_reset(); + uip_abort(); + return; + } + + } else { + printf("## Error: couldn't find boundary!\n"); + httpd_state_reset(); + uip_abort(); + return; + } + + /* + * OK, if we are here, it means that we found + * Content-Length and boundary values in headers + * + * We can now try to 'allocate memory' and + * find beginning of the data in first packet + */ + + webfailsafe_data_pointer = (u8_t *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS; + + if(!webfailsafe_data_pointer){ + printf("## Error: couldn't allocate RAM for data!\n"); + httpd_state_reset(); + uip_abort(); + return; + } else { + printf("Data will be downloaded at 0x%X in RAM\n", WEBFAILSAFE_UPLOAD_RAM_ADDRESS); + } + + if(httpd_findandstore_firstchunk()){ + data_start_found = 1; + } else { + data_start_found = 0; + } + + return; + + } /* else if(hs->state == STATE_UPLOAD_REQUEST) */ + + } /* uip_newdata() && hs->state == STATE_NONE */ + + // if we got ACK from remote host + if(uip_acked()){ + + // if we are in STATE_FILE_REQUEST state + if(hs->state == STATE_FILE_REQUEST){ + + // data which we send last time was received (we got ACK) + // if we send everything last time -> gently close the connection + if(hs->upload <= uip_mss()){ + + // post upload completed? + if(webfailsafe_post_done){ + + if(!webfailsafe_upload_failed){ + webfailsafe_ready_for_upgrade = 1; + } + + webfailsafe_post_done = 0; + webfailsafe_upload_failed = 0; + } + + httpd_state_reset(); + uip_close(); + return; + } + + // otherwise, send another chunk of data + // last time we sent uip_conn->len size of data + hs->dataptr += uip_conn->len; + hs->upload -= uip_conn->len; + + uip_send(hs->dataptr, (hs->upload > uip_mss() ? uip_mss() : hs->upload)); + } + + return; + + } + + // if we need to retransmit + if(uip_rexmit()){ + + // if we are in STATE_FILE_REQUEST state + if(hs->state == STATE_FILE_REQUEST){ + // send again chunk of data without changing pointer and length of data left to send + uip_send(hs->dataptr, (hs->upload > uip_mss() ? uip_mss() : hs->upload)); + } + + return; + + } + + // if we got new data frome remote host + if(uip_newdata()){ + + // if we are in STATE_UPLOAD_REQUEST state + if(hs->state == STATE_UPLOAD_REQUEST){ + + // end bufor data with NULL + uip_appdata[uip_len] = '\0'; + + // do we have to find start of data? + if(!data_start_found){ + + if(!httpd_findandstore_firstchunk()){ + printf("## Error: couldn't find start of data in next packet!\n"); + httpd_state_reset(); + uip_abort(); + return; + } else { + data_start_found = 1; + } + + return; + } + + hs->upload += (unsigned int)uip_len; + + if(!webfailsafe_upload_failed){ + memcpy((void *)webfailsafe_data_pointer, (void *)uip_appdata, uip_len); + webfailsafe_data_pointer += uip_len; + } + + httpd_download_progress(); + + // if we have collected all data + if(hs->upload >= hs->upload_total){ + + printf("\n\n"); + + // end of post upload + webfailsafe_post_done = 1; + NetBootFileXferSize = (ulong)hs->upload_total; + + // which website will be returned + if(!webfailsafe_upload_failed){ + fs_open(file_flashing_html.name, &fsfile); + } else { + fs_open(file_fail_html.name, &fsfile); + } + + httpd_state_reset(); + + hs->state = STATE_FILE_REQUEST; + hs->dataptr = (u8_t *)fsfile.data; + hs->upload = fsfile.len; + + uip_send(hs->dataptr, (hs->upload > uip_mss() ? uip_mss() : hs->upload)); + } + + } + + return; + } + + break; + + default: + // we shouldn't get here... we are listening only on port 80 + uip_abort(); + break; + } +} diff --git a/u-boot/httpd/httpd.h b/u-boot/httpd/httpd.h new file mode 100755 index 0000000..54395b4 --- /dev/null +++ b/u-boot/httpd/httpd.h @@ -0,0 +1,77 @@ +/** + * \addtogroup httpd + * @{ + */ + +/** + * \file + * HTTP server header file. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $ + * + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +void httpd_init(void); +void httpd_appcall(void); + +/* UIP_APPCALL: the name of the application function. This function + must return void and take no arguments (i.e., C type "void + appfunc(void)"). */ +#ifndef UIP_APPCALL +#define UIP_APPCALL httpd_appcall +#endif + +struct httpd_state { + u8_t state; + u16_t count; + u8_t *dataptr; + unsigned int upload; + unsigned int upload_total; +}; + +/* UIP_APPSTATE_SIZE: The size of the application-specific state + stored in the uip_conn structure. */ +#ifndef UIP_APPSTATE_SIZE +#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) +#endif + +//#define FS_STATISTICS 1 + +extern struct httpd_state *hs; + +#endif /* __HTTPD_H__ */ diff --git a/u-boot/httpd/main.c b/u-boot/httpd/main.c new file mode 100755 index 0000000..041d0bb --- /dev/null +++ b/u-boot/httpd/main.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: main.c,v 1.10.2.1 2003/10/04 22:54:17 adam Exp $ + * + */ + + +#include "uip.h" +#include "uip_arp.h" +#include "tapdev.h" +#include "httpd.h" + +#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + +#ifndef NULL +#define NULL (void *)0 +#endif /* NULL */ + +/*-----------------------------------------------------------------------------------*/ +int +main(void) +{ + u8_t i, arptimer; + tapdev_init(); + uip_init(); + httpd_init(); + arptimer = 0; + while(1) { + uip_len = tapdev_read(); + if(uip_len == 0) { + for(i = 0; i < UIP_CONNS; i++) { + uip_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + tapdev_send(); + } + } + + if(++arptimer == 20) { + uip_arp_timer(); + arptimer = 0; + } + } else { + if(BUF->type == htons(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if(uip_len > 0) { + uip_arp_out(); + tapdev_send(); + } + } else if(BUF->type == htons(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if(uip_len > 0) { + tapdev_send(); + } + } + } + } + return 0; +} diff --git a/u-boot/httpd/tapdev.c b/u-boot/httpd/tapdev.c new file mode 100755 index 0000000..f03eff2 --- /dev/null +++ b/u-boot/httpd/tapdev.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Author: Adam Dunkels + * + * $Id: tapdev.c,v 1.7.2.1 2003/10/07 13:23:19 adam Exp $ + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef linux +#include +#include +#include +#define DEVTAP "/dev/net/tun" +#else /* linux */ +#define DEVTAP "/dev/tap0" +#endif /* linux */ + +#include "uip.h" + +static int fd; + +static unsigned long lasttime; +static struct timezone tz; + +/*-----------------------------------------------------------------------------------*/ +void +tapdev_init(void) +{ + char buf[1024]; + + fd = open(DEVTAP, O_RDWR); + if(fd == -1) { + perror("tapdev: tapdev_init: open"); + exit(1); + } + +#ifdef linux + { + struct ifreq ifr; + memset(&ifr, 0, sizeof(ifr)); + ifr.ifr_flags = IFF_TAP|IFF_NO_PI; + if (ioctl(fd, TUNSETIFF, (void *) &ifr) < 0) { + perror(buf); + exit(1); + } + } +#endif /* Linux */ + + snprintf(buf, sizeof(buf), "ifconfig tap0 inet %d.%d.%d.%d", + UIP_DRIPADDR0, UIP_DRIPADDR1, UIP_DRIPADDR2, UIP_DRIPADDR3); + system(buf); + + lasttime = 0; +} + +void dump_mem(int type, int len) +{ +#if DUMP == 1 + int i; + for(i = 0; i < len; i++) + printf("%c", uip_buf[i]); + if(type) + { + printf("\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01"); + printf("\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01\01"); + } else { + printf("\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02"); + printf("\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02"); + } + fflush(stdout); +#endif +} + +/*-----------------------------------------------------------------------------------*/ +unsigned int +tapdev_read(void) +{ + fd_set fdset; + struct timeval tv, now; + int ret; + + if(lasttime >= 500000) { + lasttime = 0; + return 0; + } + + tv.tv_sec = 0; + tv.tv_usec = 500000 - lasttime; + + + FD_ZERO(&fdset); + FD_SET(fd, &fdset); + + gettimeofday(&now, &tz); + ret = select(fd + 1, &fdset, NULL, NULL, &tv); + if(ret == 0) { + lasttime = 0; + return 0; + } + ret = read(fd, uip_buf, UIP_BUFSIZE); + if(ret == -1) { + perror("tap_dev: tapdev_read: read"); + } + gettimeofday(&tv, &tz); + lasttime += (tv.tv_sec - now.tv_sec) * 1000000 + (tv.tv_usec - now.tv_usec); + dump_mem(0, ret); + return ret; +} +/*-----------------------------------------------------------------------------------*/ +void +tapdev_send(void) +{ + int ret; + struct iovec iov[2]; + +#ifdef linux + { + char tmpbuf[UIP_BUFSIZE]; + int i; + + for(i = 0; i < 40 + UIP_LLH_LEN; i++) { + tmpbuf[i] = uip_buf[i]; + } + + for(; i < uip_len; i++) { + tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; + } + + ret = write(fd, tmpbuf, uip_len); + } +#else + + if(uip_len < 40 + UIP_LLH_LEN) { + ret = write(fd, uip_buf, uip_len + UIP_LLH_LEN); + } else { + iov[0].iov_base = uip_buf; + iov[0].iov_len = 40 + UIP_LLH_LEN; + iov[1].iov_base = (char *)uip_appdata; + iov[1].iov_len = uip_len - (40 + UIP_LLH_LEN); + + ret = writev(fd, iov, 2); + } +#endif + dump_mem(1, ret); + + if(ret == -1) { + perror("tap_dev: tapdev_send: writev"); + exit(1); + } +} +/*-----------------------------------------------------------------------------------*/ diff --git a/u-boot/httpd/tapdev.h b/u-boot/httpd/tapdev.h new file mode 100755 index 0000000..5b947ef --- /dev/null +++ b/u-boot/httpd/tapdev.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: tapdev.h,v 1.1.2.1 2003/10/04 22:54:17 adam Exp $ + * + */ + +#ifndef __TAPDEV_H__ +#define __TAPDEV_H__ + +void tapdev_init(void); +unsigned int tapdev_read(void); +void tapdev_send(void); + +#endif /* __TAPDEV_H__ */ diff --git a/u-boot/httpd/uip.c b/u-boot/httpd/uip.c new file mode 100755 index 0000000..01869d3 --- /dev/null +++ b/u-boot/httpd/uip.c @@ -0,0 +1,1503 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * The uIP TCP/IP stack code. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $ + * + */ + +/* +This is a small implementation of the IP and TCP protocols (as well as +some basic ICMP stuff). The implementation couples the IP, TCP and the +application layers very tightly. To keep the size of the compiled code +down, this code also features heavy usage of the goto statement. + +The principle is that we have a small buffer, called the uip_buf, in +which the device driver puts an incoming packet. The TCP/IP stack +parses the headers in the packet, and calls upon the application. If +the remote host has sent data to the application, this data is present +in the uip_buf and the application read the data from there. It is up +to the application to put this data into a byte stream if needed. The +application will not be fed with data that is out of sequence. + +If the application whishes to send data to the peer, it should put its +data into the uip_buf, 40 bytes from the start of the buffer. The +TCP/IP stack will calculate the checksums, and fill in the necessary +header fields and finally send the packet back to the peer. +*/ + +#include "uip.h" +#include "uipopt.h" +#include "uip_arch.h" + +/*-----------------------------------------------------------------------------------*/ +/* Variable definitions. */ + + +/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */ +#if UIP_FIXEDADDR > 0 +const unsigned short int uip_hostaddr[2] = + {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1), + HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)}; +const unsigned short int uip_arp_draddr[2] = + {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1), + HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)}; +const unsigned short int uip_arp_netmask[2] = + {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1), + HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)}; +#else +unsigned short int uip_hostaddr[2]; +unsigned short int uip_arp_draddr[2], uip_arp_netmask[2]; +#endif /* UIP_FIXEDADDR */ + +u8_t uip_buf[UIP_BUFSIZE+2]; /* The packet buffer that contains + incoming packets. */ +volatile u8_t *uip_appdata; /* The uip_appdata pointer points to + application data. */ +volatile u8_t *uip_sappdata; /* The uip_appdata pointer points to the + application data which is to be sent. */ +#if UIP_URGDATA > 0 +volatile u8_t *uip_urgdata; /* The uip_urgdata pointer points to + urgent data (out-of-band data), if + present. */ +volatile u8_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + +volatile unsigned short int uip_len, uip_slen; + /* The uip_len is either 8 or 16 bits, + depending on the maximum packet + size. */ + +volatile u8_t uip_flags; /* The uip_flags variable is used for + communication between the TCP/IP stack + and the application program. */ +struct uip_conn *uip_conn; /* uip_conn always points to the current + connection. */ + +struct uip_conn uip_conns[UIP_CONNS]; + /* The uip_conns array holds all TCP + connections. */ +unsigned short int uip_listenports[UIP_LISTENPORTS]; + /* The uip_listenports list all currently + listning ports. */ +#if UIP_UDP +struct uip_udp_conn *uip_udp_conn; +struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + + +static unsigned short int ipid; /* Ths ipid variable is an increasing + number that is used for the IP ID + field. */ + +static u8_t iss[4]; /* The iss variable is used for the TCP + initial sequence number. */ + +#if UIP_ACTIVE_OPEN +static unsigned short int lastport; /* Keeps track of the last port used for + a new connection. */ +#endif /* UIP_ACTIVE_OPEN */ + +/* Temporary variables. */ +volatile u8_t uip_acc32[4]; +static u8_t c, opt; +static unsigned short int tmp16; + +/* Structures and definitions. */ +#define TCP_FIN 0x01 +#define TCP_SYN 0x02 +#define TCP_RST 0x04 +#define TCP_PSH 0x08 +#define TCP_ACK 0x10 +#define TCP_URG 0x20 +#define TCP_CTL 0x3f + +#define ICMP_ECHO_REPLY 0 +#define ICMP_ECHO 8 + +/* Macros. */ +#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0]) +#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN]) + +#if UIP_STATISTICS == 1 +struct uip_stats uip_stat; +#define UIP_STAT(s) s +#else +#define UIP_STAT(s) +#endif /* UIP_STATISTICS == 1 */ + +#if UIP_LOGGING == 1 +extern void puts(const char *s); +#define UIP_LOG(m) puts(m) +#else +#define UIP_LOG(m) +#endif /* UIP_LOGGING == 1 */ + +/*-----------------------------------------------------------------------------------*/ +void +uip_init(void) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + uip_listenports[c] = 0; + } + for(c = 0; c < UIP_CONNS; ++c) { + uip_conns[c].tcpstateflags = CLOSED; + } +#if UIP_ACTIVE_OPEN + lastport = 1024; +#endif /* UIP_ACTIVE_OPEN */ + +#if UIP_UDP + for(c = 0; c < UIP_UDP_CONNS; ++c) { + uip_udp_conns[c].lport = 0; + } +#endif /* UIP_UDP */ + + + /* IPv4 initialization. */ +#if UIP_FIXEDADDR == 0 + uip_hostaddr[0] = uip_hostaddr[1] = 0; +#endif /* UIP_FIXEDADDR */ + +} +/*-----------------------------------------------------------------------------------*/ +#if UIP_ACTIVE_OPEN +struct uip_conn * +uip_connect(unsigned short int *ripaddr, unsigned short int rport) +{ + register struct uip_conn *conn, *cconn; + + /* Find an unused local port. */ + again: + ++lastport; + + if(lastport >= 32000) { + lastport = 4096; + } + + /* Check if this port is already in use, and if so try to find + another one. */ + for(c = 0; c < UIP_CONNS; ++c) { + conn = &uip_conns[c]; + if(conn->tcpstateflags != CLOSED && + conn->lport == htons(lastport)) { + goto again; + } + } + + + conn = 0; + for(c = 0; c < UIP_CONNS; ++c) { + cconn = &uip_conns[c]; + if(cconn->tcpstateflags == CLOSED) { + conn = cconn; + break; + } + if(cconn->tcpstateflags == TIME_WAIT) { + if(conn == 0 || + cconn->timer > uip_conn->timer) { + conn = cconn; + } + } + } + + if(conn == 0) { + return 0; + } + + conn->tcpstateflags = SYN_SENT; + + conn->snd_nxt[0] = iss[0]; + conn->snd_nxt[1] = iss[1]; + conn->snd_nxt[2] = iss[2]; + conn->snd_nxt[3] = iss[3]; + + conn->initialmss = conn->mss = UIP_TCP_MSS; + + conn->len = 1; /* TCP length of the SYN is one. */ + conn->nrtx = 0; + conn->timer = 1; /* Send the SYN next time around. */ + conn->rto = UIP_RTO; + conn->sa = 0; + conn->sv = 16; + conn->lport = htons(lastport); + conn->rport = rport; + conn->ripaddr[0] = ripaddr[0]; + conn->ripaddr[1] = ripaddr[1]; + + return conn; +} +#endif /* UIP_ACTIVE_OPEN */ +/*-----------------------------------------------------------------------------------*/ +#if UIP_UDP +struct uip_udp_conn * +uip_udp_new(unsigned short int *ripaddr, unsigned short int rport) +{ + register struct uip_udp_conn *conn; + + /* Find an unused local port. */ + again: + ++lastport; + + if(lastport >= 32000) { + lastport = 4096; + } + + for(c = 0; c < UIP_UDP_CONNS; ++c) { + if(uip_udp_conns[c].lport == lastport) { + goto again; + } + } + + + conn = 0; + for(c = 0; c < UIP_UDP_CONNS; ++c) { + if(uip_udp_conns[c].lport == 0) { + conn = &uip_udp_conns[c]; + break; + } + } + + if(conn == 0) { + return 0; + } + + conn->lport = HTONS(lastport); + conn->rport = HTONS(rport); + conn->ripaddr[0] = ripaddr[0]; + conn->ripaddr[1] = ripaddr[1]; + + return conn; +} +#endif /* UIP_UDP */ +/*-----------------------------------------------------------------------------------*/ +void +uip_unlisten(unsigned short int port) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(uip_listenports[c] == port) { + uip_listenports[c] = 0; + return; + } + } +} +/*-----------------------------------------------------------------------------------*/ +void +uip_listen(unsigned short int port) +{ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(uip_listenports[c] == 0) { + uip_listenports[c] = port; + return; + } + } +} +/*-----------------------------------------------------------------------------------*/ +/* XXX: IP fragment reassembly: not well-tested. */ + +#if UIP_REASSEMBLY +#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN) +static u8_t uip_reassbuf[UIP_REASS_BUFSIZE]; +static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)]; +static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f, + 0x0f, 0x07, 0x03, 0x01}; +static unsigned short int uip_reasslen; +static u8_t uip_reassflags; +#define UIP_REASS_FLAG_LASTFRAG 0x01 +static u8_t uip_reasstmr; + +#define IP_HLEN 20 +#define IP_MF 0x20 + +static u8_t +uip_reass(void) +{ + unsigned short int offset, len; + unsigned short int i; + + /* If ip_reasstmr is zero, no packet is present in the buffer, so we + write the IP header of the fragment into the reassembly + buffer. The timer is updated with the maximum age. */ + if(uip_reasstmr == 0) { + memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN); + uip_reasstmr = UIP_REASS_MAXAGE; + uip_reassflags = 0; + /* Clear the bitmap. */ + memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0); + } + + /* Check if the incoming fragment matches the one currently present + in the reasembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] && + BUF->srcipaddr[1] == FBUF->srcipaddr[1] && + BUF->destipaddr[0] == FBUF->destipaddr[0] && + BUF->destipaddr[1] == FBUF->destipaddr[1] && + BUF->ipid[0] == FBUF->ipid[0] && + BUF->ipid[1] == FBUF->ipid[1]) { + + len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4; + offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8; + + /* If the offset or the offset + fragment length overflows the + reassembly buffer, we discard the entire packet. */ + if(offset > UIP_REASS_BUFSIZE || + offset + len > UIP_REASS_BUFSIZE) { + uip_reasstmr = 0; + goto nullreturn; + } + + /* Copy the fragment into the reassembly buffer, at the right + offset. */ + memcpy(&uip_reassbuf[IP_HLEN + offset], + (char *)BUF + (int)((BUF->vhl & 0x0f) * 4), + len); + + /* Update the bitmap. */ + if(offset / (8 * 8) == (offset + len) / (8 * 8)) { + /* If the two endpoints are in the same byte, we only update + that byte. */ + + uip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8 ) & 7] & + ~bitmap_bits[((offset + len) / 8 ) & 7]; + } else { + /* If the two endpoints are in different bytes, we update the + bytes in the endpoints and fill the stuff inbetween with + 0xff. */ + uip_reassbitmap[offset / (8 * 8)] |= + bitmap_bits[(offset / 8 ) & 7]; + for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { + uip_reassbitmap[i] = 0xff; + } + uip_reassbitmap[(offset + len) / (8 * 8)] |= + ~bitmap_bits[((offset + len) / 8 ) & 7]; + } + + /* If this fragment has the More Fragments flag set to zero, we + know that this is the last fragment, so we can calculate the + size of the entire packet. We also set the + IP_REASS_FLAG_LASTFRAG flag to indicate that we have received + the final fragment. */ + + if((BUF->ipoffset[0] & IP_MF) == 0) { + uip_reassflags |= UIP_REASS_FLAG_LASTFRAG; + uip_reasslen = offset + len; + } + + /* Finally, we check if we have a full packet in the buffer. We do + this by checking if we have the last fragment and if all bits + in the bitmap are set. */ + if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) { + /* Check all bytes up to and including all but the last byte in + the bitmap. */ + for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) { + if(uip_reassbitmap[i] != 0xff) { + goto nullreturn; + } + } + /* Check the last byte in the bitmap. It should contain just the + right amount of bits. */ + if(uip_reassbitmap[uip_reasslen / (8 * 8)] != + (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) { + goto nullreturn; + } + + /* If we have come this far, we have a full packet in the + buffer, so we allocate a pbuf and copy the packet into it. We + also reset the timer. */ + uip_reasstmr = 0; + memcpy(BUF, FBUF, uip_reasslen); + + /* Pretend to be a "normal" (i.e., not fragmented) IP packet + from now on. */ + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + BUF->len[0] = uip_reasslen >> 8; + BUF->len[1] = uip_reasslen & 0xff; + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); + + return uip_reasslen; + } + } + + nullreturn: + return 0; +} +#endif /* UIP_REASSEMBL */ +/*-----------------------------------------------------------------------------------*/ +static void +uip_add_rcv_nxt(unsigned short int n) +{ + uip_add32(uip_conn->rcv_nxt, n); + uip_conn->rcv_nxt[0] = uip_acc32[0]; + uip_conn->rcv_nxt[1] = uip_acc32[1]; + uip_conn->rcv_nxt[2] = uip_acc32[2]; + uip_conn->rcv_nxt[3] = uip_acc32[3]; +} +/*-----------------------------------------------------------------------------------*/ +void +uip_process(u8_t flag) +{ + register struct uip_conn *uip_connr = uip_conn; + + uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; + + + /* Check if we were invoked because of the perodic timer fireing. */ + if(flag == UIP_TIMER) { +#if UIP_REASSEMBLY + if(uip_reasstmr != 0) { + --uip_reasstmr; + } +#endif /* UIP_REASSEMBLY */ + /* Increase the initial sequence number. */ + if(++iss[3] == 0) { + if(++iss[2] == 0) { + if(++iss[1] == 0) { + ++iss[0]; + } + } + } + uip_len = 0; + if(uip_connr->tcpstateflags == TIME_WAIT || + uip_connr->tcpstateflags == FIN_WAIT_2) { + ++(uip_connr->timer); + if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) { + uip_connr->tcpstateflags = CLOSED; + } + } else if(uip_connr->tcpstateflags != CLOSED) { + /* If the connection has outstanding data, we increase the + connection's timer and see if it has reached the RTO value + in which case we retransmit. */ + if(uip_outstanding(uip_connr)) { + if(uip_connr->timer-- == 0) { + if(uip_connr->nrtx == UIP_MAXRTX || + ((uip_connr->tcpstateflags == SYN_SENT || + uip_connr->tcpstateflags == SYN_RCVD) && + uip_connr->nrtx == UIP_MAXSYNRTX)) { + uip_connr->tcpstateflags = CLOSED; + + /* We call UIP_APPCALL() with uip_flags set to + UIP_TIMEDOUT to inform the application that the + connection has timed out. */ + uip_flags = UIP_TIMEDOUT; + UIP_APPCALL(); + + /* We also send a reset packet to the remote host. */ + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + /* Exponential backoff. */ + uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4? + 4: + uip_connr->nrtx); + ++(uip_connr->nrtx); + + /* Ok, so we need to retransmit. We do this differently + depending on which state we are in. In ESTABLISHED, we + call upon the application so that it may prepare the + data for the retransmit. In SYN_RCVD, we resend the + SYNACK that we sent earlier and in LAST_ACK we have to + retransmit our FINACK. */ + UIP_STAT(++uip_stat.tcp.rexmit); + switch(uip_connr->tcpstateflags & TS_MASK) { + case SYN_RCVD: + /* In the SYN_RCVD state, we should retransmit our + SYNACK. */ + goto tcp_send_synack; + +#if UIP_ACTIVE_OPEN + case SYN_SENT: + /* In the SYN_SENT state, we retransmit out SYN. */ + BUF->flags = 0; + goto tcp_send_syn; +#endif /* UIP_ACTIVE_OPEN */ + + case ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application + to do the actual retransmit after which we jump into + the code for sending out the packet (the apprexmit + label). */ + uip_len = 0; + uip_slen = 0; + uip_flags = UIP_REXMIT; + UIP_APPCALL(); + goto apprexmit; + + case FIN_WAIT_1: + case CLOSING: + case LAST_ACK: + /* In all these states we should retransmit a FINACK. */ + goto tcp_send_finack; + + } + } + } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) { + /* If there was no need for a retransmission, we poll the + application for new data. */ + uip_len = 0; + uip_slen = 0; + uip_flags = UIP_POLL; + UIP_APPCALL(); + goto appsend; + } + } + goto drop; + } +#if UIP_UDP + if(flag == UIP_UDP_TIMER) { + if(uip_udp_conn->lport != 0) { + uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; + uip_len = uip_slen = 0; + uip_flags = UIP_POLL; + UIP_UDP_APPCALL(); + goto udp_send; + } else { + goto drop; + } + } +#endif + + /* This is where the input processing starts. */ + UIP_STAT(++uip_stat.ip.recv); + + + /* Start of IPv4 input header processing code. */ + + /* Check validity of the IP header. */ + if(BUF->vhl != 0x45) { /* IP version and header length. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.vhlerr); + UIP_LOG("ip: invalid version or header length."); + goto drop; + } + + /* Check the size of the packet. If the size reported to us in + uip_len doesn't match the size reported in the IP header, there + has been a transmission error and we drop the packet. */ + + if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */ + uip_len = (uip_len & 0xff) | (BUF->len[0] << 8); + } + if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */ + uip_len = (uip_len & 0xff00) | BUF->len[1]; + } + + /* Check the fragment flag. */ + if((BUF->ipoffset[0] & 0x3f) != 0 || + BUF->ipoffset[1] != 0) { +#if UIP_REASSEMBLY + uip_len = uip_reass(); + if(uip_len == 0) { + goto drop; + } +#else + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.fragerr); + UIP_LOG("ip: fragment dropped."); + goto drop; +#endif /* UIP_REASSEMBLY */ + } + + /* If we are configured to use ping IP address configuration and + hasn't been assigned an IP address yet, we accept all ICMP + packets. */ +#if UIP_PINGADDRCONF + if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { + if(BUF->proto == UIP_PROTO_ICMP) { + UIP_LOG("ip: possible ping config packet received."); + goto icmp_input; + } else { + UIP_LOG("ip: packet dropped since no address assigned."); + goto drop; + } + } +#endif /* UIP_PINGADDRCONF */ + + /* Check if the packet is destined for our IP address. */ + if(BUF->destipaddr[0] != uip_hostaddr[0]) { + UIP_STAT(++uip_stat.ip.drop); + UIP_LOG("ip: packet not for us."); + goto drop; + } + if(BUF->destipaddr[1] != uip_hostaddr[1]) { + UIP_STAT(++uip_stat.ip.drop); + UIP_LOG("ip: packet not for us."); + goto drop; + } + + if(uip_ipchksum() != 0xffff) { /* Compute and check the IP header + checksum. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.chkerr); + UIP_LOG("ip: bad checksum."); + goto drop; + } + + if(BUF->proto == UIP_PROTO_TCP) /* Check for TCP packet. If so, jump + to the tcp_input label. */ + goto tcp_input; + +#if UIP_UDP + if(BUF->proto == UIP_PROTO_UDP) + goto udp_input; +#endif /* UIP_UDP */ + + if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from + here. */ + UIP_STAT(++uip_stat.ip.drop); + UIP_STAT(++uip_stat.ip.protoerr); + UIP_LOG("ip: neither tcp nor icmp."); + goto drop; + } + + //icmp_input: + UIP_STAT(++uip_stat.icmp.recv); + + /* ICMP echo (i.e., ping) processing. This is simple, we only change + the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP + checksum before we return the packet. */ + if(ICMPBUF->type != ICMP_ECHO) { + UIP_STAT(++uip_stat.icmp.drop); + UIP_STAT(++uip_stat.icmp.typeerr); + UIP_LOG("icmp: not icmp echo."); + goto drop; + } + + /* If we are configured to use ping IP address assignment, we use + the destination IP address of this ping packet and assign it to + ourself. */ +#if UIP_PINGADDRCONF + if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) { + uip_hostaddr[0] = BUF->destipaddr[0]; + uip_hostaddr[1] = BUF->destipaddr[1]; + } +#endif /* UIP_PINGADDRCONF */ + + ICMPBUF->type = ICMP_ECHO_REPLY; + + if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) { + ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1; + } else { + ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8); + } + + /* Swap IP addresses. */ + tmp16 = BUF->destipaddr[0]; + BUF->destipaddr[0] = BUF->srcipaddr[0]; + BUF->srcipaddr[0] = tmp16; + tmp16 = BUF->destipaddr[1]; + BUF->destipaddr[1] = BUF->srcipaddr[1]; + BUF->srcipaddr[1] = tmp16; + + UIP_STAT(++uip_stat.icmp.sent); + goto send; + + /* End of IPv4 input header processing code. */ + + +#if UIP_UDP + /* UDP input processing. */ + udp_input: + /* UDP processing is really just a hack. We don't do anything to the + UDP/IP headers, but let the UDP application do all the hard + work. If the application sets uip_slen, it has a packet to + send. */ +#if UIP_UDP_CHECKSUMS + if(uip_udpchksum() != 0xffff) { + UIP_STAT(++uip_stat.udp.drop); + UIP_STAT(++uip_stat.udp.chkerr); + UIP_LOG("udp: bad checksum."); + goto drop; + } +#endif /* UIP_UDP_CHECKSUMS */ + + /* Demultiplex this UDP packet between the UDP "connections". */ + for(uip_udp_conn = &uip_udp_conns[0]; + uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS]; + ++uip_udp_conn) { + if(uip_udp_conn->lport != 0 && + UDPBUF->destport == uip_udp_conn->lport && + (uip_udp_conn->rport == 0 || + UDPBUF->srcport == uip_udp_conn->rport) && + BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] && + BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) { + goto udp_found; + } + } + goto drop; + + udp_found: + uip_len = uip_len - 28; + uip_appdata = &uip_buf[UIP_LLH_LEN + 28]; + uip_flags = UIP_NEWDATA; + uip_slen = 0; + UIP_UDP_APPCALL(); + udp_send: + if(uip_slen == 0) { + goto drop; + } + uip_len = uip_slen + 28; + + BUF->len[0] = (uip_len >> 8); + BUF->len[1] = (uip_len & 0xff); + + BUF->proto = UIP_PROTO_UDP; + + UDPBUF->udplen = HTONS(uip_slen + 8); + UDPBUF->udpchksum = 0; +#if UIP_UDP_CHECKSUMS + /* Calculate UDP checksum. */ + UDPBUF->udpchksum = ~(uip_udpchksum()); + if(UDPBUF->udpchksum == 0) { + UDPBUF->udpchksum = 0xffff; + } +#endif /* UIP_UDP_CHECKSUMS */ + + BUF->srcport = uip_udp_conn->lport; + BUF->destport = uip_udp_conn->rport; + + BUF->srcipaddr[0] = uip_hostaddr[0]; + BUF->srcipaddr[1] = uip_hostaddr[1]; + BUF->destipaddr[0] = uip_udp_conn->ripaddr[0]; + BUF->destipaddr[1] = uip_udp_conn->ripaddr[1]; + + uip_appdata = &uip_buf[UIP_LLH_LEN + 40]; + goto ip_send_nolen; +#endif /* UIP_UDP */ + + /* TCP input processing. */ + tcp_input: + UIP_STAT(++uip_stat.tcp.recv); + + /* Start of TCP input header processing code. */ + + if(uip_tcpchksum() != 0xffff) { /* Compute and check the TCP + checksum. */ + UIP_STAT(++uip_stat.tcp.drop); + UIP_STAT(++uip_stat.tcp.chkerr); + UIP_LOG("tcp: bad checksum."); + goto drop; + } + + /* Demultiplex this segment. */ + /* First check any active connections. */ + for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) { + if(uip_connr->tcpstateflags != CLOSED && + BUF->destport == uip_connr->lport && + BUF->srcport == uip_connr->rport && + BUF->srcipaddr[0] == uip_connr->ripaddr[0] && + BUF->srcipaddr[1] == uip_connr->ripaddr[1]) { + goto found; + } + } + + /* If we didn't find and active connection that expected the packet, + either this packet is an old duplicate, or this is a SYN packet + destined for a connection in LISTEN. If the SYN flag isn't set, + it is an old packet and we send a RST. */ + if((BUF->flags & TCP_CTL) != TCP_SYN) + goto reset; + + tmp16 = BUF->destport; + /* Next, check listening connections. */ + for(c = 0; c < UIP_LISTENPORTS; ++c) { + if(tmp16 == uip_listenports[c]) + goto found_listen; + } + + /* No matching connection found, so we send a RST packet. */ + UIP_STAT(++uip_stat.tcp.synrst); + reset: + + /* We do not send resets in response to resets. */ + if(BUF->flags & TCP_RST) + goto drop; + + UIP_STAT(++uip_stat.tcp.rst); + + BUF->flags = TCP_RST | TCP_ACK; + uip_len = 40; + BUF->tcpoffset = 5 << 4; + + /* Flip the seqno and ackno fields in the TCP header. */ + c = BUF->seqno[3]; + BUF->seqno[3] = BUF->ackno[3]; + BUF->ackno[3] = c; + + c = BUF->seqno[2]; + BUF->seqno[2] = BUF->ackno[2]; + BUF->ackno[2] = c; + + c = BUF->seqno[1]; + BUF->seqno[1] = BUF->ackno[1]; + BUF->ackno[1] = c; + + c = BUF->seqno[0]; + BUF->seqno[0] = BUF->ackno[0]; + BUF->ackno[0] = c; + + /* We also have to increase the sequence number we are + acknowledging. If the least significant byte overflowed, we need + to propagate the carry to the other bytes as well. */ + if(++BUF->ackno[3] == 0) { + if(++BUF->ackno[2] == 0) { + if(++BUF->ackno[1] == 0) { + ++BUF->ackno[0]; + } + } + } + + /* Swap port numbers. */ + tmp16 = BUF->srcport; + BUF->srcport = BUF->destport; + BUF->destport = tmp16; + + /* Swap IP addresses. */ + tmp16 = BUF->destipaddr[0]; + BUF->destipaddr[0] = BUF->srcipaddr[0]; + BUF->srcipaddr[0] = tmp16; + tmp16 = BUF->destipaddr[1]; + BUF->destipaddr[1] = BUF->srcipaddr[1]; + BUF->srcipaddr[1] = tmp16; + + + /* And send out the RST packet! */ + goto tcp_send_noconn; + + /* This label will be jumped to if we matched the incoming packet + with a connection in LISTEN. In that case, we should create a new + connection and send a SYNACK in return. */ + found_listen: + /* First we check if there are any connections avaliable. Unused + connections are kept in the same table as used connections, but + unused ones have the tcpstate set to CLOSED. Also, connections in + TIME_WAIT are kept track of and we'll use the oldest one if no + CLOSED connections are found. Thanks to Eddie C. Dost for a very + nice algorithm for the TIME_WAIT search. */ + uip_connr = 0; + for(c = 0; c < UIP_CONNS; ++c) { + if(uip_conns[c].tcpstateflags == CLOSED) { + uip_connr = &uip_conns[c]; + break; + } + if(uip_conns[c].tcpstateflags == TIME_WAIT) { + if(uip_connr == 0 || + uip_conns[c].timer > uip_connr->timer) { + uip_connr = &uip_conns[c]; + } + } + } + + if(uip_connr == 0) { + /* All connections are used already, we drop packet and hope that + the remote end will retransmit the packet at a time when we + have more spare connections. */ + UIP_STAT(++uip_stat.tcp.syndrop); + UIP_LOG("tcp: found no unused connections."); + goto drop; + } + uip_conn = uip_connr; + + /* Fill in the necessary fields for the new connection. */ + uip_connr->rto = uip_connr->timer = UIP_RTO; + uip_connr->sa = 0; + uip_connr->sv = 4; + uip_connr->nrtx = 0; + uip_connr->lport = BUF->destport; + uip_connr->rport = BUF->srcport; + uip_connr->ripaddr[0] = BUF->srcipaddr[0]; + uip_connr->ripaddr[1] = BUF->srcipaddr[1]; + uip_connr->tcpstateflags = SYN_RCVD; + + uip_connr->snd_nxt[0] = iss[0]; + uip_connr->snd_nxt[1] = iss[1]; + uip_connr->snd_nxt[2] = iss[2]; + uip_connr->snd_nxt[3] = iss[3]; + uip_connr->len = 1; + + /* rcv_nxt should be the seqno from the incoming packet + 1. */ + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_add_rcv_nxt(1); + + /* Parse the TCP MSS option, if present. */ + if((BUF->tcpoffset & 0xf0) > 0x50) { + for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { + opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c]; + if(opt == 0x00) { + /* End of options. */ + break; + } else if(opt == 0x01) { + ++c; + /* NOP option. */ + } else if(opt == 0x02 && + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { + /* An MSS option with the right option length. */ + tmp16 = ((unsigned short int)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | + (unsigned short int)uip_buf[40 + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = uip_connr->mss = + tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; + + /* And we are done processing options. */ + break; + } else { + /* All other options have a length field, so that we easily + can skip past them. */ + if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + + /* Our response will be a SYNACK. */ +#if UIP_ACTIVE_OPEN + tcp_send_synack: + BUF->flags = TCP_ACK; + + tcp_send_syn: + BUF->flags |= TCP_SYN; +#else /* UIP_ACTIVE_OPEN */ + tcp_send_synack: + BUF->flags = TCP_SYN | TCP_ACK; +#endif /* UIP_ACTIVE_OPEN */ + + /* We send out the TCP Maximum Segment Size option with our + SYNACK. */ + BUF->optdata[0] = 2; + BUF->optdata[1] = 4; + BUF->optdata[2] = (UIP_TCP_MSS) / 256; + BUF->optdata[3] = (UIP_TCP_MSS) & 255; + uip_len = 44; + BUF->tcpoffset = 6 << 4; + goto tcp_send; + + /* This label will be jumped to if we found an active connection. */ + found: + uip_conn = uip_connr; + uip_flags = 0; + + /* We do a very naive form of TCP reset processing; we just accept + any RST and kill our connection. We should in fact check if the + sequence number of this reset is wihtin our advertised window + before we accept the reset. */ + if(BUF->flags & TCP_RST) { + uip_connr->tcpstateflags = CLOSED; + UIP_LOG("tcp: got reset, aborting connection."); + uip_flags = UIP_ABORT; + UIP_APPCALL(); + goto drop; + } + /* Calculated the length of the data, if the application has sent + any data to us. */ + c = (BUF->tcpoffset >> 4) << 2; + /* uip_len will contain the length of the actual TCP data. This is + calculated by subtracing the length of the TCP header (in + c) and the length of the IP header (20 bytes). */ + uip_len = uip_len - c - 20; + + /* First, check if the sequence number of the incoming packet is + what we're expecting next. If not, we send out an ACK with the + correct numbers in. */ + if(uip_len > 0 && + (BUF->seqno[0] != uip_connr->rcv_nxt[0] || + BUF->seqno[1] != uip_connr->rcv_nxt[1] || + BUF->seqno[2] != uip_connr->rcv_nxt[2] || + BUF->seqno[3] != uip_connr->rcv_nxt[3])) { + goto tcp_send_ack; + } + + /* Next, check if the incoming segment acknowledges any outstanding + data. If so, we update the sequence number, reset the length of + the outstanding data, calculate RTT estimations, and reset the + retransmission timer. */ + if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) { + uip_add32(uip_connr->snd_nxt, uip_connr->len); + if(BUF->ackno[0] == uip_acc32[0] && + BUF->ackno[1] == uip_acc32[1] && + BUF->ackno[2] == uip_acc32[2] && + BUF->ackno[3] == uip_acc32[3]) { + /* Update sequence number. */ + uip_connr->snd_nxt[0] = uip_acc32[0]; + uip_connr->snd_nxt[1] = uip_acc32[1]; + uip_connr->snd_nxt[2] = uip_acc32[2]; + uip_connr->snd_nxt[3] = uip_acc32[3]; + + + /* Do RTT estimation, unless we have done retransmissions. */ + if(uip_connr->nrtx == 0) { + signed char m; + m = uip_connr->rto - uip_connr->timer; + /* This is taken directly from VJs original code in his paper */ + m = m - (uip_connr->sa >> 3); + uip_connr->sa += m; + if(m < 0) { + m = -m; + } + m = m - (uip_connr->sv >> 2); + uip_connr->sv += m; + uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv; + + } + /* Set the acknowledged flag. */ + uip_flags = UIP_ACKDATA; + /* Reset the retransmission timer. */ + uip_connr->timer = uip_connr->rto; + } + + } + + /* Do different things depending on in what state the connection is. */ + switch(uip_connr->tcpstateflags & TS_MASK) { + /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not + implemented, since we force the application to close when the + peer sends a FIN (hence the application goes directly from + ESTABLISHED to LAST_ACK). */ + case SYN_RCVD: + /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and + we are waiting for an ACK that acknowledges the data we sent + out the last time. Therefore, we want to have the UIP_ACKDATA + flag set. If so, we enter the ESTABLISHED state. */ + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = ESTABLISHED; + uip_flags = UIP_CONNECTED; + uip_connr->len = 0; + if(uip_len > 0) { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt(uip_len); + } + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + goto drop; +#if UIP_ACTIVE_OPEN + case SYN_SENT: + /* In SYN_SENT, we wait for a SYNACK that is sent in response to + our SYN. The rcv_nxt is set to sequence number in the SYNACK + plus one, and we send an ACK. We move into the ESTABLISHED + state. */ + if((uip_flags & UIP_ACKDATA) && + BUF->flags == (TCP_SYN | TCP_ACK)) { + + /* Parse the TCP MSS option, if present. */ + if((BUF->tcpoffset & 0xf0) > 0x50) { + for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) { + opt = uip_buf[40 + UIP_LLH_LEN + c]; + if(opt == 0x00) { + /* End of options. */ + break; + } else if(opt == 0x01) { + ++c; + /* NOP option. */ + } else if(opt == 0x02 && + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) { + /* An MSS option with the right option length. */ + tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) | + uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c]; + uip_connr->initialmss = + uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16; + + /* And we are done processing options. */ + break; + } else { + /* All other options have a length field, so that we easily + can skip past them. */ + if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) { + /* If the length field is zero, the options are malformed + and we don't process them further. */ + break; + } + c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c]; + } + } + } + uip_connr->tcpstateflags = ESTABLISHED; + uip_connr->rcv_nxt[0] = BUF->seqno[0]; + uip_connr->rcv_nxt[1] = BUF->seqno[1]; + uip_connr->rcv_nxt[2] = BUF->seqno[2]; + uip_connr->rcv_nxt[3] = BUF->seqno[3]; + uip_add_rcv_nxt(1); + uip_flags = UIP_CONNECTED | UIP_NEWDATA; + uip_connr->len = 0; + uip_len = 0; + uip_slen = 0; + UIP_APPCALL(); + goto appsend; + } + goto reset; +#endif /* UIP_ACTIVE_OPEN */ + + case ESTABLISHED: + /* In the ESTABLISHED state, we call upon the application to feed + data into the uip_buf. If the UIP_ACKDATA flag is set, the + application should put new data into the buffer, otherwise we are + retransmitting an old segment, and the application should put that + data into the buffer. + + If the incoming packet is a FIN, we should close the connection on + this side as well, and we send out a FIN and enter the LAST_ACK + state. We require that there is no outstanding data; otherwise the + sequence numbers will be screwed up. */ + + if(BUF->flags & TCP_FIN) { + if(uip_outstanding(uip_connr)) { + goto drop; + } + uip_add_rcv_nxt(1 + uip_len); + uip_flags = UIP_CLOSE; + if(uip_len > 0) { + uip_flags |= UIP_NEWDATA; + } + UIP_APPCALL(); + uip_connr->len = 1; + uip_connr->tcpstateflags = LAST_ACK; + uip_connr->nrtx = 0; + tcp_send_finack: + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* Check the URG flag. If this is set, the segment carries urgent + data that we must pass to the application. */ + if(BUF->flags & TCP_URG) { +#if UIP_URGDATA > 0 + uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1]; + if(uip_urglen > uip_len) { + /* There is more urgent data in the next segment to come. */ + uip_urglen = uip_len; + } + uip_add_rcv_nxt(uip_urglen); + uip_len -= uip_urglen; + uip_urgdata = uip_appdata; + uip_appdata += uip_urglen; + } else { + uip_urglen = 0; +#endif /* UIP_URGDATA > 0 */ + uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1]; + uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1]; + } + + + /* If uip_len > 0 we have TCP data in the packet, and we flag this + by setting the UIP_NEWDATA flag and update the sequence number + we acknowledge. If the application has stopped the dataflow + using uip_stop(), we must not accept any data packets from the + remote host. */ + if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) { + uip_flags |= UIP_NEWDATA; + uip_add_rcv_nxt(uip_len); + } + + /* Check if the available buffer space advertised by the other end + is smaller than the initial MSS for this connection. If so, we + set the current MSS to the window size to ensure that the + application does not send more data than the other end can + handle. + + If the remote host advertises a zero window, we set the MSS to + the initial MSS so that the application will send an entire MSS + of data. This data will not be acknowledged by the receiver, + and the application will retransmit it. This is called the + "persistent timer" and uses the retransmission mechanim. + */ + tmp16 = ((unsigned short int)BUF->wnd[0] << 8) + (unsigned short int)BUF->wnd[1]; + if(tmp16 > uip_connr->initialmss || + tmp16 == 0) { + tmp16 = uip_connr->initialmss; + } + uip_connr->mss = tmp16; + + /* If this packet constitutes an ACK for outstanding data (flagged + by the UIP_ACKDATA flag, we should call the application since it + might want to send more data. If the incoming packet had data + from the peer (as flagged by the UIP_NEWDATA flag), the + application must also be notified. + + When the application is called, the global variable uip_len + contains the length of the incoming data. The application can + access the incoming data through the global pointer + uip_appdata, which usually points 40 bytes into the uip_buf + array. + + If the application wishes to send any data, this data should be + put into the uip_appdata and the length of the data should be + put into uip_len. If the application don't have any data to + send, uip_len must be set to 0. */ + if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) { + uip_slen = 0; + UIP_APPCALL(); + + appsend: + + if(uip_flags & UIP_ABORT) { + uip_slen = 0; + uip_connr->tcpstateflags = CLOSED; + BUF->flags = TCP_RST | TCP_ACK; + goto tcp_send_nodata; + } + + if(uip_flags & UIP_CLOSE) { + uip_slen = 0; + uip_connr->len = 1; + uip_connr->tcpstateflags = FIN_WAIT_1; + uip_connr->nrtx = 0; + BUF->flags = TCP_FIN | TCP_ACK; + goto tcp_send_nodata; + } + + /* If uip_slen > 0, the application has data to be sent. */ + if(uip_slen > 0) { + + /* If the connection has acknowledged data, the contents of + the ->len variable should be discarded. */ + if((uip_flags & UIP_ACKDATA) != 0) { + uip_connr->len = 0; + } + + /* If the ->len variable is non-zero the connection has + already data in transit and cannot send anymore right + now. */ + if(uip_connr->len == 0) { + + /* The application cannot send more than what is allowed by + the mss (the minumum of the MSS and the available + window). */ + if(uip_slen > uip_connr->mss) { + uip_slen = uip_connr->mss; + } + + /* Remember how much data we send out now so that we know + when everything has been acknowledged. */ + uip_connr->len = uip_slen; + } else { + + /* If the application already had unacknowledged data, we + make sure that the application does not send (i.e., + retransmit) out more than it previously sent out. */ + uip_slen = uip_connr->len; + } + } else { + uip_connr->len = 0; + } + uip_connr->nrtx = 0; + apprexmit: + uip_appdata = uip_sappdata; + + /* If the application has data to be sent, or if the incoming + packet had new data in it, we must send out a packet. */ + if(uip_slen > 0 && uip_connr->len > 0) { + /* Add the length of the IP and TCP headers. */ + uip_len = uip_connr->len + UIP_TCPIP_HLEN; + /* We always set the ACK flag in response packets. */ + BUF->flags = TCP_ACK | TCP_PSH; + /* Send the packet. */ + goto tcp_send_noopts; + } + /* If there is no data to send, just send out a pure ACK if + there is newdata. */ + if(uip_flags & UIP_NEWDATA) { + uip_len = UIP_TCPIP_HLEN; + BUF->flags = TCP_ACK; + goto tcp_send_noopts; + } + } + goto drop; + case LAST_ACK: + /* We can close this connection if the peer has acknowledged our + FIN. This is indicated by the UIP_ACKDATA flag. */ + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = CLOSED; + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + } + break; + + case FIN_WAIT_1: + /* The application has closed the connection, but the remote host + hasn't closed its end yet. Thus we do nothing but wait for a + FIN from the other side. */ + if(uip_len > 0) { + uip_add_rcv_nxt(uip_len); + } + if(BUF->flags & TCP_FIN) { + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + uip_connr->len = 0; + } else { + uip_connr->tcpstateflags = CLOSING; + } + uip_add_rcv_nxt(1); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } else if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = FIN_WAIT_2; + uip_connr->len = 0; + goto drop; + } + if(uip_len > 0) { + goto tcp_send_ack; + } + goto drop; + + case FIN_WAIT_2: + if(uip_len > 0) { + uip_add_rcv_nxt(uip_len); + } + if(BUF->flags & TCP_FIN) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + uip_add_rcv_nxt(1); + uip_flags = UIP_CLOSE; + UIP_APPCALL(); + goto tcp_send_ack; + } + if(uip_len > 0) { + goto tcp_send_ack; + } + goto drop; + + case TIME_WAIT: + goto tcp_send_ack; + + case CLOSING: + if(uip_flags & UIP_ACKDATA) { + uip_connr->tcpstateflags = TIME_WAIT; + uip_connr->timer = 0; + } + } + goto drop; + + + /* We jump here when we are ready to send the packet, and just want + to set the appropriate TCP sequence numbers in the TCP header. */ + tcp_send_ack: + BUF->flags = TCP_ACK; + tcp_send_nodata: + uip_len = 40; + tcp_send_noopts: + BUF->tcpoffset = 5 << 4; + tcp_send: + /* We're done with the input processing. We are now ready to send a + reply. Our job is to fill in all the fields of the TCP and IP + headers before calculating the checksum and finally send the + packet. */ + BUF->ackno[0] = uip_connr->rcv_nxt[0]; + BUF->ackno[1] = uip_connr->rcv_nxt[1]; + BUF->ackno[2] = uip_connr->rcv_nxt[2]; + BUF->ackno[3] = uip_connr->rcv_nxt[3]; + + BUF->seqno[0] = uip_connr->snd_nxt[0]; + BUF->seqno[1] = uip_connr->snd_nxt[1]; + BUF->seqno[2] = uip_connr->snd_nxt[2]; + BUF->seqno[3] = uip_connr->snd_nxt[3]; + + BUF->proto = UIP_PROTO_TCP; + + BUF->srcport = uip_connr->lport; + BUF->destport = uip_connr->rport; + + BUF->srcipaddr[0] = uip_hostaddr[0]; + BUF->srcipaddr[1] = uip_hostaddr[1]; + BUF->destipaddr[0] = uip_connr->ripaddr[0]; + BUF->destipaddr[1] = uip_connr->ripaddr[1]; + + + if(uip_connr->tcpstateflags & UIP_STOPPED) { + /* If the connection has issued uip_stop(), we advertise a zero + window so that the remote host will stop sending data. */ + BUF->wnd[0] = BUF->wnd[1] = 0; + } else { + BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8); + BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); + } + + tcp_send_noconn: + + BUF->len[0] = (uip_len >> 8); + BUF->len[1] = (uip_len & 0xff); + + /* Calculate TCP checksum. */ + BUF->tcpchksum = 0; + BUF->tcpchksum = ~(uip_tcpchksum()); + + //ip_send_nolen: + + BUF->vhl = 0x45; + BUF->tos = 0; + BUF->ipoffset[0] = BUF->ipoffset[1] = 0; + BUF->ttl = UIP_TTL; + ++ipid; + BUF->ipid[0] = ipid >> 8; + BUF->ipid[1] = ipid & 0xff; + + /* Calculate IP checksum. */ + BUF->ipchksum = 0; + BUF->ipchksum = ~(uip_ipchksum()); + + UIP_STAT(++uip_stat.tcp.sent); + send: + UIP_STAT(++uip_stat.ip.sent); + /* Return and let the caller do the actual transmission. */ + return; + drop: + uip_len = 0; + return; +} +/*-----------------------------------------------------------------------------------*/ +/*unsigned short int +htons(unsigned short int val) +{ + return HTONS(val); +}*/ +/*-----------------------------------------------------------------------------------*/ +/** @} */ diff --git a/u-boot/httpd/uip.h b/u-boot/httpd/uip.h new file mode 100755 index 0000000..acd9784 --- /dev/null +++ b/u-boot/httpd/uip.h @@ -0,0 +1,1066 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \file + * Header file for the uIP TCP/IP stack. + * \author Adam Dunkels + * + * The uIP TCP/IP stack header file contains definitions for a number + * of C macros that are used by uIP programs as well as internal uIP + * structures, TCP/IP header structures and function declarations. + * + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $ + * + */ + +#ifndef __UIP_H__ +#define __UIP_H__ +#include +#include +#include +#include +#include + + +#include "uipopt.h" + +/*-----------------------------------------------------------------------------------*/ +/* First, the functions that should be called from the + * system. Initialization, the periodic timer and incoming packets are + * handled by the following three functions. + */ + +/** + * \defgroup uipconffunc uIP configuration functions + * @{ + * + * The uIP configuration functions are used for setting run-time + * parameters in uIP such as IP addresses. + */ + +/** + * Set the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * \param addr A pointer to a 4-byte representation of the IP address. + * + * \hideinitializer + */ +#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \ + uip_hostaddr[1] = addr[1]; } while(0) + +/** + * Get the IP address of this host. + * + * The IP address is represented as a 4-byte array where the first + * octet of the IP address is put in the first member of the 4-byte + * array. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the currently configured IP address. + * + * \hideinitializer + */ +#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \ + addr[1] = uip_hostaddr[1]; } while(0) + +/** @} */ + +/** + * \defgroup uipinit uIP initialization functions + * @{ + * + * The uIP initialization functions are used for booting uIP. + */ + +/** + * uIP initialization function. + * + * This function should be called at boot up to initilize the uIP + * TCP/IP stack. + */ +void uip_init(void); + +/** @} */ + +/** + * \defgroup uipdevfunc uIP device driver functions + * @{ + * + * These functions are used by a network device driver for interacting + * with uIP. + */ + +/** + * Process an incoming packet. + * + * This function should be called when the device driver has received + * a packet from the network. The packet from the device driver must + * be present in the uip_buf buffer, and the length of the packet + * should be placed in the uip_len variable. + * + * When the function returns, there may be an outbound packet placed + * in the uip_buf packet buffer. If so, the uip_len variable is set to + * the length of the packet. If no packet is to be sent out, the + * uip_len variable is set to 0. + * + * The usual way of calling the function is presented by the source + * code below. + \code + uip_len = devicedriver_poll(); + if(uip_len > 0) { + uip_input(); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uIP ARP code before calling + * this function: + \code + #define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + uip_len = ethernet_devicedrver_poll(); + if(uip_len > 0) { + if(BUF->type == HTONS(UIP_ETHTYPE_IP)) { + uip_arp_ipin(); + uip_input(); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) { + uip_arp_arpin(); + if(uip_len > 0) { + ethernet_devicedriver_send(); + } + } + \endcode + * + * \hideinitializer + */ +#define uip_input() uip_process(UIP_DATA) + +/** + * Periodic processing for a connection identified by its number. + * + * This function does the necessary periodic processing (timers, + * polling) for a uIP TCP conneciton, and should be called when the + * periodic uIP timer goes off. It should be called for every + * connection, regardless of whether they are open of closed. + * + * When the function returns, it may have an outbound packet waiting + * for service in the uIP packet buffer, and if so the uip_len + * variable is set to a value larger than zero. The device driver + * should be called to send out the packet. + * + * The ususal way of calling the function is through a for() loop like + * this: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note If you are writing a uIP device driver that needs ARP + * (Address Resolution Protocol), e.g., when running uIP over + * Ethernet, you will need to call the uip_arp_out() function before + * calling the device driver: + \code + for(i = 0; i < UIP_CONNS; ++i) { + uip_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the connection which is to be periodically polled. + * + * \hideinitializer + */ +#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \ + uip_process(UIP_TIMER); } while (0) + +/** + * Periodic processing for a connection identified by a pointer to its structure. + * + * Same as uip_periodic() but takes a pointer to the actual uip_conn + * struct instead of an integer as its argument. This function can be + * used to force periodic processing of a specific connection. + * + * \param conn A pointer to the uip_conn struct for the connection to + * be processed. + * + * \hideinitializer + */ +#define uip_periodic_conn(conn) do { uip_conn = conn; \ + uip_process(UIP_TIMER); } while (0) + +#if UIP_UDP +/** + * Periodic processing for a UDP connection identified by its number. + * + * This function is essentially the same as uip_prerioic(), but for + * UDP connections. It is called in a similar fashion as the + * uip_periodic() function: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + devicedriver_send(); + } + } + \endcode + * + * \note As for the uip_periodic() function, special care has to be + * taken when using uIP together with ARP and Ethernet: + \code + for(i = 0; i < UIP_UDP_CONNS; i++) { + uip_udp_periodic(i); + if(uip_len > 0) { + uip_arp_out(); + ethernet_devicedriver_send(); + } + } + \endcode + * + * \param conn The number of the UDP connection to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \ + uip_process(UIP_UDP_TIMER); } while (0) + +/** + * Periodic processing for a UDP connection identified by a pointer to + * its structure. + * + * Same as uip_udp_periodic() but takes a pointer to the actual + * uip_conn struct instead of an integer as its argument. This + * function can be used to force periodic processing of a specific + * connection. + * + * \param conn A pointer to the uip_udp_conn struct for the connection + * to be processed. + * + * \hideinitializer + */ +#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \ + uip_process(UIP_UDP_TIMER); } while (0) + + +#endif /* UIP_UDP */ + +/** + * The uIP packet buffer. + * + * The uip_buf array is used to hold incoming and outgoing + * packets. The device driver should place incoming data into this + * buffer. When sending data, the device driver should read the link + * level headers and the TCP/IP headers from this buffer. The size of + * the link level headers is configured by the UIP_LLH_LEN define. + * + * \note The application data need not be placed in this buffer, so + * the device driver must read it from the place pointed to by the + * uip_appdata pointer as illustrated by the following example: + \code + void + devicedriver_send(void) + { + hwsend(&uip_buf[0], UIP_LLH_LEN); + hwsend(&uip_buf[UIP_LLH_LEN], 40); + hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN); + } + \endcode + */ +extern u8_t uip_buf[UIP_BUFSIZE+2]; + +/** @} */ + +/*-----------------------------------------------------------------------------------*/ +/* Functions that are used by the uIP application program. Opening and + * closing connections, sending and receiving data, etc. is all + * handled by the functions below. +*/ +/** + * \defgroup uipappfunc uIP application functions + * @{ + * + * Functions used by an application running of top of uIP. + */ + +/** + * Start listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_listen(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_listen(u16_t port); + +/** + * Stop listening to the specified port. + * + * \note Since this function expects the port number in network byte + * order, a conversion using HTONS() or htons() is necessary. + * + \code + uip_unlisten(HTONS(80)); + \endcode + * + * \param port A 16-bit port number in network byte order. + */ +void uip_unlisten(u16_t port); + +/** + * Connect to a remote host using TCP. + * + * This function is used to start a new connection to the specified + * port on the specied host. It allocates a new connection identifier, + * sets the connection to the SYN_SENT state and sets the + * retransmission timer to 0. This will cause a TCP SYN segment to be + * sent out the next time this connection is periodically processed, + * which usually is done within 0.5 seconds after the call to + * uip_connect(). + * + * \note This function is avaliable only if support for active open + * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h. + * + * \note Since this function requires the port number to be in network + * byte order, a convertion using HTONS() or htons() is necessary. + * + \code + u16_t ipaddr[2]; + + uip_ipaddr(ipaddr, 192,168,1,2); + uip_connect(ipaddr, HTONS(80)); + \endcode + * + * \param ripaddr A pointer to a 4-byte array representing the IP + * address of the remote hot. + * + * \param port A 16-bit port number in network byte order. + * + * \return A pointer to the uIP connection identifier for the new connection, + * or NULL if no connection could be allocated. + * + */ +struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port); + + + +/** + * \internal + * + * Check if a connection has outstanding (i.e., unacknowledged) data. + * + * \param conn A pointer to the uip_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_outstanding(conn) ((conn)->len) + +/** + * Send data on the current connection. + * + * This function is used to send out a single segment of TCP + * data. Only applications that have been invoked by uIP for event + * processing can send data. + * + * The amount of data that actually is sent out after a call to this + * funcion is determined by the maximum amount of data TCP allows. uIP + * will automatically crop the data so that only the appropriate + * amount of data is sent. The function uip_mss() can be used to query + * uIP for the amount of data that actually will be sent. + * + * \note This function does not guarantee that the sent data will + * arrive at the destination. If the data is lost in the network, the + * application will be invoked with the uip_rexmit() event being + * set. The application will then have to resend the data using this + * function. + * + * \param data A pointer to the data which is to be sent. + * + * \param len The maximum amount of data bytes to be sent. + * + * \hideinitializer + */ +#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0) + +/** + * The length of any incoming data that is currently avaliable (if avaliable) + * in the uip_appdata buffer. + * + * The test function uip_data() must first be used to check if there + * is any data available at all. + * + * \hideinitializer + */ +#define uip_datalen() uip_len + +/** + * The length of any out-of-band data (urgent data) that has arrived + * on the connection. + * + * \note The configuration parameter UIP_URGDATA must be set for this + * function to be enabled. + * + * \hideinitializer + */ +#define uip_urgdatalen() uip_urglen + +/** + * Close the current connection. + * + * This function will close the current connection in a nice way. + * + * \hideinitializer + */ +#define uip_close() (uip_flags = UIP_CLOSE) + +/** + * Abort the current connection. + * + * This function will abort (reset) the current connection, and is + * usually used when an error has occured that prevents using the + * uip_close() function. + * + * \hideinitializer + */ +#define uip_abort() (uip_flags = UIP_ABORT) + +/** + * Tell the sending host to stop sending data. + * + * This function will close our receiver's window so that we stop + * receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_stop() (uip_conn->tcpstateflags |= UIP_STOPPED) + +/** + * Find out if the current connection has been previously stopped with + * uip_stop(). + * + * \hideinitializer + */ +#define uip_stopped(conn) ((conn)->tcpstateflags & UIP_STOPPED) + +/** + * Restart the current connection, if is has previously been stopped + * with uip_stop(). + * + * This function will open the receiver's window again so that we + * start receiving data for the current connection. + * + * \hideinitializer + */ +#define uip_restart() do { uip_flags |= UIP_NEWDATA; \ + uip_conn->tcpstateflags &= ~UIP_STOPPED; \ + } while(0) + + +/* uIP tests that can be made to determine in what state the current + connection is, and what the application function should do. */ + +/** + * Is new incoming data available? + * + * Will reduce to non-zero if there is new data for the application + * present at the uip_appdata pointer. The size of the data is + * avaliable through the uip_len variable. + * + * \hideinitializer + */ +#define uip_newdata() (uip_flags & UIP_NEWDATA) + +/** + * Has previously sent data been acknowledged? + * + * Will reduce to non-zero if the previously sent data has been + * acknowledged by the remote host. This means that the application + * can send new data. + * + * \hideinitializer + */ +#define uip_acked() (uip_flags & UIP_ACKDATA) + +/** + * Has the connection just been connected? + * + * Reduces to non-zero if the current connection has been connected to + * a remote host. This will happen both if the connection has been + * actively opened (with uip_connect()) or passively opened (with + * uip_listen()). + * + * \hideinitializer + */ +#define uip_connected() (uip_flags & UIP_CONNECTED) + +/** + * Has the connection been closed by the other end? + * + * Is non-zero if the connection has been closed by the remote + * host. The application may then do the necessary clean-ups. + * + * \hideinitializer + */ +#define uip_closed() (uip_flags & UIP_CLOSE) + +/** + * Has the connection been aborted by the other end? + * + * Non-zero if the current connection has been aborted (reset) by the + * remote host. + * + * \hideinitializer + */ +#define uip_aborted() (uip_flags & UIP_ABORT) + +/** + * Has the connection timed out? + * + * Non-zero if the current connection has been aborted due to too many + * retransmissions. + * + * \hideinitializer + */ +#define uip_timedout() (uip_flags & UIP_TIMEDOUT) + +/** + * Do we need to retransmit previously data? + * + * Reduces to non-zero if the previously sent data has been lost in + * the network, and the application should retransmit it. The + * application should send the exact same data as it did the last + * time, using the uip_send() function. + * + * \hideinitializer + */ +#define uip_rexmit() (uip_flags & UIP_REXMIT) + +/** + * Is the connection being polled by uIP? + * + * Is non-zero if the reason the application is invoked is that the + * current connection has been idle for a while and should be + * polled. + * + * The polling event can be used for sending data without having to + * wait for the remote host to send data. + * + * \hideinitializer + */ +#define uip_poll() (uip_flags & UIP_POLL) + +/** + * Get the initial maxium segment size (MSS) of the current + * connection. + * + * \hideinitializer + */ +#define uip_initialmss() (uip_conn->initialmss) + +/** + * Get the current maxium segment size that can be sent on the current + * connection. + * + * The current maxiumum segment size that can be sent on the + * connection is computed from the receiver's window and the MSS of + * the connection (which also is available by calling + * uip_initialmss()). + * + * \hideinitializer + */ +#define uip_mss() (uip_conn->mss) + +/** + * Set up a new UDP connection. + * + * \param ripaddr A pointer to a 4-byte structure representing the IP + * address of the remote host. + * + * \param rport The remote port number in network byte order. + * + * \return The uip_udp_conn structure for the new connection or NULL + * if no connection could be allocated. + */ +struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport); + +/** + * Removed a UDP connection. + * + * \param conn A pointer to the uip_udp_conn structure for the connection. + * + * \hideinitializer + */ +#define uip_udp_remove(conn) (conn)->lport = 0 + +/** + * Send a UDP datagram of length len on the current connection. + * + * This function can only be called in response to a UDP event (poll + * or newdata). The data must be present in the uip_buf buffer, at the + * place pointed to by the uip_appdata pointer. + * + * \param len The length of the data in the uip_buf buffer. + * + * \hideinitializer + */ +#define uip_udp_send(len) uip_slen = (len) + +/** @} */ + +/* uIP convenience and converting functions. */ + +/** + * \defgroup uipconvfunc uIP conversion functions + * @{ + * + * These functions can be used for converting between different data + * formats used by uIP. + */ + +/** + * Pack an IP address into a 4-byte array which is used by uIP to + * represent IP addresses. + * + * Example: + \code + u16_t ipaddr[2]; + + uip_ipaddr(&ipaddr, 192,168,1,2); + \endcode + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the IP addres. + * \param addr0 The first octet of the IP address. + * \param addr1 The second octet of the IP address. + * \param addr2 The third octet of the IP address. + * \param addr3 The forth octet of the IP address. + * + * \hideinitializer + */ +#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \ + (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \ + (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \ + } while(0) + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This macro is primarily used for converting constants from host + * byte order to network byte order. For converting variables to + * network byte order, use the htons() function instead. + * + * \hideinitializer + */ +#ifndef HTONS +# if BYTE_ORDER == BIG_ENDIAN +# define HTONS(n) (n) +# else /* BYTE_ORDER == BIG_ENDIAN */ +# define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8)) +# endif /* BYTE_ORDER == BIG_ENDIAN */ +#endif /* HTONS */ + +/** + * Convert 16-bit quantity from host byte order to network byte order. + * + * This function is primarily used for converting variables from host + * byte order to network byte order. For converting constants to + * network byte order, use the HTONS() macro instead. + */ +#ifndef htons +u16_t htons(u16_t val); +#endif /* htons */ + +/** @} */ + +/** + * Pointer to the application data in the packet buffer. + * + * This pointer points to the application data when the application is + * called. If the application wishes to send data, the application may + * use this space to write the data into before calling uip_send(). + */ +extern volatile u8_t *uip_appdata; +extern volatile u8_t *uip_sappdata; + +#if UIP_URGDATA > 0 +/* u8_t *uip_urgdata: + * + * This pointer points to any urgent data that has been received. Only + * present if compiled with support for urgent data (UIP_URGDATA). + */ +extern volatile u8_t *uip_urgdata; +#endif /* UIP_URGDATA > 0 */ + + +/* u[8|16]_t uip_len: + * + * When the application is called, uip_len contains the length of any + * new data that has been received from the remote host. The + * application should set this variable to the size of any data that + * the application wishes to send. When the network device driver + * output function is called, uip_len should contain the length of the + * outgoing packet. + */ +extern volatile u16_t uip_len, uip_slen; + +#if UIP_URGDATA > 0 +extern volatile u8_t uip_urglen, uip_surglen; +#endif /* UIP_URGDATA > 0 */ + + +/** + * Representation of a uIP TCP connection. + * + * The uip_conn structure is used for identifying a connection. All + * but one field in the structure are to be considered read-only by an + * application. The only exception is the appstate field whos purpose + * is to let the application store application-specific state (e.g., + * file pointers) for the connection. The size of this field is + * configured in the "uipopt.h" header file. + */ +struct uip_conn { + u16_t ripaddr[2]; /**< The IP address of the remote host. */ + + u16_t lport; /**< The local TCP port, in network byte order. */ + u16_t rport; /**< The local remote TCP port, in network byte + order. */ + + u8_t rcv_nxt[4]; /**< The sequence number that we expect to + receive next. */ + u8_t snd_nxt[4]; /**< The sequence number that was last sent by + us. */ + u16_t len; /**< Length of the data that was previously sent. */ + u16_t mss; /**< Current maximum segment size for the + connection. */ + u16_t initialmss; /**< Initial maximum segment size for the + connection. */ + u8_t sa; /**< Retransmission time-out calculation state + variable. */ + u8_t sv; /**< Retransmission time-out calculation state + variable. */ + u8_t rto; /**< Retransmission time-out. */ + u8_t tcpstateflags; /**< TCP state and flags. */ + u8_t timer; /**< The retransmission timer. */ + u8_t nrtx; /**< The number of retransmissions for the last + segment sent. */ + + /** The application state. */ + u8_t appstate[UIP_APPSTATE_SIZE]; +}; + + +/* Pointer to the current connection. */ +extern struct uip_conn *uip_conn; +/* The array containing all uIP connections. */ +extern struct uip_conn uip_conns[UIP_CONNS]; +/** + * \addtogroup uiparch + * @{ + */ + +/** + * 4-byte array used for the 32-bit sequence number calculations. + */ +extern volatile u8_t uip_acc32[4]; + +/** @} */ + + +#if UIP_UDP +/** + * Representation of a uIP UDP connection. + */ +struct uip_udp_conn { + u16_t ripaddr[2]; /**< The IP address of the remote peer. */ + u16_t lport; /**< The local port number in network byte order. */ + u16_t rport; /**< The remote port number in network byte order. */ +}; + +extern struct uip_udp_conn *uip_udp_conn; +extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS]; +#endif /* UIP_UDP */ + +/** + * The structure holding the TCP/IP statistics that are gathered if + * UIP_STATISTICS is set to 1. + * + */ +struct uip_stats { + struct { + uip_stats_t drop; /**< Number of dropped packets at the IP + layer. */ + uip_stats_t recv; /**< Number of received packets at the IP + layer. */ + uip_stats_t sent; /**< Number of sent packets at the IP + layer. */ + uip_stats_t vhlerr; /**< Number of packets dropped due to wrong + IP version or header length. */ + uip_stats_t hblenerr; /**< Number of packets dropped due to wrong + IP length, high byte. */ + uip_stats_t lblenerr; /**< Number of packets dropped due to wrong + IP length, low byte. */ + uip_stats_t fragerr; /**< Number of packets dropped since they + were IP fragments. */ + uip_stats_t chkerr; /**< Number of packets dropped due to IP + checksum errors. */ + uip_stats_t protoerr; /**< Number of packets dropped since they + were neither ICMP, UDP nor TCP. */ + } ip; /**< IP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped ICMP packets. */ + uip_stats_t recv; /**< Number of received ICMP packets. */ + uip_stats_t sent; /**< Number of sent ICMP packets. */ + uip_stats_t typeerr; /**< Number of ICMP packets with a wrong + type. */ + } icmp; /**< ICMP statistics. */ + struct { + uip_stats_t drop; /**< Number of dropped TCP segments. */ + uip_stats_t recv; /**< Number of recived TCP segments. */ + uip_stats_t sent; /**< Number of sent TCP segments. */ + uip_stats_t chkerr; /**< Number of TCP segments with a bad + checksum. */ + uip_stats_t ackerr; /**< Number of TCP segments with a bad ACK + number. */ + uip_stats_t rst; /**< Number of recevied TCP RST (reset) segments. */ + uip_stats_t rexmit; /**< Number of retransmitted TCP segments. */ + uip_stats_t syndrop; /**< Number of dropped SYNs due to too few + connections was avaliable. */ + uip_stats_t synrst; /**< Number of SYNs for closed ports, + triggering a RST. */ + } tcp; /**< TCP statistics. */ +}; + +/** + * The uIP TCP/IP statistics. + * + * This is the variable in which the uIP TCP/IP statistics are gathered. + */ +extern struct uip_stats uip_stat; + + +/*-----------------------------------------------------------------------------------*/ +/* All the stuff below this point is internal to uIP and should not be + * used directly by an application or by a device driver. + */ +/*-----------------------------------------------------------------------------------*/ +/* u8_t uip_flags: + * + * When the application is called, uip_flags will contain the flags + * that are defined in this file. Please read below for more + * infomation. + */ +extern volatile u8_t uip_flags; + +/* The following flags may be set in the global variable uip_flags + before calling the application callback. The UIP_ACKDATA and + UIP_NEWDATA flags may both be set at the same time, whereas the + others are mutualy exclusive. Note that these flags should *NOT* be + accessed directly, but through the uIP functions/macros. */ + +#define UIP_ACKDATA 1 /* Signifies that the outstanding data was + acked and the application should send + out new data instead of retransmitting + the last data. */ +#define UIP_NEWDATA 2 /* Flags the fact that the peer has sent + us new data. */ +#define UIP_REXMIT 4 /* Tells the application to retransmit the + data that was last sent. */ +#define UIP_POLL 8 /* Used for polling the application, to + check if the application has data that + it wants to send. */ +#define UIP_CLOSE 16 /* The remote host has closed the + connection, thus the connection has + gone away. Or the application signals + that it wants to close the + connection. */ +#define UIP_ABORT 32 /* The remote host has aborted the + connection, thus the connection has + gone away. Or the application signals + that it wants to abort the + connection. */ +#define UIP_CONNECTED 64 /* We have got a connection from a remote + host and have set up a new connection + for it, or an active connection has + been successfully established. */ + +#define UIP_TIMEDOUT 128 /* The connection has been aborted due to + too many retransmissions. */ + + +/* uip_process(flag): + * + * The actual uIP function which does all the work. + */ +void uip_process(u8_t flag); + +/* The following flags are passed as an argument to the uip_process() + function. They are used to distinguish between the two cases where + uip_process() is called. It can be called either because we have + incoming data that should be processed, or because the periodic + timer has fired. */ + +#define UIP_DATA 1 /* Tells uIP that there is incoming data in + the uip_buf buffer. The length of the + data is stored in the global variable + uip_len. */ +#define UIP_TIMER 2 /* Tells uIP that the periodic timer has + fired. */ +#if UIP_UDP +#define UIP_UDP_TIMER 3 +#endif /* UIP_UDP */ + +/* The TCP states used in the uip_conn->tcpstateflags. */ +#define CLOSED 0 +#define SYN_RCVD 1 +#define SYN_SENT 2 +#define ESTABLISHED 3 +#define FIN_WAIT_1 4 +#define FIN_WAIT_2 5 +#define CLOSING 6 +#define TIME_WAIT 7 +#define LAST_ACK 8 +#define TS_MASK 15 + +#define UIP_STOPPED 16 + +#define UIP_TCPIP_HLEN 40 + +/* The TCP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + + /* TCP header. */ + u16_t srcport, + destport; + u8_t seqno[4], + ackno[4], + tcpoffset, + flags, + wnd[2]; + u16_t tcpchksum; + u8_t urgp[2]; + u8_t optdata[4]; +} uip_tcpip_hdr; + +/* The ICMP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + /* ICMP (echo) header. */ + u8_t type, icode; + u16_t icmpchksum; + u16_t id, seqno; +} uip_icmpip_hdr; + + +/* The UDP and IP headers. */ +typedef struct { + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; + + /* UDP header. */ + u16_t srcport, + destport; + u16_t udplen; + u16_t udpchksum; +} uip_udpip_hdr; + +#define UIP_PROTO_ICMP 1 +#define UIP_PROTO_TCP 6 +#define UIP_PROTO_UDP 17 + +#if UIP_FIXEDADDR +extern const u16_t uip_hostaddr[2]; +#else /* UIP_FIXEDADDR */ +extern u16_t uip_hostaddr[2]; +#endif /* UIP_FIXEDADDR */ + +#endif /* __UIP_H__ */ + + +/** @} */ + diff --git a/u-boot/httpd/uip_arch.c b/u-boot/httpd/uip_arch.c new file mode 100755 index 0000000..cb3952b --- /dev/null +++ b/u-boot/httpd/uip_arch.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $ + * + */ + + +#include "uip.h" +#include "uip_arch.h" + +#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN]) +#define IP_PROTO_TCP 6 + +/*-----------------------------------------------------------------------------------*/ +void +uip_add32(u8_t *op32, u16_t op16) +{ + + uip_acc32[3] = op32[3] + (op16 & 0xff); + uip_acc32[2] = op32[2] + (op16 >> 8); + uip_acc32[1] = op32[1]; + uip_acc32[0] = op32[0]; + + if(uip_acc32[2] < (op16 >> 8)) { + ++uip_acc32[1]; + if(uip_acc32[1] == 0) { + ++uip_acc32[0]; + } + } + + + if(uip_acc32[3] < (op16 & 0xff)) { + ++uip_acc32[2]; + if(uip_acc32[2] == 0) { + ++uip_acc32[1]; + if(uip_acc32[1] == 0) { + ++uip_acc32[0]; + } + } + } +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_chksum(u16_t *sdata, u16_t len) +{ + u16_t acc; + + for(acc = 0; len > 1; len -= 2) { + acc += *sdata; + if(acc < *sdata) { + /* Overflow, so we add the carry to acc (i.e., increase by + one). */ + ++acc; + } + ++sdata; + } + + /* add up any odd byte */ + if(len == 1) { + acc += htons(((u16_t)(*(u8_t *)sdata)) << 8); + if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) { + ++acc; + } + } + + return acc; +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_ipchksum(void) +{ + return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20); +} +/*-----------------------------------------------------------------------------------*/ +u16_t +uip_tcpchksum(void) +{ + u16_t hsum, sum; + + + /* Compute the checksum of the TCP header. */ + hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20); + + /* Compute the checksum of the data in the TCP packet and add it to + the TCP header checksum. */ + sum = uip_chksum((u16_t *)uip_appdata, + (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40))); + + if((sum += hsum) < hsum) { + ++sum; + } + + if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) { + ++sum; + } + if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) { + ++sum; + } + if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) { + ++sum; + } + if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) { + ++sum; + } + if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) { + ++sum; + } + + hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20); + + if((sum += hsum) < hsum) { + ++sum; + } + + return sum; +} +/*-----------------------------------------------------------------------------------*/ diff --git a/u-boot/httpd/uip_arch.h b/u-boot/httpd/uip_arch.h new file mode 100755 index 0000000..947d84c --- /dev/null +++ b/u-boot/httpd/uip_arch.h @@ -0,0 +1,130 @@ +/** + * \defgroup uiparch Architecture specific uIP functions + * @{ + * + * The functions in the architecture specific module implement the IP + * check sum and 32-bit additions. + * + * The IP checksum calculation is the most computationally expensive + * operation in the TCP/IP stack and it therefore pays off to + * implement this in efficient assembler. The purpose of the uip-arch + * module is to let the checksum functions to be implemented in + * architecture specific assembler. + * + */ + +/** + * \file + * Declarations of architecture specific functions. + * \author Adam Dunkels + */ + +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $ + * + */ + +#ifndef __UIP_ARCH_H__ +#define __UIP_ARCH_H__ + +#include "uip.h" + +/** + * Carry out a 32-bit addition. + * + * Because not all architectures for which uIP is intended has native + * 32-bit arithmetic, uIP uses an external C function for doing the + * required 32-bit additions in the TCP protocol processing. This + * function should add the two arguments and place the result in the + * global variable uip_acc32. + * + * \note The 32-bit integer pointed to by the op32 parameter and the + * result in the uip_acc32 variable are in network byte order (big + * endian). + * + * \param op32 A pointer to a 4-byte array representing a 32-bit + * integer in network byte order (big endian). + * + * \param op16 A 16-bit integer in host byte order. + */ +void uip_add32(u8_t *op32, u16_t op16); + +/** + * Calculate the Internet checksum over a buffer. + * + * The Internet checksum is the one's complement of the one's + * complement sum of all 16-bit words in the buffer. + * + * See RFC1071. + * + * \note This function is not called in the current version of uIP, + * but future versions might make use of it. + * + * \param buf A pointer to the buffer over which the checksum is to be + * computed. + * + * \param len The length of the buffer over which the checksum is to + * be computed. + * + * \return The Internet checksum of the buffer. + */ +u16_t uip_chksum(u16_t *buf, u16_t len); + +/** + * Calculate the IP header checksum of the packet header in uip_buf. + * + * The IP header checksum is the Internet checksum of the 20 bytes of + * the IP header. + * + * \return The IP header checksum of the IP header in the uip_buf + * buffer. + */ +u16_t uip_ipchksum(void); + +/** + * Calculate the TCP checksum of the packet in uip_buf and uip_appdata. + * + * The TCP checksum is the Internet checksum of data contents of the + * TCP segment, and a pseudo-header as defined in RFC793. + * + * \note The uip_appdata pointer that points to the packet data may + * point anywhere in memory, so it is not possible to simply calculate + * the Internet checksum of the contents of the uip_buf buffer. + * + * \return The TCP checksum of the TCP segment in uip_buf and pointed + * to by uip_appdata. + */ +u16_t uip_tcpchksum(void); + +/** @} */ + +#endif /* __UIP_ARCH_H__ */ diff --git a/u-boot/httpd/uip_arp.c b/u-boot/httpd/uip_arp.c new file mode 100755 index 0000000..e531015 --- /dev/null +++ b/u-boot/httpd/uip_arp.c @@ -0,0 +1,421 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \defgroup uiparp uIP Address Resolution Protocol + * @{ + * + * The Address Resolution Protocol ARP is used for mapping between IP + * addresses and link level addresses such as the Ethernet MAC + * addresses. ARP uses broadcast queries to ask for the link level + * address of a known IP address and the host which is configured with + * the IP address for which the query was meant, will respond with its + * link level address. + * + * \note This ARP implementation only supports Ethernet. + */ + +/** + * \file + * Implementation of the ARP Address Resolution Protocol. + * \author Adam Dunkels + * + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $ + * + */ + + +#include "uip_arp.h" + +struct arp_hdr { + struct uip_eth_hdr ethhdr; + u16_t hwtype; + u16_t protocol; + u8_t hwlen; + u8_t protolen; + u16_t opcode; + struct uip_eth_addr shwaddr; + u16_t sipaddr[2]; + struct uip_eth_addr dhwaddr; + u16_t dipaddr[2]; +}; + +struct ethip_hdr { + struct uip_eth_hdr ethhdr; + /* IP header. */ + u8_t vhl, + tos, + len[2], + ipid[2], + ipoffset[2], + ttl, + proto; + u16_t ipchksum; + u16_t srcipaddr[2], + destipaddr[2]; +}; + +#define ARP_REQUEST 1 +#define ARP_REPLY 2 + +#define ARP_HWTYPE_ETH 1 + +struct arp_entry { + u16_t ipaddr[2]; + struct uip_eth_addr ethaddr; + u8_t time; +}; + +struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0, + UIP_ETHADDR1, + UIP_ETHADDR2, + UIP_ETHADDR3, + UIP_ETHADDR4, + UIP_ETHADDR5}}; + +static struct arp_entry arp_table[UIP_ARPTAB_SIZE]; +static u16_t ipaddr[2]; +static u8_t i, c; + +static u8_t arptime; +static u8_t tmpage; + +#define BUF ((struct arp_hdr *)&uip_buf[0]) +#define IPBUF ((struct ethip_hdr *)&uip_buf[0]) +/*-----------------------------------------------------------------------------------*/ +/** + * Initialize the ARP module. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_init(void) +{ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + memset(arp_table[i].ipaddr, 0, 4); + } +} +/*-----------------------------------------------------------------------------------*/ +/** + * Periodic ARP processing function. + * + * This function performs periodic timer processing in the ARP module + * and should be called at regular intervals. The recommended interval + * is 10 seconds between the calls. + * + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_timer(void) +{ + struct arp_entry *tabptr; + + ++arptime; + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 && + arptime - tabptr->time >= UIP_ARP_MAXAGE) { + memset(tabptr->ipaddr, 0, 4); + } + } + +} +/*-----------------------------------------------------------------------------------*/ +static void +uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr) +{ + register struct arp_entry *tabptr = 0; + /* Walk through the ARP mapping table and try to find an entry to + update. If none is found, the IP -> MAC address mapping is + inserted in the ARP table. */ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + + tabptr = &arp_table[i]; + /* Only check those entries that are actually in use. */ + if(tabptr->ipaddr[0] != 0 && + tabptr->ipaddr[1] != 0) { + + /* Check if the source IP address of the incoming packet matches + the IP address in this ARP table entry. */ + if(ipaddr[0] == tabptr->ipaddr[0] && + ipaddr[1] == tabptr->ipaddr[1]) { + + /* An old entry found, update this and return. */ + memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); + tabptr->time = arptime; + + return; + } + } + } + + /* If we get here, no existing ARP table entry was found, so we + create one. */ + + /* First, we try to find an unused entry in the ARP table. */ + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(tabptr->ipaddr[0] == 0 && + tabptr->ipaddr[1] == 0) { + break; + } + } + + /* If no unused entry is found, we try to find the oldest entry and + throw it away. */ + if(i == UIP_ARPTAB_SIZE) { + tmpage = 0; + c = 0; + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(arptime - tabptr->time > tmpage) { + tmpage = arptime - tabptr->time; + c = i; + } + } + i = c; + } + + /* Now, i is the ARP table entry which we will fill with the new + information. */ + memcpy(tabptr->ipaddr, ipaddr, 4); + memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6); + tabptr->time = arptime; +} +/*-----------------------------------------------------------------------------------*/ +/** + * ARP processing for incoming IP packets + * + * This function should be called by the device driver when an IP + * packet has been received. The function will check if the address is + * in the ARP cache, and if so the ARP cache entry will be + * refreshed. If no ARP cache entry was found, a new one is created. + * + * This function expects an IP packet with a prepended Ethernet header + * in the uip_buf[] buffer, and the length of the packet in the global + * variable uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_ipin(void) +{ + uip_len -= sizeof(struct uip_eth_hdr); + + /* Only insert/update an entry if the source IP address of the + incoming IP packet comes from a host on the local network. */ + if((IPBUF->srcipaddr[0] & uip_arp_netmask[0]) != + (uip_hostaddr[0] & uip_arp_netmask[0])) { + return; + } + if((IPBUF->srcipaddr[1] & uip_arp_netmask[1]) != + (uip_hostaddr[1] & uip_arp_netmask[1])) { + return; + } + uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src)); + + return; +} +/*-----------------------------------------------------------------------------------*/ +/** + * ARP processing for incoming ARP packets. + * + * This function should be called by the device driver when an ARP + * packet has been received. The function will act differently + * depending on the ARP packet type: if it is a reply for a request + * that we previously sent out, the ARP cache will be filled in with + * the values from the ARP reply. If the incoming ARP packet is an ARP + * request for our IP address, an ARP reply packet is created and put + * into the uip_buf[] buffer. + * + * When the function returns, the value of the global variable uip_len + * indicates whether the device driver should send out a packet or + * not. If uip_len is zero, no packet should be sent. If uip_len is + * non-zero, it contains the length of the outbound packet that is + * present in the uip_buf[] buffer. + * + * This function expects an ARP packet with a prepended Ethernet + * header in the uip_buf[] buffer, and the length of the packet in the + * global variable uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_arpin(void) +{ + + if(uip_len < sizeof(struct arp_hdr)) { + uip_len = 0; + return; + } + + uip_len = 0; + + switch(BUF->opcode) { + case HTONS(ARP_REQUEST): + /* ARP request. If it asked for our address, we send out a + reply. */ + if(BUF->dipaddr[0] == uip_hostaddr[0] && + BUF->dipaddr[1] == uip_hostaddr[1]) { + /* The reply opcode is 2. */ + BUF->opcode = HTONS(2); + + memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6); + memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); + memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6); + + BUF->dipaddr[0] = BUF->sipaddr[0]; + BUF->dipaddr[1] = BUF->sipaddr[1]; + BUF->sipaddr[0] = uip_hostaddr[0]; + BUF->sipaddr[1] = uip_hostaddr[1]; + + BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); + uip_len = sizeof(struct arp_hdr); + } + break; + case HTONS(ARP_REPLY): + /* ARP reply. We insert or update the ARP table if it was meant + for us. */ + if(BUF->dipaddr[0] == uip_hostaddr[0] && + BUF->dipaddr[1] == uip_hostaddr[1]) { + + uip_arp_update(BUF->sipaddr, &BUF->shwaddr); + } + break; + } + + return; +} +/*-----------------------------------------------------------------------------------*/ +/** + * Prepend Ethernet header to an outbound IP packet and see if we need + * to send out an ARP request. + * + * This function should be called before sending out an IP packet. The + * function checks the destination IP address of the IP packet to see + * what Ethernet MAC address that should be used as a destination MAC + * address on the Ethernet. + * + * If the destination IP address is in the local network (determined + * by logical ANDing of netmask and our IP address), the function + * checks the ARP cache to see if an entry for the destination IP + * address is found. If so, an Ethernet header is prepended and the + * function returns. If no ARP cache entry is found for the + * destination IP address, the packet in the uip_buf[] is replaced by + * an ARP request packet for the IP address. The IP packet is dropped + * and it is assumed that they higher level protocols (e.g., TCP) + * eventually will retransmit the dropped packet. + * + * If the destination IP address is not on the local network, the IP + * address of the default router is used instead. + * + * When the function returns, a packet is present in the uip_buf[] + * buffer, and the length of the packet is in the global variable + * uip_len. + */ +/*-----------------------------------------------------------------------------------*/ +void +uip_arp_out(void) +{ + struct arp_entry *tabptr = 0; + /* Find the destination IP address in the ARP table and construct + the Ethernet header. If the destination IP addres isn't on the + local network, we use the default router's IP address instead. + + If not ARP table entry is found, we overwrite the original IP + packet with an ARP request for the IP address. */ + + /* Check if the destination address is on the local network. */ + if((IPBUF->destipaddr[0] & uip_arp_netmask[0]) != + (uip_hostaddr[0] & uip_arp_netmask[0]) || + (IPBUF->destipaddr[1] & uip_arp_netmask[1]) != + (uip_hostaddr[1] & uip_arp_netmask[1])) { + /* Destination address was not on the local network, so we need to + use the default router's IP address instead of the destination + address when determining the MAC address. */ + ipaddr[0] = uip_arp_draddr[0]; + ipaddr[1] = uip_arp_draddr[1]; + } else { + /* Else, we use the destination IP address. */ + ipaddr[0] = IPBUF->destipaddr[0]; + ipaddr[1] = IPBUF->destipaddr[1]; + } + + for(i = 0; i < UIP_ARPTAB_SIZE; ++i) { + tabptr = &arp_table[i]; + if(ipaddr[0] == tabptr->ipaddr[0] && + ipaddr[1] == tabptr->ipaddr[1]) + break; + } + + if(i == UIP_ARPTAB_SIZE) { + /* The destination address was not in our ARP table, so we + overwrite the IP packet with an ARP request. */ + + memset(BUF->ethhdr.dest.addr, 0xff, 6); + memset(BUF->dhwaddr.addr, 0x00, 6); + memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6); + + BUF->dipaddr[0] = ipaddr[0]; + BUF->dipaddr[1] = ipaddr[1]; + BUF->sipaddr[0] = uip_hostaddr[0]; + BUF->sipaddr[1] = uip_hostaddr[1]; + BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */ + BUF->hwtype = HTONS(ARP_HWTYPE_ETH); + BUF->protocol = HTONS(UIP_ETHTYPE_IP); + BUF->hwlen = 6; + BUF->protolen = 4; + BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP); + + uip_appdata = &uip_buf[40 + UIP_LLH_LEN]; + + uip_len = sizeof(struct arp_hdr); + return; + } + + /* Build an ethernet header. */ + memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6); + memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6); + + IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP); + + uip_len += sizeof(struct uip_eth_hdr); +} +/*-----------------------------------------------------------------------------------*/ + +/** @} */ +/** @} */ diff --git a/u-boot/httpd/uip_arp.h b/u-boot/httpd/uip_arp.h new file mode 100755 index 0000000..0371cd6 --- /dev/null +++ b/u-boot/httpd/uip_arp.h @@ -0,0 +1,201 @@ +/** + * \addtogroup uip + * @{ + */ + +/** + * \addtogroup uiparp + * @{ + */ + +/** + * \file + * Macros and definitions for the ARP module. + * \author Adam Dunkels + */ + + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $ + * + */ + +#ifndef __UIP_ARP_H__ +#define __UIP_ARP_H__ + +#include "uip.h" + + +/** + * Representation of a 48-bit Ethernet address. + */ +struct uip_eth_addr { + u8_t addr[6]; +}; + +extern struct uip_eth_addr uip_ethaddr; + +/** + * The Ethernet header. + */ +struct uip_eth_hdr { + struct uip_eth_addr dest; + struct uip_eth_addr src; + u16_t type; +}; + +#define UIP_ETHTYPE_ARP 0x0806 +#define UIP_ETHTYPE_IP 0x0800 +#define UIP_ETHTYPE_IP6 0x86dd + + +/* The uip_arp_init() function must be called before any of the other + ARP functions. */ +void uip_arp_init(void); + +/* The uip_arp_ipin() function should be called whenever an IP packet + arrives from the Ethernet. This function refreshes the ARP table or + inserts a new mapping if none exists. The function assumes that an + IP packet with an Ethernet header is present in the uip_buf buffer + and that the length of the packet is in the uip_len variable. */ +void uip_arp_ipin(void); + +/* The uip_arp_arpin() should be called when an ARP packet is received + by the Ethernet driver. This function also assumes that the + Ethernet frame is present in the uip_buf buffer. When the + uip_arp_arpin() function returns, the contents of the uip_buf + buffer should be sent out on the Ethernet if the uip_len variable + is > 0. */ +void uip_arp_arpin(void); + +/* The uip_arp_out() function should be called when an IP packet + should be sent out on the Ethernet. This function creates an + Ethernet header before the IP header in the uip_buf buffer. The + Ethernet header will have the correct Ethernet MAC destination + address filled in if an ARP table entry for the destination IP + address (or the IP address of the default router) is present. If no + such table entry is found, the IP packet is overwritten with an ARP + request and we rely on TCP to retransmit the packet that was + overwritten. In any case, the uip_len variable holds the length of + the Ethernet frame that should be transmitted. */ +void uip_arp_out(void); + +/* The uip_arp_timer() function should be called every ten seconds. It + is responsible for flushing old entries in the ARP table. */ +void uip_arp_timer(void); + +/** @} */ + +/** + * \addtogroup uipconffunc + * @{ + */ + +/** + * Set the default router's IP address. + * + * \param addr A pointer to a 4-byte array containing the IP address + * of the default router. + * + * \hideinitializer + */ +#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \ + uip_arp_draddr[1] = addr[1]; } while(0) + +/** + * Set the netmask. + * + * \param addr A pointer to a 4-byte array containing the IP address + * of the netmask. + * + * \hideinitializer + */ +#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \ + uip_arp_netmask[1] = addr[1]; } while(0) + + +/** + * Get the default router's IP address. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the IP address of the default router. + * + * \hideinitializer + */ +#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \ + addr[1] = uip_arp_draddr[1]; } while(0) + +/** + * Get the netmask. + * + * \param addr A pointer to a 4-byte array that will be filled in with + * the value of the netmask. + * + * \hideinitializer + */ +#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \ + addr[1] = uip_arp_netmask[1]; } while(0) + + +/** + * Specifiy the Ethernet MAC address. + * + * The ARP code needs to know the MAC address of the Ethernet card in + * order to be able to respond to ARP queries and to generate working + * Ethernet headers. + * + * \note This macro only specifies the Ethernet MAC address to the ARP + * code. It cannot be used to change the MAC address of the Ethernet + * card. + * + * \param eaddr A pointer to a struct uip_eth_addr containing the + * Ethernet MAC address of the Ethernet card. + * + * \hideinitializer + */ +#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \ + uip_ethaddr.addr[1] = eaddr.addr[1];\ + uip_ethaddr.addr[2] = eaddr.addr[2];\ + uip_ethaddr.addr[3] = eaddr.addr[3];\ + uip_ethaddr.addr[4] = eaddr.addr[4];\ + uip_ethaddr.addr[5] = eaddr.addr[5];} while(0) + +/** @} */ + +/** + * \internal Internal variables that are set using the macros + * uip_setdraddr and uip_setnetmask. + */ +extern u16_t uip_arp_draddr[2], uip_arp_netmask[2]; +#endif /* __UIP_ARP_H__ */ + + diff --git a/u-boot/httpd/uipopt.h b/u-boot/httpd/uipopt.h new file mode 100755 index 0000000..77bafe7 --- /dev/null +++ b/u-boot/httpd/uipopt.h @@ -0,0 +1,559 @@ +/** + * \defgroup uipopt Configuration options for uIP + * @{ + * + * uIP is configured using the per-project configuration file + * "uipopt.h". This file contains all compile-time options for uIP and + * should be tweaked to match each specific project. The uIP + * distribution contains a documented example "uipopt.h" that can be + * copied and modified for each project. + */ + +/** + * \file + * Configuration options for uIP. + * \author Adam Dunkels + * + * This file is used for tweaking various configuration options for + * uIP. You should make a copy of this file into one of your project's + * directories instead of editing this example "uipopt.h" file that + * comes with the uIP distribution. + */ + +/* + * Copyright (c) 2001-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $ + * + */ + +#ifndef __UIPOPT_H__ +#define __UIPOPT_H__ + +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipopttypedef uIP type definitions + * @{ + */ + +/** + * The 8-bit unsigned data type. + * + * This may have to be tweaked for your particular compiler. "unsigned + * char" works for most compilers. + */ +typedef unsigned char u8_t; + +/** + * The 16-bit unsigned data type. + * + * This may have to be tweaked for your particular compiler. "unsigned + * short" works for most compilers. + */ +typedef unsigned short u16_t; + +/** + * The statistics data type. + * + * This datatype determines how high the statistics counters are able + * to count. + */ +typedef unsigned short uip_stats_t; + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptstaticconf Static configuration options + * @{ + * + * These configuration options can be used for setting the IP address + * settings statically, but only if UIP_FIXEDADDR is set to 1. The + * configuration options for a specific node includes IP address, + * netmask and default router as well as the Ethernet address. The + * netmask, default router and Ethernet address are appliciable only + * if uIP should be run over Ethernet. + * + * All of these should be changed to suit your project. +*/ + +/** + * Determines if uIP should use a fixed IP address or not. + * + * If uIP should use a fixed IP address, the settings are set in the + * uipopt.h file. If not, the macros uip_sethostaddr(), + * uip_setdraddr() and uip_setnetmask() should be used instead. + * + * \hideinitializer + */ +#define UIP_FIXEDADDR 0 + +/** + * Ping IP address asignment. + * + * uIP uses a "ping" packets for setting its own IP address if this + * option is set. If so, uIP will start with an empty IP address and + * the destination IP address of the first incoming "ping" (ICMP echo) + * packet will be used for setting the hosts IP address. + * + * \note This works only if UIP_FIXEDADDR is 0. + * + * \hideinitializer + */ +#define UIP_PINGADDRCONF 0 + +#define UIP_IPADDR0 192 /**< The first octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR1 168 /**< The second octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR2 0 /**< The third octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_IPADDR3 250 /**< The fourth octet of the IP address of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#define UIP_NETMASK0 255 /**< The first octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK1 255 /**< The second octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK2 255 /**< The third octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_NETMASK3 0 /**< The fourth octet of the netmask of + this uIP node, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +#define UIP_DRIPADDR0 192 /**< The first octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR1 168 /**< The second octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR2 0 /**< The third octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ +#define UIP_DRIPADDR3 1 /**< The fourth octet of the IP address of + the default router, if UIP_FIXEDADDR is + 1. \hideinitializer */ + +/** + * Specifies if the uIP ARP module should be compiled with a fixed + * Ethernet MAC address or not. + * + * If this configuration option is 0, the macro uip_setethaddr() can + * be used to specify the Ethernet address at run-time. + * + * \hideinitializer + */ +#define UIP_FIXEDETHADDR 0 + +#define UIP_ETHADDR0 0x00 /**< The first octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR1 0xbd /**< The second octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR2 0x3b /**< The third octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR3 0x33 /**< The fourth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR4 0x05 /**< The fifth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ +#define UIP_ETHADDR5 0x71 /**< The sixth octet of the Ethernet + address if UIP_FIXEDETHADDR is + 1. \hideinitializer */ + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptip IP configuration options + * @{ + * + */ +/** + * The IP TTL (time to live) of IP packets sent by uIP. + * + * This should normally not be changed. + */ +#define UIP_TTL 255 + +/** + * Turn on support for IP packet reassembly. + * + * uIP supports reassembly of fragmented IP packets. This features + * requires an additonal amount of RAM to hold the reassembly buffer + * and the reassembly code size is approximately 700 bytes. The + * reassembly buffer is of the same size as the uip_buf buffer + * (configured by UIP_BUFSIZE). + * + * \note IP packet reassembly is not heavily tested. + * + * \hideinitializer + */ +#define UIP_REASSEMBLY 0 + +/** + * The maximum time an IP fragment should wait in the reassembly + * buffer before it is dropped. + * + */ +#define UIP_REASS_MAXAGE 40 + +/** @} */ + +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptudp UDP configuration options + * @{ + * + * \note The UDP support in uIP is still not entirely complete; there + * is no support for sending or receiving broadcast or multicast + * packets, but it works well enough to support a number of vital + * applications such as DNS queries, though + */ + +/** + * Toggles wether UDP support should be compiled in or not. + * + * \hideinitializer + */ +#define UIP_UDP 0 + +/** + * Toggles if UDP checksums should be used or not. + * + * \note Support for UDP checksums is currently not included in uIP, + * so this option has no function. + * + * \hideinitializer + */ +#define UIP_UDP_CHECKSUMS 0 + +/** + * The maximum amount of concurrent UDP connections. + * + * \hideinitializer + */ +#define UIP_UDP_CONNS 10 + +/** + * The name of the function that should be called when UDP datagrams arrive. + * + * \hideinitializer + */ +#define UIP_UDP_APPCALL udp_appcall + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipopttcp TCP configuration options + * @{ + */ + +/** + * Determines if support for opening connections from uIP should be + * compiled in. + * + * If the applications that are running on top of uIP for this project + * do not need to open outgoing TCP connections, this configration + * option can be turned off to reduce the code size of uIP. + * + * \hideinitializer + */ +#define UIP_ACTIVE_OPEN 0 + +/** + * The maximum number of simultaneously open TCP connections. + * + * Since the TCP connections are statically allocated, turning this + * configuration knob down results in less RAM used. Each TCP + * connection requires approximatly 30 bytes of memory. + * + * \hideinitializer + */ +#define UIP_CONNS 2 + +/** + * The maximum number of simultaneously listening TCP ports. + * + * Each listening TCP port requires 2 bytes of memory. + * + * \hideinitializer + */ +#define UIP_LISTENPORTS 1 + +/** + * The size of the advertised receiver's window. + * + * Should be set low (i.e., to the size of the uip_buf buffer) is the + * application is slow to process incoming data, or high (32768 bytes) + * if the application processes data quickly. + * + * \hideinitializer + */ +//#define UIP_RECEIVE_WINDOW 32768 +#define UIP_RECEIVE_WINDOW 3000 + +/** + * Determines if support for TCP urgent data notification should be + * compiled in. + * + * Urgent data (out-of-band data) is a rarely used TCP feature that + * very seldom would be required. + * + * \hideinitializer + */ +//#define UIP_URGDATA 0 +#define UIP_URGDATA 1 + +/** + * The initial retransmission timeout counted in timer pulses. + * + * This should not be changed. + */ +#define UIP_RTO 3 + +/** + * The maximum number of times a segment should be retransmitted + * before the connection should be aborted. + * + * This should not be changed. + */ +#define UIP_MAXRTX 8 + +/** + * The maximum number of times a SYN segment should be retransmitted + * before a connection request should be deemed to have been + * unsuccessful. + * + * This should not need to be changed. + */ +#define UIP_MAXSYNRTX 3 + +/** + * The TCP maximum segment size. + * + * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40. + */ +#define UIP_TCP_MSS (UIP_BUFSIZE - UIP_LLH_LEN - 40) + +/** + * How long a connection should stay in the TIME_WAIT state. + * + * This configiration option has no real implication, and it should be + * left untouched. + */ +#define UIP_TIME_WAIT_TIMEOUT 120 + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptarp ARP configuration options + * @{ + */ + +/** + * The size of the ARP table. + * + * This option should be set to a larger value if this uIP node will + * have many connections from the local network. + * + * \hideinitializer + */ +#define UIP_ARPTAB_SIZE 2 + +/** + * The maxium age of ARP table entries measured in 10ths of seconds. + * + * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD + * default). + */ +#define UIP_ARP_MAXAGE 120 + +/** @} */ + +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptgeneral General configuration options + * @{ + */ + +/** + * The size of the uIP packet buffer. + * + * The uIP packet buffer should not be smaller than 60 bytes, and does + * not need to be larger than 1500 bytes. Lower size results in lower + * TCP throughput, larger size results in higher TCP throughput. + * + * \hideinitializer + */ +#define UIP_BUFSIZE 1500 + + +/** + * Determines if statistics support should be compiled in. + * + * The statistics is useful for debugging and to show the user. + * + * \hideinitializer + */ +#define UIP_STATISTICS 0 + +/** + * Determines if logging of certain events should be compiled in. + * + * This is useful mostly for debugging. The function uip_log() + * must be implemented to suit the architecture of the project, if + * logging is turned on. + * + * \hideinitializer + */ +#define UIP_LOGGING 0 + +/** + * Print out a uIP log message. + * + * This function must be implemented by the module that uses uIP, and + * is called by uIP whenever a log message is generated. + */ +void uip_log(char *msg); + +/** + * The link level header length. + * + * This is the offset into the uip_buf where the IP header can be + * found. For Ethernet, this should be set to 14. For SLIP, this + * should be set to 0. + * + * \hideinitializer + */ +#define UIP_LLH_LEN 14 + + +/** @} */ +/*------------------------------------------------------------------------------*/ +/** + * \defgroup uipoptcpu CPU architecture configuration + * @{ + * + * The CPU architecture configuration is where the endianess of the + * CPU on which uIP is to be run is specified. Most CPUs today are + * little endian, and the most notable exception are the Motorolas + * which are big endian. The BYTE_ORDER macro should be changed to + * reflect the CPU architecture on which uIP is to be run. + */ +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 3412 +#endif /* LITTLE_ENDIAN */ +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 1234 +#endif /* BIGE_ENDIAN */ + +/** + * The byte order of the CPU architecture on which uIP is to be run. + * + * This option can be either BIG_ENDIAN (Motorola byte order) or + * LITTLE_ENDIAN (Intel byte order). + * + * \hideinitializer + */ +/*#ifndef BYTE_ORDER*/ +#define BYTE_ORDER BIG_ENDIAN +/*#endif*/ /* BYTE_ORDER */ + +/** @} */ +/*------------------------------------------------------------------------------*/ + +/** + * \defgroup uipoptapp Appication specific configurations + * @{ + * + * An uIP application is implemented using a single application + * function that is called by uIP whenever a TCP/IP event occurs. The + * name of this function must be registered with uIP at compile time + * using the UIP_APPCALL definition. + * + * uIP applications can store the application state within the + * uip_conn structure by specifying the size of the application + * structure with the UIP_APPSTATE_SIZE macro. + * + * The file containing the definitions must be included in the + * uipopt.h file. + * + * The following example illustrates how this can look. + \code + +void httpd_appcall(void); +#define UIP_APPCALL httpd_appcall + +struct httpd_state { + u8_t state; + u16_t count; + char *dataptr; + char *script; +}; +#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state)) + \endcode + */ + +/** + * \var #define UIP_APPCALL + * + * The name of the application function that uIP should call in + * response to TCP/IP events. + * + */ + +/** + * \var #define UIP_APPSTATE_SIZE + * + * The size of the application state that is to be stored in the + * uip_conn structure. + */ +/** @} */ + +/* Include the header file for the application program that should be + used. If you don't use the example web server, you should change + this. */ +#include "httpd.h" + + +#endif /* __UIPOPT_H__ */ diff --git a/u-boot/include/LzmaWrapper.h b/u-boot/include/LzmaWrapper.h new file mode 100755 index 0000000..2f9a3ff --- /dev/null +++ b/u-boot/include/LzmaWrapper.h @@ -0,0 +1,36 @@ +/****************************************************************************** +** +** FILE NAME : LzmaWrapper.h +** PROJECT : bootloader +** MODULES : U-boot +** +** DATE : 2 Nov 2006 +** AUTHOR : Lin Mars +** DESCRIPTION : LZMA decoder support for U-boot 1.1.5 +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from +** LZMA v4.43 SDK +*******************************************************************************/ +#ifndef __LZMA_WRAPPER_H__ +#define __LZMA_WRAPPER_H__ + +#ifndef LZMA_RESULT_OK +#define LZMA_RESULT_OK 0 +#endif +#ifndef LZMA_RESULT_DATA_ERROR +#define LZMA_RESULT_DATA_ERROR 1 +#endif + +extern int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len); + +#endif /*__LZMA_WRAPPER_H__*/ diff --git a/u-boot/include/ar7240_soc.h b/u-boot/include/ar7240_soc.h new file mode 100755 index 0000000..7d9f006 --- /dev/null +++ b/u-boot/include/ar7240_soc.h @@ -0,0 +1,620 @@ +/* + * Atheror AR7240 series processor SOC registers + * + * (C) Copyright 2008 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _AR7240_SOC_H +#define _AR7240_SOC_H + +#include + +#ifdef CONFIG_WASP_SUPPORT +#include +#endif + +#ifdef CONFIG_AR7240_EMU +#define AR7240_EMU 1 +#endif + +#ifdef CONFIG_WASP_EMU +#define WASP_EMU 1 +#endif +/* + * Address map + */ +#define AR7240_PCI_MEM_BASE 0x10000000 /* 128M */ +#define AR7240_APB_BASE 0x18000000 /* 384M */ +#define AR7240_GE0_BASE 0x19000000 /* 16M */ +#define AR7240_GE1_BASE 0x1a000000 /* 16M */ +#define AR7240_USB_EHCI_BASE 0x1b000000 +#define AR7240_USB_OHCI_BASE 0x1c000000 +#define AR7240_SPI_BASE 0x1f000000 +#define ATH_NAND_FLASH_BASE 0x1b000000u + +/* + * APB block + */ +#define AR7240_DDR_CTL_BASE AR7240_APB_BASE+0x00000000 +#define AR7240_CPU_BASE AR7240_APB_BASE+0x00010000 +#define AR7240_UART_BASE AR7240_APB_BASE+0x00020000 +#define AR7240_USB_CONFIG_BASE AR7240_APB_BASE+0x00030000 +#define AR7240_GPIO_BASE AR7240_APB_BASE+0x00040000 +#define AR7240_PLL_BASE AR7240_APB_BASE+0x00050000 +#define AR7240_RESET_BASE AR7240_APB_BASE+0x00060000 +#define AR7240_PCI_LCL_BASE AR7240_APB_BASE+0x000f0000 + +/* + * DDR block + */ +#define AR7240_DDR_CONFIG AR7240_DDR_CTL_BASE+0 +#define AR7240_DDR_CONFIG2 AR7240_DDR_CTL_BASE+4 +#define AR7240_DDR_MODE AR7240_DDR_CTL_BASE+0x08 +#define AR7240_DDR_EXT_MODE AR7240_DDR_CTL_BASE+0x0c +#define AR7240_DDR_CONTROL AR7240_DDR_CTL_BASE+0x10 +#define AR7240_DDR_REFRESH AR7240_DDR_CTL_BASE+0x14 +#define AR7240_DDR_RD_DATA_THIS_CYCLE AR7240_DDR_CTL_BASE+0x18 +#define AR7240_DDR_TAP_CONTROL0 AR7240_DDR_CTL_BASE+0x1c +#define AR7240_DDR_TAP_CONTROL1 AR7240_DDR_CTL_BASE+0x20 +#define AR7240_DDR_TAP_CONTROL2 AR7240_DDR_CTL_BASE+0x24 +#define AR7240_DDR_TAP_CONTROL3 AR7240_DDR_CTL_BASE+0x28 + +#ifdef CONFIG_WASP +#define AR7240_DDR_DDR2_CONFIG AR7240_DDR_CTL_BASE+0xb8 +#else +#define AR7240_DDR_DDR2_CONFIG AR7240_DDR_CTL_BASE+0x8c +#endif + +#define AR7240_DDR_BURST AR7240_DDR_CTL_BASE+0xc4 +#define AR7240_DDR_BURST2 AR7240_DDR_CTL_BASE+0xc8 +#define AR7240_AHB_MASTER_TIMEOUT AR7240_DDR_CTL_BASE+0xcc +#define AR7240_DDR_CTL_CONFIG AR7240_DDR_CTL_BASE+0x108 +#define AR7240_DDR_DEBUG_RD_CNTL AR7240_DDR_CTL_BASE+0x118 + +#define AR7240_DDR_CONFIG_16BIT (1 << 31) +#define AR7240_DDR_CONFIG_PAGE_OPEN (1 << 30) +#define AR7240_DDR_CONFIG_CAS_LAT_SHIFT 27 +#define AR7240_DDR_CONFIG_TMRD_SHIFT 23 +#define AR7240_DDR_CONFIG_TRFC_SHIFT 17 +#define AR7240_DDR_CONFIG_TRRD_SHIFT 13 +#define AR7240_DDR_CONFIG_TRP_SHIFT 9 +#define AR7240_DDR_CONFIG_TRCD_SHIFT 5 +#define AR7240_DDR_CONFIG_TRAS_SHIFT 0 + +#define AR7240_DDR_CONFIG2_BL2 (2 << 0) +#define AR7240_DDR_CONFIG2_BL4 (4 << 0) +#define AR7240_DDR_CONFIG2_BL8 (8 << 0) + +#define AR7240_DDR_CONFIG2_BT_IL (1 << 4) +#define AR7240_DDR_CONFIG2_CNTL_OE_EN (1 << 5) +#define AR7240_DDR_CONFIG2_PHASE_SEL (1 << 6) +#define AR7240_DDR_CONFIG2_DRAM_CKE (1 << 7) +#define AR7240_DDR_CONFIG2_TWR_SHIFT 8 +#define AR7240_DDR_CONFIG2_TRTW_SHIFT 12 +#define AR7240_DDR_CONFIG2_TRTP_SHIFT 17 +#define AR7240_DDR_CONFIG2_TWTR_SHIFT 21 +#define AR7240_DDR_CONFIG2_HALF_WIDTH_L (1 << 31) + +#define AR7240_DDR_TAP_DEFAULT 0x18 + +/* + * PLL + */ +#define AR7240_CPU_PLL_CONFIG AR7240_PLL_BASE +#define AR7240_USB_PLL_CONFIG AR7240_PLL_BASE+0x4 +#define AR7240_PCIE_PLL_CONFIG AR7240_PLL_BASE+0x10 +#define AR7240_CPU_CLOCK_CONTROL AR7240_PLL_BASE+8 + +#ifndef CONFIG_WASP_SUPPORT +#define AR7240_USB_PLL_GE0_OFFSET AR7240_PLL_BASE+0x10 +#define AR7240_USB_PLL_GE1_OFFSET AR7240_PLL_BASE+0x14 +#define AR7240_S26_CLK_CTRL_OFFSET AR7240_PLL_BASE+0x24 +#endif + +#define AR7242_ETH_XMII_CONFIG AR7240_PLL_BASE+0x2c +#define AR934X_CPU_PLL_DITHER AR7240_PLL_BASE+0x0048 +#define AR934X_DDR_PLL_DITHER AR7240_PLL_BASE+0x0044 +#define AR934X_BB_PLL_CONFIG AR7240_PLL_BASE+0x0040 +#define AR934X_CURRENT_AUDIO_PLL_MODULATION AR7240_PLL_BASE+0x003c +#define AR934X_AUDIO_PLL_MOD_STEP AR7240_PLL_BASE+0x0038 +#define AR934X_AUDIO_PLL_MODULATION AR7240_PLL_BASE+0x0034 +#define AR934X_AUDIO_PLL_CONFIG AR7240_PLL_BASE+0x0030 +#define AR934X_ETH_XMII AR7240_PLL_BASE+0x002c +#define AR934X_CURRENT_PCIE_PLL_DITHER AR7240_PLL_BASE+0x0028 +#define AR934X_SWITCH_CLOCK_SPARE AR7240_PLL_BASE+0x0024 +#define AR934X_LDO_POWER_CONTROL AR7240_PLL_BASE+0x0020 +#define AR934X_PCIE_PLL_DITHER_STEP AR7240_PLL_BASE+0x001c +#define AR934X_PCIE_PLL_DITHER_DIV_MIN AR7240_PLL_BASE+0x0018 +#define AR934X_PCIE_PLL_DITHER_DIV_MAX AR7240_PLL_BASE+0x0014 +#define AR934X_PCIE_PLL_CONFIG AR7240_PLL_BASE+0x0010 +#define AR934X_CPU_SYNC AR7240_PLL_BASE+0x000c +#define AR934X_CPU_DDR_CLOCK_CONTROL AR7240_PLL_BASE+0x0008 +#define AR934X_DDR_PLL_CONFIG AR7240_PLL_BASE+0x0004 +#define AR934X_CPU_PLL_CONFIG AR7240_PLL_BASE+0x0000 + +#define PLL_CONFIG_PLL_DIV_SHIFT 0 +#define PLL_CONFIG_PLL_DIV_MASK (0x3ff<< PLL_CONFIG_PLL_DIV_SHIFT) +#define PLL_CONFIG_PLL_REF_DIV_SHIFT 10 +#define PLL_CONFIG_PLL_REF_DIV_MASK (0xf << PLL_CONFIG_PLL_REF_DIV_SHIFT) +#define PLL_CONFIG_PLL_BYPASS_SHIFT 16 +#define PLL_CONFIG_PLL_BYPASS_MASK (0x1 << PLL_CONFIG_PLL_BYPASS_SHIFT) +#define PLL_CONFIG_PLL_UPDATE_SHIFT 17 +#define PLL_CONFIG_PLL_UPDATE_MASK (0x1 << PLL_CONFIG_PLL_UPDATE_SHIFT) +#define PLL_CONFIG_PLL_NOPWD_SHIFT 18 +#define PLL_CONFIG_PLL_NOPWD_MASK (0x1 << PLL_CONFIG_PLL_NOPWD_SHIFT) +#define PLL_CONFIG_AHB_DIV_SHIFT 19 +#define PLL_CONFIG_AHB_DIV_MASK (0x1 << PLL_CONFIG_AHB_DIV_SHIFT) +#define PLL_CONFIG_DDR_DIV_SHIFT 22 +#define PLL_CONFIG_DDR_DIV_MASK (0x1 << PLL_CONFIG_DDR_DIV_SHIFT) +#define PLL_CONFIG_PLL_RESET_SHIFT 25 +#define PLL_CONFIG_PLL_RESET_MASK (0x1 << PLL_CONFIG_PLL_RESET_SHIFT) + +/* Hornet's CPU PLL Configuration Register */ +#define HORNET_PLL_CONFIG_NINT_SHIFT 10 +#define HORNET_PLL_CONFIG_NINT_MASK (0x3f << HORNET_PLL_CONFIG_NINT_SHIFT) +#define HORNET_PLL_CONFIG_REFDIV_SHIFT 16 +#define HORNET_PLL_CONFIG_REFDIV_MASK (0x1f << HORNET_PLL_CONFIG_REFDIV_SHIFT) +#define HORNET_PLL_CONFIG_OUTDIV_SHIFT 23 +#define HORNET_PLL_CONFIG_OUTDIV_MASK (0x7 << HORNET_PLL_CONFIG_OUTDIV_SHIFT) +#define HORNET_PLL_CONFIG_PLLPWD_SHIFT 30 +#define HORNET_PLL_CONFIG_PLLPWD_MASK (0x1 << HORNET_PLL_CONFIG_PLLPWD_SHIFT) +#define HORNET_PLL_CONFIG_UPDATING_SHIFT 31 +#define HORNET_PLL_CONFIG_UPDATING_MASK (0x1 << HORNET_PLL_CONFIG_UPDATING_SHIFT) + +/* Hornet's CPU PLL Configuration 2 Register */ +#define HORNET_PLL_CONFIG2_SETTLE_TIME_SHIFT 0 +#define HORNET_PLL_CONFIG2_SETTLE_TIME_MASK (0xfff << HORNET_PLL_CONFIG2_SETTLE_TIME_SHIFT) + +/* Hornet's CPU Clock Control Register */ +#define HORNET_CLOCK_CONTROL_BYPASS_SHIFT 2 +#define HORNET_CLOCK_CONTROL_BYPASS_MASK (0x1 << HORNET_CLOCK_CONTROL_BYPASS_SHIFT) +#define HORNET_CLOCK_CONTROL_CPU_POST_DIV_SHIFT 5 +#define HORNET_CLOCK_CONTROL_CPU_POST_DIV_MASK (0x3 << HORNET_CLOCK_CONTROL_CPU_POST_DIV_SHIFT) +#define HORNET_CLOCK_CONTROL_DDR_POST_DIV_SFIFT 10 +#define HORNET_CLOCK_CONTROL_DDR_POST_DIV_MASK (0x3 << HORNET_CLOCK_CONTROL_DDR_POST_DIV_SFIFT) +#define HORNET_CLOCK_CONTROL_AHB_POST_DIV_SFIFT 15 +#define HORNET_CLOCK_CONTROL_AHB_POST_DIV_MASK (0x3 << HORNET_CLOCK_CONTROL_AHB_POST_DIV_SFIFT) + +#define CLOCK_CONTROL_CLOCK_SWITCH_SHIFT 0 +#define CLOCK_CONTROL_CLOCK_SWITCH_MASK (1 << CLOCK_CONTROL_CLOCK_SWITCH_SHIFT) +#define CLOCK_CONTROL_RST_SWITCH_SHIFT 1 +#define CLOCK_CONTROL_RST_SWITCH_MASK (1 << CLOCK_CONTROL_RST_SWITCH_SHIFT) + +/* +** PLL config for different CPU/DDR/AHB frequencies +*/ +#define PLL_CONFIG_PLL_NOPWD_VAL (1 << PLL_CONFIG_PLL_NOPWD_SHIFT) + +#define UBOOT_SIZE (256 * 1024) +#define PLL_FLASH_ADDR (CFG_FLASH_BASE + UBOOT_SIZE) +#define PLL_CONFIG_VAL_F (PLL_FLASH_ADDR + CFG_FLASH_SECTOR_SIZE - 0x20) +#define PLL_MAGIC 0xaabbccdd +#define SRIF_PLL_CONFIG_VAL_F (PLL_CONFIG_VAL_F - 12) +#define SRIF_PLL_MAGIC 0x73726966 /* srif */ + +/* + * PLL block + */ +#define AR7240_PLL_CONFIG AR7240_PLL_BASE+0x0 + +/* + * CLOCK + */ +#define AR7240_CPU_CLOCK_CONTROL AR7240_PLL_BASE+8 + +/* + * FIFO flushes + */ +#define AR7240_DDR_GE0_FLUSH AR7240_DDR_CTL_BASE+0x9c +#define AR7240_DDR_GE1_FLUSH AR7240_DDR_CTL_BASE+0xa0 +#define AR7240_DDR_PCI_FLUSH AR7240_DDR_CTL_BASE+0xa8 + +/* + * USB block + */ +#define AR7240_USB_FLADJ_VAL AR7240_USB_CONFIG_BASE +#define AR7240_USB_CONFIG AR7240_USB_CONFIG_BASE+0x4 +#define AR7240_USB_WINDOW 0x1000000 + +/* + * PCI block + */ +#define AR7240_PCI_WINDOW 0x8000000 /* 128MB */ +#define AR7240_PCI_WINDOW0_OFFSET AR7240_DDR_CTL_BASE+0x7c +#define AR7240_PCI_WINDOW1_OFFSET AR7240_DDR_CTL_BASE+0x80 +#define AR7240_PCI_WINDOW2_OFFSET AR7240_DDR_CTL_BASE+0x84 +#define AR7240_PCI_WINDOW3_OFFSET AR7240_DDR_CTL_BASE+0x88 +#define AR7240_PCI_WINDOW4_OFFSET AR7240_DDR_CTL_BASE+0x8c +#define AR7240_PCI_WINDOW5_OFFSET AR7240_DDR_CTL_BASE+0x90 +#define AR7240_PCI_WINDOW6_OFFSET AR7240_DDR_CTL_BASE+0x94 +#define AR7240_PCI_WINDOW7_OFFSET AR7240_DDR_CTL_BASE+0x98 + +#define AR7240_PCI_WINDOW0_VAL 0x10000000 +#define AR7240_PCI_WINDOW1_VAL 0x11000000 +#define AR7240_PCI_WINDOW2_VAL 0x12000000 +#define AR7240_PCI_WINDOW3_VAL 0x13000000 +#define AR7240_PCI_WINDOW4_VAL 0x14000000 +#define AR7240_PCI_WINDOW5_VAL 0x15000000 +#define AR7240_PCI_WINDOW6_VAL 0x16000000 +#define AR7240_PCI_WINDOW7_VAL 0x07000000 + +/* + * CRP. To access the host controller config and status registers + */ +#define AR7240_PCI_CRP 0x180c0000 +#define AR7240_PCI_DEV_CFGBASE 0x14000000 + +#define AR7240_PCI_CRP_AD_CBE AR7240_PCI_CRP +#define AR7240_PCI_CRP_WRDATA AR7240_PCI_CRP+0x4 +#define AR7240_PCI_CRP_RDDATA AR7240_PCI_CRP+0x8 +#define AR7240_PCI_ERROR AR7240_PCI_CRP+0x1c +#define AR7240_PCI_ERROR_ADDRESS AR7240_PCI_CRP+0x20 +#define AR7240_PCI_AHB_ERROR AR7240_PCI_CRP+0x24 +#define AR7240_PCI_AHB_ERROR_ADDRESS AR7240_PCI_CRP+0x28 + +#define AR7240_CRP_CMD_WRITE 0x00010000 +#define AR7240_CRP_CMD_READ 0x00000000 + +/* + * PCI CFG. To generate config cycles + */ +#define AR7240_PCI_CFG_AD AR7240_PCI_CRP+0xc +#define AR7240_PCI_CFG_CBE AR7240_PCI_CRP+0x10 +#define AR7240_PCI_CFG_WRDATA AR7240_PCI_CRP+0x14 +#define AR7240_PCI_CFG_RDDATA AR7240_PCI_CRP+0x18 +#define AR7240_CFG_CMD_READ 0x0000000a +#define AR7240_CFG_CMD_WRITE 0x0000000b + +#define AR7240_PCI_IDSEL_ADLINE_START 17 +#define AR7240_PCI_LCL_RESET AR7240_PCI_LCL_BASE+0x18 + +/* + * gpio configs + */ +#define AR7240_GPIO_OE AR7240_GPIO_BASE+0x0 +#define AR7240_GPIO_IN AR7240_GPIO_BASE+0x4 +#define AR7240_GPIO_OUT AR7240_GPIO_BASE+0x8 +#define AR7240_GPIO_SET AR7240_GPIO_BASE+0xc +#define AR7240_GPIO_CLEAR AR7240_GPIO_BASE+0x10 +#define AR7240_GPIO_INT_ENABLE AR7240_GPIO_BASE+0x14 +#define AR7240_GPIO_INT_TYPE AR7240_GPIO_BASE+0x18 +#define AR7240_GPIO_INT_POLARITY AR7240_GPIO_BASE+0x1c +#define AR7240_GPIO_INT_PENDING AR7240_GPIO_BASE+0x20 +#define AR7240_GPIO_INT_MASK AR7240_GPIO_BASE+0x24 +#define AR7240_GPIO_FUNC AR7240_GPIO_BASE+0x28 + +/* + * IRQ Map. + * There are 4 conceptual ICs in the system. We generally give a block of 16 + * irqs to each IC. + * CPU: 0 - 0xf + * MISC: 0x10 - 0x1f + * GPIO: 0x20 - 0x2f + * PCI : 0x30 - 0x40 + * + */ +#define AR7240_CPU_IRQ_BASE 0x00 +#define AR7240_MISC_IRQ_BASE 0x10 +#define AR7240_GPIO_IRQ_BASE 0x20 +#define AR7240_PCI_IRQ_BASE 0x30 + +/* + * The IPs. Connected to CPU (hardware IP's; the first two are software) + */ +#define AR7240_CPU_IRQ_PCI AR7240_CPU_IRQ_BASE+2 +#define AR7240_CPU_IRQ_USB AR7240_CPU_IRQ_BASE+3 +#define AR7240_CPU_IRQ_GE0 AR7240_CPU_IRQ_BASE+4 +#define AR7240_CPU_IRQ_GE1 AR7240_CPU_IRQ_BASE+5 +#define AR7240_CPU_IRQ_MISC AR7240_CPU_IRQ_BASE+6 +#define AR7240_CPU_IRQ_TIMER AR7240_CPU_IRQ_BASE+7 + +/* + * Interrupts connected to the CPU->Misc line. + */ +#define AR7240_MISC_IRQ_TIMER AR7240_MISC_IRQ_BASE+0 +#define AR7240_MISC_IRQ_ERROR AR7240_MISC_IRQ_BASE+1 +#define AR7240_MISC_IRQ_GPIO AR7240_MISC_IRQ_BASE+2 +#define AR7240_MISC_IRQ_UART AR7240_MISC_IRQ_BASE+3 +#define AR7240_MISC_IRQ_WATCHDOG AR7240_MISC_IRQ_BASE+4 +#define AR7240_MISC_IRQ_COUNT 5 + +#define MIMR_TIMER 0x01 +#define MIMR_ERROR 0x02 +#define MIMR_GPIO 0x04 +#define MIMR_UART 0x08 +#define MIMR_WATCHDOG 0x10 + +#define MISR_TIMER MIMR_TIMER +#define MISR_ERROR MIMR_ERROR +#define MISR_GPIO MIMR_GPIO +#define MISR_UART MIMR_UART +#define MISR_WATCHDOG MIMR_WATCHDOG + +/* + * Interrupts connected to the Misc->GPIO line + */ +#define AR7240_GPIO_IRQn(_gpio) AR7240_GPIO_IRQ_BASE+(_gpio) +#define AR7240_GPIO_IRQ_COUNT 16 + +/* + * Interrupts connected to CPU->PCI + */ +#define AR7240_PCI_IRQ_DEV0 AR7240_PCI_IRQ_BASE+0 +#define AR7240_PCI_IRQ_DEV1 AR7240_PCI_IRQ_BASE+1 +#define AR7240_PCI_IRQ_DEV2 AR7240_PCI_IRQ_BASE+2 +#define AR7240_PCI_IRQ_CORE AR7240_PCI_IRQ_BASE+3 +#define AR7240_PCI_IRQ_COUNT 4 + +/* + * PCI interrupt mask and status + */ +#define PIMR_DEV0 0x01 +#define PIMR_DEV1 0x02 +#define PIMR_DEV2 0x04 +#define PIMR_CORE 0x10 + +#define PISR_DEV0 PIMR_DEV0 +#define PISR_DEV1 PIMR_DEV1 +#define PISR_DEV2 PIMR_DEV2 +#define PISR_CORE PIMR_CORE + +#define AR7240_GPIO_COUNT 16 + +/* + * Reset block + */ +#define AR7240_GENERAL_TMR AR7240_RESET_BASE+0 +#define AR7240_GENERAL_TMR_RELOAD AR7240_RESET_BASE+4 +#define AR7240_WATCHDOG_TMR_CONTROL AR7240_RESET_BASE+8 +#define AR7240_WATCHDOG_TMR AR7240_RESET_BASE+0xc +#define AR7240_MISC_INT_STATUS AR7240_RESET_BASE+0x10 +#define AR7240_MISC_INT_MASK AR7240_RESET_BASE+0x14 +#define AR7240_GLOBAL_INT_STATUS AR7240_RESET_BASE+0x18 +#define AR7240_RESET AR7240_RESET_BASE+0x1c +#define HORNET_BOOTSTRAP_STATUS AR7240_RESET_BASE+0xac /* Hornet's bootstrap register */ +#define AR7240_REV_ID (AR7240_RESET_BASE + 0x90) +#define AR7240_REV_ID_MASK 0xffff +#define HORNET_REV_ID_MASK 0xfff +#define AR9344_REV_ID_MASK 0xfff0 /* Ignore minor id */ +#define HORNET_BOOTSTRAP_SEL_25M_40M_MASK 0x00000001 /* Hornet's bootstrap register */ +#define HORNET_BOOTSTRAP_MEM_TYPE_MASK 0x00003000 /* Hornet's bootstrap register */ +#define HORNET_BOOTSTRAP_MDIO_SLAVE_MASK 0x00020000 /* Hornet's bootstrap register */ + +// WASP BootStrap Register +#define WASP_BOOTSTRAP_REG (AR7240_RESET_BASE + 0xb0) +#define WASP_REF_CLK_25 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ +#define WASP_RAM_TYPE(a) ((a) & 0x3) + +#define CFG_934X_SDRAM_CONFIG_VAL 0x7fbe8cd0 +#define CFG_934X_SDRAM_MODE_VAL_INIT 0x133 +#define CFG_934X_SDRAM_MODE_VAL 0x33 +#define CFG_934X_SDRAM_CONFIG2_VAL 0x959f66a8 +#define CFG_934X_SDRAM_TAP_VAL 0x1f1f + +#define CFG_934X_DDR1_CONFIG_VAL 0x7fd48cd0 // 0xc7d48cd0 +#define CFG_934X_DDR1_MODE_VAL_INIT 0x133 +#define CFG_934X_DDR1_EXT_MODE_VAL 0x2 // 0x0 +#define CFG_934X_DDR1_MODE_VAL 0x33 +#define CFG_934X_DDR1_CONFIG2_VAL 0x99d0e6a8 // 0x9dd0e6a8 + +#if (CFG_PLL_FREQ == CFG_PLL_500_500_250) +#define CFG_934X_DDR2_CONFIG_VAL 0xcfbc8cd0 +#define CFG_934X_DDR2_MODE_VAL_INIT 0x143 +#define CFG_934X_DDR2_EXT_MODE_VAL 0x402 +#define CFG_934X_DDR2_MODE_VAL 0x43 +#define CFG_934X_DDR2_CONFIG2_VAL 0xa5d0e6a8 +#define CFG_934X_DDR2_EN_TWL_VAL 0x1659 +#define CFG_934X_DDR2_TAP_VAL 0 +#elif (CFG_PLL_FREQ == CFG_PLL_650_600_300) || \ + (CFG_PLL_FREQ == CFG_PLL_600_600_300) || \ + (CFG_PLL_FREQ == CFG_PLL_600_550_275) || \ + (CFG_PLL_FREQ == CFG_PLL_600_575_287) + +#define CFG_934X_DDR2_CONFIG_VAL 0xcfd48cd0 +#define CFG_934X_DDR2_MODE_VAL_INIT 0x143 +#define CFG_934X_DDR2_EXT_MODE_VAL 0x402 +#define CFG_934X_DDR2_MODE_VAL 0x43 +#define CFG_934X_DDR2_CONFIG2_VAL 0xa1d0e6a8 +#define CFG_934X_DDR2_EN_TWL_VAL 0x1659 +#define CFG_934X_DDR2_TAP_VAL 0x5 +#else +/* +* Date: 2011-030-24 +* Name: Charles Teng +* Reason: patch from LSDK-9.2.0.312 +*/ +#define CFG_934X_DDR2_CONFIG_VAL 0xc7d48cd0 +#define CFG_934X_DDR2_MODE_VAL_INIT 0x133 +#define CFG_934X_DDR2_EXT_MODE_VAL_INIT 0x382 +#define CFG_934X_DDR2_EXT_MODE_VAL 0x402 +#define CFG_934X_DDR2_MODE_VAL 0x33 +#define CFG_934X_DDR2_CONFIG2_VAL 0x9dd0e6a8 +#define CFG_934X_DDR2_EN_TWL_VAL 0xe59 +#define CFG_934X_DDR2_TAP_VAL 0x10012 +#endif + +#define CFG_934X_DDR1_TAP_VAL 0x14 + +#define AR7240_REV_ID_AR7130 0xa0 +#define AR7240_REV_ID_AR7141 0xa1 +#define AR7240_REV_ID_AR7161 0xa2 +#define AR7240_REV_1_0 0xc0 +#define AR7240_REV_1_1 0xc1 +#define AR7240_REV_1_2 0xc2 +#define AR7241_REV_1_0 0x0100 +#define AR7242_REV_1_0 0x1100 +#define AR7241_REV_1_1 0x0101 +#define AR7242_REV_1_1 0x1101 + +#define AR9330_REV_1_0 0x0110 /* 5-port:0x110, 4-port 0x1110 */ +#define AR9331_REV_1_0 0x1110 +#define AR9330_REV_1_1 0x0111 /* 5-port:0x111, 4-port 0x1111 */ +#define AR9331_REV_1_1 0x1111 +#define AR9330_REV_1_2 0x0112 +#define AR9331_REV_1_2 0x1112 + +#define AR9344_REV_1_x 0x2120 /* Wasp 1.x, ignore minor id */ +#define AR9342_REV_1_x 0x1120 +#define AR9341_REV_1_x 0x0120 + +#define AR9344_REV_1_0 0x2120 /* Wasp 1.0 */ +#define AR9342_REV_1_0 0x1120 +#define AR9341_REV_1_0 0x0120 + +#define AR9344_REV_1_1 0x2121 /* Wasp 1.1 */ +#define AR9342_REV_1_1 0x1121 +#define AR9341_REV_1_1 0x0121 + +#define is_ar7240() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_1) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_0)) + +#define is_ar7241() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7241_REV_1_0) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7241_REV_1_1)) + +#define is_ar7242() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7242_REV_1_0) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7242_REV_1_1)) + +#define is_ar9330() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_0) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_1) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_2)) + +#define is_ar9331() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_0) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_1) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_2)) + +#define is_ar933x_10() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_0) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_0)) + +#define is_ar933x_11() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_1) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_1)) + +#define is_ar933x_12() (((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9330_REV_1_2) || \ + ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR9331_REV_1_2)) + + +#define is_ar933x() (is_ar9330() || is_ar9331()) + +#define is_ar9344() ((ar7240_reg_rd(AR7240_REV_ID) & AR9344_REV_ID_MASK) == AR9344_REV_1_x) +#define is_ar9342() ((ar7240_reg_rd(AR7240_REV_ID) & AR9344_REV_ID_MASK) == AR9342_REV_1_x) +#define is_ar9341() ((ar7240_reg_rd(AR7240_REV_ID) & AR9344_REV_ID_MASK) == AR9341_REV_1_x) + +#ifdef CONFIG_WASP_SUPPORT + #define is_wasp() 1 + #define is_ar934x() 1 +#else + #define is_wasp() 0 + #define is_ar934x() 0 +#endif + +#ifdef CONFIG_AR7240_EMU + #define is_emu() 1 +#else + #define is_emu() 0 +#endif + +#ifdef CONFIG_F1E_PHY + #define is_f1e() 1 +#else + #define is_f1e() 0 +#endif + +#ifdef CONFIG_F2E_PHY + #define is_f2e() 1 +#else + #define is_f2e() 0 +#endif + +#ifdef CONFIG_ATHRS16_PHY + #define is_s16() 1 +#else + #define is_s16() 0 +#endif + +/* + * AR7240_RESET bit defines + */ +#define AR7240_RESET_EXTERNAL (1 << 28) +#define AR7240_RESET_WMAC (1 << 27) +#define AR7240_RESET_FULL_CHIP (1 << 24) +#define AR7240_RESET_CPU_NMI (1 << 21) +#define AR7240_RESET_CPU_COLD_RESET_MASK (1 << 20) +#define AR7240_RESET_DDR (1 << 16) +#define AR7240_RESET_GE1_MAC (1 << 13) +#define AR7240_RESET_GE1_MDIO (1 << 23) +#define AR7240_RESET_GE1_PHY (1 << 12) /* Not valid */ +#define AR7240_RESET_PCIE_PHY_SERIAL (1 << 10) +#define AR7240_RESET_GE0_MAC (1 << 9) +#define AR7240_RESET_GE0_MDIO (1 << 22) +#define AR7240_RESET_GE0_PHY (1 << 8) /* Switch reset */ +#define AR7240_RESET_PCIE_PHY (1 << 7) +#define AR7240_RESET_PCIE (1 << 6) +#define AR7240_RESET_USB_HOST (1 << 5) +#define AR7240_RESET_USB_OHCI_DLL (1 << 3) + +#define AR7240_MII0_CTRL 0x18070000 +#define AR7240_MII1_CTRL 0x18070004 + +#define K1BASE KSEG1 + +#ifndef __ASSEMBLY__ +typedef enum { + AR7240_DDR_16B_LOW, + AR7240_DDR_16B_HIGH, + AR7240_DDR_32B, +}ar7240_ddr_width_t; + +#define ar7240_reg_rd(_phys) (*(volatile unsigned int *)KSEG1ADDR(_phys)) +#define ar7240_reg_wr_nf(_phys, _val) ((*(volatile unsigned int *)KSEG1ADDR(_phys)) = (_val)) + +#define ar7240_reg_wr(_phys, _val) do { ar7240_reg_wr_nf(_phys, _val); ar7240_reg_rd(_phys); } while(0); + +#define ar7240_write_pci_window(_no) \ + ar7240_reg_wr(AR7240_PCI_WINDOW##_no##_OFFSET, AR7240_PCI_WINDOW##_no##_VAL); + +#define BIT(_x) (1 << (_x)) + +#define ar7240_reg_rmw_set(_reg, _mask) do { \ + ar7240_reg_wr((_reg), (ar7240_reg_rd((_reg)) | (_mask))); \ + ar7240_reg_rd((_reg)); \ +}while(0); + +#define ar7240_reg_rmw_clear(_reg, _mask) do { \ + ar7240_reg_wr((_reg), (ar7240_reg_rd((_reg)) & ~(_mask))); \ + ar7240_reg_rd((_reg)); \ +}while(0); + +#define ar7240_get_bit(_reg, _bit) (ar7240_reg_rd((_reg)) & (1 << (_bit))) + +#define ar7240_flush_ge(_unit) do { \ + u32 reg = (_unit) ? AR7240_DDR_GE1_FLUSH : AR7240_DDR_GE0_FLUSH; \ + ar7240_reg_wr(reg, 1); \ + while((ar7240_reg_rd(reg) & 0x1)); \ + ar7240_reg_wr(reg, 1); \ + while((ar7240_reg_rd(reg) & 0x1)); \ +}while(0); + +#define ar7240_flush_pci() do { \ + ar7240_reg_wr(AR7240_DDR_PCI_FLUSH, 1); \ + while((ar7240_reg_rd(AR7240_DDR_PCI_FLUSH) & 0x1)); \ + ar7240_reg_wr(AR7240_DDR_PCI_FLUSH, 1); \ + while((ar7240_reg_rd(AR7240_DDR_PCI_FLUSH) & 0x1)); \ +}while(0); + +#endif /*__ASSEMBLY*/ +#endif diff --git a/u-boot/include/ar934x_soc.h b/u-boot/include/ar934x_soc.h new file mode 100755 index 0000000..b412cfc --- /dev/null +++ b/u-boot/include/ar934x_soc.h @@ -0,0 +1,2785 @@ +/* + * Atheros AR924X series processor SOC registers + * + * (C) Copyright 2008 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _AR934X_SOC_H +#define _AR934X_SOC_H + +// 32'h0000 (CPU_PLL_CONFIG) +#define CPU_PLL_CONFIG_UPDATING_MSB 31 +#define CPU_PLL_CONFIG_UPDATING_LSB 31 +#define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define CPU_PLL_CONFIG_UPDATING_GET(x) (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB) +#define CPU_PLL_CONFIG_UPDATING_SET(x) (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK) +#define CPU_PLL_CONFIG_UPDATING_RESET 1 +#define CPU_PLL_CONFIG_PLLPWD_MSB 30 +#define CPU_PLL_CONFIG_PLLPWD_LSB 30 +#define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000 +#define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB) +#define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK) +#define CPU_PLL_CONFIG_PLLPWD_RESET 1 +#define CPU_PLL_CONFIG_SPARE_MSB 29 +#define CPU_PLL_CONFIG_SPARE_LSB 22 +#define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000 +#define CPU_PLL_CONFIG_SPARE_GET(x) (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB) +#define CPU_PLL_CONFIG_SPARE_SET(x) (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK) +#define CPU_PLL_CONFIG_SPARE_RESET 0 +#define CPU_PLL_CONFIG_OUTDIV_MSB 21 +#define CPU_PLL_CONFIG_OUTDIV_LSB 19 +#define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000 +#define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB) +#define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK) +#define CPU_PLL_CONFIG_OUTDIV_RESET 0 +#define CPU_PLL_CONFIG_RANGE_MSB 18 +#define CPU_PLL_CONFIG_RANGE_LSB 17 +#define CPU_PLL_CONFIG_RANGE_MASK 0x00060000 +#define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB) +#define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK) +#define CPU_PLL_CONFIG_RANGE_RESET 3 +#define CPU_PLL_CONFIG_REFDIV_MSB 16 +#define CPU_PLL_CONFIG_REFDIV_LSB 12 +#define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000 +#define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB) +#define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK) +#define CPU_PLL_CONFIG_REFDIV_RESET 2 +#define CPU_PLL_CONFIG_NINT_MSB 11 +#define CPU_PLL_CONFIG_NINT_LSB 6 +#define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0 +#define CPU_PLL_CONFIG_NINT_GET(x) (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB) +#define CPU_PLL_CONFIG_NINT_SET(x) (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK) +#define CPU_PLL_CONFIG_NINT_RESET 20 +#define CPU_PLL_CONFIG_NFRAC_MSB 5 +#define CPU_PLL_CONFIG_NFRAC_LSB 0 +#define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f +#define CPU_PLL_CONFIG_NFRAC_GET(x) (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB) +#define CPU_PLL_CONFIG_NFRAC_SET(x) (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK) +#define CPU_PLL_CONFIG_NFRAC_RESET 16 +#define CPU_PLL_CONFIG_ADDRESS 0x0000 +#define CPU_PLL_CONFIG_OFFSET 0x0000 +// SW modifiable bits +#define CPU_PLL_CONFIG_SW_MASK 0xffffffff +// bits defined at reset +#define CPU_PLL_CONFIG_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define CPU_PLL_CONFIG_RESET 0xc0062510 + +// 32'h0004 (DDR_PLL_CONFIG) +#define DDR_PLL_CONFIG_UPDATING_MSB 31 +#define DDR_PLL_CONFIG_UPDATING_LSB 31 +#define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define DDR_PLL_CONFIG_UPDATING_GET(x) (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB) +#define DDR_PLL_CONFIG_UPDATING_SET(x) (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK) +#define DDR_PLL_CONFIG_UPDATING_RESET 1 +#define DDR_PLL_CONFIG_PLLPWD_MSB 30 +#define DDR_PLL_CONFIG_PLLPWD_LSB 30 +#define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000 +#define DDR_PLL_CONFIG_PLLPWD_GET(x) (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB) +#define DDR_PLL_CONFIG_PLLPWD_SET(x) (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK) +#define DDR_PLL_CONFIG_PLLPWD_RESET 1 +#define DDR_PLL_CONFIG_SPARE_MSB 29 +#define DDR_PLL_CONFIG_SPARE_LSB 26 +#define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000 +#define DDR_PLL_CONFIG_SPARE_GET(x) (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB) +#define DDR_PLL_CONFIG_SPARE_SET(x) (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK) +#define DDR_PLL_CONFIG_SPARE_RESET 0 +#define DDR_PLL_CONFIG_OUTDIV_MSB 25 +#define DDR_PLL_CONFIG_OUTDIV_LSB 23 +#define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000 +#define DDR_PLL_CONFIG_OUTDIV_GET(x) (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB) +#define DDR_PLL_CONFIG_OUTDIV_SET(x) (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK) +#define DDR_PLL_CONFIG_OUTDIV_RESET 0 +#define DDR_PLL_CONFIG_RANGE_MSB 22 +#define DDR_PLL_CONFIG_RANGE_LSB 21 +#define DDR_PLL_CONFIG_RANGE_MASK 0x00600000 +#define DDR_PLL_CONFIG_RANGE_GET(x) (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB) +#define DDR_PLL_CONFIG_RANGE_SET(x) (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK) +#define DDR_PLL_CONFIG_RANGE_RESET 3 +#define DDR_PLL_CONFIG_REFDIV_MSB 20 +#define DDR_PLL_CONFIG_REFDIV_LSB 16 +#define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000 +#define DDR_PLL_CONFIG_REFDIV_GET(x) (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB) +#define DDR_PLL_CONFIG_REFDIV_SET(x) (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK) +#define DDR_PLL_CONFIG_REFDIV_RESET 2 +#define DDR_PLL_CONFIG_NINT_MSB 15 +#define DDR_PLL_CONFIG_NINT_LSB 10 +#define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00 +#define DDR_PLL_CONFIG_NINT_GET(x) (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB) +#define DDR_PLL_CONFIG_NINT_SET(x) (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK) +#define DDR_PLL_CONFIG_NINT_RESET 20 +#define DDR_PLL_CONFIG_NFRAC_MSB 9 +#define DDR_PLL_CONFIG_NFRAC_LSB 0 +#define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff +#define DDR_PLL_CONFIG_NFRAC_GET(x) (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB) +#define DDR_PLL_CONFIG_NFRAC_SET(x) (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK) +#define DDR_PLL_CONFIG_NFRAC_RESET 512 +#define DDR_PLL_CONFIG_ADDRESS 0x0004 +#define DDR_PLL_CONFIG_OFFSET 0x0004 +// SW modifiable bits +#define DDR_PLL_CONFIG_SW_MASK 0xffffffff +// bits defined at reset +#define DDR_PLL_CONFIG_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define DDR_PLL_CONFIG_RESET 0xc0625200 + +// 32'h0008 (CPU_DDR_CLOCK_CONTROL) +#define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31 +#define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25 +#define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000 +#define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB) +#define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) +#define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0 +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24 +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24 +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000 +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 1 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0 +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MSB 21 +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB 21 +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK 0x00200000 +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_RESET 1 +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MSB 20 +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB 20 +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK 0x00100000 +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_RESET 1 +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19 +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15 +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000 +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0 +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14 +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10 +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00 +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0 +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9 +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5 +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0 +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0 +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4 +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4 +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010 +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 1 +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3 +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3 +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008 +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 1 +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2 +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2 +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004 +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 1 +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1 +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1 +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002 +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0 +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0 +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0 +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001 +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0 +#define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x0008 +#define CPU_DDR_CLOCK_CONTROL_OFFSET 0x0008 +// SW modifiable bits +#define CPU_DDR_CLOCK_CONTROL_SW_MASK 0xffffffff +// bits defined at reset +#define CPU_DDR_CLOCK_CONTROL_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define CPU_DDR_CLOCK_CONTROL_RESET 0x0130001c + +// 32'h000c (CPU_SYNC) +#define CPU_SYNC_LENGTH_MSB 19 +#define CPU_SYNC_LENGTH_LSB 16 +#define CPU_SYNC_LENGTH_MASK 0x000f0000 +#define CPU_SYNC_LENGTH_GET(x) (((x) & CPU_SYNC_LENGTH_MASK) >> CPU_SYNC_LENGTH_LSB) +#define CPU_SYNC_LENGTH_SET(x) (((x) << CPU_SYNC_LENGTH_LSB) & CPU_SYNC_LENGTH_MASK) +#define CPU_SYNC_LENGTH_RESET 0 +#define CPU_SYNC_PATTERN_MSB 15 +#define CPU_SYNC_PATTERN_LSB 0 +#define CPU_SYNC_PATTERN_MASK 0x0000ffff +#define CPU_SYNC_PATTERN_GET(x) (((x) & CPU_SYNC_PATTERN_MASK) >> CPU_SYNC_PATTERN_LSB) +#define CPU_SYNC_PATTERN_SET(x) (((x) << CPU_SYNC_PATTERN_LSB) & CPU_SYNC_PATTERN_MASK) +#define CPU_SYNC_PATTERN_RESET 65535 +#define CPU_SYNC_ADDRESS 0x000c +#define CPU_SYNC_OFFSET 0x000c +// SW modifiable bits +#define CPU_SYNC_SW_MASK 0x000fffff +// bits defined at reset +#define CPU_SYNC_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define CPU_SYNC_RESET 0x0000ffff + +// 32'h0010 (PCIE_PLL_CONFIG) +#define PCIE_PLL_CONFIG_UPDATING_MSB 31 +#define PCIE_PLL_CONFIG_UPDATING_LSB 31 +#define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB) +#define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK) +#define PCIE_PLL_CONFIG_UPDATING_RESET 0 +#define PCIE_PLL_CONFIG_PLLPWD_MSB 30 +#define PCIE_PLL_CONFIG_PLLPWD_LSB 30 +#define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000 +#define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB) +#define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK) +#define PCIE_PLL_CONFIG_PLLPWD_RESET 1 +#define PCIE_PLL_CONFIG_BYPASS_MSB 16 +#define PCIE_PLL_CONFIG_BYPASS_LSB 16 +#define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000 +#define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB) +#define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK) +#define PCIE_PLL_CONFIG_BYPASS_RESET 1 +#define PCIE_PLL_CONFIG_REFDIV_MSB 14 +#define PCIE_PLL_CONFIG_REFDIV_LSB 10 +#define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00 +#define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB) +#define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK) +#define PCIE_PLL_CONFIG_REFDIV_RESET 1 +#define PCIE_PLL_CONFIG_ADDRESS 0x0010 +#define PCIE_PLL_CONFIG_OFFSET 0x0010 +// SW modifiable bits +#define PCIE_PLL_CONFIG_SW_MASK 0xc0017c00 +// bits defined at reset +#define PCIE_PLL_CONFIG_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PLL_CONFIG_RESET 0x40010400 + +// 32'h0014 (PCIE_PLL_DITHER_DIV_MAX) +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31 +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31 +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000 +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 1 +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30 +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30 +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000 +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 1 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 19 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 16383 +#define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x0014 +#define PCIE_PLL_DITHER_DIV_MAX_OFFSET 0x0014 +// SW modifiable bits +#define PCIE_PLL_DITHER_DIV_MAX_SW_MASK 0xc01ffffe +// bits defined at reset +#define PCIE_PLL_DITHER_DIV_MAX_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PLL_DITHER_DIV_MAX_RESET 0xc009fffe + +// 32'h0018 (PCIE_PLL_DITHER_DIV_MIN) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 19 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 14749 +#define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x0018 +#define PCIE_PLL_DITHER_DIV_MIN_OFFSET 0x0018 +// SW modifiable bits +#define PCIE_PLL_DITHER_DIV_MIN_SW_MASK 0x001ffffe +// bits defined at reset +#define PCIE_PLL_DITHER_DIV_MIN_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PLL_DITHER_DIV_MIN_RESET 0x0009f33a + +// 32'h001c (PCIE_PLL_DITHER_STEP) +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31 +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28 +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000 +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0 +#define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24 +#define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15 +#define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000 +#define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB) +#define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) +#define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0 +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14 +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1 +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 10 +#define PCIE_PLL_DITHER_STEP_ADDRESS 0x001c +#define PCIE_PLL_DITHER_STEP_OFFSET 0x001c +// SW modifiable bits +#define PCIE_PLL_DITHER_STEP_SW_MASK 0xf1fffffe +// bits defined at reset +#define PCIE_PLL_DITHER_STEP_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PLL_DITHER_STEP_RESET 0x00000014 + +// 32'h0020 (LDO_POWER_CONTROL) +#define LDO_POWER_CONTROL_PKG_SEL_MSB 5 +#define LDO_POWER_CONTROL_PKG_SEL_LSB 5 +#define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020 +#define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB) +#define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK) +#define LDO_POWER_CONTROL_PKG_SEL_RESET 0 +#define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4 +#define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4 +#define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010 +#define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB) +#define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) +#define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0 +#define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3 +#define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3 +#define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008 +#define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB) +#define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) +#define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0 +#define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2 +#define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1 +#define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006 +#define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB) +#define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) +#define LDO_POWER_CONTROL_CPU_REFSEL_RESET 3 +#define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0 +#define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0 +#define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001 +#define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB) +#define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) +#define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0 +#define LDO_POWER_CONTROL_ADDRESS 0x0020 +#define LDO_POWER_CONTROL_OFFSET 0x0020 +// SW modifiable bits +#define LDO_POWER_CONTROL_SW_MASK 0x0000003f +// bits defined at reset +#define LDO_POWER_CONTROL_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define LDO_POWER_CONTROL_RESET 0x00000006 + +// 32'h0024 (SWITCH_CLOCK_SPARE) +#define SWITCH_CLOCK_SPARE_SPARE_MSB 31 +#define SWITCH_CLOCK_SPARE_SPARE_LSB 12 +#define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfffff000 +#define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB) +#define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK) +#define SWITCH_CLOCK_SPARE_SPARE_RESET 0 +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11 +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8 +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00 +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 5 +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7 +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7 +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080 +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0 +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MSB 6 +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB 6 +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK 0x00000040 +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_RESET 0 +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 5 +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 5 +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00000020 +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 1 +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 4 +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 4 +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00000010 +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 1 +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 3 +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 3 +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00000008 +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MSB 2 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB 2 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK 0x00000004 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_RESET 0 +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 1 +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 1 +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00000002 +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 0 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 0 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00000001 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 1 +#define SWITCH_CLOCK_SPARE_ADDRESS 0x0024 +#define SWITCH_CLOCK_SPARE_OFFSET 0x0024 +// SW modifiable bits +#define SWITCH_CLOCK_SPARE_SW_MASK 0xffffffff +// bits defined at reset +#define SWITCH_CLOCK_SPARE_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define SWITCH_CLOCK_SPARE_RESET 0x00000531 + +// 32'h0028 (CURRENT_PCIE_PLL_DITHER) +#define CURRENT_PCIE_PLL_DITHER_INT_MSB 20 +#define CURRENT_PCIE_PLL_DITHER_INT_LSB 15 +#define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000 +#define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB) +#define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK) +#define CURRENT_PCIE_PLL_DITHER_INT_RESET 1 +#define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13 +#define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0 +#define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff +#define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB) +#define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) +#define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0 +#define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x0028 +#define CURRENT_PCIE_PLL_DITHER_OFFSET 0x0028 +// SW modifiable bits +#define CURRENT_PCIE_PLL_DITHER_SW_MASK 0x001fbfff +// bits defined at reset +#define CURRENT_PCIE_PLL_DITHER_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define CURRENT_PCIE_PLL_DITHER_RESET 0x00008000 + +// 32'h002c (ETH_XMII) +#define ETH_XMII_TX_INVERT_MSB 31 +#define ETH_XMII_TX_INVERT_LSB 31 +#define ETH_XMII_TX_INVERT_MASK 0x80000000 +#define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB) +#define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK) +#define ETH_XMII_TX_INVERT_RESET 0 +#define ETH_XMII_GIGE_QUAD_MSB 30 +#define ETH_XMII_GIGE_QUAD_LSB 30 +#define ETH_XMII_GIGE_QUAD_MASK 0x40000000 +#define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB) +#define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK) +#define ETH_XMII_GIGE_QUAD_RESET 0 +#define ETH_XMII_RX_DELAY_MSB 29 +#define ETH_XMII_RX_DELAY_LSB 28 +#define ETH_XMII_RX_DELAY_MASK 0x30000000 +#define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB) +#define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK) +#define ETH_XMII_RX_DELAY_RESET 0 +#define ETH_XMII_TX_DELAY_MSB 27 +#define ETH_XMII_TX_DELAY_LSB 26 +#define ETH_XMII_TX_DELAY_MASK 0x0c000000 +#define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB) +#define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK) +#define ETH_XMII_TX_DELAY_RESET 0 +#define ETH_XMII_GIGE_MSB 25 +#define ETH_XMII_GIGE_LSB 25 +#define ETH_XMII_GIGE_MASK 0x02000000 +#define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB) +#define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK) +#define ETH_XMII_GIGE_RESET 0 +#define ETH_XMII_OFFSET_PHASE_MSB 24 +#define ETH_XMII_OFFSET_PHASE_LSB 24 +#define ETH_XMII_OFFSET_PHASE_MASK 0x01000000 +#define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB) +#define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK) +#define ETH_XMII_OFFSET_PHASE_RESET 0 +#define ETH_XMII_OFFSET_COUNT_MSB 23 +#define ETH_XMII_OFFSET_COUNT_LSB 16 +#define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000 +#define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB) +#define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK) +#define ETH_XMII_OFFSET_COUNT_RESET 0 +#define ETH_XMII_PHASE1_COUNT_MSB 15 +#define ETH_XMII_PHASE1_COUNT_LSB 8 +#define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00 +#define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB) +#define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK) +#define ETH_XMII_PHASE1_COUNT_RESET 1 +#define ETH_XMII_PHASE0_COUNT_MSB 7 +#define ETH_XMII_PHASE0_COUNT_LSB 0 +#define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff +#define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB) +#define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK) +#define ETH_XMII_PHASE0_COUNT_RESET 1 +#define ETH_XMII_ADDRESS 0x002c +#define ETH_XMII_OFFSET 0x002c +// SW modifiable bits +#define ETH_XMII_SW_MASK 0xffffffff +// bits defined at reset +#define ETH_XMII_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define ETH_XMII_RESET 0x00000101 + +// 32'h0030 (AUDIO_PLL_CONFIG) +#define AUDIO_PLL_CONFIG_UPDATING_MSB 31 +#define AUDIO_PLL_CONFIG_UPDATING_LSB 31 +#define AUDIO_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define AUDIO_PLL_CONFIG_UPDATING_GET(x) (((x) & AUDIO_PLL_CONFIG_UPDATING_MASK) >> AUDIO_PLL_CONFIG_UPDATING_LSB) +#define AUDIO_PLL_CONFIG_UPDATING_SET(x) (((x) << AUDIO_PLL_CONFIG_UPDATING_LSB) & AUDIO_PLL_CONFIG_UPDATING_MASK) +#define AUDIO_PLL_CONFIG_UPDATING_RESET 1 +#define AUDIO_PLL_CONFIG_EXT_DIV_MSB 14 +#define AUDIO_PLL_CONFIG_EXT_DIV_LSB 12 +#define AUDIO_PLL_CONFIG_EXT_DIV_MASK 0x00007000 +#define AUDIO_PLL_CONFIG_EXT_DIV_GET(x) (((x) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) >> AUDIO_PLL_CONFIG_EXT_DIV_LSB) +#define AUDIO_PLL_CONFIG_EXT_DIV_SET(x) (((x) << AUDIO_PLL_CONFIG_EXT_DIV_LSB) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) +#define AUDIO_PLL_CONFIG_EXT_DIV_RESET 1 +#define AUDIO_PLL_CONFIG_POSTPLLDIV_MSB 9 +#define AUDIO_PLL_CONFIG_POSTPLLDIV_LSB 7 +#define AUDIO_PLL_CONFIG_POSTPLLDIV_MASK 0x00000380 +#define AUDIO_PLL_CONFIG_POSTPLLDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) >> AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) +#define AUDIO_PLL_CONFIG_POSTPLLDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) +#define AUDIO_PLL_CONFIG_POSTPLLDIV_RESET 1 +#define AUDIO_PLL_CONFIG_PLLPWD_MSB 5 +#define AUDIO_PLL_CONFIG_PLLPWD_LSB 5 +#define AUDIO_PLL_CONFIG_PLLPWD_MASK 0x00000020 +#define AUDIO_PLL_CONFIG_PLLPWD_GET(x) (((x) & AUDIO_PLL_CONFIG_PLLPWD_MASK) >> AUDIO_PLL_CONFIG_PLLPWD_LSB) +#define AUDIO_PLL_CONFIG_PLLPWD_SET(x) (((x) << AUDIO_PLL_CONFIG_PLLPWD_LSB) & AUDIO_PLL_CONFIG_PLLPWD_MASK) +#define AUDIO_PLL_CONFIG_PLLPWD_RESET 1 +#define AUDIO_PLL_CONFIG_BYPASS_MSB 4 +#define AUDIO_PLL_CONFIG_BYPASS_LSB 4 +#define AUDIO_PLL_CONFIG_BYPASS_MASK 0x00000010 +#define AUDIO_PLL_CONFIG_BYPASS_GET(x) (((x) & AUDIO_PLL_CONFIG_BYPASS_MASK) >> AUDIO_PLL_CONFIG_BYPASS_LSB) +#define AUDIO_PLL_CONFIG_BYPASS_SET(x) (((x) << AUDIO_PLL_CONFIG_BYPASS_LSB) & AUDIO_PLL_CONFIG_BYPASS_MASK) +#define AUDIO_PLL_CONFIG_BYPASS_RESET 1 +#define AUDIO_PLL_CONFIG_REFDIV_MSB 3 +#define AUDIO_PLL_CONFIG_REFDIV_LSB 0 +#define AUDIO_PLL_CONFIG_REFDIV_MASK 0x0000000f +#define AUDIO_PLL_CONFIG_REFDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_REFDIV_MASK) >> AUDIO_PLL_CONFIG_REFDIV_LSB) +#define AUDIO_PLL_CONFIG_REFDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_REFDIV_LSB) & AUDIO_PLL_CONFIG_REFDIV_MASK) +#define AUDIO_PLL_CONFIG_REFDIV_RESET 3 +#define AUDIO_PLL_CONFIG_ADDRESS 0x0030 +#define AUDIO_PLL_CONFIG_OFFSET 0x0030 +// SW modifiable bits +#define AUDIO_PLL_CONFIG_SW_MASK 0x800073bf +// bits defined at reset +#define AUDIO_PLL_CONFIG_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define AUDIO_PLL_CONFIG_RESET 0x800010b3 + +// 32'h0034 (AUDIO_PLL_MODULATION) +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MSB 28 +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB 11 +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK 0x1ffff800 +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) +#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_RESET 84222 +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MSB 6 +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB 1 +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK 0x0000007e +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) +#define AUDIO_PLL_MODULATION_TGT_DIV_INT_RESET 20 +#define AUDIO_PLL_MODULATION_START_MSB 0 +#define AUDIO_PLL_MODULATION_START_LSB 0 +#define AUDIO_PLL_MODULATION_START_MASK 0x00000001 +#define AUDIO_PLL_MODULATION_START_GET(x) (((x) & AUDIO_PLL_MODULATION_START_MASK) >> AUDIO_PLL_MODULATION_START_LSB) +#define AUDIO_PLL_MODULATION_START_SET(x) (((x) << AUDIO_PLL_MODULATION_START_LSB) & AUDIO_PLL_MODULATION_START_MASK) +#define AUDIO_PLL_MODULATION_START_RESET 0 +#define AUDIO_PLL_MODULATION_ADDRESS 0x0034 +#define AUDIO_PLL_MODULATION_OFFSET 0x0034 +// SW modifiable bits +#define AUDIO_PLL_MODULATION_SW_MASK 0x1ffff87f +// bits defined at reset +#define AUDIO_PLL_MODULATION_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define AUDIO_PLL_MODULATION_RESET 0x0a47f028 + +// 32'h0038 (AUDIO_PLL_MOD_STEP) +#define AUDIO_PLL_MOD_STEP_FRAC_MSB 31 +#define AUDIO_PLL_MOD_STEP_FRAC_LSB 14 +#define AUDIO_PLL_MOD_STEP_FRAC_MASK 0xffffc000 +#define AUDIO_PLL_MOD_STEP_FRAC_GET(x) (((x) & AUDIO_PLL_MOD_STEP_FRAC_MASK) >> AUDIO_PLL_MOD_STEP_FRAC_LSB) +#define AUDIO_PLL_MOD_STEP_FRAC_SET(x) (((x) << AUDIO_PLL_MOD_STEP_FRAC_LSB) & AUDIO_PLL_MOD_STEP_FRAC_MASK) +#define AUDIO_PLL_MOD_STEP_FRAC_RESET 1 +#define AUDIO_PLL_MOD_STEP_INT_MSB 13 +#define AUDIO_PLL_MOD_STEP_INT_LSB 4 +#define AUDIO_PLL_MOD_STEP_INT_MASK 0x00003ff0 +#define AUDIO_PLL_MOD_STEP_INT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_INT_MASK) >> AUDIO_PLL_MOD_STEP_INT_LSB) +#define AUDIO_PLL_MOD_STEP_INT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_INT_LSB) & AUDIO_PLL_MOD_STEP_INT_MASK) +#define AUDIO_PLL_MOD_STEP_INT_RESET 0 +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MSB 3 +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB 0 +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK 0x0000000f +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) >> AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) +#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_RESET 0 +#define AUDIO_PLL_MOD_STEP_ADDRESS 0x0038 +#define AUDIO_PLL_MOD_STEP_OFFSET 0x0038 +// SW modifiable bits +#define AUDIO_PLL_MOD_STEP_SW_MASK 0xffffffff +// bits defined at reset +#define AUDIO_PLL_MOD_STEP_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define AUDIO_PLL_MOD_STEP_RESET 0x00004000 + +// 32'h003c (CURRENT_AUDIO_PLL_MODULATION) +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MSB 27 +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB 10 +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK 0x0ffffc00 +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) >> CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) +#define CURRENT_AUDIO_PLL_MODULATION_FRAC_RESET 1 +#define CURRENT_AUDIO_PLL_MODULATION_INT_MSB 6 +#define CURRENT_AUDIO_PLL_MODULATION_INT_LSB 1 +#define CURRENT_AUDIO_PLL_MODULATION_INT_MASK 0x0000007e +#define CURRENT_AUDIO_PLL_MODULATION_INT_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) >> CURRENT_AUDIO_PLL_MODULATION_INT_LSB) +#define CURRENT_AUDIO_PLL_MODULATION_INT_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_INT_LSB) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) +#define CURRENT_AUDIO_PLL_MODULATION_INT_RESET 0 +#define CURRENT_AUDIO_PLL_MODULATION_ADDRESS 0x003c +#define CURRENT_AUDIO_PLL_MODULATION_OFFSET 0x003c +// SW modifiable bits +#define CURRENT_AUDIO_PLL_MODULATION_SW_MASK 0x0ffffc7e +// bits defined at reset +#define CURRENT_AUDIO_PLL_MODULATION_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define CURRENT_AUDIO_PLL_MODULATION_RESET 0x00000400 + +#define RST_BOOTSTRAP_ADDRESS 0x180600b0 + +// 32'h0040 (BB_PLL_CONFIG) +#define BB_PLL_CONFIG_UPDATING_MSB 31 +#define BB_PLL_CONFIG_UPDATING_LSB 31 +#define BB_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB) +#define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK) +#define BB_PLL_CONFIG_UPDATING_RESET 1 +#define BB_PLL_CONFIG_PLLPWD_MSB 30 +#define BB_PLL_CONFIG_PLLPWD_LSB 30 +#define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000 +#define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB) +#define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK) +#define BB_PLL_CONFIG_PLLPWD_RESET 1 +#define BB_PLL_CONFIG_SPARE_MSB 29 +#define BB_PLL_CONFIG_SPARE_LSB 29 +#define BB_PLL_CONFIG_SPARE_MASK 0x20000000 +#define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB) +#define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK) +#define BB_PLL_CONFIG_SPARE_RESET 0 +#define BB_PLL_CONFIG_REFDIV_MSB 28 +#define BB_PLL_CONFIG_REFDIV_LSB 24 +#define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000 +#define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB) +#define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK) +#define BB_PLL_CONFIG_REFDIV_RESET 1 +#define BB_PLL_CONFIG_NINT_MSB 21 +#define BB_PLL_CONFIG_NINT_LSB 16 +#define BB_PLL_CONFIG_NINT_MASK 0x003f0000 +#define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB) +#define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK) +#define BB_PLL_CONFIG_NINT_RESET 2 +#define BB_PLL_CONFIG_NFRAC_MSB 13 +#define BB_PLL_CONFIG_NFRAC_LSB 0 +#define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff +#define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB) +#define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK) +#define BB_PLL_CONFIG_NFRAC_RESET 3276 +#define BB_PLL_CONFIG_ADDRESS 0x0040 +#define BB_PLL_CONFIG_OFFSET 0x0040 +// SW modifiable bits +#define BB_PLL_CONFIG_SW_MASK 0xff3f3fff +// bits defined at reset +#define BB_PLL_CONFIG_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define BB_PLL_CONFIG_RESET 0xc1020ccc + +// 32'h0044 (DDR_PLL_DITHER) +#define DDR_PLL_DITHER_DITHER_EN_MSB 31 +#define DDR_PLL_DITHER_DITHER_EN_LSB 31 +#define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000 +#define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB) +#define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK) +#define DDR_PLL_DITHER_DITHER_EN_RESET 0 +#define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30 +#define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27 +#define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000 +#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB) +#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) +#define DDR_PLL_DITHER_UPDATE_COUNT_RESET 15 +#define DDR_PLL_DITHER_NFRAC_STEP_MSB 26 +#define DDR_PLL_DITHER_NFRAC_STEP_LSB 20 +#define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000 +#define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB) +#define DDR_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK) +#define DDR_PLL_DITHER_NFRAC_STEP_RESET 1 +#define DDR_PLL_DITHER_NFRAC_MIN_MSB 19 +#define DDR_PLL_DITHER_NFRAC_MIN_LSB 10 +#define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00 +#define DDR_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB) +#define DDR_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK) +#define DDR_PLL_DITHER_NFRAC_MIN_RESET 25 +#define DDR_PLL_DITHER_NFRAC_MAX_MSB 9 +#define DDR_PLL_DITHER_NFRAC_MAX_LSB 0 +#define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff +#define DDR_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB) +#define DDR_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK) +#define DDR_PLL_DITHER_NFRAC_MAX_RESET 1000 +#define DDR_PLL_DITHER_ADDRESS 0x0044 +#define DDR_PLL_DITHER_OFFSET 0x0044 +// SW modifiable bits +#define DDR_PLL_DITHER_SW_MASK 0xffffffff +// bits defined at reset +#define DDR_PLL_DITHER_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define DDR_PLL_DITHER_RESET 0x781067e8 + +// 32'h0048 (CPU_PLL_DITHER) +#define CPU_PLL_DITHER_DITHER_EN_MSB 31 +#define CPU_PLL_DITHER_DITHER_EN_LSB 31 +#define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000 +#define CPU_PLL_DITHER_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB) +#define CPU_PLL_DITHER_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK) +#define CPU_PLL_DITHER_DITHER_EN_RESET 0 +#define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23 +#define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18 +#define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000 +#define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB) +#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) +#define CPU_PLL_DITHER_UPDATE_COUNT_RESET 20 +#define CPU_PLL_DITHER_NFRAC_STEP_MSB 17 +#define CPU_PLL_DITHER_NFRAC_STEP_LSB 12 +#define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000 +#define CPU_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB) +#define CPU_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK) +#define CPU_PLL_DITHER_NFRAC_STEP_RESET 1 +#define CPU_PLL_DITHER_NFRAC_MIN_MSB 11 +#define CPU_PLL_DITHER_NFRAC_MIN_LSB 6 +#define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0 +#define CPU_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB) +#define CPU_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK) +#define CPU_PLL_DITHER_NFRAC_MIN_RESET 3 +#define CPU_PLL_DITHER_NFRAC_MAX_MSB 5 +#define CPU_PLL_DITHER_NFRAC_MAX_LSB 0 +#define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f +#define CPU_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB) +#define CPU_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK) +#define CPU_PLL_DITHER_NFRAC_MAX_RESET 60 +#define CPU_PLL_DITHER_ADDRESS 0x0048 +#define CPU_PLL_DITHER_OFFSET 0x0048 +// SW modifiable bits +#define CPU_PLL_DITHER_SW_MASK 0x80ffffff +// bits defined at reset +#define CPU_PLL_DITHER_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define CPU_PLL_DITHER_RESET 0x005010fc + +// 32'h1806001c (RST_RESET) +#define RST_RESET_HOST_RESET_MSB 31 +#define RST_RESET_HOST_RESET_LSB 31 +#define RST_RESET_HOST_RESET_MASK 0x80000000 +#define RST_RESET_HOST_RESET_GET(x) (((x) & RST_RESET_HOST_RESET_MASK) >> RST_RESET_HOST_RESET_LSB) +#define RST_RESET_HOST_RESET_SET(x) (((x) << RST_RESET_HOST_RESET_LSB) & RST_RESET_HOST_RESET_MASK) +#define RST_RESET_HOST_RESET_RESET 0 +#define RST_RESET_SLIC_RESET_MSB 30 +#define RST_RESET_SLIC_RESET_LSB 30 +#define RST_RESET_SLIC_RESET_MASK 0x40000000 +#define RST_RESET_SLIC_RESET_GET(x) (((x) & RST_RESET_SLIC_RESET_MASK) >> RST_RESET_SLIC_RESET_LSB) +#define RST_RESET_SLIC_RESET_SET(x) (((x) << RST_RESET_SLIC_RESET_LSB) & RST_RESET_SLIC_RESET_MASK) +#define RST_RESET_SLIC_RESET_RESET 0 +#define RST_RESET_HDMA_RESET_MSB 29 +#define RST_RESET_HDMA_RESET_LSB 29 +#define RST_RESET_HDMA_RESET_MASK 0x20000000 +#define RST_RESET_HDMA_RESET_GET(x) (((x) & RST_RESET_HDMA_RESET_MASK) >> RST_RESET_HDMA_RESET_LSB) +#define RST_RESET_HDMA_RESET_SET(x) (((x) << RST_RESET_HDMA_RESET_LSB) & RST_RESET_HDMA_RESET_MASK) +#define RST_RESET_HDMA_RESET_RESET 1 +#define RST_RESET_EXTERNAL_RESET_MSB 28 +#define RST_RESET_EXTERNAL_RESET_LSB 28 +#define RST_RESET_EXTERNAL_RESET_MASK 0x10000000 +#define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB) +#define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK) +#define RST_RESET_EXTERNAL_RESET_RESET 0 +#define RST_RESET_RTC_RESET_MSB 27 +#define RST_RESET_RTC_RESET_LSB 27 +#define RST_RESET_RTC_RESET_MASK 0x08000000 +#define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB) +#define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK) +#define RST_RESET_RTC_RESET_RESET 1 +#define RST_RESET_PCIEEP_RST_INT_MSB 26 +#define RST_RESET_PCIEEP_RST_INT_LSB 26 +#define RST_RESET_PCIEEP_RST_INT_MASK 0x04000000 +#define RST_RESET_PCIEEP_RST_INT_GET(x) (((x) & RST_RESET_PCIEEP_RST_INT_MASK) >> RST_RESET_PCIEEP_RST_INT_LSB) +#define RST_RESET_PCIEEP_RST_INT_SET(x) (((x) << RST_RESET_PCIEEP_RST_INT_LSB) & RST_RESET_PCIEEP_RST_INT_MASK) +#define RST_RESET_PCIEEP_RST_INT_RESET 0 +#define RST_RESET_CHKSUM_ACC_RESET_MSB 25 +#define RST_RESET_CHKSUM_ACC_RESET_LSB 25 +#define RST_RESET_CHKSUM_ACC_RESET_MASK 0x02000000 +#define RST_RESET_CHKSUM_ACC_RESET_GET(x) (((x) & RST_RESET_CHKSUM_ACC_RESET_MASK) >> RST_RESET_CHKSUM_ACC_RESET_LSB) +#define RST_RESET_CHKSUM_ACC_RESET_SET(x) (((x) << RST_RESET_CHKSUM_ACC_RESET_LSB) & RST_RESET_CHKSUM_ACC_RESET_MASK) +#define RST_RESET_CHKSUM_ACC_RESET_RESET 0 +#define RST_RESET_FULL_CHIP_RESET_MSB 24 +#define RST_RESET_FULL_CHIP_RESET_LSB 24 +#define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000 +#define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB) +#define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK) +#define RST_RESET_FULL_CHIP_RESET_RESET 0 +#define RST_RESET_GE1_MDIO_RESET_MSB 23 +#define RST_RESET_GE1_MDIO_RESET_LSB 23 +#define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000 +#define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB) +#define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK) +#define RST_RESET_GE1_MDIO_RESET_RESET 1 +#define RST_RESET_GE0_MDIO_RESET_MSB 22 +#define RST_RESET_GE0_MDIO_RESET_LSB 22 +#define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000 +#define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB) +#define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK) +#define RST_RESET_GE0_MDIO_RESET_RESET 1 +#define RST_RESET_CPU_NMI_MSB 21 +#define RST_RESET_CPU_NMI_LSB 21 +#define RST_RESET_CPU_NMI_MASK 0x00200000 +#define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB) +#define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK) +#define RST_RESET_CPU_NMI_RESET 0 +#define RST_RESET_CPU_COLD_RESET_MSB 20 +#define RST_RESET_CPU_COLD_RESET_LSB 20 +#define RST_RESET_CPU_COLD_RESET_MASK 0x00100000 +#define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB) +#define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK) +#define RST_RESET_CPU_COLD_RESET_RESET 0 +#define RST_RESET_HOST_RESET_INT_MSB 19 +#define RST_RESET_HOST_RESET_INT_LSB 19 +#define RST_RESET_HOST_RESET_INT_MASK 0x00080000 +#define RST_RESET_HOST_RESET_INT_GET(x) (((x) & RST_RESET_HOST_RESET_INT_MASK) >> RST_RESET_HOST_RESET_INT_LSB) +#define RST_RESET_HOST_RESET_INT_SET(x) (((x) << RST_RESET_HOST_RESET_INT_LSB) & RST_RESET_HOST_RESET_INT_MASK) +#define RST_RESET_HOST_RESET_INT_RESET 0 +#define RST_RESET_PCIEEP_RESET_MSB 18 +#define RST_RESET_PCIEEP_RESET_LSB 18 +#define RST_RESET_PCIEEP_RESET_MASK 0x00040000 +#define RST_RESET_PCIEEP_RESET_GET(x) (((x) & RST_RESET_PCIEEP_RESET_MASK) >> RST_RESET_PCIEEP_RESET_LSB) +#define RST_RESET_PCIEEP_RESET_SET(x) (((x) << RST_RESET_PCIEEP_RESET_LSB) & RST_RESET_PCIEEP_RESET_MASK) +#define RST_RESET_PCIEEP_RESET_RESET 0 +#define RST_RESET_UART1_RESET_MSB 17 +#define RST_RESET_UART1_RESET_LSB 17 +#define RST_RESET_UART1_RESET_MASK 0x00020000 +#define RST_RESET_UART1_RESET_GET(x) (((x) & RST_RESET_UART1_RESET_MASK) >> RST_RESET_UART1_RESET_LSB) +#define RST_RESET_UART1_RESET_SET(x) (((x) << RST_RESET_UART1_RESET_LSB) & RST_RESET_UART1_RESET_MASK) +#define RST_RESET_UART1_RESET_RESET 0 +#define RST_RESET_DDR_RESET_MSB 16 +#define RST_RESET_DDR_RESET_LSB 16 +#define RST_RESET_DDR_RESET_MASK 0x00010000 +#define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB) +#define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK) +#define RST_RESET_DDR_RESET_RESET 0 +#define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15 +#define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15 +#define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000 +#define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) +#define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) +#define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0 +#define RST_RESET_NANDF_RESET_MSB 14 +#define RST_RESET_NANDF_RESET_LSB 14 +#define RST_RESET_NANDF_RESET_MASK 0x00004000 +#define RST_RESET_NANDF_RESET_GET(x) (((x) & RST_RESET_NANDF_RESET_MASK) >> RST_RESET_NANDF_RESET_LSB) +#define RST_RESET_NANDF_RESET_SET(x) (((x) << RST_RESET_NANDF_RESET_LSB) & RST_RESET_NANDF_RESET_MASK) +#define RST_RESET_NANDF_RESET_RESET 1 +#define RST_RESET_GE1_MAC_RESET_MSB 13 +#define RST_RESET_GE1_MAC_RESET_LSB 13 +#define RST_RESET_GE1_MAC_RESET_MASK 0x00002000 +#define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB) +#define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK) +#define RST_RESET_GE1_MAC_RESET_RESET 1 +#define RST_RESET_ETH_SWITCH_ARESET_MSB 12 +#define RST_RESET_ETH_SWITCH_ARESET_LSB 12 +#define RST_RESET_ETH_SWITCH_ARESET_MASK 0x00001000 +#define RST_RESET_ETH_SWITCH_ARESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_ARESET_MASK) >> RST_RESET_ETH_SWITCH_ARESET_LSB) +#define RST_RESET_ETH_SWITCH_ARESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_ARESET_LSB) & RST_RESET_ETH_SWITCH_ARESET_MASK) +#define RST_RESET_ETH_SWITCH_ARESET_RESET 1 +#define RST_RESET_USB_PHY_ARESET_MSB 11 +#define RST_RESET_USB_PHY_ARESET_LSB 11 +#define RST_RESET_USB_PHY_ARESET_MASK 0x00000800 +#define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB) +#define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK) +#define RST_RESET_USB_PHY_ARESET_RESET 1 +#define RST_RESET_RESERVED_MSB 10 +#define RST_RESET_RESERVED_LSB 10 +#define RST_RESET_RESERVED_MASK 0x00000400 +#define RST_RESET_RESERVED_GET(x) (((x) & RST_RESET_RESERVED_MASK) >> RST_RESET_RESERVED_LSB) +#define RST_RESET_RESERVED_SET(x) (((x) << RST_RESET_RESERVED_LSB) & RST_RESET_RESERVED_MASK) +#define RST_RESET_RESERVED_RESET 1 +#define RST_RESET_GE0_MAC_RESET_MSB 9 +#define RST_RESET_GE0_MAC_RESET_LSB 9 +#define RST_RESET_GE0_MAC_RESET_MASK 0x00000200 +#define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB) +#define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK) +#define RST_RESET_GE0_MAC_RESET_RESET 1 +#define RST_RESET_ETH_SWITCH_RESET_MSB 8 +#define RST_RESET_ETH_SWITCH_RESET_LSB 8 +#define RST_RESET_ETH_SWITCH_RESET_MASK 0x00000100 +#define RST_RESET_ETH_SWITCH_RESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_RESET_MASK) >> RST_RESET_ETH_SWITCH_RESET_LSB) +#define RST_RESET_ETH_SWITCH_RESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_RESET_LSB) & RST_RESET_ETH_SWITCH_RESET_MASK) +#define RST_RESET_ETH_SWITCH_RESET_RESET 1 +#define RST_RESET_PCIE_PHY_RESET_MSB 7 +#define RST_RESET_PCIE_PHY_RESET_LSB 7 +#define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080 +#define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB) +#define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK) +#define RST_RESET_PCIE_PHY_RESET_RESET 1 +#define RST_RESET_PCIE_RESET_MSB 6 +#define RST_RESET_PCIE_RESET_LSB 6 +#define RST_RESET_PCIE_RESET_MASK 0x00000040 +#define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB) +#define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK) +#define RST_RESET_PCIE_RESET_RESET 1 +#define RST_RESET_USB_HOST_RESET_MSB 5 +#define RST_RESET_USB_HOST_RESET_LSB 5 +#define RST_RESET_USB_HOST_RESET_MASK 0x00000020 +#define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB) +#define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK) +#define RST_RESET_USB_HOST_RESET_RESET 1 +#define RST_RESET_USB_PHY_RESET_MSB 4 +#define RST_RESET_USB_PHY_RESET_LSB 4 +#define RST_RESET_USB_PHY_RESET_MASK 0x00000010 +#define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB) +#define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK) +#define RST_RESET_USB_PHY_RESET_RESET 1 +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3 +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3 +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008 +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0 +#define RST_RESET_LUT_RESET_MSB 2 +#define RST_RESET_LUT_RESET_LSB 2 +#define RST_RESET_LUT_RESET_MASK 0x00000004 +#define RST_RESET_LUT_RESET_GET(x) (((x) & RST_RESET_LUT_RESET_MASK) >> RST_RESET_LUT_RESET_LSB) +#define RST_RESET_LUT_RESET_SET(x) (((x) << RST_RESET_LUT_RESET_LSB) & RST_RESET_LUT_RESET_MASK) +#define RST_RESET_LUT_RESET_RESET 0 +#define RST_RESET_MBOX_RESET_MSB 1 +#define RST_RESET_MBOX_RESET_LSB 1 +#define RST_RESET_MBOX_RESET_MASK 0x00000002 +#define RST_RESET_MBOX_RESET_GET(x) (((x) & RST_RESET_MBOX_RESET_MASK) >> RST_RESET_MBOX_RESET_LSB) +#define RST_RESET_MBOX_RESET_SET(x) (((x) << RST_RESET_MBOX_RESET_LSB) & RST_RESET_MBOX_RESET_MASK) +#define RST_RESET_MBOX_RESET_RESET 0 +#define RST_RESET_I2S_RESET_MSB 0 +#define RST_RESET_I2S_RESET_LSB 0 +#define RST_RESET_I2S_RESET_MASK 0x00000001 +#define RST_RESET_I2S_RESET_GET(x) (((x) & RST_RESET_I2S_RESET_MASK) >> RST_RESET_I2S_RESET_LSB) +#define RST_RESET_I2S_RESET_SET(x) (((x) << RST_RESET_I2S_RESET_LSB) & RST_RESET_I2S_RESET_MASK) +#define RST_RESET_I2S_RESET_RESET 0 +#define RST_RESET_ADDRESS 0x1806001c +#define RST_RESET_OFFSET 0x001c +// SW modifiable bits +#define RST_RESET_SW_MASK 0xffffffff +// bits defined at reset +#define RST_RESET_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define RST_RESET_RESET 0x28c07ff0 + +#define RST_MISC2_SPARE_MSB 31 +#define RST_MISC2_SPARE_LSB 26 +#define RST_MISC2_SPARE_MASK 0xfc000000 +#define RST_MISC2_SPARE_GET(x) (((x) & RST_MISC2_SPARE_MASK) >> RST_MISC2_SPARE_LSB) +#define RST_MISC2_SPARE_SET(x) (((x) << RST_MISC2_SPARE_LSB) & RST_MISC2_SPARE_MASK) +#define RST_MISC2_SPARE_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L2_EXIT_INT_MSB 25 +#define RST_MISC2_PCIEEP_L2_EXIT_INT_LSB 25 +#define RST_MISC2_PCIEEP_L2_EXIT_INT_MASK 0x02000000 +#define RST_MISC2_PCIEEP_L2_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L2_EXIT_INT_LSB) +#define RST_MISC2_PCIEEP_L2_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK) +#define RST_MISC2_PCIEEP_L2_EXIT_INT_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L2_ENTR_INT_MSB 24 +#define RST_MISC2_PCIEEP_L2_ENTR_INT_LSB 24 +#define RST_MISC2_PCIEEP_L2_ENTR_INT_MASK 0x01000000 +#define RST_MISC2_PCIEEP_L2_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L2_ENTR_INT_LSB) +#define RST_MISC2_PCIEEP_L2_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK) +#define RST_MISC2_PCIEEP_L2_ENTR_INT_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L1_EXIT_INT_MSB 23 +#define RST_MISC2_PCIEEP_L1_EXIT_INT_LSB 23 +#define RST_MISC2_PCIEEP_L1_EXIT_INT_MASK 0x00800000 +#define RST_MISC2_PCIEEP_L1_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L1_EXIT_INT_LSB) +#define RST_MISC2_PCIEEP_L1_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK) +#define RST_MISC2_PCIEEP_L1_EXIT_INT_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L1_ENTR_INT_MSB 22 +#define RST_MISC2_PCIEEP_L1_ENTR_INT_LSB 22 +#define RST_MISC2_PCIEEP_L1_ENTR_INT_MASK 0x00400000 +#define RST_MISC2_PCIEEP_L1_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L1_ENTR_INT_LSB) +#define RST_MISC2_PCIEEP_L1_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK) +#define RST_MISC2_PCIEEP_L1_ENTR_INT_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MSB 21 +#define RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB 21 +#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK 0x00200000 +#define RST_MISC2_PCIEEP_L0S_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB) +#define RST_MISC2_PCIEEP_L0S_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK) +#define RST_MISC2_PCIEEP_L0S_EXIT_INT_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MSB 20 +#define RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB 20 +#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK 0x00100000 +#define RST_MISC2_PCIEEP_L0S_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB) +#define RST_MISC2_PCIEEP_L0S_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK) +#define RST_MISC2_PCIEEP_L0S_ENTR_INT_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_REGWR_EN_MSB 19 +#define RST_MISC2_PCIEEP_REGWR_EN_LSB 19 +#define RST_MISC2_PCIEEP_REGWR_EN_MASK 0x00080000 +#define RST_MISC2_PCIEEP_REGWR_EN_GET(x) (((x) & RST_MISC2_PCIEEP_REGWR_EN_MASK) >> RST_MISC2_PCIEEP_REGWR_EN_LSB) +#define RST_MISC2_PCIEEP_REGWR_EN_SET(x) (((x) << RST_MISC2_PCIEEP_REGWR_EN_LSB) & RST_MISC2_PCIEEP_REGWR_EN_MASK) +#define RST_MISC2_PCIEEP_REGWR_EN_RESET 0x1 // 1 +#define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18 +#define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18 +#define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000 +#define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) +#define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) +#define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_RST_INT_MASK_MSB 17 +#define RST_MISC2_PCIEEP_RST_INT_MASK_LSB 17 +#define RST_MISC2_PCIEEP_RST_INT_MASK_MASK 0x00020000 +#define RST_MISC2_PCIEEP_RST_INT_MASK_GET(x) (((x) & RST_MISC2_PCIEEP_RST_INT_MASK_MASK) >> RST_MISC2_PCIEEP_RST_INT_MASK_LSB) +#define RST_MISC2_PCIEEP_RST_INT_MASK_SET(x) (((x) << RST_MISC2_PCIEEP_RST_INT_MASK_LSB) & RST_MISC2_PCIEEP_RST_INT_MASK_MASK) +#define RST_MISC2_PCIEEP_RST_INT_MASK_RESET 0x0 // 0 +#define RST_MISC2_HOST_RESET_INT_MASK_MSB 16 +#define RST_MISC2_HOST_RESET_INT_MASK_LSB 16 +#define RST_MISC2_HOST_RESET_INT_MASK_MASK 0x00010000 +#define RST_MISC2_HOST_RESET_INT_MASK_GET(x) (((x) & RST_MISC2_HOST_RESET_INT_MASK_MASK) >> RST_MISC2_HOST_RESET_INT_MASK_LSB) +#define RST_MISC2_HOST_RESET_INT_MASK_SET(x) (((x) << RST_MISC2_HOST_RESET_INT_MASK_LSB) & RST_MISC2_HOST_RESET_INT_MASK_MASK) +#define RST_MISC2_HOST_RESET_INT_MASK_RESET 0x0 // 0 +#define RST_MISC2_CPU_HOST_WA_MSB 15 +#define RST_MISC2_CPU_HOST_WA_LSB 15 +#define RST_MISC2_CPU_HOST_WA_MASK 0x00008000 +#define RST_MISC2_CPU_HOST_WA_GET(x) (((x) & RST_MISC2_CPU_HOST_WA_MASK) >> RST_MISC2_CPU_HOST_WA_LSB) +#define RST_MISC2_CPU_HOST_WA_SET(x) (((x) << RST_MISC2_CPU_HOST_WA_LSB) & RST_MISC2_CPU_HOST_WA_MASK) +#define RST_MISC2_CPU_HOST_WA_RESET 0x0 // 0 +#define RST_MISC2_PERSTN_EPPHY_MSB 14 +#define RST_MISC2_PERSTN_EPPHY_LSB 14 +#define RST_MISC2_PERSTN_EPPHY_MASK 0x00004000 +#define RST_MISC2_PERSTN_EPPHY_GET(x) (((x) & RST_MISC2_PERSTN_EPPHY_MASK) >> RST_MISC2_PERSTN_EPPHY_LSB) +#define RST_MISC2_PERSTN_EPPHY_SET(x) (((x) << RST_MISC2_PERSTN_EPPHY_LSB) & RST_MISC2_PERSTN_EPPHY_MASK) +#define RST_MISC2_PERSTN_EPPHY_RESET 0x1 // 1 +#define RST_MISC2_PERSTN_RCPHY_MSB 13 +#define RST_MISC2_PERSTN_RCPHY_LSB 13 +#define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000 +#define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB) +#define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK) +#define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1 +#define RST_MISC2_PCIEEP_LTSSM_STATE_MSB 12 +#define RST_MISC2_PCIEEP_LTSSM_STATE_LSB 8 +#define RST_MISC2_PCIEEP_LTSSM_STATE_MASK 0x00001f00 +#define RST_MISC2_PCIEEP_LTSSM_STATE_GET(x) (((x) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK) >> RST_MISC2_PCIEEP_LTSSM_STATE_LSB) +#define RST_MISC2_PCIEEP_LTSSM_STATE_SET(x) (((x) << RST_MISC2_PCIEEP_LTSSM_STATE_LSB) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK) +#define RST_MISC2_PCIEEP_LTSSM_STATE_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L2_INT_MASK_MSB 7 +#define RST_MISC2_PCIEEP_L2_INT_MASK_LSB 7 +#define RST_MISC2_PCIEEP_L2_INT_MASK_MASK 0x00000080 +#define RST_MISC2_PCIEEP_L2_INT_MASK_GET(x) (((x) & RST_MISC2_PCIEEP_L2_INT_MASK_MASK) >> RST_MISC2_PCIEEP_L2_INT_MASK_LSB) +#define RST_MISC2_PCIEEP_L2_INT_MASK_SET(x) (((x) << RST_MISC2_PCIEEP_L2_INT_MASK_LSB) & RST_MISC2_PCIEEP_L2_INT_MASK_MASK) +#define RST_MISC2_PCIEEP_L2_INT_MASK_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L1_INT_MASK_MSB 6 +#define RST_MISC2_PCIEEP_L1_INT_MASK_LSB 6 +#define RST_MISC2_PCIEEP_L1_INT_MASK_MASK 0x00000040 +#define RST_MISC2_PCIEEP_L1_INT_MASK_GET(x) (((x) & RST_MISC2_PCIEEP_L1_INT_MASK_MASK) >> RST_MISC2_PCIEEP_L1_INT_MASK_LSB) +#define RST_MISC2_PCIEEP_L1_INT_MASK_SET(x) (((x) << RST_MISC2_PCIEEP_L1_INT_MASK_LSB) & RST_MISC2_PCIEEP_L1_INT_MASK_MASK) +#define RST_MISC2_PCIEEP_L1_INT_MASK_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_L0S_INT_MASK_MSB 5 +#define RST_MISC2_PCIEEP_L0S_INT_MASK_LSB 5 +#define RST_MISC2_PCIEEP_L0S_INT_MASK_MASK 0x00000020 +#define RST_MISC2_PCIEEP_L0S_INT_MASK_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_INT_MASK_MASK) >> RST_MISC2_PCIEEP_L0S_INT_MASK_LSB) +#define RST_MISC2_PCIEEP_L0S_INT_MASK_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_INT_MASK_LSB) & RST_MISC2_PCIEEP_L0S_INT_MASK_MASK) +#define RST_MISC2_PCIEEP_L0S_INT_MASK_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_LINK_STATUS_MSB 4 +#define RST_MISC2_PCIEEP_LINK_STATUS_LSB 4 +#define RST_MISC2_PCIEEP_LINK_STATUS_MASK 0x00000010 +#define RST_MISC2_PCIEEP_LINK_STATUS_GET(x) (((x) & RST_MISC2_PCIEEP_LINK_STATUS_MASK) >> RST_MISC2_PCIEEP_LINK_STATUS_LSB) +#define RST_MISC2_PCIEEP_LINK_STATUS_SET(x) (((x) << RST_MISC2_PCIEEP_LINK_STATUS_LSB) & RST_MISC2_PCIEEP_LINK_STATUS_MASK) +#define RST_MISC2_PCIEEP_LINK_STATUS_RESET 0x0 // 0 +#define RST_MISC2_RESERVED_MSB 3 +#define RST_MISC2_RESERVED_LSB 1 +#define RST_MISC2_RESERVED_MASK 0x0000000e +#define RST_MISC2_RESERVED_GET(x) (((x) & RST_MISC2_RESERVED_MASK) >> RST_MISC2_RESERVED_LSB) +#define RST_MISC2_RESERVED_SET(x) (((x) << RST_MISC2_RESERVED_LSB) & RST_MISC2_RESERVED_MASK) +#define RST_MISC2_RESERVED_RESET 0x0 // 0 +#define RST_MISC2_PCIEEP_CFG_DONE_MSB 0 +#define RST_MISC2_PCIEEP_CFG_DONE_LSB 0 +#define RST_MISC2_PCIEEP_CFG_DONE_MASK 0x00000001 +#define RST_MISC2_PCIEEP_CFG_DONE_GET(x) (((x) & RST_MISC2_PCIEEP_CFG_DONE_MASK) >> RST_MISC2_PCIEEP_CFG_DONE_LSB) +#define RST_MISC2_PCIEEP_CFG_DONE_SET(x) (((x) << RST_MISC2_PCIEEP_CFG_DONE_LSB) & RST_MISC2_PCIEEP_CFG_DONE_MASK) +#define RST_MISC2_PCIEEP_CFG_DONE_RESET 0x0 // 0 +#define RST_MISC2_ADDRESS 0x180600bc + +#define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31 +#define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31 +#define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000 +#define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB) +#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) +//#define DDR_CONFIG_CAS_LATENCY_MSB_RESET 1'd0 +#define DDR_CONFIG_OPEN_PAGE_MSB 30 +#define DDR_CONFIG_OPEN_PAGE_LSB 30 +#define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000 +#define DDR_CONFIG_OPEN_PAGE_GET(x) (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB) +#define DDR_CONFIG_OPEN_PAGE_SET(x) (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK) +//#define DDR_CONFIG_OPEN_PAGE_RESET 1'd1 +#define DDR_CONFIG_CAS_LATENCY_MSB 29 +#define DDR_CONFIG_CAS_LATENCY_LSB 27 +#define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000 +#define DDR_CONFIG_CAS_LATENCY_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB) +#define DDR_CONFIG_CAS_LATENCY_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK) +//#define DDR_CONFIG_CAS_LATENCY_RESET 3'd6 +#define DDR_CONFIG_TMRD_MSB 26 +#define DDR_CONFIG_TMRD_LSB 23 +#define DDR_CONFIG_TMRD_MASK 0x07800000 +#define DDR_CONFIG_TMRD_GET(x) (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB) +#define DDR_CONFIG_TMRD_SET(x) (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK) +//#define DDR_CONFIG_TMRD_RESET 4'd15 +#define DDR_CONFIG_TRFC_MSB 22 +#define DDR_CONFIG_TRFC_LSB 17 +#define DDR_CONFIG_TRFC_MASK 0x007e0000 +#define DDR_CONFIG_TRFC_GET(x) (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB) +#define DDR_CONFIG_TRFC_SET(x) (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK) +//#define DDR_CONFIG_TRFC_RESET 6'd31 +#define DDR_CONFIG_TRRD_MSB 16 +#define DDR_CONFIG_TRRD_LSB 13 +#define DDR_CONFIG_TRRD_MASK 0x0001e000 +#define DDR_CONFIG_TRRD_GET(x) (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB) +#define DDR_CONFIG_TRRD_SET(x) (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK) +//#define DDR_CONFIG_TRRD_RESET 4'd4 +#define DDR_CONFIG_TRP_MSB 12 +#define DDR_CONFIG_TRP_LSB 9 +#define DDR_CONFIG_TRP_MASK 0x00001e00 +#define DDR_CONFIG_TRP_GET(x) (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB) +#define DDR_CONFIG_TRP_SET(x) (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK) +//#define DDR_CONFIG_TRP_RESET 4'd6 +#define DDR_CONFIG_TRCD_MSB 8 +#define DDR_CONFIG_TRCD_LSB 5 +#define DDR_CONFIG_TRCD_MASK 0x000001e0 +#define DDR_CONFIG_TRCD_GET(x) (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB) +#define DDR_CONFIG_TRCD_SET(x) (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK) +//#define DDR_CONFIG_TRCD_RESET 4'd6 +#define DDR_CONFIG_TRAS_MSB 4 +#define DDR_CONFIG_TRAS_LSB 0 +#define DDR_CONFIG_TRAS_MASK 0x0000001f +#define DDR_CONFIG_TRAS_GET(x) (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB) +#define DDR_CONFIG_TRAS_SET(x) (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK) +//#define DDR_CONFIG_TRAS_RESET 5'd16 +#define DDR_CONFIG_ADDRESS 0x18000000 + +// 32'h18000004 (DDR_CONFIG2) +#define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31 +#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31 +#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000 +#define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB) +#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) +//#define DDR_CONFIG2_HALF_WIDTH_LOW_RESET 1'd1 +#define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29 +#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26 +#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000 +#define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) +#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) +//#define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET 4'd6 +#define DDR_CONFIG2_TWTR_MSB 25 +#define DDR_CONFIG2_TWTR_LSB 21 +#define DDR_CONFIG2_TWTR_MASK 0x03e00000 +#define DDR_CONFIG2_TWTR_GET(x) (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB) +#define DDR_CONFIG2_TWTR_SET(x) (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK) +//#define DDR_CONFIG2_TWTR_RESET 5'd14 +#define DDR_CONFIG2_TRTP_MSB 20 +#define DDR_CONFIG2_TRTP_LSB 17 +#define DDR_CONFIG2_TRTP_MASK 0x001e0000 +#define DDR_CONFIG2_TRTP_GET(x) (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB) +#define DDR_CONFIG2_TRTP_SET(x) (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK) +//#define DDR_CONFIG2_TRTP_RESET 4'd8 +#define DDR_CONFIG2_TRTW_MSB 16 +#define DDR_CONFIG2_TRTW_LSB 12 +#define DDR_CONFIG2_TRTW_MASK 0x0001f000 +#define DDR_CONFIG2_TRTW_GET(x) (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB) +#define DDR_CONFIG2_TRTW_SET(x) (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK) +//#define DDR_CONFIG2_TRTW_RESET 5'd16 +#define DDR_CONFIG2_TWR_MSB 11 +#define DDR_CONFIG2_TWR_LSB 8 +#define DDR_CONFIG2_TWR_MASK 0x00000f00 +#define DDR_CONFIG2_TWR_GET(x) (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB) +#define DDR_CONFIG2_TWR_SET(x) (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK) +//#define DDR_CONFIG2_TWR_RESET 4'd6 +#define DDR_CONFIG2_CKE_MSB 7 +#define DDR_CONFIG2_CKE_LSB 7 +#define DDR_CONFIG2_CKE_MASK 0x00000080 +#define DDR_CONFIG2_CKE_GET(x) (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB) +#define DDR_CONFIG2_CKE_SET(x) (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK) +//#define DDR_CONFIG2_CKE_RESET 1'd0 +#define DDR_CONFIG2_PHASE_SELECT_MSB 6 +#define DDR_CONFIG2_PHASE_SELECT_LSB 6 +#define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040 +#define DDR_CONFIG2_PHASE_SELECT_GET(x) (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB) +#define DDR_CONFIG2_PHASE_SELECT_SET(x) (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK) +//#define DDR_CONFIG2_PHASE_SELECT_RESET 1'd0 +#define DDR_CONFIG2_CNTL_OE_EN_MSB 5 +#define DDR_CONFIG2_CNTL_OE_EN_LSB 5 +#define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020 +#define DDR_CONFIG2_CNTL_OE_EN_GET(x) (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB) +#define DDR_CONFIG2_CNTL_OE_EN_SET(x) (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK) +//#define DDR_CONFIG2_CNTL_OE_EN_RESET 1'd1 +#define DDR_CONFIG2_BURST_TYPE_MSB 4 +#define DDR_CONFIG2_BURST_TYPE_LSB 4 +#define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010 +#define DDR_CONFIG2_BURST_TYPE_GET(x) (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB) +#define DDR_CONFIG2_BURST_TYPE_SET(x) (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK) +//#define DDR_CONFIG2_BURST_TYPE_RESET 1'd0 +#define DDR_CONFIG2_BURST_LENGTH_MSB 3 +#define DDR_CONFIG2_BURST_LENGTH_LSB 0 +#define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f +#define DDR_CONFIG2_BURST_LENGTH_GET(x) (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB) +#define DDR_CONFIG2_BURST_LENGTH_SET(x) (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK) +//#define DDR_CONFIG2_BURST_LENGTH_RESET 4'd8 +#define DDR_CONFIG2_ADDRESS 0x18000004 + + +#define DDR2_CONFIG_DDR2_TWL_MSB 13 +#define DDR2_CONFIG_DDR2_TWL_LSB 10 +#define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00 +#define DDR2_CONFIG_DDR2_TWL_GET(x) (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB) +#define DDR2_CONFIG_DDR2_TWL_SET(x) (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK) +//#define DDR2_CONFIG_DDR2_TWL_RESET 4'd1 +#define DDR2_CONFIG_DDR2_ODT_MSB 9 +#define DDR2_CONFIG_DDR2_ODT_LSB 9 +#define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200 +#define DDR2_CONFIG_DDR2_ODT_GET(x) (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB) +#define DDR2_CONFIG_DDR2_ODT_SET(x) (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK) +//#define DDR2_CONFIG_DDR2_ODT_RESET 1'd1 +#define DDR2_CONFIG_TFAW_MSB 7 +#define DDR2_CONFIG_TFAW_LSB 2 +#define DDR2_CONFIG_TFAW_MASK 0x000000fc +#define DDR2_CONFIG_TFAW_GET(x) (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB) +#define DDR2_CONFIG_TFAW_SET(x) (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK) +//#define DDR2_CONFIG_TFAW_RESET 6'd22 +#define DDR2_CONFIG_ENABLE_DDR2_MSB 0 +#define DDR2_CONFIG_ENABLE_DDR2_LSB 0 +#define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001 +#define DDR2_CONFIG_ENABLE_DDR2_GET(x) (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB) +#define DDR2_CONFIG_ENABLE_DDR2_SET(x) (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK) +//#define DDR2_CONFIG_ENABLE_DDR2_RESET 1'd0 +#define DDR2_CONFIG_ADDRESS 0x180000b8 + +#define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31 +#define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30 +#define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000 +#define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB) +#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) +#define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_SPARE_MSB 20 +#define DDR_CTL_CONFIG_SPARE_LSB 6 +#define DDR_CTL_CONFIG_SPARE_MASK 0x001fffc0 +#define DDR_CTL_CONFIG_SPARE_GET(x) (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB) +#define DDR_CTL_CONFIG_SPARE_SET(x) (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK) +#define DDR_CTL_CONFIG_SPARE_RESET 0x4 // 4 +#define DDR_CTL_CONFIG_PREFETCH_CNT_MSB 5 +#define DDR_CTL_CONFIG_PREFETCH_CNT_LSB 2 +#define DDR_CTL_CONFIG_PREFETCH_CNT_MASK 0x0000003c +#define DDR_CTL_CONFIG_PREFETCH_CNT_GET(x) (((x) & DDR_CTL_CONFIG_PREFETCH_CNT_MASK) >> DDR_CTL_CONFIG_PREFETCH_CNT_LSB) +#define DDR_CTL_CONFIG_PREFETCH_CNT_SET(x) (((x) << DDR_CTL_CONFIG_PREFETCH_CNT_LSB) & DDR_CTL_CONFIG_PREFETCH_CNT_MASK) +#define DDR_CTL_CONFIG_PREFETCH_CNT_RESET 0x3 // 3 +#define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1 +#define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1 +#define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002 +#define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB) +#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) +#define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_SRAM_MODE_EN_MSB 0 +#define DDR_CTL_CONFIG_SRAM_MODE_EN_LSB 0 +#define DDR_CTL_CONFIG_SRAM_MODE_EN_MASK 0x00000001 +#define DDR_CTL_CONFIG_SRAM_MODE_EN_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SRAM_MODE_EN_LSB) +#define DDR_CTL_CONFIG_SRAM_MODE_EN_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SRAM_MODE_EN_MASK) +#define DDR_CTL_CONFIG_SRAM_MODE_EN_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_ADDRESS 0x18000108 + + +#define CPU_DPLL3_MEAS_AT_TXON_MSB 31 +#define CPU_DPLL3_MEAS_AT_TXON_LSB 31 +#define CPU_DPLL3_MEAS_AT_TXON_MASK 0x80000000 +#define CPU_DPLL3_MEAS_AT_TXON_GET(x) (((x) & CPU_DPLL3_MEAS_AT_TXON_MASK) >> CPU_DPLL3_MEAS_AT_TXON_LSB) +#define CPU_DPLL3_MEAS_AT_TXON_SET(x) (((x) << CPU_DPLL3_MEAS_AT_TXON_LSB) & CPU_DPLL3_MEAS_AT_TXON_MASK) +#define CPU_DPLL3_MEAS_AT_TXON_RESET 0x0 // 0 +#define CPU_DPLL3_DO_MEAS_MSB 30 +#define CPU_DPLL3_DO_MEAS_LSB 30 +#define CPU_DPLL3_DO_MEAS_MASK 0x40000000 +#define CPU_DPLL3_DO_MEAS_GET(x) (((x) & CPU_DPLL3_DO_MEAS_MASK) >> CPU_DPLL3_DO_MEAS_LSB) +#define CPU_DPLL3_DO_MEAS_SET(x) (((x) << CPU_DPLL3_DO_MEAS_LSB) & CPU_DPLL3_DO_MEAS_MASK) +#define CPU_DPLL3_DO_MEAS_RESET 0x0 // 0 +#define CPU_DPLL3_PHASE_SHIFT_MSB 29 +#define CPU_DPLL3_PHASE_SHIFT_LSB 23 +#define CPU_DPLL3_PHASE_SHIFT_MASK 0x3f800000 +#define CPU_DPLL3_PHASE_SHIFT_GET(x) (((x) & CPU_DPLL3_PHASE_SHIFT_MASK) >> CPU_DPLL3_PHASE_SHIFT_LSB) +#define CPU_DPLL3_PHASE_SHIFT_SET(x) (((x) << CPU_DPLL3_PHASE_SHIFT_LSB) & CPU_DPLL3_PHASE_SHIFT_MASK) +#define CPU_DPLL3_PHASE_SHIFT_RESET 0x0 // 0 +#define CPU_DPLL3_SQSUM_DVC_MSB 22 +#define CPU_DPLL3_SQSUM_DVC_LSB 3 +#define CPU_DPLL3_SQSUM_DVC_MASK 0x007ffff8 +#define CPU_DPLL3_SQSUM_DVC_GET(x) (((x) & CPU_DPLL3_SQSUM_DVC_MASK) >> CPU_DPLL3_SQSUM_DVC_LSB) +#define CPU_DPLL3_SQSUM_DVC_SET(x) (((x) << CPU_DPLL3_SQSUM_DVC_LSB) & CPU_DPLL3_SQSUM_DVC_MASK) +#define CPU_DPLL3_SQSUM_DVC_RESET 0x0 // 0 +#define CPU_DPLL3_SPARE_MSB 2 +#define CPU_DPLL3_SPARE_LSB 0 +#define CPU_DPLL3_SPARE_MASK 0x00000007 +#define CPU_DPLL3_SPARE_GET(x) (((x) & CPU_DPLL3_SPARE_MASK) >> CPU_DPLL3_SPARE_LSB) +#define CPU_DPLL3_SPARE_SET(x) (((x) << CPU_DPLL3_SPARE_LSB) & CPU_DPLL3_SPARE_MASK) +#define CPU_DPLL3_SPARE_RESET 0x0 // 0 +#define CPU_DPLL3_ADDRESS 0x181161c8 +#define CPU_DPLL4_MEAN_DVC_MSB 31 +#define CPU_DPLL4_MEAN_DVC_LSB 21 +#define CPU_DPLL4_MEAN_DVC_MASK 0xffe00000 +#define CPU_DPLL4_MEAN_DVC_GET(x) (((x) & CPU_DPLL4_MEAN_DVC_MASK) >> CPU_DPLL4_MEAN_DVC_LSB) +#define CPU_DPLL4_MEAN_DVC_SET(x) (((x) << CPU_DPLL4_MEAN_DVC_LSB) & CPU_DPLL4_MEAN_DVC_MASK) +#define CPU_DPLL4_MEAN_DVC_RESET 0x0 // 0 +#define CPU_DPLL4_VC_MEAS0_MSB 20 +#define CPU_DPLL4_VC_MEAS0_LSB 4 +#define CPU_DPLL4_VC_MEAS0_MASK 0x001ffff0 +#define CPU_DPLL4_VC_MEAS0_GET(x) (((x) & CPU_DPLL4_VC_MEAS0_MASK) >> CPU_DPLL4_VC_MEAS0_LSB) +#define CPU_DPLL4_VC_MEAS0_SET(x) (((x) << CPU_DPLL4_VC_MEAS0_LSB) & CPU_DPLL4_VC_MEAS0_MASK) +#define CPU_DPLL4_VC_MEAS0_RESET 0x0 // 0 +#define CPU_DPLL4_MEAS_DONE_MSB 3 +#define CPU_DPLL4_MEAS_DONE_LSB 3 +#define CPU_DPLL4_MEAS_DONE_MASK 0x00000008 +#define CPU_DPLL4_MEAS_DONE_GET(x) (((x) & CPU_DPLL4_MEAS_DONE_MASK) >> CPU_DPLL4_MEAS_DONE_LSB) +#define CPU_DPLL4_MEAS_DONE_SET(x) (((x) << CPU_DPLL4_MEAS_DONE_LSB) & CPU_DPLL4_MEAS_DONE_MASK) +#define CPU_DPLL4_MEAS_DONE_RESET 0x0 // 0 +#define CPU_DPLL4_SPARE_MSB 2 +#define CPU_DPLL4_SPARE_LSB 0 +#define CPU_DPLL4_SPARE_MASK 0x00000007 +#define CPU_DPLL4_SPARE_GET(x) (((x) & CPU_DPLL4_SPARE_MASK) >> CPU_DPLL4_SPARE_LSB) +#define CPU_DPLL4_SPARE_SET(x) (((x) << CPU_DPLL4_SPARE_LSB) & CPU_DPLL4_SPARE_MASK) +#define CPU_DPLL4_SPARE_RESET 0x0 // 0 +#define CPU_DPLL4_ADDRESS 0x181161cc + +#define DDR_DPLL3_MEAS_AT_TXON_MSB 31 +#define DDR_DPLL3_MEAS_AT_TXON_LSB 31 +#define DDR_DPLL3_MEAS_AT_TXON_MASK 0x80000000 +#define DDR_DPLL3_MEAS_AT_TXON_GET(x) (((x) & DDR_DPLL3_MEAS_AT_TXON_MASK) >> DDR_DPLL3_MEAS_AT_TXON_LSB) +#define DDR_DPLL3_MEAS_AT_TXON_SET(x) (((x) << DDR_DPLL3_MEAS_AT_TXON_LSB) & DDR_DPLL3_MEAS_AT_TXON_MASK) +#define DDR_DPLL3_MEAS_AT_TXON_RESET 0x0 // 0 +#define DDR_DPLL3_DO_MEAS_MSB 30 +#define DDR_DPLL3_DO_MEAS_LSB 30 +#define DDR_DPLL3_DO_MEAS_MASK 0x40000000 +#define DDR_DPLL3_DO_MEAS_GET(x) (((x) & DDR_DPLL3_DO_MEAS_MASK) >> DDR_DPLL3_DO_MEAS_LSB) +#define DDR_DPLL3_DO_MEAS_SET(x) (((x) << DDR_DPLL3_DO_MEAS_LSB) & DDR_DPLL3_DO_MEAS_MASK) +#define DDR_DPLL3_DO_MEAS_RESET 0x0 // 0 +#define DDR_DPLL3_PHASE_SHIFT_MSB 29 +#define DDR_DPLL3_PHASE_SHIFT_LSB 23 +#define DDR_DPLL3_PHASE_SHIFT_MASK 0x3f800000 +#define DDR_DPLL3_PHASE_SHIFT_GET(x) (((x) & DDR_DPLL3_PHASE_SHIFT_MASK) >> DDR_DPLL3_PHASE_SHIFT_LSB) +#define DDR_DPLL3_PHASE_SHIFT_SET(x) (((x) << DDR_DPLL3_PHASE_SHIFT_LSB) & DDR_DPLL3_PHASE_SHIFT_MASK) +#define DDR_DPLL3_PHASE_SHIFT_RESET 0x0 // 0 +#define DDR_DPLL3_SQSUM_DVC_MSB 22 +#define DDR_DPLL3_SQSUM_DVC_LSB 3 +#define DDR_DPLL3_SQSUM_DVC_MASK 0x007ffff8 +#define DDR_DPLL3_SQSUM_DVC_GET(x) (((x) & DDR_DPLL3_SQSUM_DVC_MASK) >> DDR_DPLL3_SQSUM_DVC_LSB) +#define DDR_DPLL3_SQSUM_DVC_SET(x) (((x) << DDR_DPLL3_SQSUM_DVC_LSB) & DDR_DPLL3_SQSUM_DVC_MASK) +#define DDR_DPLL3_SQSUM_DVC_RESET 0x0 // 0 +#define DDR_DPLL3_SPARE_MSB 2 +#define DDR_DPLL3_SPARE_LSB 0 +#define DDR_DPLL3_SPARE_MASK 0x00000007 +#define DDR_DPLL3_SPARE_GET(x) (((x) & DDR_DPLL3_SPARE_MASK) >> DDR_DPLL3_SPARE_LSB) +#define DDR_DPLL3_SPARE_SET(x) (((x) << DDR_DPLL3_SPARE_LSB) & DDR_DPLL3_SPARE_MASK) +#define DDR_DPLL3_SPARE_RESET 0x0 // 0 +#define DDR_DPLL3_ADDRESS 0x18116248 + +// 32'h1811624c (DDR_DPLL4) +#define DDR_DPLL4_MEAN_DVC_MSB 31 +#define DDR_DPLL4_MEAN_DVC_LSB 21 +#define DDR_DPLL4_MEAN_DVC_MASK 0xffe00000 +#define DDR_DPLL4_MEAN_DVC_GET(x) (((x) & DDR_DPLL4_MEAN_DVC_MASK) >> DDR_DPLL4_MEAN_DVC_LSB) +#define DDR_DPLL4_MEAN_DVC_SET(x) (((x) << DDR_DPLL4_MEAN_DVC_LSB) & DDR_DPLL4_MEAN_DVC_MASK) +#define DDR_DPLL4_MEAN_DVC_RESET 0x0 // 0 +#define DDR_DPLL4_VC_MEAS0_MSB 20 +#define DDR_DPLL4_VC_MEAS0_LSB 4 +#define DDR_DPLL4_VC_MEAS0_MASK 0x001ffff0 +#define DDR_DPLL4_VC_MEAS0_GET(x) (((x) & DDR_DPLL4_VC_MEAS0_MASK) >> DDR_DPLL4_VC_MEAS0_LSB) +#define DDR_DPLL4_VC_MEAS0_SET(x) (((x) << DDR_DPLL4_VC_MEAS0_LSB) & DDR_DPLL4_VC_MEAS0_MASK) +#define DDR_DPLL4_VC_MEAS0_RESET 0x0 // 0 +#define DDR_DPLL4_MEAS_DONE_MSB 3 +#define DDR_DPLL4_MEAS_DONE_LSB 3 +#define DDR_DPLL4_MEAS_DONE_MASK 0x00000008 +#define DDR_DPLL4_MEAS_DONE_GET(x) (((x) & DDR_DPLL4_MEAS_DONE_MASK) >> DDR_DPLL4_MEAS_DONE_LSB) +#define DDR_DPLL4_MEAS_DONE_SET(x) (((x) << DDR_DPLL4_MEAS_DONE_LSB) & DDR_DPLL4_MEAS_DONE_MASK) +#define DDR_DPLL4_MEAS_DONE_RESET 0x0 // 0 +#define DDR_DPLL4_SPARE_MSB 2 +#define DDR_DPLL4_SPARE_LSB 0 +#define DDR_DPLL4_SPARE_MASK 0x00000007 +#define DDR_DPLL4_SPARE_GET(x) (((x) & DDR_DPLL4_SPARE_MASK) >> DDR_DPLL4_SPARE_LSB) +#define DDR_DPLL4_SPARE_SET(x) (((x) << DDR_DPLL4_SPARE_LSB) & DDR_DPLL4_SPARE_MASK) +#define DDR_DPLL4_SPARE_RESET 0x0 // 0 +#define DDR_DPLL4_ADDRESS 0x1811624c + +#define DPLL2_ADDRESS_c4 0x181161c4 +#define DPLL3_ADDRESS_c8 CPU_DPLL3_ADDRESS +#define DPLL2_ADDRESS_44 0x18116244 +#define DPLL3_ADDRESS_48 DDR_DPLL3_ADDRESS +#define DPLL3_ADDRESS_88 0x18116188 + +#define PCIe_DPLL_REFDIV_MSB 31 +#define PCIe_DPLL_REFDIV_LSB 27 +#define PCIe_DPLL_REFDIV_MASK 0xf8000000 +#define PCIe_DPLL_REFDIV_GET(x) (((x) & PCIe_DPLL_REFDIV_MASK) >> PCIe_DPLL_REFDIV_LSB) +#define PCIe_DPLL_REFDIV_SET(x) (((x) << PCIe_DPLL_REFDIV_LSB) & PCIe_DPLL_REFDIV_MASK) +#define PCIe_DPLL_REFDIV_RESET 0x1 // 1 +#define PCIe_DPLL_NINT_MSB 26 +#define PCIe_DPLL_NINT_LSB 18 +#define PCIe_DPLL_NINT_MASK 0x07fc0000 +#define PCIe_DPLL_NINT_GET(x) (((x) & PCIe_DPLL_NINT_MASK) >> PCIe_DPLL_NINT_LSB) +#define PCIe_DPLL_NINT_SET(x) (((x) << PCIe_DPLL_NINT_LSB) & PCIe_DPLL_NINT_MASK) +#define PCIe_DPLL_NINT_RESET 0x10 // 16 +#define PCIe_DPLL_NFRAC_MSB 17 +#define PCIe_DPLL_NFRAC_LSB 0 +#define PCIe_DPLL_NFRAC_MASK 0x0003ffff +#define PCIe_DPLL_NFRAC_GET(x) (((x) & PCIe_DPLL_NFRAC_MASK) >> PCIe_DPLL_NFRAC_LSB) +#define PCIe_DPLL_NFRAC_SET(x) (((x) << PCIe_DPLL_NFRAC_LSB) & PCIe_DPLL_NFRAC_MASK) +#define PCIe_DPLL_NFRAC_RESET 0x0 // 0 +#define PCIe_DPLL_ADDRESS 0x18116c00 + +// 32'h18116c04 (PCIe_DPLL2) +#define PCIe_DPLL2_RANGE_MSB 31 +#define PCIe_DPLL2_RANGE_LSB 31 +#define PCIe_DPLL2_RANGE_MASK 0x80000000 +#define PCIe_DPLL2_RANGE_GET(x) (((x) & PCIe_DPLL2_RANGE_MASK) >> PCIe_DPLL2_RANGE_LSB) +#define PCIe_DPLL2_RANGE_SET(x) (((x) << PCIe_DPLL2_RANGE_LSB) & PCIe_DPLL2_RANGE_MASK) +#define PCIe_DPLL2_RANGE_RESET 0x0 // 0 +#define PCIe_DPLL2_LOCAL_PLL_MSB 30 +#define PCIe_DPLL2_LOCAL_PLL_LSB 30 +#define PCIe_DPLL2_LOCAL_PLL_MASK 0x40000000 +#define PCIe_DPLL2_LOCAL_PLL_GET(x) (((x) & PCIe_DPLL2_LOCAL_PLL_MASK) >> PCIe_DPLL2_LOCAL_PLL_LSB) +#define PCIe_DPLL2_LOCAL_PLL_SET(x) (((x) << PCIe_DPLL2_LOCAL_PLL_LSB) & PCIe_DPLL2_LOCAL_PLL_MASK) +#define PCIe_DPLL2_LOCAL_PLL_RESET 0x0 // 0 +#define PCIe_DPLL2_KI_MSB 29 +#define PCIe_DPLL2_KI_LSB 26 +#define PCIe_DPLL2_KI_MASK 0x3c000000 +#define PCIe_DPLL2_KI_GET(x) (((x) & PCIe_DPLL2_KI_MASK) >> PCIe_DPLL2_KI_LSB) +#define PCIe_DPLL2_KI_SET(x) (((x) << PCIe_DPLL2_KI_LSB) & PCIe_DPLL2_KI_MASK) +#define PCIe_DPLL2_KI_RESET 0x6 // 6 +#define PCIe_DPLL2_KD_MSB 25 +#define PCIe_DPLL2_KD_LSB 19 +#define PCIe_DPLL2_KD_MASK 0x03f80000 +#define PCIe_DPLL2_KD_GET(x) (((x) & PCIe_DPLL2_KD_MASK) >> PCIe_DPLL2_KD_LSB) +#define PCIe_DPLL2_KD_SET(x) (((x) << PCIe_DPLL2_KD_LSB) & PCIe_DPLL2_KD_MASK) +#define PCIe_DPLL2_KD_RESET 0x7f // 127 +#define PCIe_DPLL2_EN_NEGTRIG_MSB 18 +#define PCIe_DPLL2_EN_NEGTRIG_LSB 18 +#define PCIe_DPLL2_EN_NEGTRIG_MASK 0x00040000 +#define PCIe_DPLL2_EN_NEGTRIG_GET(x) (((x) & PCIe_DPLL2_EN_NEGTRIG_MASK) >> PCIe_DPLL2_EN_NEGTRIG_LSB) +#define PCIe_DPLL2_EN_NEGTRIG_SET(x) (((x) << PCIe_DPLL2_EN_NEGTRIG_LSB) & PCIe_DPLL2_EN_NEGTRIG_MASK) +#define PCIe_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 +#define PCIe_DPLL2_SEL_1SDM_MSB 17 +#define PCIe_DPLL2_SEL_1SDM_LSB 17 +#define PCIe_DPLL2_SEL_1SDM_MASK 0x00020000 +#define PCIe_DPLL2_SEL_1SDM_GET(x) (((x) & PCIe_DPLL2_SEL_1SDM_MASK) >> PCIe_DPLL2_SEL_1SDM_LSB) +#define PCIe_DPLL2_SEL_1SDM_SET(x) (((x) << PCIe_DPLL2_SEL_1SDM_LSB) & PCIe_DPLL2_SEL_1SDM_MASK) +#define PCIe_DPLL2_SEL_1SDM_RESET 0x0 // 0 +#define PCIe_DPLL2_PLL_PWD_MSB 16 +#define PCIe_DPLL2_PLL_PWD_LSB 16 +#define PCIe_DPLL2_PLL_PWD_MASK 0x00010000 +#define PCIe_DPLL2_PLL_PWD_GET(x) (((x) & PCIe_DPLL2_PLL_PWD_MASK) >> PCIe_DPLL2_PLL_PWD_LSB) +#define PCIe_DPLL2_PLL_PWD_SET(x) (((x) << PCIe_DPLL2_PLL_PWD_LSB) & PCIe_DPLL2_PLL_PWD_MASK) +#define PCIe_DPLL2_PLL_PWD_RESET 0x1 // 1 +#define PCIe_DPLL2_OUTDIV_MSB 15 +#define PCIe_DPLL2_OUTDIV_LSB 13 +#define PCIe_DPLL2_OUTDIV_MASK 0x0000e000 +#define PCIe_DPLL2_OUTDIV_GET(x) (((x) & PCIe_DPLL2_OUTDIV_MASK) >> PCIe_DPLL2_OUTDIV_LSB) +#define PCIe_DPLL2_OUTDIV_SET(x) (((x) << PCIe_DPLL2_OUTDIV_LSB) & PCIe_DPLL2_OUTDIV_MASK) +#define PCIe_DPLL2_OUTDIV_RESET 0x0 // 0 +#define PCIe_DPLL2_DELTA_MSB 12 +#define PCIe_DPLL2_DELTA_LSB 7 +#define PCIe_DPLL2_DELTA_MASK 0x00001f80 +#define PCIe_DPLL2_DELTA_GET(x) (((x) & PCIe_DPLL2_DELTA_MASK) >> PCIe_DPLL2_DELTA_LSB) +#define PCIe_DPLL2_DELTA_SET(x) (((x) << PCIe_DPLL2_DELTA_LSB) & PCIe_DPLL2_DELTA_MASK) +#define PCIe_DPLL2_DELTA_RESET 0x1e // 30 +#define PCIe_DPLL2_SPARE_MSB 6 +#define PCIe_DPLL2_SPARE_LSB 0 +#define PCIe_DPLL2_SPARE_MASK 0x0000007f +#define PCIe_DPLL2_SPARE_GET(x) (((x) & PCIe_DPLL2_SPARE_MASK) >> PCIe_DPLL2_SPARE_LSB) +#define PCIe_DPLL2_SPARE_SET(x) (((x) << PCIe_DPLL2_SPARE_LSB) & PCIe_DPLL2_SPARE_MASK) +#define PCIe_DPLL2_SPARE_RESET 0x0 // 0 +#define PCIe_DPLL2_ADDRESS 0x18116c04 + +#define PCIe_DPLL3_MEAS_AT_TXON_MSB 31 +#define PCIe_DPLL3_MEAS_AT_TXON_LSB 31 +#define PCIe_DPLL3_MEAS_AT_TXON_MASK 0x80000000 +#define PCIe_DPLL3_MEAS_AT_TXON_GET(x) (((x) & PCIe_DPLL3_MEAS_AT_TXON_MASK) >> PCIe_DPLL3_MEAS_AT_TXON_LSB) +#define PCIe_DPLL3_MEAS_AT_TXON_SET(x) (((x) << PCIe_DPLL3_MEAS_AT_TXON_LSB) & PCIe_DPLL3_MEAS_AT_TXON_MASK) +#define PCIe_DPLL3_MEAS_AT_TXON_RESET 0x0 // 0 +#define PCIe_DPLL3_DO_MEAS_MSB 30 +#define PCIe_DPLL3_DO_MEAS_LSB 30 +#define PCIe_DPLL3_DO_MEAS_MASK 0x40000000 +#define PCIe_DPLL3_DO_MEAS_GET(x) (((x) & PCIe_DPLL3_DO_MEAS_MASK) >> PCIe_DPLL3_DO_MEAS_LSB) +#define PCIe_DPLL3_DO_MEAS_SET(x) (((x) << PCIe_DPLL3_DO_MEAS_LSB) & PCIe_DPLL3_DO_MEAS_MASK) +#define PCIe_DPLL3_DO_MEAS_RESET 0x0 // 0 +#define PCIe_DPLL3_PHASE_SHIFT_MSB 29 +#define PCIe_DPLL3_PHASE_SHIFT_LSB 23 +#define PCIe_DPLL3_PHASE_SHIFT_MASK 0x3f800000 +#define PCIe_DPLL3_PHASE_SHIFT_GET(x) (((x) & PCIe_DPLL3_PHASE_SHIFT_MASK) >> PCIe_DPLL3_PHASE_SHIFT_LSB) +#define PCIe_DPLL3_PHASE_SHIFT_SET(x) (((x) << PCIe_DPLL3_PHASE_SHIFT_LSB) & PCIe_DPLL3_PHASE_SHIFT_MASK) +#define PCIe_DPLL3_PHASE_SHIFT_RESET 0x0 // 0 +#define PCIe_DPLL3_SQSUM_DVC_MSB 22 +#define PCIe_DPLL3_SQSUM_DVC_LSB 3 +#define PCIe_DPLL3_SQSUM_DVC_MASK 0x007ffff8 +#define PCIe_DPLL3_SQSUM_DVC_GET(x) (((x) & PCIe_DPLL3_SQSUM_DVC_MASK) >> PCIe_DPLL3_SQSUM_DVC_LSB) +#define PCIe_DPLL3_SQSUM_DVC_SET(x) (((x) << PCIe_DPLL3_SQSUM_DVC_LSB) & PCIe_DPLL3_SQSUM_DVC_MASK) +#define PCIe_DPLL3_SQSUM_DVC_RESET 0x0 // 0 +#define PCIe_DPLL3_SPARE_MSB 2 +#define PCIe_DPLL3_SPARE_LSB 0 +#define PCIe_DPLL3_SPARE_MASK 0x00000007 +#define PCIe_DPLL3_SPARE_GET(x) (((x) & PCIe_DPLL3_SPARE_MASK) >> PCIe_DPLL3_SPARE_LSB) +#define PCIe_DPLL3_SPARE_SET(x) (((x) << PCIe_DPLL3_SPARE_LSB) & PCIe_DPLL3_SPARE_MASK) +#define PCIe_DPLL3_SPARE_RESET 0x0 // 0 +#define PCIe_DPLL3_ADDRESS 0x18116c08 + +#define PCIe_DPLL4_MEAN_DVC_MSB 31 +#define PCIe_DPLL4_MEAN_DVC_LSB 21 +#define PCIe_DPLL4_MEAN_DVC_MASK 0xffe00000 +#define PCIe_DPLL4_MEAN_DVC_GET(x) (((x) & PCIe_DPLL4_MEAN_DVC_MASK) >> PCIe_DPLL4_MEAN_DVC_LSB) +#define PCIe_DPLL4_MEAN_DVC_SET(x) (((x) << PCIe_DPLL4_MEAN_DVC_LSB) & PCIe_DPLL4_MEAN_DVC_MASK) +#define PCIe_DPLL4_MEAN_DVC_RESET 0x0 // 0 +#define PCIe_DPLL4_VC_MEAS0_MSB 20 +#define PCIe_DPLL4_VC_MEAS0_LSB 4 +#define PCIe_DPLL4_VC_MEAS0_MASK 0x001ffff0 +#define PCIe_DPLL4_VC_MEAS0_GET(x) (((x) & PCIe_DPLL4_VC_MEAS0_MASK) >> PCIe_DPLL4_VC_MEAS0_LSB) +#define PCIe_DPLL4_VC_MEAS0_SET(x) (((x) << PCIe_DPLL4_VC_MEAS0_LSB) & PCIe_DPLL4_VC_MEAS0_MASK) +#define PCIe_DPLL4_VC_MEAS0_RESET 0x0 // 0 +#define PCIe_DPLL4_MEAS_DONE_MSB 3 +#define PCIe_DPLL4_MEAS_DONE_LSB 3 +#define PCIe_DPLL4_MEAS_DONE_MASK 0x00000008 +#define PCIe_DPLL4_MEAS_DONE_GET(x) (((x) & PCIe_DPLL4_MEAS_DONE_MASK) >> PCIe_DPLL4_MEAS_DONE_LSB) +#define PCIe_DPLL4_MEAS_DONE_SET(x) (((x) << PCIe_DPLL4_MEAS_DONE_LSB) & PCIe_DPLL4_MEAS_DONE_MASK) +#define PCIe_DPLL4_MEAS_DONE_RESET 0x0 // 0 +#define PCIe_DPLL4_SPARE_MSB 2 +#define PCIe_DPLL4_SPARE_LSB 0 +#define PCIe_DPLL4_SPARE_MASK 0x00000007 +#define PCIe_DPLL4_SPARE_GET(x) (((x) & PCIe_DPLL4_SPARE_MASK) >> PCIe_DPLL4_SPARE_LSB) +#define PCIe_DPLL4_SPARE_SET(x) (((x) << PCIe_DPLL4_SPARE_LSB) & PCIe_DPLL4_SPARE_MASK) +#define PCIe_DPLL4_SPARE_RESET 0x0 // 0 +#define PCIe_DPLL4_ADDRESS 0x18116c0c + +#define ATH_DDR_COUNT_LOC 0xbd000000 +#define ATH_CPU_COUNT_LOC 0xbd000004 + +#define XTAL_ADDRESS 0x18116290 + +#define GPIO_OE_ADDRESS 0x18040000 + + +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MSB 31 +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB 31 +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK 0x80000000 +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MSB 30 +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB 29 +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK 0x60000000 +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_PERSTDELAY_MSB 28 +#define PCIE_PHY_REG_1_PERSTDELAY_LSB 27 +#define PCIE_PHY_REG_1_PERSTDELAY_MASK 0x18000000 +#define PCIE_PHY_REG_1_PERSTDELAY_GET(x) (((x) & PCIE_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_PHY_REG_1_PERSTDELAY_LSB) +#define PCIE_PHY_REG_1_PERSTDELAY_SET(x) (((x) << PCIE_PHY_REG_1_PERSTDELAY_LSB) & PCIE_PHY_REG_1_PERSTDELAY_MASK) +#define PCIE_PHY_REG_1_PERSTDELAY_RESET 0x2 // 2 +#define PCIE_PHY_REG_1_CLKOBSSEL_MSB 26 +#define PCIE_PHY_REG_1_CLKOBSSEL_LSB 25 +#define PCIE_PHY_REG_1_CLKOBSSEL_MASK 0x06000000 +#define PCIE_PHY_REG_1_CLKOBSSEL_GET(x) (((x) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_PHY_REG_1_CLKOBSSEL_LSB) +#define PCIE_PHY_REG_1_CLKOBSSEL_SET(x) (((x) << PCIE_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) +#define PCIE_PHY_REG_1_CLKOBSSEL_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_DATAOBSEN_MSB 24 +#define PCIE_PHY_REG_1_DATAOBSEN_LSB 24 +#define PCIE_PHY_REG_1_DATAOBSEN_MASK 0x01000000 +#define PCIE_PHY_REG_1_DATAOBSEN_GET(x) (((x) & PCIE_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_PHY_REG_1_DATAOBSEN_LSB) +#define PCIE_PHY_REG_1_DATAOBSEN_SET(x) (((x) << PCIE_PHY_REG_1_DATAOBSEN_LSB) & PCIE_PHY_REG_1_DATAOBSEN_MASK) +#define PCIE_PHY_REG_1_DATAOBSEN_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_FUNCTESTEN_MSB 23 +#define PCIE_PHY_REG_1_FUNCTESTEN_LSB 23 +#define PCIE_PHY_REG_1_FUNCTESTEN_MASK 0x00800000 +#define PCIE_PHY_REG_1_FUNCTESTEN_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_PHY_REG_1_FUNCTESTEN_LSB) +#define PCIE_PHY_REG_1_FUNCTESTEN_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) +#define PCIE_PHY_REG_1_FUNCTESTEN_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_DISABLE_MSB 22 +#define PCIE_PHY_REG_1_SERDES_DISABLE_LSB 22 +#define PCIE_PHY_REG_1_SERDES_DISABLE_MASK 0x00400000 +#define PCIE_PHY_REG_1_SERDES_DISABLE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_PHY_REG_1_SERDES_DISABLE_LSB) +#define PCIE_PHY_REG_1_SERDES_DISABLE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) +#define PCIE_PHY_REG_1_SERDES_DISABLE_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_RXCLKINV_MSB 21 +#define PCIE_PHY_REG_1_RXCLKINV_LSB 21 +#define PCIE_PHY_REG_1_RXCLKINV_MASK 0x00200000 +#define PCIE_PHY_REG_1_RXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_RXCLKINV_MASK) >> PCIE_PHY_REG_1_RXCLKINV_LSB) +#define PCIE_PHY_REG_1_RXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_RXCLKINV_LSB) & PCIE_PHY_REG_1_RXCLKINV_MASK) +#define PCIE_PHY_REG_1_RXCLKINV_RESET 0x1 // 1 +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MSB 20 +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB 20 +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK 0x00100000 +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MSB 19 +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB 19 +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK 0x00080000 +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_ENABLECLKREQ_MSB 18 +#define PCIE_PHY_REG_1_ENABLECLKREQ_LSB 18 +#define PCIE_PHY_REG_1_ENABLECLKREQ_MASK 0x00040000 +#define PCIE_PHY_REG_1_ENABLECLKREQ_GET(x) (((x) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_PHY_REG_1_ENABLECLKREQ_LSB) +#define PCIE_PHY_REG_1_ENABLECLKREQ_SET(x) (((x) << PCIE_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) +#define PCIE_PHY_REG_1_ENABLECLKREQ_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_FORCELOOPBACK_MSB 17 +#define PCIE_PHY_REG_1_FORCELOOPBACK_LSB 17 +#define PCIE_PHY_REG_1_FORCELOOPBACK_MASK 0x00020000 +#define PCIE_PHY_REG_1_FORCELOOPBACK_GET(x) (((x) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_PHY_REG_1_FORCELOOPBACK_LSB) +#define PCIE_PHY_REG_1_FORCELOOPBACK_SET(x) (((x) << PCIE_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) +#define PCIE_PHY_REG_1_FORCELOOPBACK_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SEL_CLK_MSB 16 +#define PCIE_PHY_REG_1_SEL_CLK_LSB 15 +#define PCIE_PHY_REG_1_SEL_CLK_MASK 0x00018000 +#define PCIE_PHY_REG_1_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_1_SEL_CLK_MASK) >> PCIE_PHY_REG_1_SEL_CLK_LSB) +#define PCIE_PHY_REG_1_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_1_SEL_CLK_LSB) & PCIE_PHY_REG_1_SEL_CLK_MASK) +#define PCIE_PHY_REG_1_SEL_CLK_RESET 0x2 // 2 +#define PCIE_PHY_REG_1_SERDES_RX_EQ_MSB 14 +#define PCIE_PHY_REG_1_SERDES_RX_EQ_LSB 14 +#define PCIE_PHY_REG_1_SERDES_RX_EQ_MASK 0x00004000 +#define PCIE_PHY_REG_1_SERDES_RX_EQ_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) +#define PCIE_PHY_REG_1_SERDES_RX_EQ_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) +#define PCIE_PHY_REG_1_SERDES_RX_EQ_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MSB 13 +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB 13 +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK 0x00002000 +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_RESET 0x1 // 1 +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB 12 +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB 12 +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK 0x00001000 +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MSB 11 +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB 11 +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK 0x00000800 +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_CDR_BW_MSB 10 +#define PCIE_PHY_REG_1_SERDES_CDR_BW_LSB 9 +#define PCIE_PHY_REG_1_SERDES_CDR_BW_MASK 0x00000600 +#define PCIE_PHY_REG_1_SERDES_CDR_BW_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) +#define PCIE_PHY_REG_1_SERDES_CDR_BW_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) +#define PCIE_PHY_REG_1_SERDES_CDR_BW_RESET 0x3 // 3 +#define PCIE_PHY_REG_1_SERDES_TH_LOS_MSB 8 +#define PCIE_PHY_REG_1_SERDES_TH_LOS_LSB 7 +#define PCIE_PHY_REG_1_SERDES_TH_LOS_MASK 0x00000180 +#define PCIE_PHY_REG_1_SERDES_TH_LOS_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) +#define PCIE_PHY_REG_1_SERDES_TH_LOS_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) +#define PCIE_PHY_REG_1_SERDES_TH_LOS_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MSB 6 +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB 6 +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK 0x00000040 +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_RESET 0x1 // 1 +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MSB 5 +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB 5 +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK 0x00000020 +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MSB 4 +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB 4 +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK 0x00000010 +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_RESET 0x1 // 1 +#define PCIE_PHY_REG_1_S_MSB 3 +#define PCIE_PHY_REG_1_S_LSB 0 +#define PCIE_PHY_REG_1_S_MASK 0x0000000f +#define PCIE_PHY_REG_1_S_GET(x) (((x) & PCIE_PHY_REG_1_S_MASK) >> PCIE_PHY_REG_1_S_LSB) +#define PCIE_PHY_REG_1_S_SET(x) (((x) << PCIE_PHY_REG_1_S_LSB) & PCIE_PHY_REG_1_S_MASK) +#define PCIE_PHY_REG_1_S_RESET 0xe // 14 +#define PCIE_PHY_REG_1_ADDRESS 0x18116cc0 + + +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xb // 11 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0xa // 10 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x14 // 20 +#define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030 + + +#if (CFG_PLL_FREQ == CFG_PLL_400_400_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(32) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(20) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_400_200_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(32) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(20) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(2) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(2) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(15) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_1_2G_400_200) + + #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(48) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) + + #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(32) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_500_1G_250) + + #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(48) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) + + #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(40) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_550_1_1G_275) + + #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(44) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_400_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_332_166) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_332_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_266_133) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_266_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_566_550_275) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(22) + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(13) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(768) | DDR_PLL_DITHER_NFRAC_MAX_SET(768) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_566_525_262) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(13) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) + + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(128) | DDR_PLL_DITHER_NFRAC_MAX_SET(128) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_566_500_250) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(512) | DDR_PLL_DITHER_NFRAC_MAX_SET(512) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_566_475_237) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + /* + * Date: 2011-030-24 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.312 + */ + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(19) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(11) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(41) | CPU_PLL_DITHER_NFRAC_MAX_SET(41) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(1023) + /* + * Date: 2011-030-24 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.312 + */ + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(895) | DDR_PLL_DITHER_NFRAC_MAX_SET(1023) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_566_450_225) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(36) + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(22) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) + + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(512) | DDR_PLL_DITHER_NFRAC_MAX_SET(512) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_566_400_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(16) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(10) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_560_480_240) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(19) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) + + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(25) | CPU_PLL_DITHER_NFRAC_MAX_SET(25) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(204) | DDR_PLL_DITHER_NFRAC_MAX_SET(204) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_650_600_300) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(26) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_600_300) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_550_275) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(22) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_650_325) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_525_262) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_575_287) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(23) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(14) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_450_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(18) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_533_400_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(21) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(13) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_533_500_250) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(21) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(13) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_350_175) + + #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(28) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_300_150) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(15) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_400_300) + + #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(32) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_500_400_200) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(20) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(12) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + /* + * Date: 2011-030-21 + * Name: Charles Teng + * Reason: patch from LSDK-9.2.0.303 + * WASP 1.1 support + */ + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) + + #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(32) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_700_400_200) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(28) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(17) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(3) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_500_250) + + #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) + #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_500_500_250) + + #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(20) + #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) + #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) + #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) + + #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(20) + #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) + #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) + #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) + + #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) + + #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) + #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) + #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#endif + +#endif /* _AR934X_SOC_H */ diff --git a/u-boot/include/asm-mips/addrspace.h b/u-boot/include/asm-mips/addrspace.h new file mode 100755 index 0000000..67f1537 --- /dev/null +++ b/u-boot/include/asm-mips/addrspace.h @@ -0,0 +1,84 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 by Ralf Baechle + * Copyright (C) 2000 by Maciej W. Rozycki + * + * Defitions for the address spaces of the MIPS CPUs. + */ +#ifndef __ASM_MIPS_ADDRSPACE_H +#define __ASM_MIPS_ADDRSPACE_H + +/* + * Memory segments (32bit kernel mode addresses) + */ +#define KUSEG 0x00000000 +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 +#define KSEG2 0xc0000000 +#define KSEG3 0xe0000000 + +#define K0BASE KSEG0 + +/* + * Returns the kernel segment base of a given address + */ +#ifndef __ASSEMBLY__ +#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) +#else +#define KSEGX(a) ((a) & 0xe0000000) +#endif + +/* + * Returns the physical address of a KSEG0/KSEG1 address + */ +#ifndef __ASSEMBLY__ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) +#else +#define PHYSADDR(a) ((a) & 0x1fffffff) +#endif + +/* + * Returns the uncached address of a sdram address + */ +#ifndef __ASSEMBLY__ +#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229) +/* We use a 36 bit physical address map here and + cannot access physical memory directly from core */ +#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) +#elif defined(CONFIG_AR7100) || defined(CONFIG_AR7240) +#define UNCACHED_SDRAM(a) KSEG1ADDR((a)) +#else /* !CONFIG_AR7100 */ +#define UNCACHED_SDRAM(a) PHYSADDR(a) +#endif /* CONFIG_AU1X00 */ +#endif /* __ASSEMBLY__ */ +/* + * Map an address to a certain kernel segment + */ +#ifndef __ASSEMBLY__ +#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) +#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) +#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) +#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) +#else +#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) +#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) +#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) +#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) +#endif + +/* + * Memory segments (64bit kernel mode addresses) + */ +#define XKUSEG 0x0000000000000000 +#define XKSSEG 0x4000000000000000 +#define XKPHYS 0x8000000000000000 +#define XKSEG 0xc000000000000000 +#define CKSEG0 0xffffffff80000000 +#define CKSEG1 0xffffffffa0000000 +#define CKSSEG 0xffffffffc0000000 +#define CKSEG3 0xffffffffe0000000 + +#endif /* __ASM_MIPS_ADDRSPACE_H */ diff --git a/u-boot/include/asm-mips/bitops.h b/u-boot/include/asm-mips/bitops.h new file mode 100755 index 0000000..ae2693a --- /dev/null +++ b/u-boot/include/asm-mips/bitops.h @@ -0,0 +1,913 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org) + * Copyright (c) 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_BITOPS_H +#define _ASM_BITOPS_H + +#include +#include /* sigh ... */ + +#ifdef __KERNEL__ + +#include +#include +#include + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +/* + * Only disable interrupt for kernel mode stuff to keep usermode stuff + * that dares to use kernel include files alive. + */ +#define __bi_flags unsigned long flags +#define __bi_cli() __cli() +#define __bi_save_flags(x) __save_flags(x) +#define __bi_save_and_cli(x) __save_and_cli(x) +#define __bi_restore_flags(x) __restore_flags(x) +#else +#define __bi_flags +#define __bi_cli() +#define __bi_save_flags(x) +#define __bi_save_and_cli(x) +#define __bi_restore_flags(x) +#endif /* __KERNEL__ */ + +#ifdef CONFIG_CPU_HAS_LLSC + +#include + +/* + * These functions for MIPS ISA > 1 are interrupt and SMP proof and + * interrupt friendly + */ + +/* + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +extern __inline__ void +set_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp; + + __asm__ __volatile__( + "1:\tll\t%0, %1\t\t# set_bit\n\t" + "or\t%0, %2\n\t" + "sc\t%0, %1\n\t" + "beqz\t%0, 1b" + : "=&r" (temp), "=m" (*m) + : "ir" (1UL << (nr & 0x1f)), "m" (*m)); +} + +/* + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +extern __inline__ void __set_bit(int nr, volatile void * addr) +{ + unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + + *m |= 1UL << (nr & 31); +} + +/* + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +extern __inline__ void +clear_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp; + + __asm__ __volatile__( + "1:\tll\t%0, %1\t\t# clear_bit\n\t" + "and\t%0, %2\n\t" + "sc\t%0, %1\n\t" + "beqz\t%0, 1b\n\t" + : "=&r" (temp), "=m" (*m) + : "ir" (~(1UL << (nr & 0x1f))), "m" (*m)); +} + +/* + * change_bit - Toggle a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +extern __inline__ void +change_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp; + + __asm__ __volatile__( + "1:\tll\t%0, %1\t\t# change_bit\n\t" + "xor\t%0, %2\n\t" + "sc\t%0, %1\n\t" + "beqz\t%0, 1b" + : "=&r" (temp), "=m" (*m) + : "ir" (1UL << (nr & 0x1f)), "m" (*m)); +} + +/* + * __change_bit - Toggle a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +extern __inline__ void __change_bit(int nr, volatile void * addr) +{ + unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + + *m ^= 1UL << (nr & 31); +} + +/* + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int +test_and_set_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp, res; + + __asm__ __volatile__( + ".set\tnoreorder\t\t# test_and_set_bit\n" + "1:\tll\t%0, %1\n\t" + "or\t%2, %0, %3\n\t" + "sc\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" + " and\t%2, %0, %3\n\t" + ".set\treorder" + : "=&r" (temp), "=m" (*m), "=&r" (res) + : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "memory"); + + return res != 0; +} + +/* + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + + return retval; +} + +/* + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int +test_and_clear_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp, res; + + __asm__ __volatile__( + ".set\tnoreorder\t\t# test_and_clear_bit\n" + "1:\tll\t%0, %1\n\t" + "or\t%2, %0, %3\n\t" + "xor\t%2, %3\n\t" + "sc\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" + " and\t%2, %0, %3\n\t" + ".set\treorder" + : "=&r" (temp), "=m" (*m), "=&r" (res) + : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "memory"); + + return res != 0; +} + +/* + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + + return retval; +} + +/* + * test_and_change_bit - Change a bit and return its new value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int +test_and_change_bit(int nr, volatile void *addr) +{ + unsigned long *m = ((unsigned long *) addr) + (nr >> 5); + unsigned long temp, res; + + __asm__ __volatile__( + ".set\tnoreorder\t\t# test_and_change_bit\n" + "1:\tll\t%0, %1\n\t" + "xor\t%2, %0, %3\n\t" + "sc\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" + " and\t%2, %0, %3\n\t" + ".set\treorder" + : "=&r" (temp), "=m" (*m), "=&r" (res) + : "r" (1UL << (nr & 0x1f)), "m" (*m) + : "memory"); + + return res != 0; +} + +/* + * __test_and_change_bit - Change a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + + return retval; +} + +#else /* MIPS I */ + +/* + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +extern __inline__ void set_bit(int nr, volatile void * addr) +{ + int mask; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + *a |= mask; + __bi_restore_flags(flags); +} + +/* + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +extern __inline__ void __set_bit(int nr, volatile void * addr) +{ + int mask; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +/* + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +extern __inline__ void clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + *a &= ~mask; + __bi_restore_flags(flags); +} + +/* + * change_bit - Toggle a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +extern __inline__ void change_bit(int nr, volatile void * addr) +{ + int mask; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + *a ^= mask; + __bi_restore_flags(flags); +} + +/* + * __change_bit - Toggle a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +extern __inline__ void __change_bit(int nr, volatile void * addr) +{ + unsigned long * m = ((unsigned long *) addr) + (nr >> 5); + + *m ^= 1UL << (nr & 31); +} + +/* + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + retval = (mask & *a) != 0; + *a |= mask; + __bi_restore_flags(flags); + + return retval; +} + +/* + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + + return retval; +} + +/* + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + __bi_restore_flags(flags); + + return retval; +} + +/* + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + + return retval; +} + +/* + * test_and_change_bit - Change a bit and return its new value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +extern __inline__ int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + __bi_flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __bi_save_and_cli(flags); + retval = (mask & *a) != 0; + *a ^= mask; + __bi_restore_flags(flags); + + return retval; +} + +/* + * __test_and_change_bit - Change a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +extern __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + + return retval; +} + +#undef __bi_flags +#undef __bi_cli +#undef __bi_save_flags +#undef __bi_restore_flags + +#endif /* MIPS I */ + +/* + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +extern __inline__ int test_bit(int nr, volatile void *addr) +{ + return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0; +} + +#ifndef __MIPSEB__ + +/* Little endian versions. */ + +/* + * find_first_zero_bit - find the first zero bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit-number of the first zero bit, not the number of the byte + * containing a bit. + */ +extern __inline__ int find_first_zero_bit (void *addr, unsigned size) +{ + unsigned long dummy; + int res; + + if (!size) + return 0; + + __asm__ (".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tsubu\t$1,%6,%0\n\t" + "blez\t$1,2f\n\t" + "lw\t$1,(%5)\n\t" + "addiu\t%5,4\n\t" +#if (_MIPS_ISA == _MIPS_ISA_MIPS2 ) || (_MIPS_ISA == _MIPS_ISA_MIPS3 ) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5 ) || \ + (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) + "beql\t%1,$1,1b\n\t" + "addiu\t%0,32\n\t" +#else + "addiu\t%0,32\n\t" + "beq\t%1,$1,1b\n\t" + "nop\n\t" + "subu\t%0,32\n\t" +#endif +#ifdef __MIPSEB__ +#error "Fix this for big endian" +#endif /* __MIPSEB__ */ + "li\t%1,1\n" + "1:\tand\t%2,$1,%1\n\t" + "beqz\t%2,2f\n\t" + "sll\t%1,%1,1\n\t" + "bnez\t%1,1b\n\t" + "add\t%0,%0,1\n\t" + ".set\tat\n\t" + ".set\treorder\n" + "2:" + : "=r" (res), "=r" (dummy), "=r" (addr) + : "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff), + "2" (addr), "r" (size) + : "$1"); + + return res; +} + +/* + * find_next_zero_bit - find the first zero bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The maximum size to search + */ +extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) +{ + unsigned int *p = ((unsigned int *) addr) + (offset >> 5); + int set = 0, bit = offset & 31, res; + unsigned long dummy; + + if (bit) { + /* + * Look for zero in first byte + */ +#ifdef __MIPSEB__ +#error "Fix this for big endian byte order" +#endif + __asm__(".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tand\t$1,%4,%1\n\t" + "beqz\t$1,1f\n\t" + "sll\t%1,%1,1\n\t" + "bnez\t%1,1b\n\t" + "addiu\t%0,1\n\t" + ".set\tat\n\t" + ".set\treorder\n" + "1:" + : "=r" (set), "=r" (dummy) + : "0" (0), "1" (1 << bit), "r" (*p) + : "$1"); + if (set < (32 - bit)) + return set + offset; + set = 32 - bit; + p++; + } + /* + * No zero yet, search remaining full bytes for a zero + */ + res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr)); + return offset + set + res; +} + +#endif /* !(__MIPSEB__) */ + +/* + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +extern __inline__ unsigned long ffz(unsigned long word) +{ + unsigned int __res; + unsigned int mask = 1; + + __asm__ ( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "move\t%0,$0\n" + "1:\tand\t$1,%2,%1\n\t" + "beqz\t$1,2f\n\t" + "sll\t%1,1\n\t" + "bnez\t%1,1b\n\t" + "addiu\t%0,1\n\t" + ".set\tat\n\t" + ".set\treorder\n" + "2:\n\t" + : "=&r" (__res), "=r" (mask) + : "r" (word), "1" (mask) + : "$1"); + + return __res; +} + +#ifdef __KERNEL__ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +#define ffs(x) generic_ffs(x) + +/* + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#endif /* __KERNEL__ */ + +#ifdef __MIPSEB__ +/* + * find_next_zero_bit - find the first zero bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The maximum size to search + */ +extern __inline__ int find_next_zero_bit(void *addr, int size, int offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; +found_middle: + return result + ffz(tmp); +} + +/* Linus sez that gcc can optimize the following correctly, we'll see if this + * holds on the Sparc as it does for the ALPHA. + */ + +#if 0 /* Fool kernel-doc since it doesn't do macros yet */ +/* + * find_first_zero_bit - find the first zero bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit-number of the first zero bit, not the number of the byte + * containing a bit. + */ +extern int find_first_zero_bit (void *addr, unsigned size); +#endif + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +#endif /* (__MIPSEB__) */ + +/* Now for the ext2 filesystem bit operations and helper routines. */ +#if (CONFIG_COMMANDS & CFG_CMD_EXT2) +#ifdef __MIPSEB__ +extern __inline__ int ext2_set_bit(int nr, void * addr) +{ + int mask, retval, flags; + unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_and_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR |= mask; + restore_flags(flags); + return retval; +} + +extern __inline__ int ext2_clear_bit(int nr, void * addr) +{ + int mask, retval, flags; + unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + save_and_cli(flags); + retval = (mask & *ADDR) != 0; + *ADDR &= ~mask; + restore_flags(flags); + return retval; +} + +extern __inline__ int ext2_test_bit(int nr, const void * addr) +{ + int mask; + const unsigned char *ADDR = (const unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + return ((mask & *ADDR) != 0); +} + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if(offset) { + /* We hold the little endian value in tmp, but then the + * shift is illegal. So we could keep a big endian value + * in tmp, like this: + * + * tmp = __swab32(*(p++)); + * tmp |= ~0UL >> (32-offset); + * + * but this would decrease preformance, so we change the + * shift: + */ + tmp = *(p++); + tmp |= __swab32(~0UL >> (32-offset)); + if(size < 32) + goto found_first; + if(~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while(size & ~31UL) { + if(~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if(!size) + return result; + tmp = *p; + +found_first: + /* tmp is little endian, so we would have to swab the shift, + * see above. But then we have to swab tmp below for ffz, so + * we might as well do this here. + */ + return result + ffz(__swab32(tmp) | (~0UL << size)); +found_middle: + return result + ffz(__swab32(tmp)); +} +#else /* !(__MIPSEB__) */ + +/* Native ext2 byte ordering, just collapse using defines. */ +#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr)) +#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr)) +#define ext2_test_bit(nr, addr) test_bit((nr), (addr)) +#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size)) +#define ext2_find_next_zero_bit(addr, size, offset) \ + find_next_zero_bit((addr), (size), (offset)) + +#endif /* !(__MIPSEB__) */ + +/* + * Bitmap functions for the minix filesystem. + * FIXME: These assume that Minix uses the native byte/bitorder. + * This limits the Minix filesystem's value for data exchange very much. + */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) +#endif /* (CONFIG_COMMANDS & CFG_CMD_EXT2) */ + +#endif /* _ASM_BITOPS_H */ diff --git a/u-boot/include/asm-mips/byteorder.h b/u-boot/include/asm-mips/byteorder.h new file mode 100755 index 0000000..1617a52 --- /dev/null +++ b/u-boot/include/asm-mips/byteorder.h @@ -0,0 +1,31 @@ +/* $Id: //depot/sw/releases/Aquila_9.2.0_U5/boot/u-boot/include/asm-mips/byteorder.h#1 $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) by Ralf Baechle + */ +#ifndef _MIPS_BYTEORDER_H +#define _MIPS_BYTEORDER_H + +#include + +#ifdef __GNUC__ + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#endif /* __GNUC__ */ + +#if defined (__MIPSEB__) +# include +#elif defined (__MIPSEL__) +# include +#else +# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" +#endif + +#endif /* _MIPS_BYTEORDER_H */ diff --git a/u-boot/include/asm-mips/cachectl.h b/u-boot/include/asm-mips/cachectl.h new file mode 100755 index 0000000..9cc2b87 --- /dev/null +++ b/u-boot/include/asm-mips/cachectl.h @@ -0,0 +1,24 @@ +/* + * cachectl.h -- defines for MIPS cache control system calls + * + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + */ +#ifndef __ASM_MIPS_CACHECTL +#define __ASM_MIPS_CACHECTL + +/* + * Options for cacheflush system call + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +/* + * Caching modes for the cachectl(2) call + * + * cachectl(2) is currently not supported and returns ENOSYS. + */ +#define CACHEABLE 0 /* make pages cacheable */ +#define UNCACHEABLE 1 /* make pages uncacheable */ + +#endif /* __ASM_MIPS_CACHECTL */ diff --git a/u-boot/include/asm-mips/cacheops.h b/u-boot/include/asm-mips/cacheops.h new file mode 100755 index 0000000..66b0b36 --- /dev/null +++ b/u-boot/include/asm-mips/cacheops.h @@ -0,0 +1,47 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 1997 by Ralf Baechle + */ +#ifndef __ASM_MIPS_CACHEOPS_H +#define __ASM_MIPS_CACHEOPS_H + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 + /* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + /* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b + /* 0x1c is unused */ + /* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +#endif /* __ASM_MIPS_CACHEOPS_H */ diff --git a/u-boot/include/asm-mips/global_data.h b/u-boot/include/asm-mips/global_data.h new file mode 100755 index 0000000..452f5cb --- /dev/null +++ b/u-boot/include/asm-mips/global_data.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2002-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +#include + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") + +#endif /* __ASM_GBL_DATA_H */ diff --git a/u-boot/include/asm-mips/io.h b/u-boot/include/asm-mips/io.h new file mode 100755 index 0000000..857fb03 --- /dev/null +++ b/u-boot/include/asm-mips/io.h @@ -0,0 +1,450 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995 Waldorf GmbH + * Copyright (C) 1994 - 2000 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 FSMLabs, Inc. + */ +#ifndef _ASM_IO_H +#define _ASM_IO_H + +#include +#if 0 +#include +#endif +#include +#include + +/* + * Slowdown I/O port space accesses for antique hardware. + */ +#undef CONF_SLOWDOWN_IO + +/* + * Sane hardware offers swapping of I/O space accesses in hardware; less + * sane hardware forces software to fiddle with this ... + */ +#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__) + +#define __ioswab8(x) (x) +#define __ioswab16(x) swab16(x) +#define __ioswab32(x) swab32(x) + +#else + +#define __ioswab8(x) (x) +#define __ioswab16(x) (x) +#define __ioswab32(x) (x) + +#endif + +/* + * This file contains the definitions for the MIPS counterpart of the + * x86 in/out instructions. This heap of macros and C results in much + * better code than the approach of doing it in plain C. The macros + * result in code that is to fast for certain hardware. On the other + * side the performance of the string functions should be improved for + * sake of certain devices like EIDE disks that do highspeed polled I/O. + * + * Ralf + * + * This file contains the definitions for the x86 IO instructions + * inb/inw/inl/outb/outw/outl and the "string versions" of the same + * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" + * versions of the single-IO instructions (inb_p/inw_p/..). + * + * This file is not meant to be obfuscating: it's just complicated + * to (a) handle it all in a way that makes gcc able to optimize it + * as well as possible and (b) trying to avoid writing the same thing + * over and over again with slight variations and possibly making a + * mistake somewhere. + */ + +/* + * On MIPS I/O ports are memory mapped, so we access them using normal + * load/store instructions. mips_io_port_base is the virtual address to + * which all ports are being mapped. For sake of efficiency some code + * assumes that this is an address that can be loaded with a single lui + * instruction, so the lower 16 bits must be zero. Should be true on + * on any sane architecture; generic code does not use this assumption. + */ +extern unsigned long mips_io_port_base; + +/* + * Thanks to James van Artsdalen for a better timing-fix than + * the two short jumps: using outb's to a nonexistent port seems + * to guarantee better timings even on fast machines. + * + * On the other hand, I'd like to be sure of a non-existent port: + * I feel a bit unsafe about using 0x80 (should be safe, though) + * + * Linus + * + */ + +#define __SLOW_DOWN_IO \ + __asm__ __volatile__( \ + "sb\t$0,0x80(%0)" \ + : : "r" (mips_io_port_base)); + +#ifdef CONF_SLOWDOWN_IO +#ifdef REALLY_SLOW_IO +#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } +#else +#define SLOW_DOWN_IO __SLOW_DOWN_IO +#endif +#else +#define SLOW_DOWN_IO +#endif + +/* + * Change virtual addresses to physical addresses and vv. + * These are trivial on the 1:1 Linux/MIPS mapping + */ +extern inline unsigned long virt_to_phys(volatile void * address) +{ + return PHYSADDR(address); +} + +extern inline void * phys_to_virt(unsigned long address) +{ + return (void *)KSEG0ADDR(address); +} + +/* + * IO bus memory addresses are also 1:1 with the physical address + */ +extern inline unsigned long virt_to_bus(volatile void * address) +{ + return PHYSADDR(address); +} + +extern inline void * bus_to_virt(unsigned long address) +{ + return (void *)KSEG0ADDR(address); +} + +/* + * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped + * for the processor. + */ +extern unsigned long isa_slot_offset; + +extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); + +#if 0 +extern inline void *ioremap(unsigned long offset, unsigned long size) +{ + return __ioremap(offset, size, _CACHE_UNCACHED); +} + +extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) +{ + return __ioremap(offset, size, _CACHE_UNCACHED); +} + +extern void iounmap(void *addr); +#endif + +/* + * XXX We need system specific versions of these to handle EISA address bits + * 24-31 on SNI. + * XXX more SNI hacks. + */ +#define readb(addr) (*(volatile unsigned char *)(addr)) +#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr))) +#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr))) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl + +#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b) +#define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b)) +#define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b)) +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +/* END SNI HACKS ... */ + +/* + * ISA space is 'always mapped' on currently supported MIPS systems, no need + * to explicitly ioremap() it. The fact that the ISA IO space is mapped + * to PAGE_OFFSET is pure coincidence - it does not mean ISA values + * are physical addresses. The following constant pointer can be + * used as the IO-area pointer (it can be iounmapped as well, so the + * analogy with PCI is quite large): + */ +#define __ISA_IO_base ((char *)(PAGE_OFFSET)) + +#define isa_readb(a) readb(a) +#define isa_readw(a) readw(a) +#define isa_readl(a) readl(a) +#define isa_writeb(b,a) writeb(b,a) +#define isa_writew(w,a) writew(w,a) +#define isa_writel(l,a) writel(l,a) + +#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) +#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) + +/* + * We don't have csum_partial_copy_fromio() yet, so we cheat here and + * just copy it. The net code will then do the checksum later. + */ +#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) +#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d)) + +static inline int check_signature(unsigned long io_addr, + const unsigned char *signature, int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} +#define isa_check_signature(io, s, l) check_signature(i,s,l) + +/* + * Talk about misusing macros.. + */ + +#define __OUT1(s) \ +extern inline void __out##s(unsigned int value, unsigned int port) { + +#define __OUT2(m) \ +__asm__ __volatile__ ("s" #m "\t%0,%1(%2)" + +#define __OUT(m,s,w) \ +__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \ +__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \ +__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \ + SLOW_DOWN_IO; } \ +__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \ + SLOW_DOWN_IO; } + +#define __IN1(t,s) \ +extern __inline__ t __in##s(unsigned int port) { t _v; + +/* + * Required nops will be inserted by the assembler + */ +#define __IN2(m) \ +__asm__ __volatile__ ("l" #m "\t%0,%1(%2)" + +#define __IN(t,m,s,w) \ +__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \ +__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \ +__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \ +__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); } + +#define __INS1(s) \ +extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) { + +#define __INS2(m) \ +if (count) \ +__asm__ __volatile__ ( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n" \ + "1:\tl" #m "\t$1,%4(%5)\n\t" \ + "subu\t%1,1\n\t" \ + "s" #m "\t$1,(%0)\n\t" \ + "bne\t$0,%1,1b\n\t" \ + "addiu\t%0,%6\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" + +#define __INS(m,s,i) \ +__INS1(s) __INS2(m) \ + : "=r" (addr), "=r" (count) \ + : "0" (addr), "1" (count), "i" (0), \ + "r" (mips_io_port_base+port), "I" (i) \ + : "$1");} \ +__INS1(s##c) __INS2(m) \ + : "=r" (addr), "=r" (count) \ + : "0" (addr), "1" (count), "ir" (port), \ + "r" (mips_io_port_base), "I" (i) \ + : "$1");} + +#define __OUTS1(s) \ +extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { + +#define __OUTS2(m) \ +if (count) \ +__asm__ __volatile__ ( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n" \ + "1:\tl" #m "\t$1,(%0)\n\t" \ + "subu\t%1,1\n\t" \ + "s" #m "\t$1,%4(%5)\n\t" \ + "bne\t$0,%1,1b\n\t" \ + "addiu\t%0,%6\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" + +#define __OUTS(m,s,i) \ +__OUTS1(s) __OUTS2(m) \ + : "=r" (addr), "=r" (count) \ + : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ + : "$1");} \ +__OUTS1(s##c) __OUTS2(m) \ + : "=r" (addr), "=r" (count) \ + : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ + : "$1");} + +__IN(unsigned char,b,b,8) +__IN(unsigned short,h,w,16) +__IN(unsigned int,w,l,32) + +__OUT(b,b,8) +__OUT(h,w,16) +__OUT(w,l,32) + +__INS(b,b,1) +__INS(h,w,2) +__INS(w,l,4) + +__OUTS(b,b,1) +__OUTS(h,w,2) +__OUTS(w,l,4) + + +/* + * Note that due to the way __builtin_constant_p() works, you + * - can't use it inside an inline function (it will never be true) + * - you don't have to worry about side effects within the __builtin.. + */ +#define outb(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outbc((val),(port)) : \ + __outb((val),(port))) + +#define inb(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inbc(port) : \ + __inb(port)) + +#define outb_p(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outbc_p((val),(port)) : \ + __outb_p((val),(port))) + +#define inb_p(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inbc_p(port) : \ + __inb_p(port)) + +#define outw(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outwc((val),(port)) : \ + __outw((val),(port))) + +#define inw(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inwc(port) : \ + __inw(port)) + +#define outw_p(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outwc_p((val),(port)) : \ + __outw_p((val),(port))) + +#define inw_p(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inwc_p(port) : \ + __inw_p(port)) + +#define outl(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outlc((val),(port)) : \ + __outl((val),(port))) + +#define inl(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inlc(port) : \ + __inl(port)) + +#define outl_p(val,port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outlc_p((val),(port)) : \ + __outl_p((val),(port))) + +#define inl_p(port) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inlc_p(port) : \ + __inl_p(port)) + + +#define outsb(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outsbc((port),(addr),(count)) : \ + __outsb ((port),(addr),(count))) + +#define insb(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __insbc((port),(addr),(count)) : \ + __insb((port),(addr),(count))) + +#define outsw(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outswc((port),(addr),(count)) : \ + __outsw ((port),(addr),(count))) + +#define insw(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inswc((port),(addr),(count)) : \ + __insw((port),(addr),(count))) + +#define outsl(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __outslc((port),(addr),(count)) : \ + __outsl ((port),(addr),(count))) + +#define insl(port,addr,count) \ +((__builtin_constant_p((port)) && (port) < 32768) ? \ + __inslc((port),(addr),(count)) : \ + __insl((port),(addr),(count))) + +#define IO_SPACE_LIMIT 0xffff + +/* + * The caches on some architectures aren't dma-coherent and have need to + * handle this in software. There are three types of operations that + * can be applied to dma buffers. + * + * - dma_cache_wback_inv(start, size) makes caches and coherent by + * writing the content of the caches back to memory, if necessary. + * The function also invalidates the affected part of the caches as + * necessary before DMA transfers from outside to memory. + * - dma_cache_wback(start, size) makes caches and coherent by + * writing the content of the caches back to memory, if necessary. + * The function also invalidates the affected part of the caches as + * necessary before DMA transfers from outside to memory. + * - dma_cache_inv(start, size) invalidates the affected parts of the + * caches. Dirty lines of the caches may be written back or simply + * be discarded. This operation is necessary before dma operations + * to the memory. + */ +extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); +extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); +extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); + +#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size) +#define dma_cache_wback(start,size) _dma_cache_wback(start,size) +#define dma_cache_inv(start,size) _dma_cache_inv(start,size) + +#endif /* _ASM_IO_H */ diff --git a/u-boot/include/asm-mips/isadep.h b/u-boot/include/asm-mips/isadep.h new file mode 100755 index 0000000..3cd1eb8 --- /dev/null +++ b/u-boot/include/asm-mips/isadep.h @@ -0,0 +1,35 @@ +/* + * Various ISA level dependant constants. + * Most of the following constants reflect the different layout + * of Coprocessor 0 registers. + * + * Copyright (c) 1998 Harald Koerfgen + */ +#include + +#ifndef __ASM_ISADEP_H +#define __ASM_ISADEP_H + +#if defined(CONFIG_CPU_R3000) +/* + * R2000 or R3000 + */ + +/* + * kernel or user mode? (CP0_STATUS) + */ +#define KU_MASK 0x08 +#define KU_USER 0x08 +#define KU_KERN 0x00 + +#else +/* + * kernel or user mode? + */ +#define KU_MASK 0x18 +#define KU_USER 0x10 +#define KU_KERN 0x00 + +#endif + +#endif /* __ASM_ISADEP_H */ diff --git a/u-boot/include/asm-mips/mipsregs.h b/u-boot/include/asm-mips/mipsregs.h new file mode 100755 index 0000000..0586c53 --- /dev/null +++ b/u-boot/include/asm-mips/mipsregs.h @@ -0,0 +1,547 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2003 Maciej W. Rozycki + */ +#ifndef _ASM_MIPSREGS_H +#define _ASM_MIPSREGS_H + +#if 0 +#include +#endif + +/* + * The following macros are especially useful for __asm__ + * inline assembler. + */ +#ifndef __STR +#define __STR(x) #x +#endif +#ifndef STR +#define STR(x) __STR(x) +#endif + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONF $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_INFO $7 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + +/* + * FPU Status Register Values + */ +/* + * Status Register Values + */ + +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* rounding mode */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + + +/* + * Values for PageMask register + */ +#include +#ifdef CONFIG_CPU_VR41XX +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 +#else +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#endif + +/* + * Values used for computation of new tlb entries + */ +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 + +/* + * Macros to access the system control coprocessor + */ +#define read_32bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "mfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +#define read_32bit_cp0_set1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* + * For now use this only with interrupts disabled! + */ +#define read_64bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0,"STR(source)"\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res;}) + +#define write_32bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_32bit_cp0_set1_register(register,value) \ + __asm__ __volatile__( \ + "ctc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_64bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%0,"STR(register)"\n\t" \ + ".set\tmips0" \ + : : "r" (value)) + +/* + * This should be changed when we get a compiler that support the MIPS32 ISA. + */ +#define read_mips32_cp0_config1() \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ + __res;}) + +#define tlb_write_indexed() \ + __asm__ __volatile__( \ + ".set noreorder\n\t" \ + "tlbwi\n\t" \ +".set reorder") + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (1<< 8) +#define IE_SW1 (1<< 9) +#define IE_IRQ0 (1<<10) +#define IE_IRQ1 (1<<11) +#define IE_IRQ2 (1<<12) +#define IE_IRQ3 (1<<13) +#define IE_IRQ4 (1<<14) +#define IE_IRQ5 (1<<15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (1<< 8) +#define C_SW1 (1<< 9) +#define C_IRQ0 (1<<10) +#define C_IRQ1 (1<<11) +#define C_IRQ2 (1<<12) +#define C_IRQ3 (1<<13) +#define C_IRQ4 (1<<14) +#define C_IRQ5 (1<<15) + +#ifndef _LANGUAGE_ASSEMBLY +/* + * Manipulate the status register. + * Mostly used to access the interrupt bits. + */ +#define __BUILD_SET_CP0(name,register) \ +extern __inline__ unsigned int \ +set_cp0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res |= set; \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} \ + \ +extern __inline__ unsigned int \ +clear_cp0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res &= ~clear; \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} \ + \ +extern __inline__ unsigned int \ +change_cp0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res &= ~change; \ + res |= (new & change); \ + if(change) \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} + +__BUILD_SET_CP0(status,CP0_STATUS) +__BUILD_SET_CP0(cause,CP0_CAUSE) +__BUILD_SET_CP0(config,CP0_CONFIG) + +#endif /* defined (_LANGUAGE_ASSEMBLY) */ + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (1 << 4) +#define ST0_IL (1 << 23) +#define ST0_DL (1 << 24) + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (1 << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (1 << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (1 << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (1 << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (1 << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (1 << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (1 << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (1 << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (1 << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (1 << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (1 << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (1 << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (1 << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (1 << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (1 << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (1 << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (31 << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (255 << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (1 << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (1 << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (1 << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (1 << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (1 << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (1 << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (1 << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (1 << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (1 << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (3 << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (1 << 31) + +/* + * Bits in the coprozessor 0 config register. + */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_DB (1 << 4) +#define CONF_IB (1 << 5) +#define CONF_SC (1 << 17) +#define CONF_AC (1 << 23) +#define CONF_HALT (1 << 25) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which priviledge mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + +#endif /* _ASM_MIPSREGS_H */ diff --git a/u-boot/include/asm-mips/posix_types.h b/u-boot/include/asm-mips/posix_types.h new file mode 100755 index 0000000..01c480f --- /dev/null +++ b/u-boot/include/asm-mips/posix_types.h @@ -0,0 +1,123 @@ +/* $Id: //depot/sw/releases/Aquila_9.2.0_U5/boot/u-boot/include/asm-mips/posix_types.h#1 $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle + */ +#ifndef _ASM_POSIX_TYPES_H +#define _ASM_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned int __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned int __kernel_mode_t; +typedef int __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef int __kernel_ipc_pid_t; +typedef int __kernel_uid_t; +typedef int __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef long __kernel_daddr_t; +typedef char * __kernel_caddr_t; + +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef int __kernel_uid32_t; +typedef int __kernel_gid32_t; +typedef __kernel_uid_t __kernel_old_uid_t; +typedef __kernel_gid_t __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { + long val[2]; +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* _ASM_POSIX_TYPES_H */ diff --git a/u-boot/include/asm-mips/processor.h b/u-boot/include/asm-mips/processor.h new file mode 100755 index 0000000..6838aee --- /dev/null +++ b/u-boot/include/asm-mips/processor.h @@ -0,0 +1,283 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 Waldorf GMBH + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle + * Copyright (C) 1996 Paul M. Antoine + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#ifndef _ASM_PROCESSOR_H +#define _ASM_PROCESSOR_H + +#include + +#include + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#if !defined (_LANGUAGE_ASSEMBLY) +#if 0 +#include +#endif +#include +#include +#include +#include + +struct mips_cpuinfo { + unsigned long udelay_val; + unsigned long *pgd_quick; + unsigned long *pte_quick; + unsigned long pgtable_cache_sz; +}; + +/* + * System setup and hardware flags.. + * XXX: Should go into mips_cpuinfo. + */ +extern void (*cpu_wait)(void); /* only available on R4[26]00 and R3081 */ +extern void r3081_wait(void); +extern void r4k_wait(void); +extern char cyclecounter_available; /* only available from R4000 upwards. */ + +extern struct mips_cpuinfo boot_cpu_data; +extern unsigned int vced_count, vcei_count; + +#ifdef CONFIG_SMP +extern struct mips_cpuinfo cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] +#else +#define cpu_data &boot_cpu_data +#define current_cpu_data boot_cpu_data +#endif + +/* + * Bus types (default is ISA, but people can check others with these..) + * MCA_bus hardcoded to 0 for now. + * + * This needs to be extended since MIPS systems are being delivered with + * numerous different types of bus systems. + */ +extern int EISA_bus; +#define MCA_bus 0 +#define MCA_bus__is_a_macro /* for versions in ksyms.c */ + +/* + * MIPS has no problems with write protection + */ +#define wp_works_ok 1 +#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ + +/* Lazy FPU handling on uni-processor */ +extern struct task_struct *last_task_used_math; + +/* + * User space process size: 2GB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. TASK_SIZE + * for a 64 bit kernel expandable to 8192EB, of which the current MIPS + * implementations will "only" be able to use 1TB ... + */ +#define TASK_SIZE (0x7fff8000UL) + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Size of io_bitmap in longwords: 32 is ports 0-0x3ff. + */ +#define IO_BITMAP_SIZE 32 + +#define NUM_FPU_REGS 32 + +struct mips_fpu_hard_struct { + double fp_regs[NUM_FPU_REGS]; + unsigned int control; +}; + +/* + * It would be nice to add some more fields for emulator statistics, but there + * are a number of fixed offsets in offset.h and elsewhere that would have to + * be recalculated by hand. So the additional information will be private to + * the FPU emulator for now. See asm-mips/fpu_emulator.h. + */ +typedef u64 fpureg_t; +struct mips_fpu_soft_struct { + fpureg_t regs[NUM_FPU_REGS]; + unsigned int sr; +}; + +union mips_fpu_union { + struct mips_fpu_hard_struct hard; + struct mips_fpu_soft_struct soft; +}; + +#define INIT_FPU { \ + {{0,},} \ +} + +typedef struct { + unsigned long seg; +} mm_segment_t; + +/* + * If you change thread_struct remember to change the #defines below too! + */ +struct thread_struct { + /* Saved main processor registers. */ + unsigned long reg16; + unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; + unsigned long reg29, reg30, reg31; + + /* Saved cp0 stuff. */ + unsigned long cp0_status; + + /* Saved fpu/fpu emulator stuff. */ + union mips_fpu_union fpu; + + /* Other stuff associated with the thread. */ + unsigned long cp0_badvaddr; /* Last user fault */ + unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ + unsigned long error_code; + unsigned long trap_no; +#define MF_FIXADE 1 /* Fix address errors in software */ +#define MF_LOGADE 2 /* Log address errors to syslog */ + unsigned long mflags; + mm_segment_t current_ds; + unsigned long irix_trampoline; /* Wheee... */ + unsigned long irix_oldctx; + + /* + * These are really only needed if the full FPU emulator is configured. + * Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the + * fact that having offset.h rebuilt differently for different config + * options would be asking for trouble. + * + * Saved EPC during delay-slot emulation (see math-emu/cp1emu.c) + */ + unsigned long dsemul_epc; + + /* + * Pointer to instruction used to induce address error + */ + unsigned long dsemul_aerpc; +}; + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define INIT_THREAD { \ + /* \ + * saved main processor registers \ + */ \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, \ + /* \ + * saved cp0 stuff \ + */ \ + 0, \ + /* \ + * saved fpu/fpu emulator stuff \ + */ \ + INIT_FPU, \ + /* \ + * Other stuff associated with the process \ + */ \ + 0, 0, 0, 0, \ + /* \ + * For now the default is to fix address errors \ + */ \ + MF_FIXADE, { 0 }, 0, 0, \ + /* \ + * dsemul_epc and dsemul_aerpc should never be used uninitialized, \ + * but... \ + */ \ + 0 ,0 \ +} + +#ifdef __KERNEL__ + +#define KERNEL_STACK_SIZE 8192 + +#if !defined (_LANGUAGE_ASSEMBLY) + +/* Free all resources held by a thread. */ +#define release_thread(thread) do { } while(0) + +extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); + +/* Copy and release all segment info associated with a VM */ +#define copy_segments(p, mm) do { } while(0) +#define release_segments(mm) do { } while(0) + +/* + * Return saved PC of a blocked thread. + */ +extern inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + extern void ret_from_fork(void); + + /* New born processes are a special case */ + if (t->reg31 == (unsigned long) ret_from_fork) + return t->reg31; + + return ((unsigned long *)t->reg29)[10]; +} + +/* + * Do necessary setup to start up a newly executed thread. + */ +#define start_thread(regs, new_pc, new_sp) do { \ + /* New thread looses kernel privileges. */ \ + regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\ + regs->cp0_epc = new_pc; \ + regs->regs[29] = new_sp; \ + current->thread.current_ds = USER_DS; \ +} while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs)) +#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32) +#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc))) +#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29]))) + +/* Allocation and freeing of basic task resources. */ +/* + * NOTE! The task struct and the stack go together + */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +#define cpu_relax() do { } while (0) + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ +#endif /* __KERNEL__ */ + +/* + * Return_address is a replacement for __builtin_return_address(count) + * which on certain architectures cannot reasonably be implemented in GCC + * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). + * Note that __builtin_return_address(x>=1) is forbidden because GCC + * aborts compilation on some CPUs. It's simply not possible to unwind + * some CPU's stackframes. + * + * __builtin_return_address works only for non-leaf functions. We avoid the + * overhead of a function call by forcing the compiler to save the return + * address register on the stack. + */ +#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) + +#endif /* _ASM_PROCESSOR_H */ diff --git a/u-boot/include/asm-mips/ptrace.h b/u-boot/include/asm-mips/ptrace.h new file mode 100755 index 0000000..2517adb --- /dev/null +++ b/u-boot/include/asm-mips/ptrace.h @@ -0,0 +1,86 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle + * + * Machine dependent structs and defines to help the user use + * the ptrace system call. + */ +#ifndef _ASM_PTRACE_H +#define _ASM_PTRACE_H + +#include +#include + +/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ +#define FPR_BASE 32 +#define PC 64 +#define CAUSE 65 +#define BADVADDR 66 +#define MMHI 67 +#define MMLO 68 +#define FPC_CSR 69 +#define FPC_EIR 70 + +#ifndef _LANGUAGE_ASSEMBLY +/* + * This struct defines the way the registers are stored on the stack during a + * system call/exception. As usual the registers k0/k1 aren't being saved. + */ +struct pt_regs { + /* Pad bytes for argument save space on the stack. */ + unsigned long pad0[6]; + + /* Saved main processor registers. */ + unsigned long regs[32]; + + /* Other saved registers. */ + unsigned long lo; + unsigned long hi; + + /* + * saved cp0 registers + */ + unsigned long cp0_epc; + unsigned long cp0_badvaddr; + unsigned long cp0_status; + unsigned long cp0_cause; +}; + +#endif /* !(_LANGUAGE_ASSEMBLY) */ + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +/* #define PTRACE_GETREGS 12 */ +/* #define PTRACE_SETREGS 13 */ +/* #define PTRACE_GETFPREGS 14 */ +/* #define PTRACE_SETFPREGS 15 */ +/* #define PTRACE_GETFPXREGS 18 */ +/* #define PTRACE_SETFPXREGS 19 */ + +#define PTRACE_SETOPTIONS 21 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +#if 0 /* def _LANGUAGE_ASSEMBLY */ +#include +#endif + +#ifdef __KERNEL__ + +#ifndef _LANGUAGE_ASSEMBLY +/* + * Does the process account for user or for system time? + */ +#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) + +#define instruction_pointer(regs) ((regs)->cp0_epc) + +extern void show_regs(struct pt_regs *); +#endif /* !(_LANGUAGE_ASSEMBLY) */ + +#endif + +#endif /* _ASM_PTRACE_H */ diff --git a/u-boot/include/asm-mips/reg.h b/u-boot/include/asm-mips/reg.h new file mode 100755 index 0000000..35505b7 --- /dev/null +++ b/u-boot/include/asm-mips/reg.h @@ -0,0 +1,66 @@ +/* + * Various register offset definitions for debuggers, core file + * examiners and whatnot. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1999 by Ralf Baechle + */ +#ifndef __ASM_MIPS_REG_H +#define __ASM_MIPS_REG_H + +/* + * This defines/structures correspond to the register layout on stack - + * if the order here is changed, it needs to be updated in + * include/asm-mips/stackframe.h + */ +#define EF_REG0 6 +#define EF_REG1 7 +#define EF_REG2 8 +#define EF_REG3 9 +#define EF_REG4 10 +#define EF_REG5 11 +#define EF_REG6 12 +#define EF_REG7 13 +#define EF_REG8 14 +#define EF_REG9 15 +#define EF_REG10 16 +#define EF_REG11 17 +#define EF_REG12 18 +#define EF_REG13 19 +#define EF_REG14 20 +#define EF_REG15 21 +#define EF_REG16 22 +#define EF_REG17 23 +#define EF_REG18 24 +#define EF_REG19 25 +#define EF_REG20 26 +#define EF_REG21 27 +#define EF_REG22 28 +#define EF_REG23 29 +#define EF_REG24 30 +#define EF_REG25 31 +/* + * k0/k1 unsaved + */ +#define EF_REG28 34 +#define EF_REG29 35 +#define EF_REG30 36 +#define EF_REG31 37 + +/* + * Saved special registers + */ +#define EF_LO 38 +#define EF_HI 39 + +#define EF_CP0_EPC 40 +#define EF_CP0_BADVADDR 41 +#define EF_CP0_STATUS 42 +#define EF_CP0_CAUSE 44 + +#define EF_SIZE 180 /* size in bytes */ + +#endif /* __ASM_MIPS_REG_H */ diff --git a/u-boot/include/asm-mips/regdef.h b/u-boot/include/asm-mips/regdef.h new file mode 100755 index 0000000..691d047 --- /dev/null +++ b/u-boot/include/asm-mips/regdef.h @@ -0,0 +1,52 @@ +/* + * include/asm-mips/regdefs.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995 by Ralf Baechle + */ + +#ifndef __ASM_MIPS_REGDEF_H +#define __ASM_MIPS_REGDEF_H + +/* + * Symbolic register names for 32 bit ABI + */ +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ + +#endif /* __ASM_MIPS_REGDEF_H */ diff --git a/u-boot/include/asm-mips/sgidefs.h b/u-boot/include/asm-mips/sgidefs.h new file mode 100755 index 0000000..67f2658 --- /dev/null +++ b/u-boot/include/asm-mips/sgidefs.h @@ -0,0 +1,44 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1999, 2001 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. + */ +#ifndef __ASM_SGIDEFS_H +#define __ASM_SGIDEFS_H + +/* + * Using a Linux compiler for building Linux seems logic but not to + * everybody. + */ +#if 0 /* ndef __linux__ */ +#error Use a Linux compiler or give up. +#endif + +/* + * Definitions for the ISA levels + * + * With the introduction of MIPS32 / MIPS64 instruction sets definitions + * MIPS ISAs are no longer subsets of each other. Therefore comparisons + * on these symbols except with == may result in unexpected results and + * are forbidden! + */ +#define _MIPS_ISA_MIPS1 1 +#define _MIPS_ISA_MIPS2 2 +#define _MIPS_ISA_MIPS3 3 +#define _MIPS_ISA_MIPS4 4 +#define _MIPS_ISA_MIPS5 5 +#define _MIPS_ISA_MIPS32 6 +#define _MIPS_ISA_MIPS64 7 + +/* + * Subprogram calling convention + */ +#define _MIPS_SIM_ABI32 1 +#define _MIPS_SIM_NABI32 2 +#define _MIPS_SIM_ABI64 3 + +#endif /* __ASM_SGIDEFS_H */ diff --git a/u-boot/include/asm-mips/string.h b/u-boot/include/asm-mips/string.h new file mode 100755 index 0000000..dab4e70 --- /dev/null +++ b/u-boot/include/asm-mips/string.h @@ -0,0 +1,157 @@ +/* $Id: //depot/sw/releases/Aquila_9.2.0_U5/boot/u-boot/include/asm-mips/string.h#1 $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle + */ +#ifndef __ASM_MIPS_STRING_H +#define __ASM_MIPS_STRING_H + +#include + +#define __HAVE_ARCH_STRCPY +extern __inline__ char *strcpy(char *__dest, __const__ char *__src) +{ + char *__xdest = __dest; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t$1,(%1)\n\t" + "addiu\t%1,1\n\t" + "sb\t$1,(%0)\n\t" + "bnez\t$1,1b\n\t" + "addiu\t%0,1\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__dest), "=r" (__src) + : "0" (__dest), "1" (__src) + : "$1","memory"); + + return __xdest; +} + +#define __HAVE_ARCH_STRNCPY +extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) +{ + char *__xdest = __dest; + + if (__n == 0) + return __xdest; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t$1,(%1)\n\t" + "subu\t%2,1\n\t" + "sb\t$1,(%0)\n\t" + "beqz\t$1,2f\n\t" + "addiu\t%0,1\n\t" + "bnez\t%2,1b\n\t" + "addiu\t%1,1\n" + "2:\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__dest), "=r" (__src), "=r" (__n) + : "0" (__dest), "1" (__src), "2" (__n) + : "$1","memory"); + + return __dest; +} + +#define __HAVE_ARCH_STRCMP +extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) +{ + int __res; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "lbu\t%2,(%0)\n" + "1:\tlbu\t$1,(%1)\n\t" + "addiu\t%0,1\n\t" + "bne\t$1,%2,2f\n\t" + "addiu\t%1,1\n\t" + "bnez\t%2,1b\n\t" + "lbu\t%2,(%0)\n\t" +#if defined(CONFIG_CPU_R3000) + "nop\n\t" +#endif + "move\t%2,$1\n" + "2:\tsubu\t%2,$1\n" + "3:\t.set\tat\n\t" + ".set\treorder" + : "=r" (__cs), "=r" (__ct), "=r" (__res) + : "0" (__cs), "1" (__ct) + : "$1"); + + return __res; +} + +#define __HAVE_ARCH_STRNCMP +extern __inline__ int +strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) +{ + int __res; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t%3,(%0)\n\t" + "beqz\t%2,2f\n\t" + "lbu\t$1,(%1)\n\t" + "subu\t%2,1\n\t" + "bne\t$1,%3,3f\n\t" + "addiu\t%0,1\n\t" + "bnez\t%3,1b\n\t" + "addiu\t%1,1\n" + "2:\n\t" +#if defined(CONFIG_CPU_R3000) + "nop\n\t" +#endif + "move\t%3,$1\n" + "3:\tsubu\t%3,$1\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) + : "0" (__cs), "1" (__ct), "2" (__count) + : "$1"); + + return __res; +} + +#undef __HAVE_ARCH_MEMSET +extern void *memset(void *__s, int __c, size_t __count); + +#undef __HAVE_ARCH_MEMCPY +extern void *memcpy(void *__to, __const__ void *__from, size_t __n); + +#undef __HAVE_ARCH_MEMMOVE +extern void *memmove(void *__dest, __const__ void *__src, size_t __n); + +/* Don't build bcopy at all ... */ +#define __HAVE_ARCH_BCOPY + +#define __HAVE_ARCH_MEMSCAN +extern __inline__ void *memscan(void *__addr, int __c, size_t __size) +{ + char *__end = (char *)__addr + __size; + + __asm__(".set\tpush\n\t" + ".set\tnoat\n\t" + ".set\treorder\n\t" + "1:\tbeq\t%0,%1,2f\n\t" + "addiu\t%0,1\n\t" + "lb\t$1,-1(%0)\n\t" + "bne\t$1,%4,1b\n" + "2:\t.set\tpop" + : "=r" (__addr), "=r" (__end) + : "0" (__addr), "1" (__end), "r" (__c) + : "$1"); + + return __addr; +} + +#endif /* __ASM_MIPS_STRING_H */ diff --git a/u-boot/include/asm-mips/system.h b/u-boot/include/asm-mips/system.h new file mode 100755 index 0000000..b6d50e2 --- /dev/null +++ b/u-boot/include/asm-mips/system.h @@ -0,0 +1,268 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1994 - 1999 by Ralf Baechle + * + * Changed set_except_vector declaration to allow return of previous + * vector address value - necessary for "borrowing" vectors. + * + * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#ifndef _ASM_SYSTEM_H +#define _ASM_SYSTEM_H + +#include +#include +#include +#if 0 +#include +#endif + +extern __inline__ void +__sti(void) +{ + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\treorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$12\n\t" + "ori\t$1,0x1f\n\t" + "xori\t$1,0x1e\n\t" + "mtc0\t$1,$12\n\t" + ".set\tpop\n\t" + : /* no outputs */ + : /* no inputs */ + : "$1", "memory"); +} + +/* + * For cli() we have to insert nops to make shure that the new value + * has actually arrived in the status register before the end of this + * macro. + * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs + * no nops at all. + */ +extern __inline__ void +__cli(void) +{ + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\treorder\n\t" + ".set\tnoat\n\t" + "mfc0\t$1,$12\n\t" + "ori\t$1,1\n\t" + "xori\t$1,1\n\t" + ".set\tnoreorder\n\t" + "mtc0\t$1,$12\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set\tpop\n\t" + : /* no outputs */ + : /* no inputs */ + : "$1", "memory"); +} + +#define __save_flags(x) \ +__asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "mfc0\t%0,$12\n\t" \ + ".set\tpop\n\t" \ + : "=r" (x)) + +#define __save_and_cli(x) \ +__asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + ".set\tnoat\n\t" \ + "mfc0\t%0,$12\n\t" \ + "ori\t$1,%0,1\n\t" \ + "xori\t$1,1\n\t" \ + ".set\tnoreorder\n\t" \ + "mtc0\t$1,$12\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + ".set\tpop\n\t" \ + : "=r" (x) \ + : /* no inputs */ \ + : "$1", "memory") + +#define __restore_flags(flags) \ +do { \ + unsigned long __tmp1; \ + \ + __asm__ __volatile__( \ + ".set\tnoreorder\t\t\t# __restore_flags\n\t" \ + ".set\tnoat\n\t" \ + "mfc0\t$1, $12\n\t" \ + "andi\t%0, 1\n\t" \ + "ori\t$1, 1\n\t" \ + "xori\t$1, 1\n\t" \ + "or\t%0, $1\n\t" \ + "mtc0\t%0, $12\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + "nop\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + : "=r" (__tmp1) \ + : "0" (flags) \ + : "$1", "memory"); \ +} while(0) + +#ifdef CONFIG_SMP + +extern void __global_sti(void); +extern void __global_cli(void); +extern unsigned long __global_save_flags(void); +extern void __global_restore_flags(unsigned long); +# define sti() __global_sti() +# define cli() __global_cli() +# define save_flags(x) do { x = __global_save_flags(); } while (0) +# define restore_flags(x) __global_restore_flags(x) +# define save_and_cli(x) do { save_flags(x); cli(); } while(0) + +#else /* Single processor */ + +# define sti() __sti() +# define cli() __cli() +# define save_flags(x) __save_flags(x) +# define save_and_cli(x) __save_and_cli(x) +# define restore_flags(x) __restore_flags(x) + +#endif /* SMP */ + +/* For spinlocks etc */ +#define local_irq_save(x) __save_and_cli(x); +#define local_irq_restore(x) __restore_flags(x); +#define local_irq_disable() __cli(); +#define local_irq_enable() __sti(); + +/* + * These are probably defined overly paranoid ... + */ +#ifdef CONFIG_CPU_HAS_WB + +#include +#define rmb() do { } while(0) +#define wmb() wbflush() +#define mb() wbflush() + +#else /* CONFIG_CPU_HAS_WB */ + +#define mb() \ +__asm__ __volatile__( \ + "# prevent instructions being moved around\n\t" \ + ".set\tnoreorder\n\t" \ + "# 8 nops to fool the R4400 pipeline\n\t" \ + "nop;nop;nop;nop;nop;nop;nop;nop\n\t" \ + ".set\treorder" \ + : /* no output */ \ + : /* no input */ \ + : "memory") +#define rmb() mb() +#define wmb() mb() + +#endif /* CONFIG_CPU_HAS_WB */ + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#endif + +#define set_mb(var, value) \ +do { var = value; mb(); } while (0) + +#define set_wmb(var, value) \ +do { var = value; wmb(); } while (0) + +#if !defined (_LANGUAGE_ASSEMBLY) +/* + * switch_to(n) should switch tasks to task nr n, first + * checking that n isn't the current task, in which case it does nothing. + */ +#if 0 +extern asmlinkage void *resume(void *last, void *next); +#endif +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define prepare_to_switch() do { } while(0) +#define switch_to(prev,next,last) \ +do { \ + (last) = resume(prev, next); \ +} while(0) + +/* + * For 32 and 64 bit operands we can take advantage of ll and sc. + * FIXME: This doesn't work for R3000 machines. + */ +extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) +{ +#ifdef CONFIG_CPU_HAS_LLSC + unsigned long dummy; + + __asm__ __volatile__( + ".set\tnoreorder\t\t\t# xchg_u32\n\t" + ".set\tnoat\n\t" + "ll\t%0, %3\n" + "1:\tmove\t$1, %2\n\t" + "sc\t$1, %1\n\t" + "beqzl\t$1, 1b\n\t" + " ll\t%0, %3\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (val), "=o" (*m), "=r" (dummy) + : "o" (*m), "2" (val) + : "memory"); + + return val; +#else + unsigned long flags, retval; + + save_flags(flags); + cli(); + retval = *m; + *m = val; + restore_flags(flags); + return retval; +#endif /* Processor-dependent optimization */ +} + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define tas(ptr) (xchg((ptr),1)) + +static __inline__ unsigned long +__xchg(unsigned long x, volatile void * ptr, int size) +{ + switch (size) { + case 4: + return xchg_u32(ptr, x); + } + return x; +} + +extern void *set_except_vector(int n, void *addr); + +extern void __die(const char *, struct pt_regs *, const char *where, + unsigned long line) __attribute__((noreturn)); +extern void __die_if_kernel(const char *, struct pt_regs *, const char *where, + unsigned long line); + +#define die(msg, regs) \ + __die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) +#define die_if_kernel(msg, regs) \ + __die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + +#endif /* _ASM_SYSTEM_H */ diff --git a/u-boot/include/asm-mips/types.h b/u-boot/include/asm-mips/types.h new file mode 100755 index 0000000..21a04d4 --- /dev/null +++ b/u-boot/include/asm-mips/types.h @@ -0,0 +1,77 @@ +/* $Id: //depot/sw/releases/Aquila_9.2.0_U5/boot/u-boot/include/asm-mips/types.h#1 $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#ifndef _ASM_TYPES_H +#define _ASM_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if (_MIPS_SZLONG == 64) + +typedef __signed__ long __s64; +typedef unsigned long __u64; + +#else + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef __signed char s8; +typedef unsigned char u8; + +typedef __signed short s16; +typedef unsigned short u16; + +typedef __signed int s32; +typedef unsigned int u32; + +#if (_MIPS_SZLONG == 64) + +typedef __signed__ long s64; +typedef unsigned long u64; + +#else + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long s64; +typedef unsigned long long u64; +#endif + +#endif + +#define BITS_PER_LONG _MIPS_SZLONG + +typedef unsigned long dma_addr_t; + +#endif /* __KERNEL__ */ + +#endif /* _ASM_TYPES_H */ diff --git a/u-boot/include/asm-mips/u-boot.h b/u-boot/include/asm-mips/u-boot.h new file mode 100755 index 0000000..25c5cd5 --- /dev/null +++ b/u-boot/include/asm-mips/u-boot.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ +} bd_t; + +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/u-boot/include/bzlib.h b/u-boot/include/bzlib.h new file mode 100755 index 0000000..2d864d5 --- /dev/null +++ b/u-boot/include/bzlib.h @@ -0,0 +1,329 @@ +/* + * This file is a modified version of bzlib.h from the bzip2-1.0.2 + * distribution which can be found at http://sources.redhat.com/bzip2/ + */ + +/*-------------------------------------------------------------*/ +/*--- Public header file for the library. ---*/ +/*--- bzlib.h ---*/ +/*-------------------------------------------------------------*/ + +/*-- + This file is a part of bzip2 and/or libbzip2, a program and + library for lossless, block-sorting data compression. + + Copyright (C) 1996-2002 Julian R Seward. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + 2. The origin of this software must not be misrepresented; you must + not claim that you wrote the original software. If you use this + software in a product, an acknowledgment in the product + documentation would be appreciated but is not required. + + 3. Altered source versions must be plainly marked as such, and must + not be misrepresented as being the original software. + + 4. The name of the author may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Julian Seward, Cambridge, UK. + jseward@acm.org + bzip2/libbzip2 version 1.0 of 21 March 2000 + + This program is based on (at least) the work of: + Mike Burrows + David Wheeler + Peter Fenwick + Alistair Moffat + Radford Neal + Ian H. Witten + Robert Sedgewick + Jon L. Bentley + + For more information on these sources, see the manual. +--*/ + + +#ifndef _BZLIB_H +#define _BZLIB_H + +/* Configure for U-Boot environment */ +#define BZ_NO_STDIO +#define BZ_NO_COMPRESS +/* End of configuration for U-Boot environment */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BZ_RUN 0 +#define BZ_FLUSH 1 +#define BZ_FINISH 2 + +#define BZ_OK 0 +#define BZ_RUN_OK 1 +#define BZ_FLUSH_OK 2 +#define BZ_FINISH_OK 3 +#define BZ_STREAM_END 4 +#define BZ_SEQUENCE_ERROR (-1) +#define BZ_PARAM_ERROR (-2) +#define BZ_MEM_ERROR (-3) +#define BZ_DATA_ERROR (-4) +#define BZ_DATA_ERROR_MAGIC (-5) +#define BZ_IO_ERROR (-6) +#define BZ_UNEXPECTED_EOF (-7) +#define BZ_OUTBUFF_FULL (-8) +#define BZ_CONFIG_ERROR (-9) + +typedef + struct { + char *next_in; + unsigned int avail_in; + unsigned int total_in_lo32; + unsigned int total_in_hi32; + + char *next_out; + unsigned int avail_out; + unsigned int total_out_lo32; + unsigned int total_out_hi32; + + void *state; + + void *(*bzalloc)(void *,int,int); + void (*bzfree)(void *,void *); + void *opaque; + } + bz_stream; + + +#ifndef BZ_IMPORT +#define BZ_EXPORT +#endif + +#ifdef _WIN32 +# include +# ifdef small + /* windows.h define small to char */ +# undef small +# endif +# ifdef BZ_EXPORT +# define BZ_API(func) WINAPI func +# define BZ_EXTERN extern +# else + /* import windows dll dynamically */ +# define BZ_API(func) (WINAPI * func) +# define BZ_EXTERN +# endif +#else +# define BZ_API(func) func +# define BZ_EXTERN extern +#endif + + +/*-- Core (low-level) library functions --*/ + +BZ_EXTERN int BZ_API(BZ2_bzCompressInit) ( + bz_stream* strm, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN int BZ_API(BZ2_bzCompress) ( + bz_stream* strm, + int action + ); + +BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) ( + bz_stream* strm + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) ( + bz_stream *strm, + int verbosity, + int small + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompress) ( + bz_stream* strm + ); + +BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) ( + bz_stream *strm + ); + + +/*-- High(er) level library functions --*/ + +#ifndef BZ_NO_STDIO +#define BZ_MAX_UNUSED 5000 + +/* Need a definitition for FILE */ +#include + +typedef void BZFILE; + +BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) ( + int* bzerror, + FILE* f, + int verbosity, + int small, + void* unused, + int nUnused + ); + +BZ_EXTERN void BZ_API(BZ2_bzReadClose) ( + int* bzerror, + BZFILE* b + ); + +BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) ( + int* bzerror, + BZFILE* b, + void** unused, + int* nUnused + ); + +BZ_EXTERN int BZ_API(BZ2_bzRead) ( + int* bzerror, + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) ( + int* bzerror, + FILE* f, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN void BZ_API(BZ2_bzWrite) ( + int* bzerror, + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN void BZ_API(BZ2_bzWriteClose) ( + int* bzerror, + BZFILE* b, + int abandon, + unsigned int* nbytes_in, + unsigned int* nbytes_out + ); + +BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) ( + int* bzerror, + BZFILE* b, + int abandon, + unsigned int* nbytes_in_lo32, + unsigned int* nbytes_in_hi32, + unsigned int* nbytes_out_lo32, + unsigned int* nbytes_out_hi32 + ); +#endif + + +/*-- Utility functions --*/ + +BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) ( + char* dest, + unsigned int* destLen, + char* source, + unsigned int sourceLen, + int blockSize100k, + int verbosity, + int workFactor + ); + +BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) ( + char* dest, + unsigned int* destLen, + char* source, + unsigned int sourceLen, + int small, + int verbosity + ); + + +/*-- + Code contributed by Yoshioka Tsuneo + (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp), + to support better zlib compatibility. + This code is not _officially_ part of libbzip2 (yet); + I haven't tested it, documented it, or considered the + threading-safeness of it. + If this code breaks, please contact both Yoshioka and me. +--*/ + +BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) ( + void + ); + +#ifndef BZ_NO_STDIO +BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) ( + const char *path, + const char *mode + ); + +BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) ( + int fd, + const char *mode + ); + +BZ_EXTERN int BZ_API(BZ2_bzread) ( + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN int BZ_API(BZ2_bzwrite) ( + BZFILE* b, + void* buf, + int len + ); + +BZ_EXTERN int BZ_API(BZ2_bzflush) ( + BZFILE* b + ); + +BZ_EXTERN void BZ_API(BZ2_bzclose) ( + BZFILE* b + ); + +BZ_EXTERN const char * BZ_API(BZ2_bzerror) ( + BZFILE *b, + int *errnum + ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif + +/*-------------------------------------------------------------*/ +/*--- end bzlib.h ---*/ +/*-------------------------------------------------------------*/ diff --git a/u-boot/include/cmd_confdefs.h b/u-boot/include/cmd_confdefs.h new file mode 100755 index 0000000..5daeae5 --- /dev/null +++ b/u-boot/include/cmd_confdefs.h @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Definitions for Configuring the monitor commands + */ +#ifndef _CMD_CONFIG_H +#define _CMD_CONFIG_H + +/* + * Configurable monitor commands + */ +#define CFG_CMD_BDI 0x00000001ULL /* bdinfo */ +#define CFG_CMD_LOADS 0x00000002ULL /* loads */ +#define CFG_CMD_LOADB 0x00000004ULL /* loadb */ +#define CFG_CMD_IMI 0x00000008ULL /* iminfo */ +#define CFG_CMD_CACHE 0x00000010ULL /* icache, dcache */ +#define CFG_CMD_FLASH 0x00000020ULL /* flinfo, erase, protect */ +#define CFG_CMD_MEMORY 0x00000040ULL /* md, mm, nm, mw, cp, cmp, */ + +/* crc, base, loop, mtest */ +#define CFG_CMD_NET 0x00000080ULL /* bootp, tftpboot, rarpboot */ +#define CFG_CMD_ENV 0x00000100ULL /* saveenv */ +#define CFG_CMD_KGDB 0x0000000000000200ULL /* kgdb */ +#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */ +#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */ +#define CFG_CMD_PCI 0x00001000ULL /* pciinfo */ +#define CFG_CMD_IRQ 0x00002000ULL /* irqinfo */ +#define CFG_CMD_BOOTD 0x00004000ULL /* bootd */ +#define CFG_CMD_CONSOLE 0x00008000ULL /* coninfo */ +#define CFG_CMD_EEPROM 0x00010000ULL /* EEPROM read/write support */ +#define CFG_CMD_ASKENV 0x00020000ULL /* ask for env variable */ +#define CFG_CMD_RUN 0x00040000ULL /* run command in env variable */ +#define CFG_CMD_ECHO 0x00080000ULL /* echo arguments */ +#define CFG_CMD_I2C 0x00100000ULL /* I2C serial bus support */ +#define CFG_CMD_REGINFO 0x00200000ULL /* Register dump */ +#define CFG_CMD_IMMAP 0x00400000ULL /* IMMR dump support */ +#define CFG_CMD_DATE 0x00800000ULL /* support for RTC, date/time...*/ +#define CFG_CMD_DHCP 0x01000000ULL /* DHCP Support */ +#define CFG_CMD_BEDBUG 0x02000000ULL /* Include BedBug Debugger */ +#define CFG_CMD_FDC 0x04000000ULL /* Floppy Disk Support */ +#define CFG_CMD_SCSI 0x08000000ULL /* SCSI Support */ +#define CFG_CMD_AUTOSCRIPT 0x10000000ULL /* Autoscript Support */ +#define CFG_CMD_MII 0x20000000ULL /* MII support */ +#define CFG_CMD_SETGETDCR 0x40000000ULL /* DCR support on 4xx */ +#define CFG_CMD_BSP 0x80000000ULL /* Board Specific functions */ + +#define CFG_CMD_ELF 0x0000000100000000ULL /* ELF (VxWorks) load/boot cmd */ +#define CFG_CMD_MISC 0x0000000200000000ULL /* Misc functions like sleep etc*/ +#define CFG_CMD_USB 0x0000000400000000ULL /* USB Support */ +#define CFG_CMD_DOC 0x0000000800000000ULL /* Disk-On-Chip Support */ +#define CFG_CMD_JFFS2 0x0000001000000000ULL /* JFFS2 Support */ +#define CFG_CMD_DTT 0x0000002000000000ULL /* Digital Therm and Thermostat */ +#define CFG_CMD_SDRAM 0x0000004000000000ULL /* SDRAM DIMM SPD info printout */ +#define CFG_CMD_DIAG 0x0000008000000000ULL /* Diagnostics */ +#define CFG_CMD_FPGA 0x0000010000000000ULL /* FPGA configuration Support */ +#define CFG_CMD_HWFLOW 0x0000020000000000ULL /* RTS/CTS hw flow control */ +#define CFG_CMD_SAVES 0x0000040000000000ULL /* save S record dump */ +#define CFG_CMD_SPI 0x0000100000000000ULL /* SPI utility */ +#define CFG_CMD_FDOS 0x0000200000000000ULL /* Floppy DOS support */ +#define CFG_CMD_VFD 0x0000400000000000ULL /* VFD support (TRAB) */ +#define CFG_CMD_NAND 0x0000800000000000ULL /* NAND support */ +#define CFG_CMD_BMP 0x0001000000000000ULL /* BMP support */ +#define CFG_CMD_PORTIO 0x0002000000000000ULL /* Port I/O */ +#define CFG_CMD_PING 0x0004000000000000ULL /* ping support */ +#define CFG_CMD_MMC 0x0008000000000000ULL /* MMC support */ +#define CFG_CMD_FAT 0x0010000000000000ULL /* FAT support */ +#define CFG_CMD_IMLS 0x0020000000000000ULL /* List all found images */ +#define CFG_CMD_ITEST 0x0040000000000000ULL /* Integer (and string) test */ +#define CFG_CMD_NFS 0x0080000000000000ULL /* NFS support */ +#define CFG_CMD_REISER 0x0100000000000000ULL /* Reiserfs support */ +#define CFG_CMD_CDP 0x0200000000000000ULL /* Cisco Discovery Protocol */ +#define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */ +#define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */ +#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ +#define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */ +#define CFG_CMD_PLL 0x2000000000000001ULL /* Change CPU clock speeds */ +#define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */ +#define CFG_CMD_ETHREG 0x8000000000000000ULL /* S26 Reg RD/WR utility */ + +#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ + +/* + * Commands that are considered "non-standard" for some reason + * (memory hogs, requires special hardware, not fully tested, etc.) + */ +#define CFG_CMD_NONSTD (CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BDI | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_CDP | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_ENV | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FAT | \ + CFG_CMD_FDOS | \ + CFG_CMD_FPGA | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_IMI | \ + CFG_CMD_IMLS | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ITEST | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_LOADB | \ + CFG_CMD_LOADS | \ + CFG_CMD_MISC | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_PING | \ + CFG_CMD_PORTIO | \ + CFG_CMD_REGINFO | \ + CFG_CMD_REISER | \ + CFG_CMD_SAVES | \ + CFG_CMD_SCSI | \ + CFG_CMD_SETGETDCR |\ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP | \ + CFG_CMD_SPI | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG | \ + CFG_CMD_ETHREG | \ + CFG_CMD_VFD ) + +/* Default configuration + */ +#define CONFIG_CMD_DFL (CFG_CMD_ALL & ~CFG_CMD_NONSTD) + +#ifndef CONFIG_COMMANDS +#define CONFIG_COMMANDS CONFIG_CMD_DFL +#endif + +/* + * optional BOOTP fields + */ +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_NISDOMAIN 0x00000008 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 +#define CONFIG_BOOTP_BOOTFILESIZE 0x00000020 +#define CONFIG_BOOTP_DNS 0x00000040 +#define CONFIG_BOOTP_DNS2 0x00000080 +#define CONFIG_BOOTP_SEND_HOSTNAME 0x00000100 +#define CONFIG_BOOTP_NTPSERVER 0x00000200 +#define CONFIG_BOOTP_TIMEOFFSET 0x00000400 + +#define CONFIG_BOOTP_VENDOREX 0x80000000 + +#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX) + +#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | CONFIG_BOOTP_GATEWAY | CONFIG_BOOTP_HOSTNAME | CONFIG_BOOTP_BOOTPATH) + +#ifndef CONFIG_BOOTP_MASK +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#endif + +#endif /* _CMD_CONFIG_H */ diff --git a/u-boot/include/command.h b/u-boot/include/command.h new file mode 100755 index 0000000..656cc55 --- /dev/null +++ b/u-boot/include/command.h @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Definitions for Command Processor + */ +#ifndef __COMMAND_H +#define __COMMAND_H + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef __ASSEMBLY__ +/* + * Monitor Command Table + */ + +struct cmd_tbl_s { + char *name; /* Command Name */ + int maxargs; /* maximum number of arguments */ + int repeatable; /* autorepeat allowed? */ + int (*cmd)(struct cmd_tbl_s *, int, int, char *[]); /* Implementation function */ + char *usage; /* Usage message (short) */ +#ifdef CFG_LONGHELP + char *help; /* Help message (long) */ +#endif +}; + +typedef struct cmd_tbl_s cmd_tbl_t; + +extern cmd_tbl_t __u_boot_cmd_start; +extern cmd_tbl_t __u_boot_cmd_end; + +/* common/command.c */ +cmd_tbl_t *find_cmd(const char *cmd); + +/* + * Monitor Command + * All commands use a common argument format: + * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + */ +typedef void command_t(cmd_tbl_t *, int, int, char *[]); + +#endif /* __ASSEMBLY__ */ + +/* + * Command Flags: + */ +#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ +#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ + +/* + * Configurable monitor commands definitions have been moved + * to include/cmd_confdefs.h + */ +#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd"))) + +#ifdef CFG_LONGHELP +#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help} +#else /* no long help info */ +#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage} +#endif /* CFG_LONGHELP */ + +#endif /* __COMMAND_H */ diff --git a/u-boot/include/common.h b/u-boot/include/common.h new file mode 100755 index 0000000..1855a52 --- /dev/null +++ b/u-boot/include/common.h @@ -0,0 +1,582 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __COMMON_H_ +#define __COMMON_H_ 1 + +#undef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +typedef unsigned char uchar; +typedef volatile unsigned long vu_long; +typedef volatile unsigned short vu_short; +typedef volatile unsigned char vu_char; + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) && defined(CONFIG_440) +#include +#endif +#if defined(CONFIG_8xx) +#include +#if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \ + defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ + defined(CONFIG_MPC859DSL) || \ + defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \ + defined(CONFIG_MPC866P) +# define CONFIG_MPC866_FAMILY 1 +#elif defined(CONFIG_MPC870) \ + || defined(CONFIG_MPC875) \ + || defined(CONFIG_MPC880) \ + || defined(CONFIG_MPC885) +# define CONFIG_MPC885_FAMILY 1 +#endif +#if defined(CONFIG_MPC860) \ + || defined(CONFIG_MPC860T) \ + || defined(CONFIG_MPC866_FAMILY) \ + || defined(CONFIG_MPC885_FAMILY) +# define CONFIG_MPC86x 1 +#endif +#elif defined(CONFIG_5xx) +#include +#elif defined(CONFIG_MPC5xxx) +#include +#elif defined(CONFIG_MPC8220) +#include +#elif defined(CONFIG_8260) +#if defined(CONFIG_MPC8247) \ + || defined(CONFIG_MPC8248) \ + || defined(CONFIG_MPC8271) \ + || defined(CONFIG_MPC8272) +#define CONFIG_MPC8272_FAMILY 1 +#endif +#if defined(CONFIG_MPC8272_FAMILY) +#define CONFIG_MPC8260 1 +#endif +#include +#endif +#ifdef CONFIG_MPC85xx +#include +#include +#endif +#ifdef CONFIG_MPC83XX +#include +#include +#endif +#ifdef CONFIG_4xx +#include +#endif +#ifdef CONFIG_HYMOD +#include +#endif +#ifdef CONFIG_ARM +#define asmlinkage /* nothing */ +#endif + +#include +#include + +#ifdef DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#define debugX(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args); +#else +#define debug(fmt,args...) +#define debugX(level,fmt,args...) +#endif /* DEBUG */ + +typedef void (interrupt_handler_t)(void *); + +#include /* boot information for Linux kernel */ +#include /* global data used for startup functions */ + +/* + * enable common handling for all TQM8xxL/M boards: + * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards + * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards + */ +#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ + defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ + defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) +# ifndef CONFIG_TQM8xxM +# define CONFIG_TQM8xxM +# endif +#endif +#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ + defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ + defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) +# ifndef CONFIG_TQM8xxL +# define CONFIG_TQM8xxL +# endif +#endif + +#ifndef CONFIG_SERIAL_MULTI + +#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \ + || defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \ + || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) + +#define CONFIG_SERIAL_MULTI 1 + +#endif + +#endif /* CONFIG_SERIAL_MULTI */ + +/* + * General Purpose Utilities + */ +#define min(X, Y) \ + ({ typeof (X) __x = (X), __y = (Y); \ + (__x < __y) ? __x : __y; }) + +#define max(X, Y) \ + ({ typeof (X) __x = (X), __y = (Y); \ + (__x > __y) ? __x : __y; }) + + +/* + * Function Prototypes + */ + +void hang(void) __attribute__ ((noreturn)); + +/* */ +long int initdram(void); +void print_size(ulong, const char *); + +/* common/main.c */ +void main_loop (void); +int run_command (const char *cmd, int flag); +int readline (const char *const prompt); +void init_cmd_timeout(void); +void reset_cmd_timeout(void); + +/* lib_$(ARCH)/board.c */ +void board_init_f (ulong); +void board_init_r (gd_t *, ulong); +int checkboard (void); +int checkflash (void); +int checkdram (void); +char * strmhz(char *buf, long hz); +int last_stage_init(void); +extern ulong monitor_flash_len; + +/* common/flash.c */ +void flash_perror (int); + +/* common/cmd_autoscript.c */ +int autoscript (ulong addr); + +/* + * Only TP-Link OFW and OpenWrt for TP-Link routers + * use different (simply) image header + */ +#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) +#include "tpLinuxTag.h" +#endif + +/* common/cmd_bootm.c */ +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) +void print_image_hdr(image_header_t *hdr); +#else +void print_image_hdr(tplink_image_header_t *hdr); +#endif + +extern ulong load_addr; /* Default Load Address */ + +/* common/cmd_nvedit.c */ +int env_init (void); +void env_relocate (void); +char *getenv (char *); +int getenv_r (char *name, char *buf, unsigned len); +int saveenv (void); +void setenv (char *, char *); + + +#ifdef CONFIG_ARM +# include +# include +# include /* ARM version to be fixed! */ +#endif /* CONFIG_ARM */ +#ifdef CONFIG_I386 /* x86 version to be fixed! */ +# include +#endif /* CONFIG_I386 */ + +void pci_init (void); +int pci_init_board(void); +void pciinfo (int, int); + +#if defined(CONFIG_PCI) && defined(CONFIG_440) +# if defined(CFG_PCI_PRE_INIT) + int pci_pre_init (struct pci_controller * ); +# endif +# if defined(CFG_PCI_TARGET_INIT) + void pci_target_init (struct pci_controller *); +# endif +# if defined(CFG_PCI_MASTER_INIT) + void pci_master_init (struct pci_controller *); +# endif + int is_pci_host (struct pci_controller *); +#endif + +int misc_init_f (void); +int misc_init_r (void); + +/* common/exports.c */ +void jumptable_init(void); + +/* common/memsize.c */ +int get_ram_size (volatile long *, long); + +/* $(BOARD)/$(BOARD).c */ +void reset_phy (void); +void fdc_hw_init (void); + +/* $(BOARD)/eeprom.c */ +void eeprom_init (void); +#ifndef CONFIG_SPI +int eeprom_probe (unsigned dev_addr, unsigned offset); +#endif +int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); +int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); +#ifdef CONFIG_LWMON +extern uchar pic_read (uchar reg); +extern void pic_write (uchar reg, uchar val); +#endif + +/* + * Set this up regardless of board + * type, to prevent errors. + */ +#if defined(CONFIG_SPI) || !defined(CFG_I2C_EEPROM_ADDR) +# define CFG_DEF_EEPROM_ADDR 0 +#else +# define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR +#endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */ + +#if defined(CONFIG_SPI) +extern void spi_init_f (void); +extern void spi_init_r (void); +extern ssize_t spi_read (uchar *, int, uchar *, int); +extern ssize_t spi_write (uchar *, int, uchar *, int); +#endif + +#ifdef CONFIG_RPXCLASSIC +void rpxclassic_init (void); +#endif + +void rpxlite_init (void); + +#ifdef CONFIG_MBX +/* $(BOARD)/mbx8xx.c */ +void mbx_init (void); +void board_serial_init (void); +void board_ether_init (void); +#endif + +#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \ + defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \ + defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) +void board_get_enetaddr (uchar *addr); +#endif + +#ifdef CONFIG_HERMES +/* $(BOARD)/hermes.c */ +void hermes_start_lxt980 (int speed); +#endif + +#ifdef CONFIG_EVB64260 +void evb64260_init(void); +void debug_led(int, int); +void display_mem_map(void); +void perform_soft_reset(void); +#endif + +void load_sernum_ethaddr (void); + +/* $(BOARD)/$(BOARD).c */ +int board_early_init_f (void); +int board_late_init (void); +int board_postclk_init (void); /* after clocks/timebase, before env/serial */ +int board_early_init_r (void); +void board_poweroff (void); + +#if defined(CFG_DRAM_TEST) +int testdram(void); +#endif /* CFG_DRAM_TEST */ + +/* $(CPU)/start.S */ +#if defined(CONFIG_5xx) || \ + defined(CONFIG_8xx) +uint get_immr (uint); +#endif +uint get_pir (void); +#if defined(CONFIG_MPC5xxx) +uint get_svr (void); +#endif +uint get_pvr (void); +uint get_svr (void); +uint rd_ic_cst (void); +void wr_ic_cst (uint); +void wr_ic_adr (uint); +uint rd_dc_cst (void); +void wr_dc_cst (uint); +void wr_dc_adr (uint); +int icache_status (void); +void icache_enable (void); +void icache_disable(void); +int dcache_status (void); +void dcache_enable (void); +void dcache_disable(void); +void relocate_code (ulong, gd_t *, ulong); +void ar7240_ddr_tap_init(void); +ulong get_endaddr (void); +void trap_init (ulong); +#if defined (CONFIG_4xx) || \ + defined (CONFIG_MPC5xxx) || \ + defined (CONFIG_74xx_7xx) || \ + defined (CONFIG_74x) || \ + defined (CONFIG_75x) || \ + defined (CONFIG_74xx) || \ + defined (CONFIG_MPC8220) || \ + defined (CONFIG_MPC85xx) || \ + defined (CONFIG_MPC83XX) +unsigned char in8(unsigned int); +void out8(unsigned int, unsigned char); +unsigned short in16(unsigned int); +unsigned short in16r(unsigned int); +void out16(unsigned int, unsigned short value); +void out16r(unsigned int, unsigned short value); +unsigned long in32(unsigned int); +unsigned long in32r(unsigned int); +void out32(unsigned int, unsigned long value); +void out32r(unsigned int, unsigned long value); +void ppcDcbf(unsigned long value); +void ppcDcbi(unsigned long value); +void ppcSync(void); +void ppcDcbz(unsigned long value); +#endif + +/* $(CPU)/cpu.c */ +int checkcpu (void); +int checkicache (void); +int checkdcache (void); +void upmconfig (unsigned int, unsigned int *, unsigned int); +ulong get_tbclk (void); +void reset_cpu (ulong addr); + +/* $(CPU)/serial.c */ +int serial_init (void); +void serial_addr (unsigned int); +void serial_putc (const char); +void serial_putc_raw(const char); +void serial_puts (const char *); +int serial_getc (void); +int serial_tstc (void); + +void _serial_putc (const char, const int); +void _serial_putc_raw(const char, const int); +void _serial_puts (const char *, const int); +int _serial_getc (const int); +int _serial_tstc (const int); + +/* $(CPU)/speed.c */ +int get_clocks (void); +int get_clocks_866 (void); +int sdram_adjust_866 (void); +int adjust_sdram_tbs_8xx (void); +#if defined(CONFIG_8260) +int prt_8260_clks (void); +#elif defined(CONFIG_MPC83XX) +int print_clock_conf(void); +#elif defined(CONFIG_MPC5xxx) +int prt_mpc5xxx_clks (void); +#endif +#if defined(CONFIG_MPC8220) +int prt_mpc8220_clks (void); +#endif +#ifdef CONFIG_4xx +ulong get_OPB_freq (void); +ulong get_PCI_freq (void); +#endif +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X) +ulong get_FCLK (void); +ulong get_HCLK (void); +ulong get_PCLK (void); +ulong get_UCLK (void); +#endif +#if defined(CONFIG_LH7A40X) +ulong get_PLLCLK (void); +#endif +#if defined CONFIG_INCA_IP +uint incaip_get_cpuclk (void); +#endif +#if defined(CONFIG_IMX) +ulong get_systemPLLCLK(void); +ulong get_FCLK(void); +ulong get_HCLK(void); +ulong get_BCLK(void); +ulong get_PERCLK1(void); +ulong get_PERCLK2(void); +ulong get_PERCLK3(void); +#endif +ulong get_bus_freq (ulong); + +#if defined(CONFIG_MPC85xx) +typedef MPC85xx_SYS_INFO sys_info_t; +void get_sys_info ( sys_info_t * ); +#endif + +#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) +# if defined(CONFIG_440) + typedef PPC440_SYS_INFO sys_info_t; +# else + typedef PPC405_SYS_INFO sys_info_t; +# endif +void get_sys_info ( sys_info_t * ); +#endif + +/* $(CPU)/cpu_init.c */ +#if defined(CONFIG_8xx) || defined(CONFIG_8260) +void cpu_init_f (volatile immap_t *immr); +#endif +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) +void cpu_init_f (void); +#endif + +int cpu_init_r (void); +#if defined(CONFIG_8260) +int prt_8260_rsr (void); +#endif + +/* $(CPU)/interrupts.c */ +int interrupt_init (void); +void timer_interrupt (struct pt_regs *); +void external_interrupt (struct pt_regs *); +void irq_install_handler(int, interrupt_handler_t *, void *); +void irq_free_handler (int); +ulong get_timer (ulong base); + +/* $(CPU)/.../commproc.c */ +int dpram_init (void); +uint dpram_base(void); +uint dpram_base_align(uint align); +uint dpram_alloc(uint size); +uint dpram_alloc_align(uint size,uint align); +void post_word_store (ulong); +ulong post_word_load (void); +void bootcount_store (ulong); +ulong bootcount_load (void); +#define BOOTCOUNT_MAGIC 0xB001C041 + +/* $(CPU)/.../ */ +void mii_init (void); + +/* $(CPU)/.../lcd.c */ +ulong lcd_setmem (ulong); + +/* $(CPU)/.../vfd.c */ +ulong vfd_setmem (ulong); + +/* $(CPU)/.../video.c */ +ulong video_setmem (ulong); + +/* lib_$(ARCH)/cache.c */ +void flush_cache (unsigned long, unsigned long); + + +/* lib_$(ARCH)/ticks.S */ +unsigned long long get_ticks(void); +void wait_ticks (unsigned long); + +/* lib_$(ARCH)/time.c */ +void udelay (unsigned long); +ulong usec2ticks (unsigned long usec); +ulong ticks2usec (unsigned long ticks); +int init_timebase (void); + +/* lib_generic/vsprintf.c */ +ulong simple_strtoul(const char *cp,char **endp,unsigned int base); +#ifdef CFG_64BIT_VSPRINTF +unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); +#endif +long simple_strtol(const char *cp,char **endp,unsigned int base); +int sprintf(char * buf, const char *fmt, ...); +int vsprintf(char *buf, const char *fmt, va_list args); + +/* lib_generic/crc32.c */ +ulong crc32 (ulong, const unsigned char *, uint); +ulong crc32_no_comp (ulong, const unsigned char *, uint); + +/* common/console.c */ +int console_init_f(void); /* Before relocation; uses the serial stuff */ +int console_init_r(void); /* After relocation; uses the console stuff */ +int console_assign (int file, char *devname); /* Assign the console */ +int ctrlc (void); +int had_ctrlc (void); /* have we had a Control-C since last clear? */ +void clear_ctrlc (void); /* clear the Control-C condition */ +int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ + +/* + * STDIO based functions (can always be used) + */ + +/* serial stuff */ +void serial_printf (const char *fmt, ...); + +/* stdin */ +int getc(void); +int tstc(void); + +/* stdout */ +void putc(const char c); +void puts(const char *s); +void printf(const char *fmt, ...); +//void vprintf(const char *fmt, va_list args); + +/* stderr */ +#define eputc(c) fputc(stderr, c) +#define eputs(s) fputs(stderr, s) +#define eprintf(fmt,args...) fprintf(stderr,fmt ,##args) + +/* + * FILE based functions (can only be used AFTER relocation!) + */ + +#define stdin 0 +#define stdout 1 +#define stderr 2 +#define MAX_FILES 3 + +void fprintf(int file, const char *fmt, ...); +void fputs(int file, const char *s); +void fputc(int file, const char c); +int ftstc(int file); +int fgetc(int file); + +int pcmcia_init (void); + +#endif /* __COMMON_H_ */ diff --git a/u-boot/include/configs/ap121.h b/u-boot/include/configs/ap121.h new file mode 100755 index 0000000..f603621 --- /dev/null +++ b/u-boot/include/configs/ap121.h @@ -0,0 +1,560 @@ +/* + * This file contains the configuration parameters for the AP121 (AR9331) board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash + +/* + * We boot from this flash + */ +#define CFG_FLASH_BASE 0x9F000000 +#ifdef COMPRESSED_UBOOT + #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE + #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE +#endif + +/* + * The following #defines are needed to get flash environment right + */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +/* + * Default bootargs + */ +#undef CONFIG_BOOTARGS + +#if defined(CONFIG_FOR_TPLINK_WR703N_V1) || \ + defined(CONFIG_FOR_TPLINK_WR720N_V3) || \ + defined(CONFIG_FOR_TPLINK_MR3020_V1) || \ + defined(CONFIG_FOR_TPLINK_MR3040_V1V2) || \ + defined(CONFIG_FOR_TPLINK_MR10U_V1) || \ + defined(CONFIG_FOR_TPLINK_WR740N_V4) || \ + defined(CONFIG_FOR_TPLINK_MR3220_V2) + + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)" + +#elif defined(CONFIG_FOR_TPLINK_WR710N_V1) + + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(ART)" + +#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(ART)" + +#endif + +/* + * Other env default values + */ +#undef CONFIG_BOOTFILE +#define CONFIG_BOOTFILE "firmware.bin" + +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x80800000 + +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define CFG_LOAD_ADDR 0x9F050000 +#else + #define CFG_LOAD_ADDR 0x9F020000 +#endif + +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define CONFIG_BOOTCOMMAND "bootm 0x9F050000" +#else + #define CONFIG_BOOTCOMMAND "bootm 0x9F020000" +#endif + +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.2 + +#undef CFG_PLL_FREQ +#undef CFG_HZ +#undef CPU_PLL_CONFIG_VAL1 +#undef CPU_CLK_CONTROL_VAL2 + +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define CONFIG_40MHZ_XTAL_SUPPORT 1 // Carambola 2 has 40 MHz XTAL, TP-Link routers use 25 MHz +#endif + +// CPU-RAM-AHB frequency setting +#define CFG_PLL_FREQ CFG_PLL_400_400_200 + +/* + * MIPS32 24K Processor Core Family Software User's Manual + * + * 6.2.9 Count Register (CP0 Register 9, Select 0) + * The Count register acts as a timer, incrementing at a constant + * rate, whether or not an instruction is executed, retired, or + * any forward progress is made through the pipeline. The counter + * increments every other clock, if the DC bit in the Cause register + * is 0. + * + * Since the count is incremented every other tick, divide by 2 + * XXX derive this from CFG_PLL_FREQ + */ + + +/* + * CPU_PLL_DITHER_FRAC_VAL + * + * Value written into CPU PLL Dither FRAC Register (PLL_DITHER_FRAC) + * + * bits 0..9 NFRAC_MAX => 1000 (0x3E8) + * bits 10..13 NFRAC_MIN => 0 (minimum value is used) + * bits 20..29 NFRAC_STEP => 1 + * + */ +#define CPU_PLL_DITHER_FRAC_VAL 0x001003e8 + +/* + * CPU_PLL_SETTLE_TIME_VAL + * + * Value written into CPU Phase Lock Loop Configuration Register 2 (CPU_PLL_CONFIG2) + * + * bits 0..11 SETTLE_TIME => 580 (0x352) + * + */ +#if CONFIG_40MHZ_XTAL_SUPPORT + #define CPU_PLL_SETTLE_TIME_VAL 0x00000550 +#else + #define CPU_PLL_SETTLE_TIME_VAL 0x00000352 +#endif + +/* + * CPU_CLK_CONTROL_VAL1 + * CPU_CLK_CONTROL_VAL2 + * + * Values written into CPU Clock Control Register CLOCK_CONTROL + * with PLL bypass disabled + * + * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test purposes. Software must enable the CPU PLL for normal operation and then set this bit to 0) + * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) + * bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1) + * bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2) + * + */ + +/* + * CPU_PLL_CONFIG_VAL1 + * CPU_PLL_CONFIG_VAL2 + * + * In CPU_PLL_CONFIG_VAL1 bit 30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) + * In CPU_PLL_CONFIG_VAL2 bit 30 is unset + * + * Values written into CPU Phase Lock Loop Configuration (CPU_PLL_CONFIG) + * + * bits 10..15 (6bit) DIV_INT (The integer part of the DIV to CPU PLL) => 32 (0x20) + * bits 16..20 (5bit) REFDIV (Reference clock divider) => 1 (0x1) [doesn't start at valuse different than 1 (maybe need to change other dividers?)] + * bits 21 (1bit) RANGE (Determine the VCO frequency range of the CPU PLL) => 0 (0x0) [doesn't have impact on clock values] + * bits 23..25 (3bit) OUTDIV (Define the ratio betwee VCO output and PLL output => 1 (0x1) + * VCOOUT * (1/2^OUTDIV) = PLLOUT) + */ + +/* + * = PLL CALCULATION (guess) ============= + * PLL = (25 MHz * DIV_INT) / (2 ^ OUTDIV) // XTAL=25 MHz + * OR + * PLL = (40 MHz * DIV_INT) / (2 ^ OUTDIV) // XTAL=40 MHz + * + * CPU = PLL / CPU_POST_DIV + * DDR = PLL / DDR_POST_DIV + * AHB = PLL / AHB_POST_DIV + * + */ + +/* + * AR7240_SPI_CONTROL + * + * Value written into SPI Control (SPI_CONTROL) register + * + * bits 0..5 (6bit) CLOCK_DIVIDER (Specifies the clock divider setting. Actual clock frequency would be (AHB_CLK / ((CLOCK_DIVIDER+1)*2)) ) + * bits 6 (1bit) REMAP_DISABLE (Remaps 4 MB space over unless explicitly disabled by setting this bit to 1. If set to 1, 16 MB is accessible.) + * + */ + +#if (CFG_PLL_FREQ == CFG_PLL_400_400_200) + + #define CFG_HZ (400000000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + #if CONFIG_40MHZ_XTAL_SUPPORT + // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40815000 + #define CPU_PLL_CONFIG_VAL2 0x00815000 + #else + // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40818000 + #define CPU_PLL_CONFIG_VAL2 0x00818000 + #endif + + // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz) + #define AR7240_SPI_CONTROL 0x42 + +#elif (CFG_PLL_FREQ == CFG_PLL_412_412_206) + + #define CFG_HZ (412500000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + // DIV_INT = 33 (25 MHz * 33/2 = 412,5 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40818400 + #define CPU_PLL_CONFIG_VAL2 0x00818400 + + // CLOCK_DIVIDER = 2 (SPI clock = 206,25 / 6 ~ 34,4 MHz) + #define AR7240_SPI_CONTROL 0x42 + +#elif (CFG_PLL_FREQ == CFG_PLL_425_425_212) + + #define CFG_HZ (425000000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + // DIV_INT = 34 (25 MHz * 34/2 = 425 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40818800 + #define CPU_PLL_CONFIG_VAL2 0x00818800 + + // CLOCK_DIVIDER = 2 (SPI clock = 212,5 / 6 ~ 35,4 MHz) + #define AR7240_SPI_CONTROL 0x42 + +#elif (CFG_PLL_FREQ == CFG_PLL_437_437_218) + + #define CFG_HZ (437500000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + // DIV_INT = 35 (25 MHz * 35/2 = 437,5 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40818C00 + #define CPU_PLL_CONFIG_VAL2 0x00818C00 + + // CLOCK_DIVIDER = 2 (SPI clock = 218,75 / 6 ~ 36,5 MHz) + #define AR7240_SPI_CONTROL 0x42 + + +#elif (CFG_PLL_FREQ == CFG_PLL_450_450_225) + + #define CFG_HZ (450000000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + // DIV_INT = 36 (25 MHz * 36/2 = 450 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40819000 + #define CPU_PLL_CONFIG_VAL2 0x00819000 + + // CLOCK_DIVIDER = 3 (SPI clock = 225 / 6 ~ 37,5 MHz) + #define AR7240_SPI_CONTROL 0x42 + +#elif (CFG_PLL_FREQ == CFG_PLL_462_462_231) + + #define CFG_HZ (462500000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + // DIV_INT = 37 (25 MHz * 37/2 = 462,5 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40819400 + #define CPU_PLL_CONFIG_VAL2 0x00819400 + + // CLOCK_DIVIDER = 3 (SPI clock = 231,25 / 6 ~ 38,5 MHz) + #define AR7240_SPI_CONTROL 0x42 + +#elif (CFG_PLL_FREQ == CFG_PLL_475_475_237) + + #define CFG_HZ (475000000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + // DIV_INT = 38 (25 MHz * 38/2 = 475 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40819800 + #define CPU_PLL_CONFIG_VAL2 0x00819800 + + // CLOCK_DIVIDER = 3 (SPI clock = 237,5 / 6 ~ 39,6 MHz) + #define AR7240_SPI_CONTROL 0x42 + +#elif (CFG_PLL_FREQ == CFG_PLL_487_487_243) + + #define CFG_HZ (487500000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + // DIV_INT = 39 (25 MHz * 39/2 = 487,5 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x40819C00 + #define CPU_PLL_CONFIG_VAL2 0x00819C00 + + // CLOCK_DIVIDER = 3 (SPI clock = 243,75 / 8 ~ 30,5 MHz) + #define AR7240_SPI_CONTROL 0x43 + + +#elif (CFG_PLL_FREQ == CFG_PLL_500_500_250) + + #define CFG_HZ (500000000LU/2) + + // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018004 + #define CPU_CLK_CONTROL_VAL2 0x00008000 + + // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x4081A000 + #define CPU_PLL_CONFIG_VAL2 0x0081A000 + + // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz) + #define AR7240_SPI_CONTROL 0x43 + +#elif (CFG_PLL_FREQ == CFG_PLL_500_250_250) + + #define CFG_HZ (500000000LU/2) + + // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 2 + #define CPU_CLK_CONTROL_VAL1 0x00018404 + #define CPU_CLK_CONTROL_VAL2 0x00008400 + + // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x4081A000 + #define CPU_PLL_CONFIG_VAL2 0x0081A000 + + // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz) + #define AR7240_SPI_CONTROL 0x43 + +#elif (CFG_PLL_FREQ == CFG_PLL_562_281_140) + + #define CFG_HZ (562500000LU/2) + + // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4 + #define CPU_CLK_CONTROL_VAL1 0x00018404 + #define CPU_CLK_CONTROL_VAL2 0x00018400 + + // DIV_INT = 45 (25 MHz * 45/2 = 562,5 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x4081B400 + #define CPU_PLL_CONFIG_VAL2 0x0081B400 + + // CLOCK_DIVIDER = 1 (SPI clock = 140,625 / 4 ~ 35,2 MHz) + #define AR7240_SPI_CONTROL 0x41 + +#elif (CFG_PLL_FREQ == CFG_PLL_525_262_131) + + #define CFG_HZ (525000000LU/2) + + // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4 + #define CPU_CLK_CONTROL_VAL1 0x00018404 + #define CPU_CLK_CONTROL_VAL2 0x00018400 + + // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz) + // REFDIV = 1 + // RANGE = 0 + // OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL1 0x4081A800 + #define CPU_PLL_CONFIG_VAL2 0x0081A800 + + // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 32,8 MHz) + #define AR7240_SPI_CONTROL 0x41 + +#endif + +/* + * Cache lock for stack + */ +#define CFG_INIT_SP_OFFSET 0x1000 + +/* + * Address and size of Primary Environment Sector + */ +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define CFG_ENV_IS_IN_FLASH 1 + #undef CFG_ENV_IS_NOWHERE +#else + #undef CFG_ENV_IS_IN_FLASH + #define CFG_ENV_IS_NOWHERE 1 +#endif + +#define CFG_ENV_ADDR 0x9F040000 +#define CFG_ENV_SIZE 0x10000 + +/* + * Available commands + */ +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_NET | CFG_CMD_RUN | CFG_CMD_DATE | CFG_CMD_IMI | CFG_CMD_SNTP) +#else + #define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_NET | CFG_CMD_PING ) +#endif + +// Enable NetConsole and custom NetConsole port +#define CONFIG_NETCONSOLE +#define CONFIG_NETCONSOLE_PORT 6666 + +/* DDR init values */ +#if CONFIG_40MHZ_XTAL_SUPPORT + #define CFG_DDR_REFRESH_VAL 0x4270 +#else + #define CFG_DDR_REFRESH_VAL 0x4186 +#endif + +#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0 +#define CFG_DDR_MODE_VAL_INIT 0x133 + +#ifdef LOW_DRIVE_STRENGTH + #define CFG_DDR_EXT_MODE_VAL 0x2 +#else + #define CFG_DDR_EXT_MODE_VAL 0x0 +#endif + +#define CFG_DDR_MODE_VAL 0x33 +#define CFG_DDR_TRTW_VAL 0x1f +#define CFG_DDR_TWTR_VAL 0x1e + +//#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0 +#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1 +#define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff +#define CFG_DDR_TAP0_VAL 0x8 +#define CFG_DDR_TAP1_VAL 0x9 + +/* DDR2 Init values */ +#define CFG_DDR2_EXT_MODE_VAL 0x402 + +#define CONFIG_NET_MULTI + +/* choose eth1 first for tftpboot interface added by ZJin, 110328 */ +#define CONFIG_AG7240_SPEPHY + +/* + * Web Failsafe configuration + */ +#define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR +#define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE + +// Firmware partition offset +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000 +#else + #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000 +#endif + +// U-Boot partition size +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (256 * 1024) +#else + #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (64 * 1024) +#endif + +// ART partition size +#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024) + +// max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES) +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + // Carambola 2: 256k(U-Boot),64k(U-Boot env),64k(ART) + #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024) +#else + // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART) + #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) +#endif + +// progress state info +#define WEBFAILSAFE_PROGRESS_START 0 +#define WEBFAILSAFE_PROGRESS_TIMEOUT 1 +#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2 +#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3 +#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4 + +// update type +#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0 +#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1 +#define WEBFAILSAFE_UPGRADE_TYPE_ART 2 + +/*-----------------------------------------------------------------------*/ + +#define CFG_ATHRS26_PHY 1 +#define CFG_AG7240_NMACS 2 +#define CFG_MII0_RMII 1 +#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */ + +#undef DEBUG +#define milisecdelay(_x) udelay((_x) * 1000) + +/* MAC address, model and PIN number offsets in FLASH */ +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define OFFSET_MAC_DATA_BLOCK 0xFF0000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x000000 // Carambola 2 has two MAC addresses at the beginning of ART partition + #define OFFSET_MAC_ADDRESS2 0x000006 +#else + #define OFFSET_MAC_DATA_BLOCK 0x010000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x00FC00 +#endif + +#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) +#define OFFSET_ROUTER_MODEL 0x00FD00 +#endif + +#if defined(CONFIG_FOR_TPLINK_MR3020_V1) || \ + defined(CONFIG_FOR_TPLINK_WR740N_V4) || \ + defined(CONFIG_FOR_TPLINK_MR3220_V2) || \ + defined(CONFIG_FOR_TPLINK_WR710N_V1) + #define OFFSET_PIN_NUMBER 0x00FE00 +#endif + +#include + +#endif /* __CONFIG_H */ diff --git a/u-boot/include/configs/ar7240.h b/u-boot/include/configs/ar7240.h new file mode 100755 index 0000000..b0eb962 --- /dev/null +++ b/u-boot/include/configs/ar7240.h @@ -0,0 +1,65 @@ +/* + * This file contains the configuration parameters for the dbau1x00 board. + */ + +#ifndef __AR7240_H +#define __AR7240_H + +#ifndef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 1 /* autoboot after x seconds */ +#endif + +#define CONFIG_MENUPROMPT "Hit any key to stop autobooting: %2d " +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in:\t%d s (type 'tpl' to run U-Boot console)\n\n" +#define CONFIG_AUTOBOOT_STOP_STR "tpl" +#undef CONFIG_AUTOBOOT_DELAY_STR +#define DEBUG_BOOTKEYS 0 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200} + +/* + * Miscellaneous configurable options + */ +#define CFG_ALT_MEMTEST +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 512 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size, was: def + 16 */ +#define CFG_MAXARGS 16 /* max number of command */ +#define CFG_MALLOC_LEN 512*1024 // def: 128*1024 +#define CFG_BOOTPARAMS_LEN 512*1024 // def: 128 +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ +#define CFG_MEMTEST_START 0x80200000 +#define CFG_MEMTEST_END 0x83800000 +#define CFG_RX_ETH_BUFFER 16 + +/* + ** PLL Config for different CPU/DDR/AHB frequencies + */ +#define CFG_PLL_400_400_200 1 +#define CFG_PLL_412_412_206 2 +#define CFG_PLL_425_425_212 3 +#define CFG_PLL_437_437_218 4 +#define CFG_PLL_450_450_225 5 +#define CFG_PLL_462_462_231 6 +#define CFG_PLL_475_475_237 7 +#define CFG_PLL_487_487_243 8 +#define CFG_PLL_500_500_250 9 +#define CFG_PLL_500_250_250 10 +#define CFG_PLL_562_281_140 11 +#define CFG_PLL_525_262_131 12 + +// WASP +#define CFG_PLL_566_400_200 0x31 +#define CFG_PLL_566_500_250 0x32 +#define CFG_PLL_600_1_2G_400_200 0x33 +#define CFG_PLL_560_480_240 0x34 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_ICACHE_SIZE 65536 +#define CFG_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ diff --git a/u-boot/include/configs/db12x.h b/u-boot/include/configs/db12x.h new file mode 100755 index 0000000..9c8795c --- /dev/null +++ b/u-boot/include/configs/db12x.h @@ -0,0 +1,186 @@ +/* + * This file contains the configuration parameters for the DB12x (AR9344) board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash +/* + * We boot from this flash + */ +#define CFG_FLASH_BASE 0x9F000000 +#ifdef COMPRESSED_UBOOT + #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE + #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE +#endif + +/* + * The following #defines are needed to get flash environment right + */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +/* + * Default bootargs + */ +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)" + +/* + * Other env default values + */ +#undef CONFIG_BOOTFILE +#define CONFIG_BOOTFILE "firmware.bin" + +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x80800000 + +#define CFG_LOAD_ADDR 0x9F020000 +#define CONFIG_BOOTCOMMAND "bootm 0x9F020000" + + +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.2 + +#undef CFG_PLL_FREQ +#undef CFG_HZ + +// CPU-RAM-AHB frequency setting +#define CFG_PLL_FREQ CFG_PLL_560_480_240 +#define CFG_HZ (560000000LU/2) +#define AR7240_SPI_CONTROL 0x42 +/* + * MIPS32 24K Processor Core Family Software User's Manual + * + * 6.2.9 Count Register (CP0 Register 9, Select 0) + * The Count register acts as a timer, incrementing at a constant + * rate, whether or not an instruction is executed, retired, or + * any forward progress is made through the pipeline. The counter + * increments every other clock, if the DC bit in the Cause register + * is 0. + * + * Since the count is incremented every other tick, divide by 2 + * XXX derive this from CFG_PLL_FREQ + */ + +/* + * Cache lock for stack + */ +#define CFG_INIT_SP_OFFSET 0x1000 + +/* + * Address and size of Primary Environment Sector + */ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_NOWHERE 1 + +#define CFG_ENV_ADDR 0x9F040000 +#define CFG_ENV_SIZE 0x10000 + +/* + * Available commands + */ +#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_NET) + +// Enable NetConsole and custom NetConsole port +#define CONFIG_NETCONSOLE +#define CONFIG_NETCONSOLE_PORT 6666 + +/* DDR init values */ +#define CONFIG_NR_DRAM_BANKS 2 + +/* DDR settings for WASP */ +#define CFG_DDR_REFRESH_VAL 0x4270 +#define CFG_DDR_CONFIG_VAL 0xc7bc8cd0 +#define CFG_DDR_MODE_VAL_INIT 0x133 +#define CFG_DDR_EXT_MODE_VAL 0x0 +#define CFG_DDR_MODE_VAL 0x33 +#define CFG_DDR_TRTW_VAL 0x1f +#define CFG_DDR_TWTR_VAL 0x1e +#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 + +#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff +#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff + +#if DDR2_32BIT_SUPPORT + #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 +#else + #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 +#endif + +#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL 0xffff +#define CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL 0xffffffff + +/* DDR2 Init values */ +#define CFG_DDR2_EXT_MODE_VAL 0x402 + +#define CONFIG_NET_MULTI + +#ifdef CFG_ATHRS27_PHY + /* use eth1(LAN) as the net interface */ + #define CONFIG_AG7240_SPEPHY +#endif + +#define CONFIG_PCI 1 + +/* + * Web Failsafe configuration + */ +#define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR +#define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE + +// Firmware partition offset +#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000 + +// U-Boot partition size +#define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (64 * 1024) + +// ART partition size +#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024) + +// max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES) +// TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART) +#define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) + +// progress state info +#define WEBFAILSAFE_PROGRESS_START 0 +#define WEBFAILSAFE_PROGRESS_TIMEOUT 1 +#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2 +#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3 +#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4 + +// update type +#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0 +#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1 +#define WEBFAILSAFE_UPGRADE_TYPE_ART 2 + +/*-----------------------------------------------------------------------*/ + +/* For Merlin, both PCI, PCI-E interfaces are valid */ +#define AR7240_ART_PCICFG_OFFSET 12 + +#define WLANCAL 0x9fff1000 +#define CFG_MII0_RMII 1 +#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */ + +#undef DEBUG +#define milisecdelay(_x) udelay((_x) * 1000) + +/* MAC address, model and PIN number offsets in FLASH */ +#define OFFSET_MAC_DATA_BLOCK 0x010000 +#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 +#define OFFSET_MAC_ADDRESS 0x00FC00 +#define OFFSET_ROUTER_MODEL 0x00FD00 +#define OFFSET_PIN_NUMBER 0x00FE00 + +#include + +#endif /* __CONFIG_H */ diff --git a/u-boot/include/console.h b/u-boot/include/console.h new file mode 100755 index 0000000..06ec32a --- /dev/null +++ b/u-boot/include/console.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CONSOLE_H_ +#define _CONSOLE_H_ + +#include + +/* +** VARIABLES +*/ + +extern device_t *stdio_devices[] ; +extern char *stdio_names[MAX_FILES] ; + +int console_realloc(int top); + +#endif diff --git a/u-boot/include/crc.h b/u-boot/include/crc.h new file mode 100755 index 0000000..63399bf --- /dev/null +++ b/u-boot/include/crc.h @@ -0,0 +1,101 @@ +//========================================================================== +// +// crc.h +// +// Interface for the CRC algorithms. +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2002 Andrew Lunn +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Andrew Lunn +// Contributors: Andrew Lunn +// Date: 2002-08-06 +// Purpose: +// Description: +// +// This code is part of eCos (tm). +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#ifndef _SERVICES_CRC_CRC_H_ +#define _SERVICES_CRC_CRC_H_ + +#include + +#ifndef __externC +# ifdef __cplusplus +# define __externC extern "C" +# else +# define __externC extern +# endif +#endif + +// Compute a CRC, using the POSIX 1003 definition +extern uint32_t +cyg_posix_crc32(unsigned char *s, int len); + +// Gary S. Brown's 32 bit CRC + +extern uint32_t +cyg_crc32(unsigned char *s, int len); + +// Gary S. Brown's 32 bit CRC, but accumulate the result from a +// previous CRC calculation + +extern uint32_t +cyg_crc32_accumulate(uint32_t crc, unsigned char *s, int len); + +// Ethernet FCS Algorithm + +extern uint32_t +cyg_ether_crc32(unsigned char *s, int len); + +// Ethernet FCS algorithm, but accumulate the result from a previous +// CRC calculation. + +extern uint32_t +cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len); + +// 16 bit CRC with polynomial x^16+x^12+x^5+1 + +extern uint16_t cyg_crc16(unsigned char *s, int len); + +#endif // _SERVICES_CRC_CRC_H_ + + + diff --git a/u-boot/include/devices.h b/u-boot/include/devices.h new file mode 100755 index 0000000..2d9e282 --- /dev/null +++ b/u-boot/include/devices.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifndef _DEVICES_H_ +#define _DEVICES_H_ + +/* + * CONSOLE DEVICES + */ + +#define DEV_FLAGS_INPUT 0x00000001 /* Device can be used as input console */ +#define DEV_FLAGS_OUTPUT 0x00000002 /* Device can be used as output console */ +#define DEV_FLAGS_SYSTEM 0x80000000 /* Device is a system device */ +#define DEV_EXT_VIDEO 0x00000001 /* Video extensions supported */ + +/* Device information */ +typedef struct { + int flags; /* Device flags: input/output/system */ + int ext; /* Supported extensions */ + char name[16]; /* Device name */ + +/* GENERAL functions */ + + int (*start) (void); /* To start the device */ + int (*stop) (void); /* To stop the device */ + +/* OUTPUT functions */ + + void (*putc) (const char c); /* To put a char */ + void (*puts) (const char *s); /* To put a string (accelerator) */ + +/* INPUT functions */ + + int (*tstc) (void); /* To test if a char is ready... */ + int (*getc) (void); /* To get that char */ + +/* Other functions */ + + void *priv; /* Private extensions */ +} device_t; + +/* + * VIDEO EXTENSIONS + */ +#define VIDEO_FORMAT_RGB_INDEXED 0x0000 +#define VIDEO_FORMAT_RGB_DIRECTCOLOR 0x0001 +#define VIDEO_FORMAT_YUYV_4_4_4 0x0010 +#define VIDEO_FORMAT_YUYV_4_2_2 0x0011 + +typedef struct { + void *address; /* Address of framebuffer */ + ushort width; /* Horizontal resolution */ + ushort height; /* Vertical resolution */ + uchar format; /* Format */ + uchar colors; /* Colors number or color depth */ + void (*setcolreg) (int, int, int, int); + void (*getcolreg) (int, void *); +} video_ext_t; + +/* + * VARIABLES + */ +extern list_t devlist; +extern device_t *stdio_devices[]; +extern char *stdio_names[MAX_FILES]; + +/* + * PROTOTYPES + */ +int device_register (device_t * dev); +int devices_init (void); +int devices_done (void); +int device_deregister(char *devname); +#ifdef CONFIG_LCD +int drv_lcd_init (void); +#endif +#ifdef CONFIG_VFD +int drv_vfd_init (void); +#endif +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +int drv_video_init (void); +#endif +#ifdef CONFIG_KEYBOARD +int drv_keyboard_init (void); +#endif +#ifdef CONFIG_USB_TTY +int drv_usbtty_init (void); +#endif +#ifdef CONFIG_NETCONSOLE +int drv_nc_init (void); +#endif + +#endif /* _DEVICES_H_ */ diff --git a/u-boot/include/environment.h b/u-boot/include/environment.h new file mode 100755 index 0000000..8aa6590 --- /dev/null +++ b/u-boot/include/environment.h @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ENVIRONMENT_H_ +#define _ENVIRONMENT_H_ 1 + +/************************************************************************** + * + * The "environment" is stored as a list of '\0' terminated + * "name=value" strings. The end of the list is marked by a double + * '\0'. New entries are always added at the end. Deleting an entry + * shifts the remaining entries to the front. Replacing an entry is a + * combination of deleting the old value and adding the new one. + * + * The environment is preceeded by a 32 bit CRC over the data part. + * + ************************************************************************** + */ + +#if defined(CFG_ENV_IS_IN_FLASH) + #ifndef CFG_ENV_ADDR + #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) + #endif + + #ifndef CFG_ENV_OFFSET + #define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) + #endif + + #if !defined(CFG_ENV_ADDR_REDUND) && defined(CFG_ENV_OFFSET_REDUND) + #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + CFG_ENV_OFFSET_REDUND) + #endif + + #if defined(CFG_ENV_SECT_SIZE) || defined(CFG_ENV_SIZE) + #ifndef CFG_ENV_SECT_SIZE + #define CFG_ENV_SECT_SIZE CFG_ENV_SIZE + #endif + + #ifndef CFG_ENV_SIZE + #define CFG_ENV_SIZE CFG_ENV_SECT_SIZE + #endif + #else + #error "Both CFG_ENV_SECT_SIZE and CFG_ENV_SIZE undefined" + #endif + + #if defined(CFG_ENV_ADDR_REDUND) && !defined(CFG_ENV_SIZE_REDUND) + #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + #endif + + #if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define ENV_IS_EMBEDDED 1 + #endif + + #if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND) + #define CFG_REDUNDAND_ENVIRONMENT 1 + #endif +#endif /* CFG_ENV_IS_IN_FLASH */ + +#if defined(CFG_ENV_IS_IN_NAND) +# ifndef CFG_ENV_OFFSET +# error "Need to define CFG_ENV_OFFSET when using CFG_ENV_IS_IN_NAND" +# endif +# ifndef CFG_ENV_SIZE +# error "Need to define CFG_ENV_SIZE when using CFG_ENV_IS_IN_NAND" +# endif +# ifdef CFG_ENV_OFFSET_REDUND +# define CFG_REDUNDAND_ENVIRONMENT +# endif +#endif /* CFG_ENV_IS_IN_NAND */ + + +#ifdef CFG_REDUNDAND_ENVIRONMENT +# define ENV_HEADER_SIZE (sizeof(unsigned long) + 1) +#else +# define ENV_HEADER_SIZE (sizeof(unsigned long)) +#endif + + +#define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE) + +typedef struct environment_s { + unsigned long crc; /* CRC32 over data bytes */ +#ifdef CFG_REDUNDAND_ENVIRONMENT + unsigned char flags; /* active/obsolete flags */ +#endif + unsigned char data[ENV_SIZE]; /* Environment data */ +} env_t; + +#endif /* _ENVIRONMENT_H_ */ diff --git a/u-boot/include/exports.h b/u-boot/include/exports.h new file mode 100755 index 0000000..9598449 --- /dev/null +++ b/u-boot/include/exports.h @@ -0,0 +1,51 @@ +#ifndef __EXPORTS_H__ +#define __EXPORTS_H__ + +#ifndef __ASSEMBLY__ + +#include + +/* These are declarations of exported functions available in C code */ +unsigned long get_version(void); +int getc(void); +int tstc(void); +void putc(const char); +void puts(const char*); +void printf(const char* fmt, ...); +void install_hdlr(int, interrupt_handler_t*, void*); +void free_hdlr(int); +void *malloc(size_t); +void free(void*); +void udelay(unsigned long); +unsigned long get_timer(unsigned long); +void do_reset(void); +void app_startup(char **); + +#endif /* ifndef __ASSEMBLY__ */ + +enum { +#define EXPORT_FUNC(x) XF_ ## x , +EXPORT_FUNC(get_version) +EXPORT_FUNC(getc) +EXPORT_FUNC(tstc) +EXPORT_FUNC(putc) +EXPORT_FUNC(puts) +EXPORT_FUNC(printf) +EXPORT_FUNC(install_hdlr) +EXPORT_FUNC(free_hdlr) +EXPORT_FUNC(malloc) +EXPORT_FUNC(free) +EXPORT_FUNC(udelay) +EXPORT_FUNC(get_timer) +EXPORT_FUNC(do_reset) +#undef EXPORT_FUNC +XF_MAX +}; + +#define XF_VERSION 2 + +#if defined(CONFIG_I386) +extern gd_t *global_data; +#endif + +#endif /* __EXPORTS_H__ */ diff --git a/u-boot/include/flash.h b/u-boot/include/flash.h new file mode 100755 index 0000000..f63a360 --- /dev/null +++ b/u-boot/include/flash.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FLASH_H_ +#define _FLASH_H_ + +#ifndef CFG_NO_FLASH +/*----------------------------------------------------------------------- + * FLASH Info: contains chip specific data, per FLASH bank + */ + +typedef struct { + ulong size; /* total bank size in bytes */ + ulong sector_size; /* size of erase unit in bytes */ + ushort sector_count; /* number of erase units */ + ulong flash_id; /* combined device & manufacturer code */ + ulong start[CFG_MAX_FLASH_SECT]; /* physical sector start addresses */ + uchar protect[CFG_MAX_FLASH_SECT]; /* sector protection status */ +} flash_info_t; + + +/* Prototypes */ +extern unsigned long flash_init (void); +extern int flash_erase(flash_info_t *, int, int); +extern int flash_sect_erase(ulong addr_first, ulong addr_last); +extern int flash_sect_protect(int flag, ulong addr_first, ulong addr_last); + +/* common/flash.c */ +extern int flash_write(char *, ulong, ulong); +extern flash_info_t *addr2info(ulong); +extern int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt); + +/*----------------------------------------------------------------------- + * return codes from flash_write(): + */ +#define ERR_OK 0 +#define ERR_TIMOUT 1 +#define ERR_NOT_ERASED 2 +#define ERR_PROTECTED 4 +#define ERR_INVAL 8 +#define ERR_ALIGN 16 +#define ERR_UNKNOWN_FLASH_VENDOR 32 +#define ERR_UNKNOWN_FLASH_TYPE 64 +#define ERR_PROG_ERROR 128 + +/*----------------------------------------------------------------------- + * Device IDs + */ +#define FLASH_CUSTOM 0x1111 +#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ + +#endif /* !CFG_NO_FLASH */ + +#endif /* _FLASH_H_ */ diff --git a/u-boot/include/hornet_soc.h b/u-boot/include/hornet_soc.h new file mode 100755 index 0000000..b57e820 --- /dev/null +++ b/u-boot/include/hornet_soc.h @@ -0,0 +1,293 @@ +/* + * Atheror Hornet series processor SOC registers + * + * (C) Copyright 2010 Atheros Communications, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _HORNET_SOC_H +#define _HORNET_SOC_H +#include +#include + +/* + * UART block + */ +// 0x0000 (UARTDATA) +#define UARTDATA_UARTTXCSR_MSB 9 +#define UARTDATA_UARTTXCSR_LSB 9 +#define UARTDATA_UARTTXCSR_MASK 0x00000200 +#define UARTDATA_UARTTXCSR_GET(x) (((x) & UARTDATA_UARTTXCSR_MASK) >> UARTDATA_UARTTXCSR_LSB) +#define UARTDATA_UARTTXCSR_SET(x) (((0 | (x)) << UARTDATA_UARTTXCSR_LSB) & UARTDATA_UARTTXCSR_MASK) +#define UARTDATA_UARTTXCSR_RESET 0 +#define UARTDATA_UARTRXCSR_MSB 8 +#define UARTDATA_UARTRXCSR_LSB 8 +#define UARTDATA_UARTRXCSR_MASK 0x00000100 +#define UARTDATA_UARTRXCSR_GET(x) (((x) & UARTDATA_UARTRXCSR_MASK) >> UARTDATA_UARTRXCSR_LSB) +#define UARTDATA_UARTRXCSR_SET(x) (((0 | (x)) << UARTDATA_UARTRXCSR_LSB) & UARTDATA_UARTRXCSR_MASK) +#define UARTDATA_UARTRXCSR_RESET 0 +#define UARTDATA_UARTTXRXDATA_MSB 7 +#define UARTDATA_UARTTXRXDATA_LSB 0 +#define UARTDATA_UARTTXRXDATA_MASK 0x000000ff +#define UARTDATA_UARTTXRXDATA_GET(x) (((x) & UARTDATA_UARTTXRXDATA_MASK) >> UARTDATA_UARTTXRXDATA_LSB) +#define UARTDATA_UARTTXRXDATA_SET(x) (((0 | (x)) << UARTDATA_UARTTXRXDATA_LSB) & UARTDATA_UARTTXRXDATA_MASK) +#define UARTDATA_UARTTXRXDATA_RESET 0 +#define UARTDATA_ADDRESS 0x0000 +#define UARTDATA_HW_MASK 0x000003ff +#define UARTDATA_SW_MASK 0x000003ff +#define UARTDATA_RSTMASK 0x000003ff +#define UARTDATA_RESET 0x00000000 + +// 0x0004 (UARTCS) +#define UARTCS_UARTRXBUSY_MSB 15 +#define UARTCS_UARTRXBUSY_LSB 15 +#define UARTCS_UARTRXBUSY_MASK 0x00008000 +#define UARTCS_UARTRXBUSY_GET(x) (((x) & UARTCS_UARTRXBUSY_MASK) >> UARTCS_UARTRXBUSY_LSB) +#define UARTCS_UARTRXBUSY_SET(x) (((0 | (x)) << UARTCS_UARTRXBUSY_LSB) & UARTCS_UARTRXBUSY_MASK) +#define UARTCS_UARTRXBUSY_RESET 0 +#define UARTCS_UARTTXBUSY_MSB 14 +#define UARTCS_UARTTXBUSY_LSB 14 +#define UARTCS_UARTTXBUSY_MASK 0x00004000 +#define UARTCS_UARTTXBUSY_GET(x) (((x) & UARTCS_UARTTXBUSY_MASK) >> UARTCS_UARTTXBUSY_LSB) +#define UARTCS_UARTTXBUSY_SET(x) (((0 | (x)) << UARTCS_UARTTXBUSY_LSB) & UARTCS_UARTTXBUSY_MASK) +#define UARTCS_UARTTXBUSY_RESET 0 +#define UARTCS_UARTHOSTINTEN_MSB 13 +#define UARTCS_UARTHOSTINTEN_LSB 13 +#define UARTCS_UARTHOSTINTEN_MASK 0x00002000 +#define UARTCS_UARTHOSTINTEN_GET(x) (((x) & UARTCS_UARTHOSTINTEN_MASK) >> UARTCS_UARTHOSTINTEN_LSB) +#define UARTCS_UARTHOSTINTEN_SET(x) (((0 | (x)) << UARTCS_UARTHOSTINTEN_LSB) & UARTCS_UARTHOSTINTEN_MASK) +#define UARTCS_UARTHOSTINTEN_RESET 0 +#define UARTCS_UARTHOSTINT_MSB 12 +#define UARTCS_UARTHOSTINT_LSB 12 +#define UARTCS_UARTHOSTINT_MASK 0x00001000 +#define UARTCS_UARTHOSTINT_GET(x) (((x) & UARTCS_UARTHOSTINT_MASK) >> UARTCS_UARTHOSTINT_LSB) +#define UARTCS_UARTHOSTINT_SET(x) (((0 | (x)) << UARTCS_UARTHOSTINT_LSB) & UARTCS_UARTHOSTINT_MASK) +#define UARTCS_UARTHOSTINT_RESET 0 +#define UARTCS_UARTTXBREAK_MSB 11 +#define UARTCS_UARTTXBREAK_LSB 11 +#define UARTCS_UARTTXBREAK_MASK 0x00000800 +#define UARTCS_UARTTXBREAK_GET(x) (((x) & UARTCS_UARTTXBREAK_MASK) >> UARTCS_UARTTXBREAK_LSB) +#define UARTCS_UARTTXBREAK_SET(x) (((0 | (x)) << UARTCS_UARTTXBREAK_LSB) & UARTCS_UARTTXBREAK_MASK) +#define UARTCS_UARTTXBREAK_RESET 0 +#define UARTCS_UARTRXBREAK_MSB 10 +#define UARTCS_UARTRXBREAK_LSB 10 +#define UARTCS_UARTRXBREAK_MASK 0x00000400 +#define UARTCS_UARTRXBREAK_GET(x) (((x) & UARTCS_UARTRXBREAK_MASK) >> UARTCS_UARTRXBREAK_LSB) +#define UARTCS_UARTRXBREAK_SET(x) (((0 | (x)) << UARTCS_UARTRXBREAK_LSB) & UARTCS_UARTRXBREAK_MASK) +#define UARTCS_UARTRXBREAK_RESET 0 +#define UARTCS_UARTSERIATXREADY_MSB 9 +#define UARTCS_UARTSERIATXREADY_LSB 9 +#define UARTCS_UARTSERIATXREADY_MASK 0x00000200 +#define UARTCS_UARTSERIATXREADY_GET(x) (((x) & UARTCS_UARTSERIATXREADY_MASK) >> UARTCS_UARTSERIATXREADY_LSB) +#define UARTCS_UARTSERIATXREADY_SET(x) (((0 | (x)) << UARTCS_UARTSERIATXREADY_LSB) & UARTCS_UARTSERIATXREADY_MASK) +#define UARTCS_UARTSERIATXREADY_RESET 0 +#define UARTCS_UARTTXREADYORIDE_MSB 8 +#define UARTCS_UARTTXREADYORIDE_LSB 8 +#define UARTCS_UARTTXREADYORIDE_MASK 0x00000100 +#define UARTCS_UARTTXREADYORIDE_GET(x) (((x) & UARTCS_UARTTXREADYORIDE_MASK) >> UARTCS_UARTTXREADYORIDE_LSB) +#define UARTCS_UARTTXREADYORIDE_SET(x) (((0 | (x)) << UARTCS_UARTTXREADYORIDE_LSB) & UARTCS_UARTTXREADYORIDE_MASK) +#define UARTCS_UARTTXREADYORIDE_RESET 0 +#define UARTCS_UARTRXREADYORIDE_MSB 7 +#define UARTCS_UARTRXREADYORIDE_LSB 7 +#define UARTCS_UARTRXREADYORIDE_MASK 0x00000080 +#define UARTCS_UARTRXREADYORIDE_GET(x) (((x) & UARTCS_UARTRXREADYORIDE_MASK) >> UARTCS_UARTRXREADYORIDE_LSB) +#define UARTCS_UARTRXREADYORIDE_SET(x) (((0 | (x)) << UARTCS_UARTRXREADYORIDE_LSB) & UARTCS_UARTRXREADYORIDE_MASK) +#define UARTCS_UARTRXREADYORIDE_RESET 0 +#define UARTCS_UARTDMAEN_MSB 6 +#define UARTCS_UARTDMAEN_LSB 6 +#define UARTCS_UARTDMAEN_MASK 0x00000040 +#define UARTCS_UARTDMAEN_GET(x) (((x) & UARTCS_UARTDMAEN_MASK) >> UARTCS_UARTDMAEN_LSB) +#define UARTCS_UARTDMAEN_SET(x) (((0 | (x)) << UARTCS_UARTDMAEN_LSB) & UARTCS_UARTDMAEN_MASK) +#define UARTCS_UARTDMAEN_RESET 0 +#define UARTCS_UARTFLOWCONTROLMODE_MSB 5 +#define UARTCS_UARTFLOWCONTROLMODE_LSB 4 +#define UARTCS_UARTFLOWCONTROLMODE_MASK 0x00000030 +#define UARTCS_UARTFLOWCONTROLMODE_GET(x) (((x) & UARTCS_UARTFLOWCONTROLMODE_MASK) >> UARTCS_UARTFLOWCONTROLMODE_LSB) +#define UARTCS_UARTFLOWCONTROLMODE_SET(x) (((0 | (x)) << UARTCS_UARTFLOWCONTROLMODE_LSB) & UARTCS_UARTFLOWCONTROLMODE_MASK) +#define UARTCS_UARTFLOWCONTROLMODE_RESET 0 +#define UARTCS_UARTINTERFACEMODE_MSB 3 +#define UARTCS_UARTINTERFACEMODE_LSB 2 +#define UARTCS_UARTINTERFACEMODE_MASK 0x0000000c +#define UARTCS_UARTINTERFACEMODE_GET(x) (((x) & UARTCS_UARTINTERFACEMODE_MASK) >> UARTCS_UARTINTERFACEMODE_LSB) +#define UARTCS_UARTINTERFACEMODE_SET(x) (((0 | (x)) << UARTCS_UARTINTERFACEMODE_LSB) & UARTCS_UARTINTERFACEMODE_MASK) +#define UARTCS_UARTINTERFACEMODE_RESET 0 +#define UARTCS_UARTPARITYMODE_MSB 1 +#define UARTCS_UARTPARITYMODE_LSB 0 +#define UARTCS_UARTPARITYMODE_MASK 0x00000003 +#define UARTCS_UARTPARITYMODE_GET(x) (((x) & UARTCS_UARTPARITYMODE_MASK) >> UARTCS_UARTPARITYMODE_LSB) +#define UARTCS_UARTPARITYMODE_SET(x) (((0 | (x)) << UARTCS_UARTPARITYMODE_LSB) & UARTCS_UARTPARITYMODE_MASK) +#define UARTCS_UARTPARITYMODE_RESET 0 +#define UARTCS_ADDRESS 0x0004 +#define UARTCS_HW_MASK 0x0000ffff +#define UARTCS_SW_MASK 0x0000ffff +#define UARTCS_RSTMASK 0x000029ff +#define UARTCS_RESET 0x00000000 + +// 0x0008 (UARTCLOCK) +#define UARTCLOCK_UARTCLOCKSCALE_MSB 23 +#define UARTCLOCK_UARTCLOCKSCALE_LSB 16 +#define UARTCLOCK_UARTCLOCKSCALE_MASK 0x00ff0000 +#define UARTCLOCK_UARTCLOCKSCALE_GET(x) (((x) & UARTCLOCK_UARTCLOCKSCALE_MASK) >> UARTCLOCK_UARTCLOCKSCALE_LSB) +#define UARTCLOCK_UARTCLOCKSCALE_SET(x) (((0 | (x)) << UARTCLOCK_UARTCLOCKSCALE_LSB) & UARTCLOCK_UARTCLOCKSCALE_MASK) +#define UARTCLOCK_UARTCLOCKSCALE_RESET 0 +#define UARTCLOCK_UARTCLOCKSTEP_MSB 15 +#define UARTCLOCK_UARTCLOCKSTEP_LSB 0 +#define UARTCLOCK_UARTCLOCKSTEP_MASK 0x0000ffff +#define UARTCLOCK_UARTCLOCKSTEP_GET(x) (((x) & UARTCLOCK_UARTCLOCKSTEP_MASK) >> UARTCLOCK_UARTCLOCKSTEP_LSB) +#define UARTCLOCK_UARTCLOCKSTEP_SET(x) (((0 | (x)) << UARTCLOCK_UARTCLOCKSTEP_LSB) & UARTCLOCK_UARTCLOCKSTEP_MASK) +#define UARTCLOCK_UARTCLOCKSTEP_RESET 0 +#define UARTCLOCK_ADDRESS 0x0008 +#define UARTCLOCK_HW_MASK 0x00ffffff +#define UARTCLOCK_SW_MASK 0x00ffffff +#define UARTCLOCK_RSTMASK 0x00ffffff +#define UARTCLOCK_RESET 0x00000000 + +// 0x000c (UARTINT) +#define UARTINT_UARTTXEMPTYINT_MSB 9 +#define UARTINT_UARTTXEMPTYINT_LSB 9 +#define UARTINT_UARTTXEMPTYINT_MASK 0x00000200 +#define UARTINT_UARTTXEMPTYINT_GET(x) (((x) & UARTINT_UARTTXEMPTYINT_MASK) >> UARTINT_UARTTXEMPTYINT_LSB) +#define UARTINT_UARTTXEMPTYINT_SET(x) (((0 | (x)) << UARTINT_UARTTXEMPTYINT_LSB) & UARTINT_UARTTXEMPTYINT_MASK) +#define UARTINT_UARTTXEMPTYINT_RESET 0 +#define UARTINT_UARTRXFULLINT_MSB 8 +#define UARTINT_UARTRXFULLINT_LSB 8 +#define UARTINT_UARTRXFULLINT_MASK 0x00000100 +#define UARTINT_UARTRXFULLINT_GET(x) (((x) & UARTINT_UARTRXFULLINT_MASK) >> UARTINT_UARTRXFULLINT_LSB) +#define UARTINT_UARTRXFULLINT_SET(x) (((0 | (x)) << UARTINT_UARTRXFULLINT_LSB) & UARTINT_UARTRXFULLINT_MASK) +#define UARTINT_UARTRXFULLINT_RESET 0 +#define UARTINT_UARTRXBREAKOFFINT_MSB 7 +#define UARTINT_UARTRXBREAKOFFINT_LSB 7 +#define UARTINT_UARTRXBREAKOFFINT_MASK 0x00000080 +#define UARTINT_UARTRXBREAKOFFINT_GET(x) (((x) & UARTINT_UARTRXBREAKOFFINT_MASK) >> UARTINT_UARTRXBREAKOFFINT_LSB) +#define UARTINT_UARTRXBREAKOFFINT_SET(x) (((0 | (x)) << UARTINT_UARTRXBREAKOFFINT_LSB) & UARTINT_UARTRXBREAKOFFINT_MASK) +#define UARTINT_UARTRXBREAKOFFINT_RESET 0 +#define UARTINT_UARTRXBREAKONINT_MSB 6 +#define UARTINT_UARTRXBREAKONINT_LSB 6 +#define UARTINT_UARTRXBREAKONINT_MASK 0x00000040 +#define UARTINT_UARTRXBREAKONINT_GET(x) (((x) & UARTINT_UARTRXBREAKONINT_MASK) >> UARTINT_UARTRXBREAKONINT_LSB) +#define UARTINT_UARTRXBREAKONINT_SET(x) (((0 | (x)) << UARTINT_UARTRXBREAKONINT_LSB) & UARTINT_UARTRXBREAKONINT_MASK) +#define UARTINT_UARTRXBREAKONINT_RESET 0 +#define UARTINT_UARTRXPARITYERRINT_MSB 5 +#define UARTINT_UARTRXPARITYERRINT_LSB 5 +#define UARTINT_UARTRXPARITYERRINT_MASK 0x00000020 +#define UARTINT_UARTRXPARITYERRINT_GET(x) (((x) & UARTINT_UARTRXPARITYERRINT_MASK) >> UARTINT_UARTRXPARITYERRINT_LSB) +#define UARTINT_UARTRXPARITYERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXPARITYERRINT_LSB) & UARTINT_UARTRXPARITYERRINT_MASK) +#define UARTINT_UARTRXPARITYERRINT_RESET 0 +#define UARTINT_UARTTXOFLOWERRINT_MSB 4 +#define UARTINT_UARTTXOFLOWERRINT_LSB 4 +#define UARTINT_UARTTXOFLOWERRINT_MASK 0x00000010 +#define UARTINT_UARTTXOFLOWERRINT_GET(x) (((x) & UARTINT_UARTTXOFLOWERRINT_MASK) >> UARTINT_UARTTXOFLOWERRINT_LSB) +#define UARTINT_UARTTXOFLOWERRINT_SET(x) (((0 | (x)) << UARTINT_UARTTXOFLOWERRINT_LSB) & UARTINT_UARTTXOFLOWERRINT_MASK) +#define UARTINT_UARTTXOFLOWERRINT_RESET 0 +#define UARTINT_UARTRXOFLOWERRINT_MSB 3 +#define UARTINT_UARTRXOFLOWERRINT_LSB 3 +#define UARTINT_UARTRXOFLOWERRINT_MASK 0x00000008 +#define UARTINT_UARTRXOFLOWERRINT_GET(x) (((x) & UARTINT_UARTRXOFLOWERRINT_MASK) >> UARTINT_UARTRXOFLOWERRINT_LSB) +#define UARTINT_UARTRXOFLOWERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXOFLOWERRINT_LSB) & UARTINT_UARTRXOFLOWERRINT_MASK) +#define UARTINT_UARTRXOFLOWERRINT_RESET 0 +#define UARTINT_UARTRXFRAMINGERRINT_MSB 2 +#define UARTINT_UARTRXFRAMINGERRINT_LSB 2 +#define UARTINT_UARTRXFRAMINGERRINT_MASK 0x00000004 +#define UARTINT_UARTRXFRAMINGERRINT_GET(x) (((x) & UARTINT_UARTRXFRAMINGERRINT_MASK) >> UARTINT_UARTRXFRAMINGERRINT_LSB) +#define UARTINT_UARTRXFRAMINGERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXFRAMINGERRINT_LSB) & UARTINT_UARTRXFRAMINGERRINT_MASK) +#define UARTINT_UARTRXFRAMINGERRINT_RESET 0 +#define UARTINT_UARTTXREADYINT_MSB 1 +#define UARTINT_UARTTXREADYINT_LSB 1 +#define UARTINT_UARTTXREADYINT_MASK 0x00000002 +#define UARTINT_UARTTXREADYINT_GET(x) (((x) & UARTINT_UARTTXREADYINT_MASK) >> UARTINT_UARTTXREADYINT_LSB) +#define UARTINT_UARTTXREADYINT_SET(x) (((0 | (x)) << UARTINT_UARTTXREADYINT_LSB) & UARTINT_UARTTXREADYINT_MASK) +#define UARTINT_UARTTXREADYINT_RESET 0 +#define UARTINT_UARTRXVALIDINT_MSB 0 +#define UARTINT_UARTRXVALIDINT_LSB 0 +#define UARTINT_UARTRXVALIDINT_MASK 0x00000001 +#define UARTINT_UARTRXVALIDINT_GET(x) (((x) & UARTINT_UARTRXVALIDINT_MASK) >> UARTINT_UARTRXVALIDINT_LSB) +#define UARTINT_UARTRXVALIDINT_SET(x) (((0 | (x)) << UARTINT_UARTRXVALIDINT_LSB) & UARTINT_UARTRXVALIDINT_MASK) +#define UARTINT_UARTRXVALIDINT_RESET 0 +#define UARTINT_ADDRESS 0x000c +#define UARTINT_HW_MASK 0x000003ff +#define UARTINT_SW_MASK 0x000003ff +#define UARTINT_RSTMASK 0x000003ff +#define UARTINT_RESET 0x00000000 + +// 0x0010 (UARTINTEN) +#define UARTINTEN_UARTTXEMPTYINTEN_MSB 9 +#define UARTINTEN_UARTTXEMPTYINTEN_LSB 9 +#define UARTINTEN_UARTTXEMPTYINTEN_MASK 0x00000200 +#define UARTINTEN_UARTTXEMPTYINTEN_GET(x) (((x) & UARTINTEN_UARTTXEMPTYINTEN_MASK) >> UARTINTEN_UARTTXEMPTYINTEN_LSB) +#define UARTINTEN_UARTTXEMPTYINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXEMPTYINTEN_LSB) & UARTINTEN_UARTTXEMPTYINTEN_MASK) +#define UARTINTEN_UARTTXEMPTYINTEN_RESET 0 +#define UARTINTEN_UARTRXFULLINTEN_MSB 8 +#define UARTINTEN_UARTRXFULLINTEN_LSB 8 +#define UARTINTEN_UARTRXFULLINTEN_MASK 0x00000100 +#define UARTINTEN_UARTRXFULLINTEN_GET(x) (((x) & UARTINTEN_UARTRXFULLINTEN_MASK) >> UARTINTEN_UARTRXFULLINTEN_LSB) +#define UARTINTEN_UARTRXFULLINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXFULLINTEN_LSB) & UARTINTEN_UARTRXFULLINTEN_MASK) +#define UARTINTEN_UARTRXFULLINTEN_RESET 0 +#define UARTINTEN_UARTRXBREAKOFFINTEN_MSB 7 +#define UARTINTEN_UARTRXBREAKOFFINTEN_LSB 7 +#define UARTINTEN_UARTRXBREAKOFFINTEN_MASK 0x00000080 +#define UARTINTEN_UARTRXBREAKOFFINTEN_GET(x) (((x) & UARTINTEN_UARTRXBREAKOFFINTEN_MASK) >> UARTINTEN_UARTRXBREAKOFFINTEN_LSB) +#define UARTINTEN_UARTRXBREAKOFFINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXBREAKOFFINTEN_LSB) & UARTINTEN_UARTRXBREAKOFFINTEN_MASK) +#define UARTINTEN_UARTRXBREAKOFFINTEN_RESET 0 +#define UARTINTEN_UARTRXBREAKONINTEN_MSB 6 +#define UARTINTEN_UARTRXBREAKONINTEN_LSB 6 +#define UARTINTEN_UARTRXBREAKONINTEN_MASK 0x00000040 +#define UARTINTEN_UARTRXBREAKONINTEN_GET(x) (((x) & UARTINTEN_UARTRXBREAKONINTEN_MASK) >> UARTINTEN_UARTRXBREAKONINTEN_LSB) +#define UARTINTEN_UARTRXBREAKONINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXBREAKONINTEN_LSB) & UARTINTEN_UARTRXBREAKONINTEN_MASK) +#define UARTINTEN_UARTRXBREAKONINTEN_RESET 0 +#define UARTINTEN_UARTRXPARITYERRINTEN_MSB 5 +#define UARTINTEN_UARTRXPARITYERRINTEN_LSB 5 +#define UARTINTEN_UARTRXPARITYERRINTEN_MASK 0x00000020 +#define UARTINTEN_UARTRXPARITYERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXPARITYERRINTEN_MASK) >> UARTINTEN_UARTRXPARITYERRINTEN_LSB) +#define UARTINTEN_UARTRXPARITYERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXPARITYERRINTEN_LSB) & UARTINTEN_UARTRXPARITYERRINTEN_MASK) +#define UARTINTEN_UARTRXPARITYERRINTEN_RESET 0 +#define UARTINTEN_UARTTXOFLOWERRINTEN_MSB 4 +#define UARTINTEN_UARTTXOFLOWERRINTEN_LSB 4 +#define UARTINTEN_UARTTXOFLOWERRINTEN_MASK 0x00000010 +#define UARTINTEN_UARTTXOFLOWERRINTEN_GET(x) (((x) & UARTINTEN_UARTTXOFLOWERRINTEN_MASK) >> UARTINTEN_UARTTXOFLOWERRINTEN_LSB) +#define UARTINTEN_UARTTXOFLOWERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXOFLOWERRINTEN_LSB) & UARTINTEN_UARTTXOFLOWERRINTEN_MASK) +#define UARTINTEN_UARTTXOFLOWERRINTEN_RESET 0 +#define UARTINTEN_UARTRXOFLOWERRINTEN_MSB 3 +#define UARTINTEN_UARTRXOFLOWERRINTEN_LSB 3 +#define UARTINTEN_UARTRXOFLOWERRINTEN_MASK 0x00000008 +#define UARTINTEN_UARTRXOFLOWERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXOFLOWERRINTEN_MASK) >> UARTINTEN_UARTRXOFLOWERRINTEN_LSB) +#define UARTINTEN_UARTRXOFLOWERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXOFLOWERRINTEN_LSB) & UARTINTEN_UARTRXOFLOWERRINTEN_MASK) +#define UARTINTEN_UARTRXOFLOWERRINTEN_RESET 0 +#define UARTINTEN_UARTRXFRAMINGERRINTEN_MSB 2 +#define UARTINTEN_UARTRXFRAMINGERRINTEN_LSB 2 +#define UARTINTEN_UARTRXFRAMINGERRINTEN_MASK 0x00000004 +#define UARTINTEN_UARTRXFRAMINGERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXFRAMINGERRINTEN_MASK) >> UARTINTEN_UARTRXFRAMINGERRINTEN_LSB) +#define UARTINTEN_UARTRXFRAMINGERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXFRAMINGERRINTEN_LSB) & UARTINTEN_UARTRXFRAMINGERRINTEN_MASK) +#define UARTINTEN_UARTRXFRAMINGERRINTEN_RESET 0 +#define UARTINTEN_UARTTXREADYINTEN_MSB 1 +#define UARTINTEN_UARTTXREADYINTEN_LSB 1 +#define UARTINTEN_UARTTXREADYINTEN_MASK 0x00000002 +#define UARTINTEN_UARTTXREADYINTEN_GET(x) (((x) & UARTINTEN_UARTTXREADYINTEN_MASK) >> UARTINTEN_UARTTXREADYINTEN_LSB) +#define UARTINTEN_UARTTXREADYINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXREADYINTEN_LSB) & UARTINTEN_UARTTXREADYINTEN_MASK) +#define UARTINTEN_UARTTXREADYINTEN_RESET 0 +#define UARTINTEN_UARTRXVALIDINTEN_MSB 0 +#define UARTINTEN_UARTRXVALIDINTEN_LSB 0 +#define UARTINTEN_UARTRXVALIDINTEN_MASK 0x00000001 +#define UARTINTEN_UARTRXVALIDINTEN_GET(x) (((x) & UARTINTEN_UARTRXVALIDINTEN_MASK) >> UARTINTEN_UARTRXVALIDINTEN_LSB) +#define UARTINTEN_UARTRXVALIDINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXVALIDINTEN_LSB) & UARTINTEN_UARTRXVALIDINTEN_MASK) +#define UARTINTEN_UARTRXVALIDINTEN_RESET 0 +#define UARTINTEN_ADDRESS 0x0010 +#define UARTINTEN_HW_MASK 0x000003ff +#define UARTINTEN_SW_MASK 0x000003ff +#define UARTINTEN_RSTMASK 0x000003ff +#define UARTINTEN_RESET 0x00000000 + +#endif diff --git a/u-boot/include/image.h b/u-boot/include/image.h new file mode 100755 index 0000000..ad86284 --- /dev/null +++ b/u-boot/include/image.h @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __IMAGE_H__ +#define __IMAGE_H__ + +/* + * Operating System Codes + */ +#define IH_OS_INVALID 0 /* Invalid OS */ +#define IH_OS_OPENBSD 1 /* OpenBSD */ +#define IH_OS_NETBSD 2 /* NetBSD */ +#define IH_OS_FREEBSD 3 /* FreeBSD */ +#define IH_OS_4_4BSD 4 /* 4.4BSD */ +#define IH_OS_LINUX 5 /* Linux */ +#define IH_OS_SVR4 6 /* SVR4 */ +#define IH_OS_ESIX 7 /* Esix */ +#define IH_OS_SOLARIS 8 /* Solaris */ +#define IH_OS_IRIX 9 /* Irix */ +#define IH_OS_SCO 10 /* SCO */ +#define IH_OS_DELL 11 /* Dell */ +#define IH_OS_NCR 12 /* NCR */ +#define IH_OS_LYNXOS 13 /* LynxOS */ +#define IH_OS_VXWORKS 14 /* VxWorks */ +#define IH_OS_PSOS 15 /* pSOS */ +#define IH_OS_QNX 16 /* QNX */ +#define IH_OS_U_BOOT 17 /* Firmware */ +#define IH_OS_RTEMS 18 /* RTEMS */ +#define IH_OS_ARTOS 19 /* ARTOS */ +#define IH_OS_UNITY 20 /* Unity OS */ + +/* + * CPU Architecture Codes (supported by Linux) + */ +#define IH_CPU_INVALID 0 /* Invalid CPU */ +#define IH_CPU_ALPHA 1 /* Alpha */ +#define IH_CPU_ARM 2 /* ARM */ +#define IH_CPU_I386 3 /* Intel x86 */ +#define IH_CPU_IA64 4 /* IA64 */ +#define IH_CPU_MIPS 5 /* MIPS */ +#define IH_CPU_MIPS64 6 /* MIPS 64 Bit */ +#define IH_CPU_PPC 7 /* PowerPC */ +#define IH_CPU_S390 8 /* IBM S390 */ +#define IH_CPU_SH 9 /* SuperH */ +#define IH_CPU_SPARC 10 /* Sparc */ +#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */ +#define IH_CPU_M68K 12 /* M68K */ +#define IH_CPU_NIOS 13 /* Nios-32 */ +#define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ +#define IH_CPU_NIOS2 15 /* Nios-II */ +#define IH_CPU_BLACKFIN 16 /* Blackfin */ + +/* + * Image Types + * + * "Standalone Programs" are directly runnable in the environment + * provided by U-Boot; it is expected that (if they behave + * well) you can continue to work in U-Boot after return from + * the Standalone Program. + * "OS Kernel Images" are usually images of some Embedded OS which + * will take over control completely. Usually these programs + * will install their own set of exception handlers, device + * drivers, set up the MMU, etc. - this means, that you cannot + * expect to re-enter U-Boot except by resetting the CPU. + * "RAMDisk Images" are more or less just data blocks, and their + * parameters (address, size) are passed to an OS kernel that is + * being started. + * "Multi-File Images" contain several images, typically an OS + * (Linux) kernel image and one or more data images like + * RAMDisks. This construct is useful for instance when you want + * to boot over the network using BOOTP etc., where the boot + * server provides just a single image file, but you want to get + * for instance an OS kernel and a RAMDisk image. + * + * "Multi-File Images" start with a list of image sizes, each + * image size (in bytes) specified by an "uint32_t" in network + * byte order. This list is terminated by an "(uint32_t)0". + * Immediately after the terminating 0 follow the images, one by + * one, all aligned on "uint32_t" boundaries (size rounded up to + * a multiple of 4 bytes - except for the last file). + * + * "Firmware Images" are binary images containing firmware (like + * U-Boot or FPGA images) which usually will be programmed to + * flash memory. + * + * "Script files" are command sequences that will be executed by + * U-Boot's command interpreter; this feature is especially + * useful when you configure U-Boot to use a real shell (hush) + * as command interpreter (=> Shell Scripts). + */ + +#define IH_TYPE_INVALID 0 /* Invalid Image */ +#define IH_TYPE_STANDALONE 1 /* Standalone Program */ +#define IH_TYPE_KERNEL 2 /* OS Kernel Image */ +#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */ +#define IH_TYPE_MULTI 4 /* Multi-File Image */ +#define IH_TYPE_FIRMWARE 5 /* Firmware Image */ +#define IH_TYPE_SCRIPT 6 /* Script file */ +#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ + +/* + * Compression Types + */ +#define IH_COMP_NONE 0 /* No Compression Used */ +#define IH_COMP_GZIP 1 /* gzip Compression Used */ +#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ +#define IH_COMP_LZMA 3 /* lzma Compression Used */ + +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ + +/* + * all data in network byte order (aka natural aka bigendian) + */ + +typedef struct image_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +} image_header_t; + +#endif /* __IMAGE_H__ */ diff --git a/u-boot/include/ioports.h b/u-boot/include/ioports.h new file mode 100755 index 0000000..d7e19e1 --- /dev/null +++ b/u-boot/include/ioports.h @@ -0,0 +1,55 @@ +/* + * definitions for MPC8260 I/O Ports + * + * (in addition to those provided in ) + * + * Murray.Jensen@cmst.csiro.au, 20-Oct-00 + */ + +/* + * this structure mirrors the layout of the five port registers in + * the internal memory map - see iop8260_t in + */ +typedef struct { + unsigned int pdir; /* Port Data Direction Register (35-3) */ + unsigned int ppar; /* Port Pin Assignment Register (35-4) */ + unsigned int psor; /* Port Special Options Register (35-5) */ + unsigned int podr; /* Port Open Drain Register (35-2) */ + unsigned int pdat; /* Port Data Register (35-3) */ +} ioport_t; + +/* + * this macro calculates the address within the internal + * memory map (im) of the set of registers for a port (idx) + * + * the internal memory map aligns the above structure on + * a 0x20 byte boundary + */ +#ifdef CONFIG_MPC85xx +#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20)) +#else +#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) +#endif + +/* + * this structure provides configuration + * information for one port pin + */ +typedef struct { + unsigned char conf:1; /* if 1, configure this port */ + unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */ + unsigned char psor:1; /* Port Special Options Register (35-2) */ + unsigned char pdir:1; /* Port Data Direction Register (35-3) */ + unsigned char podr:1; /* Port Open Drain Register (35-2) */ + unsigned char pdat:1; /* Port Data Register (35-2) */ +} iop_conf_t; + +/* + * a table that contains configuration information for all 32 pins + * of all four MPC8260 I/O ports. + * + * NOTE: in the second dimension of this table, index 0 refers to pin 31 + * and index 31 refers to pin 0. this made the code in the table look more + * like the table in the 8260UM (and in the hymod manuals). + */ +extern const iop_conf_t iop_conf_tab[4][32]; diff --git a/u-boot/include/jffs2/jffs2.h b/u-boot/include/jffs2/jffs2.h new file mode 100755 index 0000000..16da112 --- /dev/null +++ b/u-boot/include/jffs2/jffs2.h @@ -0,0 +1,218 @@ +/* + * JFFS2 -- Journalling Flash File System, Version 2. + * + * Copyright (C) 2001 Red Hat, Inc. + * + * Created by David Woodhouse + * + * The original JFFS, from which the design for JFFS2 was derived, + * was designed and implemented by Axis Communications AB. + * + * The contents of this file are subject to the Red Hat eCos Public + * License Version 1.1 (the "Licence"); you may not use this file + * except in compliance with the Licence. You may obtain a copy of + * the Licence at http://www.redhat.com/ + * + * Software distributed under the Licence is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. + * See the Licence for the specific language governing rights and + * limitations under the Licence. + * + * The Original Code is JFFS2 - Journalling Flash File System, version 2 + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use your + * version of this file under the RHEPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the RHEPL or the GPL. + * + * $Id: //depot/sw/releases/Aquila_9.2.0_U5/boot/u-boot/include/jffs2/jffs2.h#1 $ + * + */ + +#ifndef __LINUX_JFFS2_H__ +#define __LINUX_JFFS2_H__ + +#include +#include + +#define JFFS2_SUPER_MAGIC 0x72b6 + +/* Values we may expect to find in the 'magic' field */ +#define JFFS2_OLD_MAGIC_BITMASK 0x1984 +#define JFFS2_MAGIC_BITMASK 0x1985 +#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */ +#define JFFS2_EMPTY_BITMASK 0xffff +#define JFFS2_DIRTY_BITMASK 0x0000 + +/* We only allow a single char for length, and 0xFF is empty flash so + we don't want it confused with a real length. Hence max 254. +*/ +#define JFFS2_MAX_NAME_LEN 254 + +/* How small can we sensibly write nodes? */ +#define JFFS2_MIN_DATA_LEN 128 + +#define JFFS2_COMPR_NONE 0x00 +#define JFFS2_COMPR_ZERO 0x01 +#define JFFS2_COMPR_RTIME 0x02 +#define JFFS2_COMPR_RUBINMIPS 0x03 +#define JFFS2_COMPR_COPY 0x04 +#define JFFS2_COMPR_DYNRUBIN 0x05 +#define JFFS2_COMPR_ZLIB 0x06 +#if defined(CONFIG_JFFS2_LZO_LZARI) +#define JFFS2_COMPR_LZO 0x07 +#define JFFS2_COMPR_LZARI 0x08 +#define JFFS2_NUM_COMPR 9 +#else +#define JFFS2_NUM_COMPR 7 +#endif + +/* Compatibility flags. */ +#define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ +#define JFFS2_NODE_ACCURATE 0x2000 +/* INCOMPAT: Fail to mount the filesystem */ +#define JFFS2_FEATURE_INCOMPAT 0xc000 +/* ROCOMPAT: Mount read-only */ +#define JFFS2_FEATURE_ROCOMPAT 0x8000 +/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */ +#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000 +/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */ +#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000 + +#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1) +#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2) +#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) +#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4) + +/* Maybe later... */ +/*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */ +/*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */ + +/* Same as the non_ECC versions, but with extra space for real + * ECC instead of just the checksum. For use on NAND flash + */ +/*#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) */ +/*#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) */ + +#define JFFS2_INO_FLAG_PREREAD 1 /* Do read_inode() for this one at + mount time, don't wait for it to + happen later */ +#define JFFS2_INO_FLAG_USERCOMPR 2 /* User has requested a specific + compression type */ + + +struct jffs2_unknown_node +{ + /* All start like this */ + __u16 magic; + __u16 nodetype; + __u32 totlen; /* So we can skip over nodes we don't grok */ + __u32 hdr_crc; +} __attribute__((packed)); + +struct jffs2_raw_dirent +{ + __u16 magic; + __u16 nodetype; /* == JFFS_NODETYPE_DIRENT */ + __u32 totlen; + __u32 hdr_crc; + __u32 pino; + __u32 version; + __u32 ino; /* == zero for unlink */ + __u32 mctime; + __u8 nsize; + __u8 type; + __u8 unused[2]; + __u32 node_crc; + __u32 name_crc; + __u8 name[0]; +} __attribute__((packed)); + +/* The JFFS2 raw inode structure: Used for storage on physical media. */ +/* The uid, gid, atime, mtime and ctime members could be longer, but + are left like this for space efficiency. If and when people decide + they really need them extended, it's simple enough to add support for + a new type of raw node. +*/ +struct jffs2_raw_inode +{ + __u16 magic; /* A constant magic number. */ + __u16 nodetype; /* == JFFS_NODETYPE_INODE */ + __u32 totlen; /* Total length of this node (inc data, etc.) */ + __u32 hdr_crc; + __u32 ino; /* Inode number. */ + __u32 version; /* Version number. */ + __u32 mode; /* The file's type or mode. */ + __u16 uid; /* The file's owner. */ + __u16 gid; /* The file's group. */ + __u32 isize; /* Total resultant size of this inode (used for truncations) */ + __u32 atime; /* Last access time. */ + __u32 mtime; /* Last modification time. */ + __u32 ctime; /* Change time. */ + __u32 offset; /* Where to begin to write. */ + __u32 csize; /* (Compressed) data size */ + __u32 dsize; /* Size of the node's data. (after decompression) */ + __u8 compr; /* Compression algorithm used */ + __u8 usercompr; /* Compression algorithm requested by the user */ + __u16 flags; /* See JFFS2_INO_FLAG_* */ + __u32 data_crc; /* CRC for the (compressed) data. */ + __u32 node_crc; /* CRC for the raw inode (excluding data) */ +/* __u8 data[dsize]; */ +} __attribute__((packed)); + +union jffs2_node_union { + struct jffs2_raw_inode i; + struct jffs2_raw_dirent d; + struct jffs2_unknown_node u; +} __attribute__((packed)); + +enum + { + DT_UNKNOWN = 0, +# define DT_UNKNOWN DT_UNKNOWN + DT_FIFO = 1, +# define DT_FIFO DT_FIFO + DT_CHR = 2, +# define DT_CHR DT_CHR + DT_DIR = 4, +# define DT_DIR DT_DIR + DT_BLK = 6, +# define DT_BLK DT_BLK + DT_REG = 8, +# define DT_REG DT_REG + DT_LNK = 10, +# define DT_LNK DT_LNK + DT_SOCK = 12, +# define DT_SOCK DT_SOCK + DT_WHT = 14 +# define DT_WHT DT_WHT + }; + + +u32 jffs2_1pass_ls(struct part_info *part,const char *fname); +u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname); +u32 jffs2_1pass_info(struct part_info *part); + +void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen); +void rubin_do_decompress(unsigned char *bits, unsigned char *in, + unsigned char *page_out, __u32 destlen); +void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, + unsigned long sourcelen, unsigned long dstlen); +long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, + __u32 srclen, __u32 destlen); +#if defined(CONFIG_JFFS2_LZO_LZARI) +int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen); +int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out, + u32 srclen, u32 destlen); +#endif + +char *mkmodestr(unsigned long mode, char *str); +#endif /* __LINUX_JFFS2_H__ */ diff --git a/u-boot/include/jffs2/load_kernel.h b/u-boot/include/jffs2/load_kernel.h new file mode 100755 index 0000000..f3bce30 --- /dev/null +++ b/u-boot/include/jffs2/load_kernel.h @@ -0,0 +1,73 @@ +#ifndef load_kernel_h +#define load_kernel_h +/*------------------------------------------------------------------------- + * Filename: load_kernel.h + * Version: $Id: //depot/sw/releases/Aquila_9.2.0_U5/boot/u-boot/include/jffs2/load_kernel.h#1 $ + * Copyright: Copyright (C) 2001, Russ Dill + * Author: Russ Dill + * Description: header for load kernel modules + *-----------------------------------------------------------------------*/ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +/* mtd device types */ +#define MTD_DEV_TYPE_NOR 0x0001 +#define MTD_DEV_TYPE_NAND 0x0002 +#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : "nor") + +struct mtd_device { + struct list_head link; + struct mtdids *id; /* parent mtd id entry */ + u16 num_parts; /* number of partitions on this device */ + struct list_head parts; /* partitions */ +}; + +struct part_info { + struct list_head link; + char *name; /* partition name */ + u8 auto_name; /* set to 1 for generated name */ + u32 size; /* total size of the partition */ + u32 offset; /* offset within device */ + void *jffs2_priv; /* used internaly by jffs2 */ + u32 mask_flags; /* kernel MTD mask flags */ + struct mtd_device *dev; /* parent device */ +}; + +struct mtdids { + struct list_head link; + u8 type; /* device type */ + u8 num; /* device number */ + u32 size; /* device size */ + char *mtd_id; /* linux kernel device id */ +}; + +#define ldr_strlen strlen +#define ldr_strncmp strncmp +#define ldr_memcpy memcpy +#define putstr(x) printf("%s", x) +#define mmalloc malloc +#define UDEBUG printf + +#define putnstr(str, size) printf("%*.*s", size, size, str) +#define ldr_output_string(x) puts(x) +#define putLabeledWord(x, y) printf("%s %08x\n", x, (unsigned int)y) +#define led_blink(x, y, z, a) + +#endif /* load_kernel_h */ diff --git a/u-boot/include/lcd.h b/u-boot/include/lcd.h new file mode 100755 index 0000000..7e23736 --- /dev/null +++ b/u-boot/include/lcd.h @@ -0,0 +1,283 @@ +/* + * MPC823 and PXA LCD Controller + * + * Modeled after video interface by Paolo Scaffardi + * + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _LCD_H_ +#define _LCD_H_ + +extern char lcd_is_enabled; + +extern int lcd_line_length; +extern int lcd_color_fg; +extern int lcd_color_bg; + +/* + * Frame buffer memory information + */ +extern void *lcd_base; /* Start of framebuffer memory */ +extern void *lcd_console_address; /* Start of console buffer */ + +extern short console_col; +extern short console_row; + +#if defined CONFIG_MPC823 +/* + * LCD controller stucture for MPC823 CPU + */ +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ + u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ + u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ + u_char vl_clor; /* Color, 0 = mono, 1 = color */ + u_char vl_tft; /* 0 = passive, 1 = TFT */ + + /* Horizontal control register. Timing from data sheet */ + ushort vl_wbl; /* Wait between lines */ + + /* Vertical control register */ + u_char vl_vpw; /* Vertical sync pulse width */ + u_char vl_lcdac; /* LCD AC timing */ + u_char vl_wbf; /* Wait between frames */ +} vidinfo_t; + +extern vidinfo_t panel_info; + +#elif defined CONFIG_PXA250 +/* + * PXA LCD DMA descriptor + */ +struct pxafb_dma_descriptor { + u_long fdadr; /* Frame descriptor address register */ + u_long fsadr; /* Frame source address register */ + u_long fidr; /* Frame ID register */ + u_long ldcmd; /* Command register */ +}; + +/* + * PXA LCD info + */ +struct pxafb_info { + + /* Misc registers */ + u_long reg_lccr3; + u_long reg_lccr2; + u_long reg_lccr1; + u_long reg_lccr0; + u_long fdadr0; + u_long fdadr1; + + /* DMA descriptors */ + struct pxafb_dma_descriptor * dmadesc_fblow; + struct pxafb_dma_descriptor * dmadesc_fbhigh; + struct pxafb_dma_descriptor * dmadesc_palette; + + u_long screen; /* physical address of frame buffer */ + u_long palette; /* physical address of palette memory */ + u_int palette_size; +}; + +/* + * LCD controller stucture for PXA CPU + */ +typedef struct vidinfo { + ushort vl_col; /* Number of columns (i.e. 640) */ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ + + /* LCD configuration register */ + u_char vl_clkp; /* Clock polarity */ + u_char vl_oep; /* Output Enable polarity */ + u_char vl_hsp; /* Horizontal Sync polarity */ + u_char vl_vsp; /* Vertical Sync polarity */ + u_char vl_dp; /* Data polarity */ + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ + u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ + u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ + u_char vl_clor; /* Color, 0 = mono, 1 = color */ + u_char vl_tft; /* 0 = passive, 1 = TFT */ + + /* Horizontal control register. Timing from data sheet */ + ushort vl_hpw; /* Horz sync pulse width */ + u_char vl_blw; /* Wait before of line */ + u_char vl_elw; /* Wait end of line */ + + /* Vertical control register. */ + u_char vl_vpw; /* Vertical sync pulse width */ + u_char vl_bfw; /* Wait before of frame */ + u_char vl_efw; /* Wait end of frame */ + + /* PXA LCD controller params */ + struct pxafb_info pxa; +} vidinfo_t; + +extern vidinfo_t panel_info; + +#endif /* CONFIG_MPC823 or CONFIG_PXA250 */ + +/* Video functions */ + +#if defined(CONFIG_RBC823) +void lcd_disable (void); +#endif + + +/* int lcd_init (void *lcdbase); */ +void lcd_putc (const char c); +void lcd_puts (const char *s); +void lcd_printf (const char *fmt, ...); + + +/************************************************************************/ +/* ** BITMAP DISPLAY SUPPORT */ +/************************************************************************/ +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +# include +# include +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ + +/* + * Information about displays we are using. This is for configuring + * the LCD controller and memory allocation. Someone has to know what + * is connected, as we can't autodetect anything. + */ +#define CFG_HIGH 0 /* Pins are active high */ +#define CFG_LOW 1 /* Pins are active low */ + +#define LCD_MONOCHROME 0 +#define LCD_COLOR2 1 +#define LCD_COLOR4 2 +#define LCD_COLOR8 3 +#define LCD_COLOR16 4 + +/*----------------------------------------------------------------------*/ +#if defined(CONFIG_LCD_INFO_BELOW_LOGO) +# define LCD_INFO_X 0 +# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) +#elif defined(CONFIG_LCD_LOGO) +# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) +# define LCD_INFO_Y (VIDEO_FONT_HEIGHT) +#else +# define LCD_INFO_X (VIDEO_FONT_WIDTH) +# define LCD_INFO_Y (VIDEO_FONT_HEIGHT) +#endif + +/* Default to 8bpp if bit depth not specified */ +#ifndef LCD_BPP +# define LCD_BPP LCD_COLOR8 +#endif +#ifndef LCD_DF +# define LCD_DF 1 +#endif + +/* Calculate nr. of bits per pixel and nr. of colors */ +#define NBITS(bit_code) (1 << (bit_code)) +#define NCOLORS(bit_code) (1 << NBITS(bit_code)) + +/************************************************************************/ +/* ** CONSOLE CONSTANTS */ +/************************************************************************/ +#if LCD_BPP == LCD_MONOCHROME + +/* + * Simple black/white definitions + */ +# define CONSOLE_COLOR_BLACK 0 +# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ + +#elif LCD_BPP == LCD_COLOR8 + +/* + * 8bpp color definitions + */ +# define CONSOLE_COLOR_BLACK 0 +# define CONSOLE_COLOR_RED 1 +# define CONSOLE_COLOR_GREEN 2 +# define CONSOLE_COLOR_YELLOW 3 +# define CONSOLE_COLOR_BLUE 4 +# define CONSOLE_COLOR_MAGENTA 5 +# define CONSOLE_COLOR_CYAN 6 +# define CONSOLE_COLOR_GREY 14 +# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ + +#else + +/* + * 16bpp color definitions + */ +# define CONSOLE_COLOR_BLACK 0x0000 +# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ + +#endif /* color definitions */ + +/************************************************************************/ +#ifndef PAGE_SIZE +# define PAGE_SIZE 4096 +#endif + +/************************************************************************/ +/* ** CONSOLE DEFINITIONS & FUNCTIONS */ +/************************************************************************/ +#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) +# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \ + / VIDEO_FONT_HEIGHT) +#else +# define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT) +#endif + +#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) +#define CONSOLE_ROW_FIRST (lcd_console_address) +#define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) +#define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ + - CONSOLE_ROW_SIZE) +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) +#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) + +#if LCD_BPP == LCD_MONOCHROME +# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ + (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) +#elif LCD_BPP == LCD_COLOR8 +# define COLOR_MASK(c) (c) +#else +# error Unsupported LCD BPP. +#endif + +/************************************************************************/ + +#endif /* _LCD_H_ */ diff --git a/u-boot/include/linux/bitops.h b/u-boot/include/linux/bitops.h new file mode 100755 index 0000000..7d41ae6 --- /dev/null +++ b/u-boot/include/linux/bitops.h @@ -0,0 +1,72 @@ +#ifndef _LINUX_BITOPS_H +#define _LINUX_BITOPS_H + + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +static inline int generic_ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +static inline unsigned int generic_hweight32(unsigned int w) +{ + unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555); + res = (res & 0x33333333) + ((res >> 2) & 0x33333333); + res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F); + res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF); + return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF); +} + +static inline unsigned int generic_hweight16(unsigned int w) +{ + unsigned int res = (w & 0x5555) + ((w >> 1) & 0x5555); + res = (res & 0x3333) + ((res >> 2) & 0x3333); + res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F); + return (res & 0x00FF) + ((res >> 8) & 0x00FF); +} + +static inline unsigned int generic_hweight8(unsigned int w) +{ + unsigned int res = (w & 0x55) + ((w >> 1) & 0x55); + res = (res & 0x33) + ((res >> 2) & 0x33); + return (res & 0x0F) + ((res >> 4) & 0x0F); +} + +#include + + +#endif diff --git a/u-boot/include/linux/byteorder/big_endian.h b/u-boot/include/linux/byteorder/big_endian.h new file mode 100755 index 0000000..19b0c86 --- /dev/null +++ b/u-boot/include/linux/byteorder/big_endian.h @@ -0,0 +1,69 @@ +#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H +#define _LINUX_BYTEORDER_BIG_ENDIAN_H + +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN 4321 +#endif +#ifndef __BIG_ENDIAN_BITFIELD +#define __BIG_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __BIG_ENDIAN + +#include + +#define __constant_htonl(x) ((__u32)(x)) +#define __constant_ntohl(x) ((__u32)(x)) +#define __constant_htons(x) ((__u16)(x)) +#define __constant_ntohs(x) ((__u16)(x)) +#define __constant_cpu_to_le64(x) ___swab64((x)) +#define __constant_le64_to_cpu(x) ___swab64((x)) +#define __constant_cpu_to_le32(x) ___swab32((x)) +#define __constant_le32_to_cpu(x) ___swab32((x)) +#define __constant_cpu_to_le16(x) ___swab16((x)) +#define __constant_le16_to_cpu(x) ___swab16((x)) +#define __constant_cpu_to_be64(x) ((__u64)(x)) +#define __constant_be64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_be32(x) ((__u32)(x)) +#define __constant_be32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_be16(x) ((__u16)(x)) +#define __constant_be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64(x) __swab64((x)) +#define __le64_to_cpu(x) __swab64((x)) +#define __cpu_to_le32(x) __swab32((x)) +#define __le32_to_cpu(x) __swab32((x)) +#define __cpu_to_le16(x) __swab16((x)) +#define __le16_to_cpu(x) __swab16((x)) +#define __cpu_to_be64(x) ((__u64)(x)) +#define __be64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_be32(x) ((__u32)(x)) +#define __be32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_be16(x) ((__u16)(x)) +#define __be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64p(x) __swab64p((x)) +#define __le64_to_cpup(x) __swab64p((x)) +#define __cpu_to_le32p(x) __swab32p((x)) +#define __le32_to_cpup(x) __swab32p((x)) +#define __cpu_to_le16p(x) __swab16p((x)) +#define __le16_to_cpup(x) __swab16p((x)) +#define __cpu_to_be64p(x) (*(__u64*)(x)) +#define __be64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_be32p(x) (*(__u32*)(x)) +#define __be32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_be16p(x) (*(__u16*)(x)) +#define __be16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_le64s(x) __swab64s((x)) +#define __le64_to_cpus(x) __swab64s((x)) +#define __cpu_to_le32s(x) __swab32s((x)) +#define __le32_to_cpus(x) __swab32s((x)) +#define __cpu_to_le16s(x) __swab16s((x)) +#define __le16_to_cpus(x) __swab16s((x)) +#define __cpu_to_be64s(x) do {} while (0) +#define __be64_to_cpus(x) do {} while (0) +#define __cpu_to_be32s(x) do {} while (0) +#define __be32_to_cpus(x) do {} while (0) +#define __cpu_to_be16s(x) do {} while (0) +#define __be16_to_cpus(x) do {} while (0) + +#include + +#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/u-boot/include/linux/byteorder/generic.h b/u-boot/include/linux/byteorder/generic.h new file mode 100755 index 0000000..cff850f --- /dev/null +++ b/u-boot/include/linux/byteorder/generic.h @@ -0,0 +1,180 @@ +#ifndef _LINUX_BYTEORDER_GENERIC_H +#define _LINUX_BYTEORDER_GENERIC_H + +/* + * linux/byteorder_generic.h + * Generic Byte-reordering support + * + * Francois-Rene Rideau 19970707 + * gathered all the good ideas from all asm-foo/byteorder.h into one file, + * cleaned them up. + * I hope it is compliant with non-GCC compilers. + * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, + * because I wasn't sure it would be ok to put it in types.h + * Upgraded it to 2.1.43 + * Francois-Rene Rideau 19971012 + * Upgraded it to 2.1.57 + * to please Linus T., replaced huge #ifdef's between little/big endian + * by nestedly #include'd files. + * Francois-Rene Rideau 19971205 + * Made it to 2.1.71; now a facelift: + * Put files under include/linux/byteorder/ + * Split swab from generic support. + * + * TODO: + * = Regular kernel maintainers could also replace all these manual + * byteswap macros that remain, disseminated among drivers, + * after some grep or the sources... + * = Linus might want to rename all these macros and files to fit his taste, + * to fit his personal naming scheme. + * = it seems that a few drivers would also appreciate + * nybble swapping support... + * = every architecture could add their byteswap macro in asm/byteorder.h + * see how some architectures already do (i386, alpha, ppc, etc) + * = cpu_to_beXX and beXX_to_cpu might some day need to be well + * distinguished throughout the kernel. This is not the case currently, + * since little endian, big endian, and pdp endian machines needn't it. + * But this might be the case for, say, a port of Linux to 20/21 bit + * architectures (and F21 Linux addict around?). + */ + +/* + * The following macros are to be defined by : + * + * Conversion of long and short int between network and host format + * ntohl(__u32 x) + * ntohs(__u16 x) + * htonl(__u32 x) + * htons(__u16 x) + * It seems that some programs (which? where? or perhaps a standard? POSIX?) + * might like the above to be functions, not macros (why?). + * if that's true, then detect them, and take measures. + * Anyway, the measure is: define only ___ntohl as a macro instead, + * and in a separate file, have + * unsigned long inline ntohl(x){return ___ntohl(x);} + * + * The same for constant arguments + * __constant_ntohl(__u32 x) + * __constant_ntohs(__u16 x) + * __constant_htonl(__u32 x) + * __constant_htons(__u16 x) + * + * Conversion of XX-bit integers (16- 32- or 64-) + * between native CPU format and little/big endian format + * 64-bit stuff only defined for proper architectures + * cpu_to_[bl]eXX(__uXX x) + * [bl]eXX_to_cpu(__uXX x) + * + * The same, but takes a pointer to the value to convert + * cpu_to_[bl]eXXp(__uXX x) + * [bl]eXX_to_cpup(__uXX x) + * + * The same, but change in situ + * cpu_to_[bl]eXXs(__uXX x) + * [bl]eXX_to_cpus(__uXX x) + * + * See asm-foo/byteorder.h for examples of how to provide + * architecture-optimized versions + * + */ + + +#if defined(__KERNEL__) +/* + * inside the kernel, we can use nicknames; + * outside of it, we must avoid POSIX namespace pollution... + */ +#define cpu_to_le64 __cpu_to_le64 +#define le64_to_cpu __le64_to_cpu +#define cpu_to_le32 __cpu_to_le32 +#define le32_to_cpu __le32_to_cpu +#define cpu_to_le16 __cpu_to_le16 +#define le16_to_cpu __le16_to_cpu +#define cpu_to_be64 __cpu_to_be64 +#define be64_to_cpu __be64_to_cpu +#define cpu_to_be32 __cpu_to_be32 +#define be32_to_cpu __be32_to_cpu +#define cpu_to_be16 __cpu_to_be16 +#define be16_to_cpu __be16_to_cpu +#define cpu_to_le64p __cpu_to_le64p +#define le64_to_cpup __le64_to_cpup +#define cpu_to_le32p __cpu_to_le32p +#define le32_to_cpup __le32_to_cpup +#define cpu_to_le16p __cpu_to_le16p +#define le16_to_cpup __le16_to_cpup +#define cpu_to_be64p __cpu_to_be64p +#define be64_to_cpup __be64_to_cpup +#define cpu_to_be32p __cpu_to_be32p +#define be32_to_cpup __be32_to_cpup +#define cpu_to_be16p __cpu_to_be16p +#define be16_to_cpup __be16_to_cpup +#define cpu_to_le64s __cpu_to_le64s +#define le64_to_cpus __le64_to_cpus +#define cpu_to_le32s __cpu_to_le32s +#define le32_to_cpus __le32_to_cpus +#define cpu_to_le16s __cpu_to_le16s +#define le16_to_cpus __le16_to_cpus +#define cpu_to_be64s __cpu_to_be64s +#define be64_to_cpus __be64_to_cpus +#define cpu_to_be32s __cpu_to_be32s +#define be32_to_cpus __be32_to_cpus +#define cpu_to_be16s __cpu_to_be16s +#define be16_to_cpus __be16_to_cpus +#endif + + +/* + * Handle ntohl and suches. These have various compatibility + * issues - like we want to give the prototype even though we + * also have a macro for them in case some strange program + * wants to take the address of the thing or something.. + * + * Note that these used to return a "long" in libc5, even though + * long is often 64-bit these days.. Thus the casts. + * + * They have to be macros in order to do the constant folding + * correctly - if the argument passed into a inline function + * it is no longer constant according to gcc.. + */ + +#undef ntohl +#undef ntohs +#undef htonl +#undef htons + +/* + * Do the prototypes. Somebody might want to take the + * address or some such sick thing.. + */ +#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) +extern __u32 ntohl(__u32); +extern __u32 htonl(__u32); +#else +extern unsigned long int ntohl(unsigned long int); +extern unsigned long int htonl(unsigned long int); +#endif +extern unsigned short int ntohs(unsigned short int); +extern unsigned short int htons(unsigned short int); + + +#if defined(__GNUC__) && (__GNUC__ >= 2) + +#define ___htonl(x) __cpu_to_be32(x) +#define ___htons(x) __cpu_to_be16(x) +#define ___ntohl(x) __be32_to_cpu(x) +#define ___ntohs(x) __be16_to_cpu(x) + +#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) +#define htonl(x) ___htonl(x) +#define ntohl(x) ___ntohl(x) +#else +#define htonl(x) ((unsigned long)___htonl(x)) +#define ntohl(x) ((unsigned long)___ntohl(x)) +#endif +#define htons(x) ___htons(x) +#define ntohs(x) ___ntohs(x) + +#endif /* OPTIMIZE */ + + +#endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/u-boot/include/linux/byteorder/little_endian.h b/u-boot/include/linux/byteorder/little_endian.h new file mode 100755 index 0000000..a46f3ec --- /dev/null +++ b/u-boot/include/linux/byteorder/little_endian.h @@ -0,0 +1,69 @@ +#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H +#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H + +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN 1234 +#endif +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __LITTLE_ENDIAN + +#include + +#define __constant_htonl(x) ___constant_swab32((x)) +#define __constant_ntohl(x) ___constant_swab32((x)) +#define __constant_htons(x) ___constant_swab16((x)) +#define __constant_ntohs(x) ___constant_swab16((x)) +#define __constant_cpu_to_le64(x) ((__u64)(x)) +#define __constant_le64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_le32(x) ((__u32)(x)) +#define __constant_le32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_le16(x) ((__u16)(x)) +#define __constant_le16_to_cpu(x) ((__u16)(x)) +#define __constant_cpu_to_be64(x) ___constant_swab64((x)) +#define __constant_be64_to_cpu(x) ___constant_swab64((x)) +#define __constant_cpu_to_be32(x) ___constant_swab32((x)) +#define __constant_be32_to_cpu(x) ___constant_swab32((x)) +#define __constant_cpu_to_be16(x) ___constant_swab16((x)) +#define __constant_be16_to_cpu(x) ___constant_swab16((x)) +#define __cpu_to_le64(x) ((__u64)(x)) +#define __le64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_le32(x) ((__u32)(x)) +#define __le32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_le16(x) ((__u16)(x)) +#define __le16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_be64(x) __swab64((x)) +#define __be64_to_cpu(x) __swab64((x)) +#define __cpu_to_be32(x) __swab32((x)) +#define __be32_to_cpu(x) __swab32((x)) +#define __cpu_to_be16(x) __swab16((x)) +#define __be16_to_cpu(x) __swab16((x)) +#define __cpu_to_le64p(x) (*(__u64*)(x)) +#define __le64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_le32p(x) (*(__u32*)(x)) +#define __le32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_le16p(x) (*(__u16*)(x)) +#define __le16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_be64p(x) __swab64p((x)) +#define __be64_to_cpup(x) __swab64p((x)) +#define __cpu_to_be32p(x) __swab32p((x)) +#define __be32_to_cpup(x) __swab32p((x)) +#define __cpu_to_be16p(x) __swab16p((x)) +#define __be16_to_cpup(x) __swab16p((x)) +#define __cpu_to_le64s(x) do {} while (0) +#define __le64_to_cpus(x) do {} while (0) +#define __cpu_to_le32s(x) do {} while (0) +#define __le32_to_cpus(x) do {} while (0) +#define __cpu_to_le16s(x) do {} while (0) +#define __le16_to_cpus(x) do {} while (0) +#define __cpu_to_be64s(x) __swab64s((x)) +#define __be64_to_cpus(x) __swab64s((x)) +#define __cpu_to_be32s(x) __swab32s((x)) +#define __be32_to_cpus(x) __swab32s((x)) +#define __cpu_to_be16s(x) __swab16s((x)) +#define __be16_to_cpus(x) __swab16s((x)) + +#include + +#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/u-boot/include/linux/byteorder/swab.h b/u-boot/include/linux/byteorder/swab.h new file mode 100755 index 0000000..b1d570e --- /dev/null +++ b/u-boot/include/linux/byteorder/swab.h @@ -0,0 +1,158 @@ +#ifndef _LINUX_BYTEORDER_SWAB_H +#define _LINUX_BYTEORDER_SWAB_H + +/* + * linux/byteorder/swab.h + * Byte-swapping, independently from CPU endianness + * swabXX[ps]?(foo) + * + * Francois-Rene Rideau 19971205 + * separated swab functions from cpu_to_XX, + * to clean up support for bizarre-endian architectures. + * + * See asm-i386/byteorder.h and suches for examples of how to provide + * architecture-dependent optimized versions + * + */ + +/* casts are necessary for constants, because we never know how for sure + * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. + */ +#define ___swab16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define ___swab32(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) +#define ___swab64(x) \ + ((__u64)( \ + (__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ + (__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) )) + +/* + * provide defaults when no architecture-specific optimization is detected + */ +#ifndef __arch__swab16 +# define __arch__swab16(x) ___swab16(x) +#endif +#ifndef __arch__swab32 +# define __arch__swab32(x) ___swab32(x) +#endif +#ifndef __arch__swab64 +# define __arch__swab64(x) ___swab64(x) +#endif + +#ifndef __arch__swab16p +# define __arch__swab16p(x) __swab16(*(x)) +#endif +#ifndef __arch__swab32p +# define __arch__swab32p(x) __swab32(*(x)) +#endif +#ifndef __arch__swab64p +# define __arch__swab64p(x) __swab64(*(x)) +#endif + +#ifndef __arch__swab16s +# define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0) +#endif +#ifndef __arch__swab32s +# define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0) +#endif +#ifndef __arch__swab64s +# define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0) +#endif + + +/* + * Allow constant folding + */ +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) +# define __swab16(x) \ +(__builtin_constant_p((__u16)(x)) ? \ + ___swab16((x)) : \ + __fswab16((x))) +# define __swab32(x) \ +(__builtin_constant_p((__u32)(x)) ? \ + ___swab32((x)) : \ + __fswab32((x))) +# define __swab64(x) \ +(__builtin_constant_p((__u64)(x)) ? \ + ___swab64((x)) : \ + __fswab64((x))) +#else +# define __swab16(x) __fswab16(x) +# define __swab32(x) __fswab32(x) +# define __swab64(x) __fswab64(x) +#endif /* OPTIMIZE */ + + +static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x) +{ + return __arch__swab16(x); +} +static __inline__ __u16 __swab16p(__u16 *x) +{ + return __arch__swab16p(x); +} +static __inline__ void __swab16s(__u16 *addr) +{ + __arch__swab16s(addr); +} + +static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) +{ + return __arch__swab32(x); +} +static __inline__ __u32 __swab32p(__u32 *x) +{ + return __arch__swab32p(x); +} +static __inline__ void __swab32s(__u32 *addr) +{ + __arch__swab32s(addr); +} + +#ifdef __BYTEORDER_HAS_U64__ +static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x) +{ +# ifdef __SWAB_64_THRU_32__ + __u32 h = x >> 32; + __u32 l = x & ((1ULL<<32)-1); + return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h))); +# else + return __arch__swab64(x); +# endif +} +static __inline__ __u64 __swab64p(__u64 *x) +{ + return __arch__swab64p(x); +} +static __inline__ void __swab64s(__u64 *addr) +{ + __arch__swab64s(addr); +} +#endif /* __BYTEORDER_HAS_U64__ */ + +#if defined(__KERNEL__) +#define swab16 __swab16 +#define swab32 __swab32 +#define swab64 __swab64 +#define swab16p __swab16p +#define swab32p __swab32p +#define swab64p __swab64p +#define swab16s __swab16s +#define swab32s __swab32s +#define swab64s __swab64s +#endif + +#endif /* _LINUX_BYTEORDER_SWAB_H */ diff --git a/u-boot/include/linux/config.h b/u-boot/include/linux/config.h new file mode 100755 index 0000000..a0194cb --- /dev/null +++ b/u-boot/include/linux/config.h @@ -0,0 +1,6 @@ +#ifndef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H + +/* #include */ + +#endif diff --git a/u-boot/include/linux/ctype.h b/u-boot/include/linux/ctype.h new file mode 100755 index 0000000..afa3639 --- /dev/null +++ b/u-boot/include/linux/ctype.h @@ -0,0 +1,54 @@ +#ifndef _LINUX_CTYPE_H +#define _LINUX_CTYPE_H + +/* + * NOTE! This ctype does not handle EOF like the standard C + * library is required to. + */ + +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ + +extern unsigned char _ctype[]; + +#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) + +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isdigit(c) ((__ismask(c)&(_D)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) + +#define isascii(c) (((unsigned char)(c))<=0x7f) +#define toascii(c) (((unsigned char)(c))&0x7f) + +static inline unsigned char __tolower(unsigned char c) +{ + if (isupper(c)) + c -= 'A'-'a'; + return c; +} + +static inline unsigned char __toupper(unsigned char c) +{ + if (islower(c)) + c -= 'a'-'A'; + return c; +} + +#define tolower(c) __tolower(c) +#define toupper(c) __toupper(c) + +#endif diff --git a/u-boot/include/linux/list.h b/u-boot/include/linux/list.h new file mode 100755 index 0000000..e6492f7 --- /dev/null +++ b/u-boot/include/linux/list.h @@ -0,0 +1,258 @@ +#ifndef _LINUX_LIST_H +#define _LINUX_LIST_H + +#ifndef ARCH_HAS_PREFETCH +#define ARCH_HAS_PREFETCH +static inline void prefetch(const void *x) {;} +#endif + +/* + * Simple doubly linked list implementation. + * + * Some of the internal functions ("__xxx") are useful when + * manipulating whole lists rather than single entries, as + * sometimes we already know the next/prev entries and we can + * generate better code by using them directly rather than + * using the generic single-entry routines. + */ + +struct list_head { + struct list_head *next, *prev; +}; + +#define LIST_HEAD_INIT(name) { &(name), &(name) } + +#define LIST_HEAD(name) \ + struct list_head name = LIST_HEAD_INIT(name) + +#define INIT_LIST_HEAD(ptr) do { \ + (ptr)->next = (ptr); (ptr)->prev = (ptr); \ +} while (0) + +/* + * Insert a new entry between two known consecutive entries. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_add(struct list_head *new, + struct list_head *prev, + struct list_head *next) +{ + next->prev = new; + new->next = next; + new->prev = prev; + prev->next = new; +} + +/** + * list_add - add a new entry + * @new: new entry to be added + * @head: list head to add it after + * + * Insert a new entry after the specified head. + * This is good for implementing stacks. + */ +static inline void list_add(struct list_head *new, struct list_head *head) +{ + __list_add(new, head, head->next); +} + +/** + * list_add_tail - add a new entry + * @new: new entry to be added + * @head: list head to add it before + * + * Insert a new entry before the specified head. + * This is useful for implementing queues. + */ +static inline void list_add_tail(struct list_head *new, struct list_head *head) +{ + __list_add(new, head->prev, head); +} + +/* + * Delete a list entry by making the prev/next entries + * point to each other. + * + * This is only for internal list manipulation where we know + * the prev/next entries already! + */ +static inline void __list_del(struct list_head *prev, struct list_head *next) +{ + next->prev = prev; + prev->next = next; +} + +/** + * list_del - deletes entry from list. + * @entry: the element to delete from the list. + * Note: list_empty on entry does not return true after this, the entry is in an undefined state. + */ +static inline void list_del(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + entry->next = (void *) 0; + entry->prev = (void *) 0; +} + +/** + * list_del_init - deletes entry from list and reinitialize it. + * @entry: the element to delete from the list. + */ +static inline void list_del_init(struct list_head *entry) +{ + __list_del(entry->prev, entry->next); + INIT_LIST_HEAD(entry); +} + +/** + * list_move - delete from one list and add as another's head + * @list: the entry to move + * @head: the head that will precede our entry + */ +static inline void list_move(struct list_head *list, struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add(list, head); +} + +/** + * list_move_tail - delete from one list and add as another's tail + * @list: the entry to move + * @head: the head that will follow our entry + */ +static inline void list_move_tail(struct list_head *list, + struct list_head *head) +{ + __list_del(list->prev, list->next); + list_add_tail(list, head); +} + +/** + * list_empty - tests whether a list is empty + * @head: the list to test. + */ +static inline int list_empty(struct list_head *head) +{ + return head->next == head; +} + +static inline void __list_splice(struct list_head *list, + struct list_head *head) +{ + struct list_head *first = list->next; + struct list_head *last = list->prev; + struct list_head *at = head->next; + + first->prev = head; + head->next = first; + + last->next = at; + at->prev = last; +} + +/** + * list_splice - join two lists + * @list: the new list to add. + * @head: the place to add it in the first list. + */ +static inline void list_splice(struct list_head *list, struct list_head *head) +{ + if (!list_empty(list)) + __list_splice(list, head); +} + +/** + * list_splice_init - join two lists and reinitialise the emptied list. + * @list: the new list to add. + * @head: the place to add it in the first list. + * + * The list at @list is reinitialised + */ +static inline void list_splice_init(struct list_head *list, + struct list_head *head) +{ + if (!list_empty(list)) { + __list_splice(list, head); + INIT_LIST_HEAD(list); + } +} + +/** + * list_entry - get the struct for this entry + * @ptr: the &struct list_head pointer. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + */ +#define list_entry(ptr, type, member) \ + ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member))) + +/** + * list_for_each - iterate over a list + * @pos: the &struct list_head to use as a loop counter. + * @head: the head for your list. + */ +#define list_for_each(pos, head) \ + for (pos = (head)->next, prefetch(pos->next); pos != (head); \ + pos = pos->next, prefetch(pos->next)) +/** + * list_for_each_prev - iterate over a list backwards + * @pos: the &struct list_head to use as a loop counter. + * @head: the head for your list. + */ +#define list_for_each_prev(pos, head) \ + for (pos = (head)->prev, prefetch(pos->prev); pos != (head); \ + pos = pos->prev, prefetch(pos->prev)) + +/** + * list_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the &struct list_head to use as a loop counter. + * @n: another &struct list_head to use as temporary storage + * @head: the head for your list. + */ +#define list_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +/** + * list_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop counter. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry(pos, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + prefetch(pos->member.next); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member), \ + prefetch(pos->member.next)) + +/** + * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop counter. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for (pos = list_entry((head)->next, typeof(*pos), member), \ + n = list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = list_entry(n->member.next, typeof(*n), member)) + +/** + * list_for_each_entry_continue - iterate over list of given type + * continuing after existing point + * @pos: the type * to use as a loop counter. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_entry(pos->member.next, typeof(*pos), member), \ + prefetch(pos->member.next); \ + &pos->member != (head); \ + pos = list_entry(pos->member.next, typeof(*pos), member), \ + prefetch(pos->member.next)) + +#endif diff --git a/u-boot/include/linux/mtd/mtd-abi.h b/u-boot/include/linux/mtd/mtd-abi.h new file mode 100755 index 0000000..7ec1b17 --- /dev/null +++ b/u-boot/include/linux/mtd/mtd-abi.h @@ -0,0 +1,99 @@ +/* + * $Id: //depot/sw/releases/Aquila_9.2.0_U5/boot/u-boot/include/linux/mtd/mtd-abi.h#1 $ + * + * Portions of MTD ABI definition which are shared by kernel and user space + */ + +#ifndef __MTD_ABI_H__ +#define __MTD_ABI_H__ + +struct erase_info_user { + uint32_t start; + uint32_t length; +}; + +struct mtd_oob_buf { + uint32_t start; + uint32_t length; + unsigned char *ptr; +}; + +#define MTD_ABSENT 0 +#define MTD_RAM 1 +#define MTD_ROM 2 +#define MTD_NORFLASH 3 +#define MTD_NANDFLASH 4 +#define MTD_PEROM 5 +#define MTD_OTHER 14 +#define MTD_UNKNOWN 15 + +#define MTD_CLEAR_BITS 1 /* Bits can be cleared (flash) */ +#define MTD_SET_BITS 2 /* Bits can be set */ +#define MTD_ERASEABLE 4 /* Has an erase function */ +#define MTD_WRITEB_WRITEABLE 8 /* Direct IO is possible */ +#define MTD_VOLATILE 16 /* Set for RAMs */ +#define MTD_XIP 32 /* eXecute-In-Place possible */ +#define MTD_OOB 64 /* Out-of-band data (NAND flash) */ +#define MTD_ECC 128 /* Device capable of automatic ECC */ +#define MTD_NO_VIRTBLOCKS 256 /* Virtual blocks not allowed */ + +/* Some common devices / combinations of capabilities */ +#define MTD_CAP_ROM 0 +#define MTD_CAP_RAM (MTD_CLEAR_BITS|MTD_SET_BITS|MTD_WRITEB_WRITEABLE) +#define MTD_CAP_NORFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE) +#define MTD_CAP_NANDFLASH (MTD_CLEAR_BITS|MTD_ERASEABLE|MTD_OOB) +#define MTD_WRITEABLE (MTD_CLEAR_BITS|MTD_SET_BITS) + + +/* Types of automatic ECC/Checksum available */ +#define MTD_ECC_NONE 0 /* No automatic ECC available */ +#define MTD_ECC_RS_DiskOnChip 1 /* Automatic ECC on DiskOnChip */ +#define MTD_ECC_SW 2 /* SW ECC for Toshiba & Samsung devices */ + +/* ECC byte placement */ +#define MTD_NANDECC_OFF 0 /* Switch off ECC (Not recommended) */ +#define MTD_NANDECC_PLACE 1 /* Use the given placement in the structure (YAFFS1 legacy mode) */ +#define MTD_NANDECC_AUTOPLACE 2 /* Use the default placement scheme */ +#define MTD_NANDECC_PLACEONLY 3 /* Use the given placement in the structure (Do not store ecc result on read) */ +#define MTD_NANDECC_AUTOPL_USR 4 /* Use the given autoplacement scheme rather than using the default */ + +struct mtd_info_user { + uint8_t type; + uint32_t flags; + uint32_t size; /* Total size of the MTD */ + uint32_t erasesize; + uint32_t oobblock; /* Size of OOB blocks (e.g. 512) */ + uint32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ + uint32_t ecctype; + uint32_t eccsize; +}; + +struct region_info_user { + uint32_t offset; /* At which this region starts, + * from the beginning of the MTD */ + uint32_t erasesize; /* For this region */ + uint32_t numblocks; /* Number of blocks in this region */ + uint32_t regionindex; +}; + +#define MEMGETINFO _IOR('M', 1, struct mtd_info_user) +#define MEMERASE _IOW('M', 2, struct erase_info_user) +#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf) +#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) +#define MEMLOCK _IOW('M', 5, struct erase_info_user) +#define MEMUNLOCK _IOW('M', 6, struct erase_info_user) +#define MEMGETREGIONCOUNT _IOR('M', 7, int) +#define MEMGETREGIONINFO _IOWR('M', 8, struct region_info_user) +#define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo) +#define MEMGETOOBSEL _IOR('M', 10, struct nand_oobinfo) +#define MEMGETBADBLOCK _IOW('M', 11, loff_t) +#define MEMSETBADBLOCK _IOW('M', 12, loff_t) + +struct nand_oobinfo { + uint32_t useecc; + uint32_t eccbytes; + uint32_t oobfree[8][2]; + uint32_t eccpos[32]; +}; + +#endif /* __MTD_ABI_H__ */ diff --git a/u-boot/include/linux/mtd/mtd.h b/u-boot/include/linux/mtd/mtd.h new file mode 100755 index 0000000..1497175 --- /dev/null +++ b/u-boot/include/linux/mtd/mtd.h @@ -0,0 +1,214 @@ +/* + * $Id: //depot/sw/releases/Aquila_9.2.0_U5/boot/u-boot/include/linux/mtd/mtd.h#1 $ + * + * Copyright (C) 1999-2003 David Woodhouse et al. + * + * Released under GPL + */ + +#ifndef __MTD_MTD_H__ +#define __MTD_MTD_H__ +#include +#include + +#define MAX_MTD_DEVICES 16 + +#define MTD_ERASE_PENDING 0x01 +#define MTD_ERASING 0x02 +#define MTD_ERASE_SUSPEND 0x04 +#define MTD_ERASE_DONE 0x08 +#define MTD_ERASE_FAILED 0x10 + +/* If the erase fails, fail_addr might indicate exactly which block failed. If + fail_addr = 0xffffffff, the failure was not at the device level or was not + specific to any particular block. */ +struct erase_info { + struct mtd_info *mtd; + u_int32_t addr; + u_int32_t len; + u_int32_t fail_addr; + u_long time; + u_long retries; + u_int dev; + u_int cell; + void (*callback) (struct erase_info *self); + u_long priv; + u_char state; + struct erase_info *next; +}; + +struct mtd_erase_region_info { + u_int32_t offset; /* At which this region starts, from the beginning of the MTD */ + u_int32_t erasesize; /* For this region */ + u_int32_t numblocks; /* Number of blocks of erasesize in this region */ +}; + +struct mtd_info { + u_char type; + u_int32_t flags; + u_int32_t size; /* Total size of the MTD */ + + /* "Major" erase size for the device. Naïve users may take this + * to be the only erase size available, or may use the more detailed + * information below if they desire + */ + u_int32_t erasesize; + + u_int32_t oobblock; /* Size of OOB blocks (e.g. 512) */ + u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ + u_int32_t oobavail; /* Number of bytes in OOB area available for fs */ + u_int32_t ecctype; + u_int32_t eccsize; + + + /* Kernel-only stuff starts here. */ + char *name; + int index; + + /* oobinfo is a nand_oobinfo structure, which can be set by iotcl (MEMSETOOBINFO) */ + struct nand_oobinfo oobinfo; + + /* Data for variable erase regions. If numeraseregions is zero, + * it means that the whole device has erasesize as given above. + */ + int numeraseregions; + struct mtd_erase_region_info *eraseregions; + + /* This really shouldn't be here. It can go away in 2.5 */ + u_int32_t bank_size; + + int (*erase) (struct mtd_info *mtd, struct erase_info *instr); + + /* This stuff for eXecute-In-Place */ + int (*point) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char **mtdbuf); + + /* We probably shouldn't allow XIP if the unpoint isn't a NULL */ + void (*unpoint) (struct mtd_info *mtd, u_char * addr, loff_t from, size_t len); + + + int (*read) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + int (*write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + + int (*read_ecc) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); + int (*write_ecc) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf, u_char *eccbuf, struct nand_oobinfo *oobsel); + + int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + + /* + * Methods to access the protection register area, present in some + * flash devices. The user data is one time programmable but the + * factory data is read only. + */ + int (*read_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + + int (*read_fact_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + + /* This function is not yet implemented */ + int (*write_user_prot_reg) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); +#if 0 + /* kvec-based read/write methods. We need these especially for NAND flash, + with its limited number of write cycles per erase. + NB: The 'count' parameter is the number of _vectors_, each of + which contains an (ofs, len) tuple. + */ + int (*readv) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, size_t *retlen); + int (*readv_ecc) (struct mtd_info *mtd, struct kvec *vecs, unsigned long count, loff_t from, + size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); + int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen); + int (*writev_ecc) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, + size_t *retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); +#endif + /* Sync */ + void (*sync) (struct mtd_info *mtd); +#if 0 + /* Chip-supported device locking */ + int (*lock) (struct mtd_info *mtd, loff_t ofs, size_t len); + int (*unlock) (struct mtd_info *mtd, loff_t ofs, size_t len); + + /* Power Management functions */ + int (*suspend) (struct mtd_info *mtd); + void (*resume) (struct mtd_info *mtd); +#endif + /* Bad block management functions */ + int (*block_isbad) (struct mtd_info *mtd, loff_t ofs); + int (*block_markbad) (struct mtd_info *mtd, loff_t ofs); + + void *priv; + + struct module *owner; + int usecount; +}; + + + /* Kernel-side ioctl definitions */ + +extern int add_mtd_device(struct mtd_info *mtd); +extern int del_mtd_device (struct mtd_info *mtd); + +extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); + +extern void put_mtd_device(struct mtd_info *mtd); + +#if 0 +struct mtd_notifier { + void (*add)(struct mtd_info *mtd); + void (*remove)(struct mtd_info *mtd); + struct list_head list; +}; + + +extern void register_mtd_user (struct mtd_notifier *new); +extern int unregister_mtd_user (struct mtd_notifier *old); + +int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t *retlen); + +int default_mtd_readv(struct mtd_info *mtd, struct kvec *vecs, + unsigned long count, loff_t from, size_t *retlen); +#endif + +#define MTD_ERASE(mtd, args...) (*(mtd->erase))(mtd, args) +#define MTD_POINT(mtd, a,b,c,d) (*(mtd->point))(mtd, a,b,c, (u_char **)(d)) +#define MTD_UNPOINT(mtd, arg) (*(mtd->unpoint))(mtd, (u_char *)arg) +#define MTD_READ(mtd, args...) (*(mtd->read))(mtd, args) +#define MTD_WRITE(mtd, args...) (*(mtd->write))(mtd, args) +#define MTD_READV(mtd, args...) (*(mtd->readv))(mtd, args) +#define MTD_WRITEV(mtd, args...) (*(mtd->writev))(mtd, args) +#define MTD_READECC(mtd, args...) (*(mtd->read_ecc))(mtd, args) +#define MTD_WRITEECC(mtd, args...) (*(mtd->write_ecc))(mtd, args) +#define MTD_READOOB(mtd, args...) (*(mtd->read_oob))(mtd, args) +#define MTD_WRITEOOB(mtd, args...) (*(mtd->write_oob))(mtd, args) +#define MTD_SYNC(mtd) do { if (mtd->sync) (*(mtd->sync))(mtd); } while (0) + + +#ifdef CONFIG_MTD_PARTITIONS +void mtd_erase_callback(struct erase_info *instr); +#else +static inline void mtd_erase_callback(struct erase_info *instr) +{ + if (instr->callback) + instr->callback(instr); +} +#endif + +/* + * Debugging macro and defines + */ +#define MTD_DEBUG_LEVEL0 (0) /* Quiet */ +#define MTD_DEBUG_LEVEL1 (1) /* Audible */ +#define MTD_DEBUG_LEVEL2 (2) /* Loud */ +#define MTD_DEBUG_LEVEL3 (3) /* Noisy */ + +#ifdef CONFIG_MTD_DEBUG +#define DEBUG(n, args...) \ + do { \ + if (n <= CONFIG_MTD_DEBUG_VERBOSE) \ + printk(KERN_INFO args); \ + } while(0) +#else /* CONFIG_MTD_DEBUG */ +#define DEBUG(n, args...) do { } while(0) + +#endif /* CONFIG_MTD_DEBUG */ + +#endif /* __MTD_MTD_H__ */ diff --git a/u-boot/include/linux/posix_types.h b/u-boot/include/linux/posix_types.h new file mode 100755 index 0000000..bd37e1f --- /dev/null +++ b/u-boot/include/linux/posix_types.h @@ -0,0 +1,48 @@ +#ifndef _LINUX_POSIX_TYPES_H +#define _LINUX_POSIX_TYPES_H + +#include + +/* + * This allows for 1024 file descriptors: if NR_OPEN is ever grown + * beyond that you'll have to change this too. But 1024 fd's seem to be + * enough even for such "real" unices like OSF/1, so hopefully this is + * one limit that doesn't have to be changed [again]. + * + * Note that POSIX wants the FD_CLEAR(fd,fdsetp) defines to be in + * (and thus ) - but this is a more logical + * place for them. Solved by having dummy defines in . + */ + +/* + * Those macros may have been defined in . But we always + * use the ones here. + */ +#undef __NFDBITS +#define __NFDBITS (8 * sizeof(unsigned long)) + +#undef __FD_SETSIZE +#define __FD_SETSIZE 1024 + +#undef __FDSET_LONGS +#define __FDSET_LONGS (__FD_SETSIZE/__NFDBITS) + +#undef __FDELT +#define __FDELT(d) ((d) / __NFDBITS) + +#undef __FDMASK +#define __FDMASK(d) (1UL << ((d) % __NFDBITS)) + +typedef struct { + unsigned long fds_bits [__FDSET_LONGS]; +} __kernel_fd_set; + +/* Type of a signal handler. */ +typedef void (*__kernel_sighandler_t)(int); + +/* Type of a SYSV IPC key. */ +typedef int __kernel_key_t; + +#include + +#endif /* _LINUX_POSIX_TYPES_H */ diff --git a/u-boot/include/linux/stat.h b/u-boot/include/linux/stat.h new file mode 100755 index 0000000..f9422cb --- /dev/null +++ b/u-boot/include/linux/stat.h @@ -0,0 +1,132 @@ +#ifndef _LINUX_STAT_H +#define _LINUX_STAT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define S_IFMT 00170000 /* type of file */ +#define S_IFSOCK 0140000 /* named socket */ +#define S_IFLNK 0120000 /* symbolic link */ +#define S_IFREG 0100000 /* regular */ +#define S_IFBLK 0060000 /* block special */ +#define S_IFDIR 0040000 /* directory */ +#define S_IFCHR 0020000 /* character special */ +#define S_IFIFO 0010000 /* fifo */ +#define S_ISUID 0004000 /* set user id on execution */ +#define S_ISGID 0002000 /* set group id on execution */ +#define S_ISVTX 0001000 /* save swapped text even after use */ + +#define S_ISLNK(m) (((m) & S_IFMT) == S_IFLNK) +#define S_ISREG(m) (((m) & S_IFMT) == S_IFREG) +#define S_ISDIR(m) (((m) & S_IFMT) == S_IFDIR) +#define S_ISCHR(m) (((m) & S_IFMT) == S_IFCHR) +#define S_ISBLK(m) (((m) & S_IFMT) == S_IFBLK) +#define S_ISFIFO(m) (((m) & S_IFMT) == S_IFIFO) +#define S_ISSOCK(m) (((m) & S_IFMT) == S_IFSOCK) + +#define S_IRWXU 00700 /* rwx for owner */ +#define S_IRUSR 00400 /* read permission for owner */ +#define S_IWUSR 00200 /* write permission for owner */ +#define S_IXUSR 00100 /* execute/search permission for owner */ + +#define S_IRWXG 00070 /* rwx for group */ +#define S_IRGRP 00040 /* read permission for group */ +#define S_IWGRP 00020 /* write permission for group */ +#define S_IXGRP 00010 /* execute/search permission for group */ + +#define S_IRWXO 00007 /* rwx for other */ +#define S_IROTH 00004 /* read permission for other */ +#define S_IWOTH 00002 /* read permission for other */ +#define S_IXOTH 00001 /* execute/search permission for other */ + +#ifdef __PPC__ + +struct stat { + dev_t st_dev; /* file system id */ + ino_t st_ino; /* file id */ + mode_t st_mode; /* ownership/protection */ + nlink_t st_nlink; /* number of links */ + uid_t st_uid; /* user id */ + gid_t st_gid; /* group id */ + dev_t st_rdev; + off_t st_size; /* file size in # of bytes */ + unsigned long st_blksize; /* block size */ + unsigned long st_blocks; /* file size in # of blocks */ + unsigned long st_atime; /* time file was last accessed */ + unsigned long __unused1; + unsigned long st_mtime; /* time file was last modified */ + unsigned long __unused2; + unsigned long st_ctime; /* time file status was last changed */ + unsigned long __unused3; + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __PPC__ */ + +#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) + +struct stat { + unsigned short st_dev; + unsigned short __pad1; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned short __pad2; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long __unused1; + unsigned long st_mtime; + unsigned long __unused2; + unsigned long st_ctime; + unsigned long __unused3; + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __ARM__ */ + +#if defined (__MIPS__) + +struct stat { + dev_t st_dev; + long st_pad1[3]; + ino_t st_ino; + mode_t st_mode; + nlink_t st_nlink; + uid_t st_uid; + gid_t st_gid; + dev_t st_rdev; + long st_pad2[2]; + off_t st_size; + long st_pad3; + /* + * Actually this should be timestruc_t st_atime, st_mtime and st_ctime + * but we don't have it under Linux. + */ + time_t st_atime; + long reserved0; + time_t st_mtime; + long reserved1; + time_t st_ctime; + long reserved2; + long st_blksize; + long st_blocks; + long st_pad4[14]; +}; + +#endif /* __MIPS__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/u-boot/include/linux/stddef.h b/u-boot/include/linux/stddef.h new file mode 100755 index 0000000..81e34c2 --- /dev/null +++ b/u-boot/include/linux/stddef.h @@ -0,0 +1,18 @@ +#ifndef _LINUX_STDDEF_H +#define _LINUX_STDDEF_H + +#undef NULL +#if defined(__cplusplus) +#define NULL 0 +#else +#define NULL ((void *)0) +#endif + +#ifndef _SIZE_T +#include +#endif + +#undef offsetof +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +#endif diff --git a/u-boot/include/linux/string.h b/u-boot/include/linux/string.h new file mode 100755 index 0000000..1a45fd3 --- /dev/null +++ b/u-boot/include/linux/string.h @@ -0,0 +1,89 @@ +#ifndef _LINUX_STRING_H_ +#define _LINUX_STRING_H_ + +#include /* for size_t */ +#include /* for NULL */ + +#ifdef __cplusplus +extern "C" { +#endif + +extern char * ___strtok; +extern char * strpbrk(const char *,const char *); +extern char * strtok(char *,const char *); +extern char * strsep(char **,const char *); +extern __kernel_size_t strspn(const char *,const char *); + + +/* + * Include machine specific inline routines + */ +#include + +#ifndef __HAVE_ARCH_STRCPY +extern char * strcpy(char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRNCPY +extern char * strncpy(char *,const char *, __kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRCAT +extern char * strcat(char *, const char *); +#endif +#ifndef __HAVE_ARCH_STRNCAT +extern char * strncat(char *, const char *, __kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRCMP +extern int strcmp(const char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRNCMP +extern int strncmp(const char *,const char *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRNICMP +extern int strnicmp(const char *, const char *, __kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRCHR +extern char * strchr(const char *,int); +#endif +#ifndef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char *,int); +#endif +#ifndef __HAVE_ARCH_STRSTR +extern char * strstr(const char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRLEN +extern __kernel_size_t strlen(const char *); +#endif +#ifndef __HAVE_ARCH_STRNLEN +extern __kernel_size_t strnlen(const char *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_STRDUP +extern char * strdup(const char *); +#endif +#ifndef __HAVE_ARCH_STRSWAB +extern char * strswab(const char *); +#endif + +#ifndef __HAVE_ARCH_MEMSET +extern void * memset(void *,int,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *,const void *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *,const void *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMSCAN +extern void * memscan(void *,int,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMCMP +extern int memcmp(const void *,const void *,__kernel_size_t); +#endif +#ifndef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *,int,__kernel_size_t); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _LINUX_STRING_H_ */ diff --git a/u-boot/include/linux/time.h b/u-boot/include/linux/time.h new file mode 100755 index 0000000..bf12b99 --- /dev/null +++ b/u-boot/include/linux/time.h @@ -0,0 +1,158 @@ +#ifndef _LINUX_TIME_H +#define _LINUX_TIME_H + +#include + +#define _DEFUN(a,b,c) a(c) +#define _CONST const +#define _AND , + +#define _REENT_ONLY + +#define SECSPERMIN 60L +#define MINSPERHOUR 60L +#define HOURSPERDAY 24L +#define SECSPERHOUR (SECSPERMIN * MINSPERHOUR) +#define SECSPERDAY (SECSPERHOUR * HOURSPERDAY) +#define DAYSPERWEEK 7 +#define MONSPERYEAR 12 + +#define YEAR_BASE 1900 +#define EPOCH_YEAR 1970 +#define EPOCH_WDAY 4 + +#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) + + +/* Used by other time functions. */ +struct tm { + int tm_sec; /* Seconds. [0-60] (1 leap second) */ + int tm_min; /* Minutes. [0-59] */ + int tm_hour; /* Hours. [0-23] */ + int tm_mday; /* Day. [1-31] */ + int tm_mon; /* Month. [0-11] */ + int tm_year; /* Year - 1900. */ + int tm_wday; /* Day of week. [0-6] */ + int tm_yday; /* Days in year.[0-365] */ + int tm_isdst; /* DST. [-1/0/1]*/ + +# ifdef __USE_BSD + long int tm_gmtoff; /* Seconds east of UTC. */ + __const char *tm_zone; /* Timezone abbreviation. */ +# else + long int __tm_gmtoff; /* Seconds east of UTC. */ + __const char *__tm_zone; /* Timezone abbreviation. */ +# endif +}; + +static inline char * +_DEFUN (asctime_r, (tim_p, result), + _CONST struct tm *tim_p _AND + char *result) +{ + static _CONST char day_name[7][3] = { + "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" + }; + static _CONST char mon_name[12][3] = { + "Jan", "Feb", "Mar", "Apr", "May", "Jun", + "Jul", "Aug", "Sep", "Oct", "Nov", "Dec" + }; + + sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n", + day_name[tim_p->tm_wday], + mon_name[tim_p->tm_mon], + tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min, + tim_p->tm_sec, 1900 + tim_p->tm_year); + return result; +} + +static inline struct tm * +_DEFUN (localtime_r, (tim_p, res), + _CONST time_t * tim_p _AND + struct tm *res) +{ + static _CONST int mon_lengths[2][MONSPERYEAR] = { + {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, + {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31} + } ; + + static _CONST int year_lengths[2] = { + 365, + 366 + } ; + + long days, rem; + int y; + int yleap; + _CONST int *ip; + + days = ((long) *tim_p) / SECSPERDAY; + rem = ((long) *tim_p) % SECSPERDAY; + while (rem < 0) + { + rem += SECSPERDAY; + --days; + } + while (rem >= SECSPERDAY) + { + rem -= SECSPERDAY; + ++days; + } + + /* compute hour, min, and sec */ + res->tm_hour = (int) (rem / SECSPERHOUR); + rem %= SECSPERHOUR; + res->tm_min = (int) (rem / SECSPERMIN); + res->tm_sec = (int) (rem % SECSPERMIN); + + /* compute day of week */ + if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0) + res->tm_wday += DAYSPERWEEK; + + /* compute year & day of year */ + y = EPOCH_YEAR; + if (days >= 0) + { + for (;;) + { + yleap = isleap(y); + if (days < year_lengths[yleap]) + break; + y++; + days -= year_lengths[yleap]; + } + } + else + { + do + { + --y; + yleap = isleap(y); + days += year_lengths[yleap]; + } while (days < 0); + } + + res->tm_year = y - YEAR_BASE; + res->tm_yday = days; + ip = mon_lengths[yleap]; + for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon) + days -= ip[res->tm_mon]; + res->tm_mday = days + 1; + + /* set daylight saving time flag */ + res->tm_isdst = -1; + + return (res); +} + +static inline char * +_DEFUN (ctime_r, (tim_p, result), + _CONST time_t * tim_p _AND + char * result) + +{ + struct tm tm; + return asctime_r (localtime_r (tim_p, &tm), result); +} + +#endif diff --git a/u-boot/include/linux/types.h b/u-boot/include/linux/types.h new file mode 100755 index 0000000..df4808f --- /dev/null +++ b/u-boot/include/linux/types.h @@ -0,0 +1,130 @@ +#ifndef _LINUX_TYPES_H +#define _LINUX_TYPES_H + +#ifdef __KERNEL__ +#include +#endif + +#include +#include + +#ifndef __KERNEL_STRICT_NAMES + +typedef __kernel_fd_set fd_set; +typedef __kernel_dev_t dev_t; +typedef __kernel_ino_t ino_t; +typedef __kernel_mode_t mode_t; +typedef __kernel_nlink_t nlink_t; +typedef __kernel_off_t off_t; +typedef __kernel_pid_t pid_t; +typedef __kernel_daddr_t daddr_t; +typedef __kernel_key_t key_t; +typedef __kernel_suseconds_t suseconds_t; + +#ifdef __KERNEL__ +typedef __kernel_uid32_t uid_t; +typedef __kernel_gid32_t gid_t; +typedef __kernel_uid16_t uid16_t; +typedef __kernel_gid16_t gid16_t; + +#ifdef CONFIG_UID16 +/* This is defined by include/asm-{arch}/posix_types.h */ +typedef __kernel_old_uid_t old_uid_t; +typedef __kernel_old_gid_t old_gid_t; +#endif /* CONFIG_UID16 */ + +/* libc5 includes this file to define uid_t, thus uid_t can never change + * when it is included by non-kernel code + */ +#else +typedef __kernel_uid_t uid_t; +typedef __kernel_gid_t gid_t; +#endif /* __KERNEL__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __kernel_loff_t loff_t; +#endif + +/* + * The following typedefs are also protected by individual ifdefs for + * historical reasons: + */ +#ifndef _SIZE_T +#define _SIZE_T +typedef __kernel_size_t size_t; +#endif + +#ifndef _SSIZE_T +#define _SSIZE_T +typedef __kernel_ssize_t ssize_t; +#endif + +#ifndef _PTRDIFF_T +#define _PTRDIFF_T +typedef __kernel_ptrdiff_t ptrdiff_t; +#endif + +#ifndef _TIME_T +#define _TIME_T +typedef __kernel_time_t time_t; +#endif + +#ifndef _CLOCK_T +#define _CLOCK_T +typedef __kernel_clock_t clock_t; +#endif + +#ifndef _CADDR_T +#define _CADDR_T +typedef __kernel_caddr_t caddr_t; +#endif + +/* bsd */ +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; + +/* sysv */ +typedef unsigned char unchar; +typedef unsigned short ushort; +typedef unsigned int uint; +typedef unsigned long ulong; + +#ifndef __BIT_TYPES_DEFINED__ +#define __BIT_TYPES_DEFINED__ + +typedef __u8 u_int8_t; +typedef __s8 int8_t; +typedef __u16 u_int16_t; +typedef __s16 int16_t; +typedef __u32 u_int32_t; +typedef __s32 int32_t; + +#endif /* !(__BIT_TYPES_DEFINED__) */ + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + +#endif /* __KERNEL_STRICT_NAMES */ + +/* + * Below are truly Linux-specific types that should never collide with + * any application/library that wants linux/types.h. + */ + +struct ustat { + __kernel_daddr_t f_tfree; + __kernel_ino_t f_tinode; + char f_fname[6]; + char f_fpack[6]; +}; + +#endif /* _LINUX_TYPES_H */ diff --git a/u-boot/include/lists.h b/u-boot/include/lists.h new file mode 100755 index 0000000..804b5cd --- /dev/null +++ b/u-boot/include/lists.h @@ -0,0 +1,77 @@ +#ifndef _LISTS_H_ +#define _LISTS_H_ + +#define LIST_START -1 /* Handy Constants that substitute for item positions */ +#define LIST_END 0 /* END_OF_LIST means one past current length of list when */ + /* inserting. Otherwise it refers the last item in the list. */ + +typedef struct + { + void *ptr; + unsigned int size; + } HandleRecord; + +typedef void **Handle; + +typedef int (*CompareFunction)(void *data1, void *data2) ; + +typedef struct ListStructTag + { + int signature; /* debugging aid */ + int percentIncrease; /* %of current size to increase by when list is out of space */ + int minNumItemsIncrease; /* fixed number of items to increase by when list is out of space */ + int listSize; /* number of items than can fit in the currently allocated memory */ + int itemSize; /* the size of each item in the list (same for every item) */ + int numItems; /* number of items currently in the list */ + unsigned char itemList[1]; /* resizable array of list elements */ + } ListStruct; + +typedef struct ListStructTag **list_t; /* The list abstract data type */ +typedef int ( * ListApplicationFunc)(int index, void *ptrToItem, void *callbackData); + +/* Basic List Operations */ +list_t ListCreate(int elementSize); +int ListNumItems(list_t list); +int ListInsertItem(list_t list, void *ptrToItem, int itemPosition); +int ListInsertItems(list_t list, void *ptrToItems, int firstItemPosition, int numItemsToInsert); +void ListDispose(list_t list); +void *ListGetPtrToItem(list_t list, int itemPosition); +void ListRemoveItem(list_t list, void *itemDestination, int itemPosition); +void ListRemoveItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToRemove); + +#if 0 /* rarely ever used; kept here for reference just in case ... */ +void ListDisposePtrList(list_t list); +void ListGetItem(list_t list, void *itemDestination, int itemPosition); +void ListReplaceItem(list_t list, void *ptrToItem, int itemPosition); +void ListRemoveItem(list_t list, void *itemDestination, int itemPosition); +void ListGetItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToGet); +void ListReplaceItems(list_t list, void *ptrToItems, int firstItemPosition, int numItemsToReplace); +void ListRemoveItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToRemove); +list_t ListCopy(list_t originalList); +int ListAppend(list_t list1, list_t list2); +void ListClear(list_t list); +int ListEqual(list_t list1, list_t list2); +int ListInsertInOrder(list_t list, void *ptrToItem, CompareFunction compareFunction); +void *ListGetDataPtr(list_t list); +int ListApplyToEach(list_t list, int ascending, ListApplicationFunc funcToApply, void *callbackData); + +/* List Searching and Sorting */ +int ListFindItem(list_t list, void *ptrToItem, int startingPosition, CompareFunction compareFunction); +void ListRemoveDuplicates(list_t list, CompareFunction compareFunction); +int ListBinSearch(list_t list, void *itemPtr, CompareFunction compareFunction); +void ListQuickSort(list_t list, CompareFunction compareFunction); +void ListHeapSort(list_t list, CompareFunction compareFunction); +void ListInsertionSort(list_t list, CompareFunction compareFunction); +int ListIsSorted(list_t list, CompareFunction compareFunction); + +/* Advanced List Functions */ +void ListSetAllocationPolicy(list_t list, int minItemsPerAlloc, int percentIncreasePerAlloc); +void ListCompact(list_t list); +int ListPreAllocate(list_t list, int numItems); +int ListGetItemSize(list_t list); +int GetIntListFromParmInfo(va_list parmInfo, int numIntegers, list_t *integerList); +int ListInsertAfterItem(list_t list, void *ptrToItem, void *ptrToItemToInsertAfter, CompareFunction compareFunction); +int ListInsertBeforeItem(list_t list, void *ptrToItem, void *ptrToItemToInsertBefore, CompareFunction compareFunction); +#endif /* 0 */ + +#endif /* _LISTS_H_ */ diff --git a/u-boot/include/malloc.h b/u-boot/include/malloc.h new file mode 100755 index 0000000..47154b0 --- /dev/null +++ b/u-boot/include/malloc.h @@ -0,0 +1,942 @@ +/* + A version of malloc/free/realloc written by Doug Lea and released to the + public domain. Send questions/comments/complaints/performance data + to dl@cs.oswego.edu + +* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) + + Note: There may be an updated version of this malloc obtainable at + ftp://g.oswego.edu/pub/misc/malloc.c + Check before installing! + +* Why use this malloc? + + This is not the fastest, most space-conserving, most portable, or + most tunable malloc ever written. However it is among the fastest + while also being among the most space-conserving, portable and tunable. + Consistent balance across these factors results in a good general-purpose + allocator. For a high-level description, see + http://g.oswego.edu/dl/html/malloc.html + +* Synopsis of public routines + + (Much fuller descriptions are contained in the program documentation below.) + + malloc(size_t n); + Return a pointer to a newly allocated chunk of at least n bytes, or null + if no space is available. + free(Void_t* p); + Release the chunk of memory pointed to by p, or no effect if p is null. + realloc(Void_t* p, size_t n); + Return a pointer to a chunk of size n that contains the same data + as does chunk p up to the minimum of (n, p's size) bytes, or null + if no space is available. The returned pointer may or may not be + the same as p. If p is null, equivalent to malloc. Unless the + #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + memalign(size_t alignment, size_t n); + Return a pointer to a newly allocated chunk of n bytes, aligned + in accord with the alignment argument, which must be a power of + two. + valloc(size_t n); + Equivalent to memalign(pagesize, n), where pagesize is the page + size of the system (or as near to this as can be figured out from + all the includes/defines below.) + pvalloc(size_t n); + Equivalent to valloc(minimum-page-that-holds(n)), that is, + round up n to nearest pagesize. + calloc(size_t unit, size_t quantity); + Returns a pointer to quantity * unit bytes, with all locations + set to zero. + cfree(Void_t* p); + Equivalent to free(p). + malloc_trim(size_t pad); + Release all but pad bytes of freed top-most memory back + to the system. Return 1 if successful, else 0. + malloc_usable_size(Void_t* p); + Report the number usable allocated bytes associated with allocated + chunk p. This may or may not report more bytes than were requested, + due to alignment and minimum size constraints. + malloc_stats(); + Prints brief summary statistics on stderr. + mallinfo() + Returns (by copy) a struct containing various summary statistics. + mallopt(int parameter_number, int parameter_value) + Changes one of the tunable parameters described below. Returns + 1 if successful in changing the parameter, else 0. + +* Vital statistics: + + Alignment: 8-byte + 8 byte alignment is currently hardwired into the design. This + seems to suffice for all current machines and C compilers. + + Assumed pointer representation: 4 or 8 bytes + Code for 8-byte pointers is untested by me but has worked + reliably by Wolfram Gloger, who contributed most of the + changes supporting this. + + Assumed size_t representation: 4 or 8 bytes + Note that size_t is allowed to be 4 bytes even if pointers are 8. + + Minimum overhead per allocated chunk: 4 or 8 bytes + Each malloced chunk has a hidden overhead of 4 bytes holding size + and status information. + + Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead) + 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) + + When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte + ptrs but 4 byte size) or 24 (for 8/8) additional bytes are + needed; 4 (8) for a trailing size field + and 8 (16) bytes for free list pointers. Thus, the minimum + allocatable size is 16/24/32 bytes. + + Even a request for zero bytes (i.e., malloc(0)) returns a + pointer to something of the minimum allocatable size. + + Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes + 8-byte size_t: 2^63 - 16 bytes + + It is assumed that (possibly signed) size_t bit values suffice to + represent chunk sizes. `Possibly signed' is due to the fact + that `size_t' may be defined on a system as either a signed or + an unsigned type. To be conservative, values that would appear + as negative numbers are avoided. + Requests for sizes with a negative sign bit when the request + size is treaded as a long will return null. + + Maximum overhead wastage per allocated chunk: normally 15 bytes + + Alignnment demands, plus the minimum allocatable size restriction + make the normal worst-case wastage 15 bytes (i.e., up to 15 + more bytes will be allocated than were requested in malloc), with + two exceptions: + 1. Because requests for zero bytes allocate non-zero space, + the worst case wastage for a request of zero bytes is 24 bytes. + 2. For requests >= mmap_threshold that are serviced via + mmap(), the worst case wastage is 8 bytes plus the remainder + from a system page (the minimal mmap unit); typically 4096 bytes. + +* Limitations + + Here are some features that are NOT currently supported + + * No user-definable hooks for callbacks and the like. + * No automated mechanism for fully checking that all accesses + to malloced memory stay within their bounds. + * No support for compaction. + +* Synopsis of compile-time options: + + People have reported using previous versions of this malloc on all + versions of Unix, sometimes by tweaking some of the defines + below. It has been tested most extensively on Solaris and + Linux. It is also reported to work on WIN32 platforms. + People have also reported adapting this malloc for use in + stand-alone embedded systems. + + The implementation is in straight, hand-tuned ANSI C. Among other + consequences, it uses a lot of macros. Because of this, to be at + all usable, this code should be compiled using an optimizing compiler + (for example gcc -O2) that can simplify expressions and control + paths. + + __STD_C (default: derived from C compiler defines) + Nonzero if using ANSI-standard C compiler, a C++ compiler, or + a C compiler sufficiently close to ANSI to get away with it. + DEBUG (default: NOT defined) + Define to enable debugging. Adds fairly extensive assertion-based + checking to help track down memory errors, but noticeably slows down + execution. + REALLOC_ZERO_BYTES_FREES (default: NOT defined) + Define this if you think that realloc(p, 0) should be equivalent + to free(p). Otherwise, since malloc returns a unique pointer for + malloc(0), so does realloc(p, 0). + HAVE_MEMCPY (default: defined) + Define if you are not otherwise using ANSI STD C, but still + have memcpy and memset in your C library and want to use them. + Otherwise, simple internal versions are supplied. + USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise) + Define as 1 if you want the C library versions of memset and + memcpy called in realloc and calloc (otherwise macro versions are used). + At least on some platforms, the simple macro versions usually + outperform libc versions. + HAVE_MMAP (default: defined as 1) + Define to non-zero to optionally make malloc() use mmap() to + allocate very large blocks. + HAVE_MREMAP (default: defined as 0 unless Linux libc set) + Define to non-zero to optionally make realloc() use mremap() to + reallocate very large blocks. + malloc_getpagesize (default: derived from system #includes) + Either a constant or routine call returning the system page size. + HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined) + Optionally define if you are on a system with a /usr/include/malloc.h + that declares struct mallinfo. It is not at all necessary to + define this even if you do, but will ensure consistency. + INTERNAL_SIZE_T (default: size_t) + Define to a 32-bit type (probably `unsigned int') if you are on a + 64-bit machine, yet do not want or need to allow malloc requests of + greater than 2^31 to be handled. This saves space, especially for + very small chunks. + INTERNAL_LINUX_C_LIB (default: NOT defined) + Defined only when compiled as part of Linux libc. + Also note that there is some odd internal name-mangling via defines + (for example, internally, `malloc' is named `mALLOc') needed + when compiling in this case. These look funny but don't otherwise + affect anything. + WIN32 (default: undefined) + Define this on MS win (95, nt) platforms to compile in sbrk emulation. + LACKS_UNISTD_H (default: undefined if not WIN32) + Define this if your system does not have a . + LACKS_SYS_PARAM_H (default: undefined if not WIN32) + Define this if your system does not have a . + MORECORE (default: sbrk) + The name of the routine to call to obtain more memory from the system. + MORECORE_FAILURE (default: -1) + The value returned upon failure of MORECORE. + MORECORE_CLEARS (default 1) + True (1) if the routine mapped to MORECORE zeroes out memory (which + holds for sbrk). + DEFAULT_TRIM_THRESHOLD + DEFAULT_TOP_PAD + DEFAULT_MMAP_THRESHOLD + DEFAULT_MMAP_MAX + Default values of tunable parameters (described in detail below) + controlling interaction with host system routines (sbrk, mmap, etc). + These values may also be changed dynamically via mallopt(). The + preset defaults are those that give best performance for typical + programs/systems. + USE_DL_PREFIX (default: undefined) + Prefix all public routines with the string 'dl'. Useful to + quickly avoid procedure declaration conflicts and linker symbol + conflicts with existing memory allocation routines. + + +*/ + + + + +/* Preliminaries */ + +#ifndef __STD_C +#ifdef __STDC__ +#define __STD_C 1 +#else +#if __cplusplus +#define __STD_C 1 +#else +#define __STD_C 0 +#endif /*__cplusplus*/ +#endif /*__STDC__*/ +#endif /*__STD_C*/ + +#ifndef Void_t +#if (__STD_C || defined(WIN32)) +#define Void_t void +#else +#define Void_t char +#endif +#endif /*Void_t*/ + +#if __STD_C +#include /* for size_t */ +#else +#include +#endif /* __STD_C */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if 0 /* not for U-Boot */ +#include /* needed for malloc_stats */ +#endif + + +/* + Compile-time options +*/ + + +/* + Debugging: + + Because freed chunks may be overwritten with link fields, this + malloc will often die when freed memory is overwritten by user + programs. This can be very effective (albeit in an annoying way) + in helping track down dangling pointers. + + If you compile with -DDEBUG, a number of assertion checks are + enabled that will catch more memory errors. You probably won't be + able to make much sense of the actual assertion errors, but they + should help you locate incorrectly overwritten memory. The + checking is fairly extensive, and will slow down execution + noticeably. Calling malloc_stats or mallinfo with DEBUG set will + attempt to check every non-mmapped allocated and free chunk in the + course of computing the summmaries. (By nature, mmapped regions + cannot be checked very much automatically.) + + Setting DEBUG may also be helpful if you are trying to modify + this code. The assertions in the check routines spell out in more + detail the assumptions and invariants underlying the algorithms. + +*/ + +#ifdef DEBUG +/* #include */ +#define assert(x) ((void)0) +#else +#define assert(x) ((void)0) +#endif + + +/* + INTERNAL_SIZE_T is the word-size used for internal bookkeeping + of chunk sizes. On a 64-bit machine, you can reduce malloc + overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' + at the expense of not being able to handle requests greater than + 2^31. This limitation is hardly ever a concern; you are encouraged + to set this. However, the default version is the same as size_t. +*/ + +#ifndef INTERNAL_SIZE_T +#define INTERNAL_SIZE_T size_t +#endif + +/* + REALLOC_ZERO_BYTES_FREES should be set if a call to + realloc with zero bytes should be the same as a call to free. + Some people think it should. Otherwise, since this malloc + returns a unique pointer for malloc(0), so does realloc(p, 0). +*/ + + +/* #define REALLOC_ZERO_BYTES_FREES */ + + +/* + WIN32 causes an emulation of sbrk to be compiled in + mmap-based options are not currently supported in WIN32. +*/ + +/* #define WIN32 */ +#ifdef WIN32 +#define MORECORE wsbrk +#define HAVE_MMAP 0 + +#define LACKS_UNISTD_H +#define LACKS_SYS_PARAM_H + +/* + Include 'windows.h' to get the necessary declarations for the + Microsoft Visual C++ data structures and routines used in the 'sbrk' + emulation. + + Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft + Visual C++ header files are included. +*/ +#define WIN32_LEAN_AND_MEAN +#include +#endif + + +/* + HAVE_MEMCPY should be defined if you are not otherwise using + ANSI STD C, but still have memcpy and memset in your C library + and want to use them in calloc and realloc. Otherwise simple + macro versions are defined here. + + USE_MEMCPY should be defined as 1 if you actually want to + have memset and memcpy called. People report that the macro + versions are often enough faster than libc versions on many + systems that it is better to use them. + +*/ + +#define HAVE_MEMCPY + +#ifndef USE_MEMCPY +#ifdef HAVE_MEMCPY +#define USE_MEMCPY 1 +#else +#define USE_MEMCPY 0 +#endif +#endif + +#if (__STD_C || defined(HAVE_MEMCPY)) + +#if __STD_C +void* memset(void*, int, size_t); +void* memcpy(void*, const void*, size_t); +#else +#ifdef WIN32 +/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */ +/* 'windows.h' */ +#else +Void_t* memset(); +Void_t* memcpy(); +#endif +#endif +#endif + +#if USE_MEMCPY + +/* The following macros are only invoked with (2n+1)-multiples of + INTERNAL_SIZE_T units, with a positive integer n. This is exploited + for fast inline execution when n is small. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T mzsz = (nbytes); \ + if(mzsz <= 9*sizeof(mzsz)) { \ + INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \ + if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; }}} \ + *mz++ = 0; \ + *mz++ = 0; \ + *mz = 0; \ + } else memset((charp), 0, mzsz); \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T mcsz = (nbytes); \ + if(mcsz <= 9*sizeof(mcsz)) { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \ + if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; }}} \ + *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + *mcdst = *mcsrc ; \ + } else memcpy(dest, src, mcsz); \ +} while(0) + +#else /* !USE_MEMCPY */ + +/* Use Duff's device for good zeroing/copying performance. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mzp++ = 0; \ + case 7: *mzp++ = 0; \ + case 6: *mzp++ = 0; \ + case 5: *mzp++ = 0; \ + case 4: *mzp++ = 0; \ + case 3: *mzp++ = 0; \ + case 2: *mzp++ = 0; \ + case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mcdst++ = *mcsrc++; \ + case 7: *mcdst++ = *mcsrc++; \ + case 6: *mcdst++ = *mcsrc++; \ + case 5: *mcdst++ = *mcsrc++; \ + case 4: *mcdst++ = *mcsrc++; \ + case 3: *mcdst++ = *mcsrc++; \ + case 2: *mcdst++ = *mcsrc++; \ + case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#endif + + +/* + Define HAVE_MMAP to optionally make malloc() use mmap() to + allocate very large blocks. These will be returned to the + operating system immediately after a free(). +*/ + +/*** +#ifndef HAVE_MMAP +#define HAVE_MMAP 1 +#endif +***/ +#undef HAVE_MMAP /* Not available for U-Boot */ + +/* + Define HAVE_MREMAP to make realloc() use mremap() to re-allocate + large blocks. This is currently only possible on Linux with + kernel versions newer than 1.3.77. +*/ + +/*** +#ifndef HAVE_MREMAP +#ifdef INTERNAL_LINUX_C_LIB +#define HAVE_MREMAP 1 +#else +#define HAVE_MREMAP 0 +#endif +#endif +***/ +#undef HAVE_MREMAP /* Not available for U-Boot */ + +#if HAVE_MMAP + +#include +#include +#include + +#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON) +#define MAP_ANONYMOUS MAP_ANON +#endif + +#endif /* HAVE_MMAP */ + +/* + Access to system page size. To the extent possible, this malloc + manages memory from the system in page-size units. + + The following mechanics for getpagesize were adapted from + bsd/gnu getpagesize.h +*/ + +#define LACKS_UNISTD_H /* Shortcut for U-Boot */ +#define malloc_getpagesize 4096 + +#ifndef LACKS_UNISTD_H +# include +#endif + +#ifndef malloc_getpagesize +# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */ +# ifndef _SC_PAGE_SIZE +# define _SC_PAGE_SIZE _SC_PAGESIZE +# endif +# endif +# ifdef _SC_PAGE_SIZE +# define malloc_getpagesize sysconf(_SC_PAGE_SIZE) +# else +# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE) + extern size_t getpagesize(); +# define malloc_getpagesize getpagesize() +# else +# ifdef WIN32 +# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */ +# else +# ifndef LACKS_SYS_PARAM_H +# include +# endif +# ifdef EXEC_PAGESIZE +# define malloc_getpagesize EXEC_PAGESIZE +# else +# ifdef NBPG +# ifndef CLSIZE +# define malloc_getpagesize NBPG +# else +# define malloc_getpagesize (NBPG * CLSIZE) +# endif +# else +# ifdef NBPC +# define malloc_getpagesize NBPC +# else +# ifdef PAGESIZE +# define malloc_getpagesize PAGESIZE +# else +# define malloc_getpagesize (4096) /* just guess */ +# endif +# endif +# endif +# endif +# endif +# endif +# endif +#endif + + +/* + + This version of malloc supports the standard SVID/XPG mallinfo + routine that returns a struct containing the same kind of + information you can get from malloc_stats. It should work on + any SVID/XPG compliant system that has a /usr/include/malloc.h + defining struct mallinfo. (If you'd like to install such a thing + yourself, cut out the preliminary declarations as described above + and below and save them in a malloc.h file. But there's no + compelling reason to bother to do this.) + + The main declaration needed is the mallinfo struct that is returned + (by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a + bunch of fields, most of which are not even meaningful in this + version of malloc. Some of these fields are are instead filled by + mallinfo() with other numbers that might possibly be of interest. + + HAVE_USR_INCLUDE_MALLOC_H should be set if you have a + /usr/include/malloc.h file that includes a declaration of struct + mallinfo. If so, it is included; else an SVID2/XPG2 compliant + version is declared below. These must be precisely the same for + mallinfo() to work. + +*/ + +/* #define HAVE_USR_INCLUDE_MALLOC_H */ + +#if HAVE_USR_INCLUDE_MALLOC_H +#include "/usr/include/malloc.h" +#else + +/* SVID2/XPG mallinfo structure */ + +struct mallinfo { + int arena; /* total space allocated from system */ + int ordblks; /* number of non-inuse chunks */ + int smblks; /* unused -- always zero */ + int hblks; /* number of mmapped regions */ + int hblkhd; /* total space in mmapped regions */ + int usmblks; /* unused -- always zero */ + int fsmblks; /* unused -- always zero */ + int uordblks; /* total allocated space */ + int fordblks; /* total non-inuse space */ + int keepcost; /* top-most, releasable (via malloc_trim) space */ +}; + +/* SVID2/XPG mallopt options */ + +#define M_MXFAST 1 /* UNUSED in this malloc */ +#define M_NLBLKS 2 /* UNUSED in this malloc */ +#define M_GRAIN 3 /* UNUSED in this malloc */ +#define M_KEEP 4 /* UNUSED in this malloc */ + +#endif + +/* mallopt options that actually do something */ + +#define M_TRIM_THRESHOLD -1 +#define M_TOP_PAD -2 +#define M_MMAP_THRESHOLD -3 +#define M_MMAP_MAX -4 + + +#ifndef DEFAULT_TRIM_THRESHOLD +#define DEFAULT_TRIM_THRESHOLD (128 * 1024) +#endif + +/* + M_TRIM_THRESHOLD is the maximum amount of unused top-most memory + to keep before releasing via malloc_trim in free(). + + Automatic trimming is mainly useful in long-lived programs. + Because trimming via sbrk can be slow on some systems, and can + sometimes be wasteful (in cases where programs immediately + afterward allocate more large chunks) the value should be high + enough so that your overall system performance would improve by + releasing. + + The trim threshold and the mmap control parameters (see below) + can be traded off with one another. Trimming and mmapping are + two different ways of releasing unused memory back to the + system. Between these two, it is often possible to keep + system-level demands of a long-lived program down to a bare + minimum. For example, in one test suite of sessions measuring + the XF86 X server on Linux, using a trim threshold of 128K and a + mmap threshold of 192K led to near-minimal long term resource + consumption. + + If you are using this malloc in a long-lived program, it should + pay to experiment with these values. As a rough guide, you + might set to a value close to the average size of a process + (program) running on your system. Releasing this much memory + would allow such a process to run in memory. Generally, it's + worth it to tune for trimming rather tham memory mapping when a + program undergoes phases where several large chunks are + allocated and released in ways that can reuse each other's + storage, perhaps mixed with phases where there are no such + chunks at all. And in well-behaved long-lived programs, + controlling release of large blocks via trimming versus mapping + is usually faster. + + However, in most programs, these parameters serve mainly as + protection against the system-level effects of carrying around + massive amounts of unneeded memory. Since frequent calls to + sbrk, mmap, and munmap otherwise degrade performance, the default + parameters are set to relatively high values that serve only as + safeguards. + + The default trim value is high enough to cause trimming only in + fairly extreme (by current memory consumption standards) cases. + It must be greater than page size to have any useful effect. To + disable trimming completely, you can set to (unsigned long)(-1); + + +*/ + + +#ifndef DEFAULT_TOP_PAD +#define DEFAULT_TOP_PAD (0) +#endif + +/* + M_TOP_PAD is the amount of extra `padding' space to allocate or + retain whenever sbrk is called. It is used in two ways internally: + + * When sbrk is called to extend the top of the arena to satisfy + a new malloc request, this much padding is added to the sbrk + request. + + * When malloc_trim is called automatically from free(), + it is used as the `pad' argument. + + In both cases, the actual amount of padding is rounded + so that the end of the arena is always a system page boundary. + + The main reason for using padding is to avoid calling sbrk so + often. Having even a small pad greatly reduces the likelihood + that nearly every malloc request during program start-up (or + after trimming) will invoke sbrk, which needlessly wastes + time. + + Automatic rounding-up to page-size units is normally sufficient + to avoid measurable overhead, so the default is 0. However, in + systems where sbrk is relatively slow, it can pay to increase + this value, at the expense of carrying around more memory than + the program needs. + +*/ + + +#ifndef DEFAULT_MMAP_THRESHOLD +#define DEFAULT_MMAP_THRESHOLD (128 * 1024) +#endif + +/* + + M_MMAP_THRESHOLD is the request size threshold for using mmap() + to service a request. Requests of at least this size that cannot + be allocated using already-existing space will be serviced via mmap. + (If enough normal freed space already exists it is used instead.) + + Using mmap segregates relatively large chunks of memory so that + they can be individually obtained and released from the host + system. A request serviced through mmap is never reused by any + other request (at least not directly; the system may just so + happen to remap successive requests to the same locations). + + Segregating space in this way has the benefit that mmapped space + can ALWAYS be individually released back to the system, which + helps keep the system level memory demands of a long-lived + program low. Mapped memory can never become `locked' between + other chunks, as can happen with normally allocated chunks, which + menas that even trimming via malloc_trim would not release them. + + However, it has the disadvantages that: + + 1. The space cannot be reclaimed, consolidated, and then + used to service later requests, as happens with normal chunks. + 2. It can lead to more wastage because of mmap page alignment + requirements + 3. It causes malloc performance to be more dependent on host + system memory management support routines which may vary in + implementation quality and may impose arbitrary + limitations. Generally, servicing a request via normal + malloc steps is faster than going through a system's mmap. + + All together, these considerations should lead you to use mmap + only for relatively large requests. + + +*/ + + +#ifndef DEFAULT_MMAP_MAX +#if HAVE_MMAP +#define DEFAULT_MMAP_MAX (64) +#else +#define DEFAULT_MMAP_MAX (0) +#endif +#endif + +/* + M_MMAP_MAX is the maximum number of requests to simultaneously + service using mmap. This parameter exists because: + + 1. Some systems have a limited number of internal tables for + use by mmap. + 2. In most systems, overreliance on mmap can degrade overall + performance. + 3. If a program allocates many large regions, it is probably + better off using normal sbrk-based allocation routines that + can reclaim and reallocate normal heap memory. Using a + small value allows transition into this mode after the + first few allocations. + + Setting to 0 disables all use of mmap. If HAVE_MMAP is not set, + the default value is 0, and attempts to set it to non-zero values + in mallopt will fail. +*/ + + +/* + USE_DL_PREFIX will prefix all public routines with the string 'dl'. + Useful to quickly avoid procedure declaration conflicts and linker + symbol conflicts with existing memory allocation routines. + +*/ + +/* #define USE_DL_PREFIX */ + + +/* + + Special defines for linux libc + + Except when compiled using these special defines for Linux libc + using weak aliases, this malloc is NOT designed to work in + multithreaded applications. No semaphores or other concurrency + control are provided to ensure that multiple malloc or free calls + don't run at the same time, which could be disasterous. A single + semaphore could be used across malloc, realloc, and free (which is + essentially the effect of the linux weak alias approach). It would + be hard to obtain finer granularity. + +*/ + + +#ifdef INTERNAL_LINUX_C_LIB + +#if __STD_C + +Void_t * __default_morecore_init (ptrdiff_t); +Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init; + +#else + +Void_t * __default_morecore_init (); +Void_t *(*__morecore)() = __default_morecore_init; + +#endif + +#define MORECORE (*__morecore) +#define MORECORE_FAILURE 0 +#define MORECORE_CLEARS 1 + +#else /* INTERNAL_LINUX_C_LIB */ + +#if __STD_C +extern Void_t* sbrk(ptrdiff_t); +#else +extern Void_t* sbrk(); +#endif + +#ifndef MORECORE +#define MORECORE sbrk +#endif + +#ifndef MORECORE_FAILURE +#define MORECORE_FAILURE -1 +#endif + +#ifndef MORECORE_CLEARS +#define MORECORE_CLEARS 1 +#endif + +#endif /* INTERNAL_LINUX_C_LIB */ + +#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__) + +#define cALLOc __libc_calloc +#define fREe __libc_free +#define mALLOc __libc_malloc +#define mEMALIGn __libc_memalign +#define rEALLOc __libc_realloc +#define vALLOc __libc_valloc +#define pvALLOc __libc_pvalloc +#define mALLINFo __libc_mallinfo +#define mALLOPt __libc_mallopt + +#pragma weak calloc = __libc_calloc +#pragma weak free = __libc_free +#pragma weak cfree = __libc_free +#pragma weak malloc = __libc_malloc +#pragma weak memalign = __libc_memalign +#pragma weak realloc = __libc_realloc +#pragma weak valloc = __libc_valloc +#pragma weak pvalloc = __libc_pvalloc +#pragma weak mallinfo = __libc_mallinfo +#pragma weak mallopt = __libc_mallopt + +#else + +#ifdef USE_DL_PREFIX +#define cALLOc dlcalloc +#define fREe dlfree +#define mALLOc dlmalloc +#define mEMALIGn dlmemalign +#define rEALLOc dlrealloc +#define vALLOc dlvalloc +#define pvALLOc dlpvalloc +#define mALLINFo dlmallinfo +#define mALLOPt dlmallopt +#else /* USE_DL_PREFIX */ +#define cALLOc calloc +#define fREe free +#define mALLOc malloc +#define mEMALIGn memalign +#define rEALLOc realloc +#define vALLOc valloc +#define pvALLOc pvalloc +#define mALLINFo mallinfo +#define mALLOPt mallopt +#endif /* USE_DL_PREFIX */ + +#endif + +/* Public routines */ + +#if __STD_C + +Void_t* mALLOc(size_t); +void fREe(Void_t*); +Void_t* rEALLOc(Void_t*, size_t); +Void_t* mEMALIGn(size_t, size_t); +Void_t* vALLOc(size_t); +Void_t* pvALLOc(size_t); +Void_t* cALLOc(size_t, size_t); +void cfree(Void_t*); +int malloc_trim(size_t); +size_t malloc_usable_size(Void_t*); +void malloc_stats(void); +int mALLOPt(int, int); +struct mallinfo mALLINFo(void); +#else +Void_t* mALLOc(); +void fREe(); +Void_t* rEALLOc(); +Void_t* mEMALIGn(); +Void_t* vALLOc(); +Void_t* pvALLOc(); +Void_t* cALLOc(); +void cfree(); +int malloc_trim(); +size_t malloc_usable_size(); +void malloc_stats(); +int mALLOPt(); +struct mallinfo mALLINFo(); +#endif + + +#ifdef __cplusplus +}; /* end of extern "C" */ +#endif diff --git a/u-boot/include/miiphy.h b/u-boot/include/miiphy.h new file mode 100755 index 0000000..48c59e9 --- /dev/null +++ b/u-boot/include/miiphy.h @@ -0,0 +1,148 @@ +/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ +| +| File Name: miiphy.h +| +| Function: Include file defining PHY registers. +| +| Author: Mark Wisner +| +| Change Activity- +| +| Date Description of Change BY +| --------- --------------------- --- +| 04-May-99 Created MKW +| 07-Jul-99 Added full duplex support MKW +| 08-Sep-01 Tweaks gvb +| ++----------------------------------------------------------------------------*/ +#ifndef _miiphy_h_ +#define _miiphy_h_ + +#include + +int miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value); +int miiphy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value); +int miiphy_info(char *devname, unsigned char addr, unsigned int *oui, unsigned char *model, unsigned char *rev); +int miiphy_reset(char *devname, unsigned char addr); +int miiphy_speed(char *devname, unsigned char addr); +int miiphy_duplex(char *devname, unsigned char addr); + +void miiphy_init(void); + +void miiphy_register(char *devname, int (* read)(char *devname, unsigned char addr, unsigned char reg, unsigned short *value), int (* write)(char *devname, unsigned char addr, unsigned char reg, unsigned short value)); + +int miiphy_set_current_dev(char *devname); +char *miiphy_get_current_dev(void); + +void miiphy_listdev(void); + +#define BB_MII_DEVNAME "bbmii" + +int bb_miiphy_read (char *devname, unsigned char addr, unsigned char reg, unsigned short *value); +int bb_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); + +/* phy speed setup */ +#define AUTO 99 +#define _1000BASET 1000 +#define _100BASET 100 +#define _10BASET 10 +#define HALF 22 +#define FULL 44 + +/* phy register offsets */ +#define PHY_BMCR 0x00 +#define PHY_BMSR 0x01 +#define PHY_PHYIDR1 0x02 +#define PHY_PHYIDR2 0x03 +#define PHY_ANAR 0x04 +#define PHY_ANLPAR 0x05 +#define PHY_ANER 0x06 +#define PHY_ANNPTR 0x07 +#define PHY_ANLPNP 0x08 +#define PHY_1000BTCR 0x09 +#define PHY_1000BTSR 0x0A +#define PHY_PHYSTS 0x10 +#define PHY_MIPSCR 0x11 +#define PHY_MIPGSR 0x12 +#define PHY_DCR 0x13 +#define PHY_FCSCR 0x14 +#define PHY_RECR 0x15 +#define PHY_PCSR 0x16 +#define PHY_LBR 0x17 +#define PHY_10BTSCR 0x18 +#define PHY_PHYCTRL 0x19 + +/* PHY BMCR */ +#define PHY_BMCR_RESET 0x8000 +#define PHY_BMCR_LOOP 0x4000 +#define PHY_BMCR_100MB 0x2000 +#define PHY_BMCR_AUTON 0x1000 +#define PHY_BMCR_POWD 0x0800 +#define PHY_BMCR_ISO 0x0400 +#define PHY_BMCR_RST_NEG 0x0200 +#define PHY_BMCR_DPLX 0x0100 +#define PHY_BMCR_COL_TST 0x0080 + +#define PHY_BMCR_SPEED_MASK 0x2040 +#define PHY_BMCR_1000_MBPS 0x0040 +#define PHY_BMCR_100_MBPS 0x2000 +#define PHY_BMCR_10_MBPS 0x0000 + +/* phy BMSR */ +#define PHY_BMSR_100T4 0x8000 +#define PHY_BMSR_100TXF 0x4000 +#define PHY_BMSR_100TXH 0x2000 +#define PHY_BMSR_10TF 0x1000 +#define PHY_BMSR_10TH 0x0800 +#define PHY_BMSR_PRE_SUP 0x0040 +#define PHY_BMSR_AUTN_COMP 0x0020 +#define PHY_BMSR_RF 0x0010 +#define PHY_BMSR_AUTN_ABLE 0x0008 +#define PHY_BMSR_LS 0x0004 +#define PHY_BMSR_JD 0x0002 +#define PHY_BMSR_EXT 0x0001 + +/*phy ANLPAR */ +#define PHY_ANLPAR_NP 0x8000 +#define PHY_ANLPAR_ACK 0x4000 +#define PHY_ANLPAR_RF 0x2000 +#define PHY_ANLPAR_T4 0x0200 +#define PHY_ANLPAR_TXFD 0x0100 +#define PHY_ANLPAR_TX 0x0080 +#define PHY_ANLPAR_10FD 0x0040 +#define PHY_ANLPAR_10 0x0020 +#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ + +#define PHY_ANLPAR_PSB_MASK 0x001f +#define PHY_ANLPAR_PSB_802_3 0x0001 +#define PHY_ANLPAR_PSB_802_9 0x0002 + +/* PHY_1000BTSR */ +#define PHY_1000BTSR_MSCF 0x8000 +#define PHY_1000BTSR_MSCR 0x4000 +#define PHY_1000BTSR_LRS 0x2000 +#define PHY_1000BTSR_RRS 0x1000 +#define PHY_1000BTSR_1000FD 0x0800 +#define PHY_1000BTSR_1000HD 0x0400 + +#endif diff --git a/u-boot/include/net.h b/u-boot/include/net.h new file mode 100755 index 0000000..a72b29a --- /dev/null +++ b/u-boot/include/net.h @@ -0,0 +1,493 @@ +/* + * LiMon Monitor (LiMon) - Network. + * + * Copyright 1994 - 2000 Neil Russell. + * (See License) + * + * + * History + * 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added + */ + +#ifndef __NET_H__ +#define __NET_H__ + +#if defined(CONFIG_8xx) +#include +# if !defined(CONFIG_NET_MULTI) +# if defined(FEC_ENET) || defined(SCC_ENET) +# define CONFIG_NET_MULTI +# endif +# endif +#endif /* CONFIG_8xx */ + +#if defined(CONFIG_MPC5xxx) +# if !defined(CONFIG_NET_MULTI) +# if defined(CONFIG_MPC5xxx_FEC) +# define CONFIG_NET_MULTI +# endif +# endif +#endif /* CONFIG_MPC5xxx */ + +#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_CPM2) +#include +#if defined(CONFIG_ETHER_ON_FCC) +#if defined(CONFIG_ETHER_ON_SCC) +#error "Ethernet not correctly defined" +#endif /* CONFIG_ETHER_ON_SCC */ +#define CONFIG_NET_MULTI +#if (CONFIG_ETHER_INDEX == 1) +#define CONFIG_ETHER_ON_FCC1 +# define CFG_CMXFCR_MASK1 CFG_CMXFCR_MASK +# define CFG_CMXFCR_VALUE1 CFG_CMXFCR_VALUE +#elif (CONFIG_ETHER_INDEX == 2) +#define CONFIG_ETHER_ON_FCC2 +# define CFG_CMXFCR_MASK2 CFG_CMXFCR_MASK +# define CFG_CMXFCR_VALUE2 CFG_CMXFCR_VALUE +#elif (CONFIG_ETHER_INDEX == 3) +#define CONFIG_ETHER_ON_FCC3 +# define CFG_CMXFCR_MASK3 CFG_CMXFCR_MASK +# define CFG_CMXFCR_VALUE3 CFG_CMXFCR_VALUE +#endif /* CONFIG_ETHER_INDEX */ +#endif /* CONFIG_ETHER_ON_FCC */ +#endif /* !CONFIG_NET_MULTI && CONFIG_8260 */ + +#include /* for nton* / ntoh* stuff */ + + +/* + * The number of receive packet buffers, and the required packet buffer + * alignment in memory. + * + */ + +#ifdef CFG_RX_ETH_BUFFER +# define PKTBUFSRX CFG_RX_ETH_BUFFER +#else +# define PKTBUFSRX 4 +#endif + +#define PKTALIGN 32 + +typedef ulong IPaddr_t; + + +/* + * The current receive packet handler. Called with a pointer to the + * application packet, and a protocol type (PORT_BOOTPC or PORT_TFTP). + * All other packets are dealt with without calling the handler. + */ +typedef void rxhand_f(uchar *, unsigned, unsigned, unsigned); + +/* + * A timeout handler. Called after time interval has expired. + */ +typedef void thand_f(void); + +#define NAMESIZE 16 + +enum eth_state_t { + ETH_STATE_INIT, + ETH_STATE_PASSIVE, + ETH_STATE_ACTIVE +}; + +struct eth_device { + char name[NAMESIZE]; + unsigned char enetaddr[6]; + int iobase; + int state; + + int (*init) (struct eth_device*, bd_t*); + int (*send) (struct eth_device*, volatile void* pachet, int length); + int (*recv) (struct eth_device*); + void (*halt) (struct eth_device*); + + struct eth_device *next; + void *priv; +}; + +extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */ +extern int eth_register(struct eth_device* dev);/* Register network device */ +extern void eth_try_another(int first_restart); /* Change the device */ +#ifdef CONFIG_NET_MULTI +extern void eth_set_current(void); /* set nterface to ethcur var. */ +#endif + + +//extern struct eth_device *eth_get_dev(void); /* get the current device MAC */ +/* get the current device MAC */ +static inline __attribute__((always_inline)) +struct eth_device *eth_get_dev(void){ + extern struct eth_device *eth_current; + return eth_current; +} + + +extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */ +extern int eth_get_dev_index (void); /* get the device index */ +extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */ + +extern int eth_init(bd_t *bis); /* Initialize the device */ +extern int eth_send(volatile void *packet, int length); /* Send a packet */ +extern int eth_rx(void); /* Check for received packets */ +extern void eth_halt(void); /* stop SCC */ +extern char *eth_get_name(void); /* get name of current device */ + +/**********************************************************************/ +/* + * Protocol headers. + */ + +/* + * Ethernet header + */ +typedef struct { + uchar et_dest[6]; /* Destination node */ + uchar et_src[6]; /* Source node */ + ushort et_protlen; /* Protocol or length */ + uchar et_dsap; /* 802 DSAP */ + uchar et_ssap; /* 802 SSAP */ + uchar et_ctl; /* 802 control */ + uchar et_snap1; /* SNAP */ + uchar et_snap2; + uchar et_snap3; + ushort et_prot; /* 802 protocol */ +} Ethernet_t; + +#define ETHER_HDR_SIZE 14 /* Ethernet header size */ +#define E802_HDR_SIZE 22 /* 802 ethernet header size */ + +/* + * Ethernet header + */ +typedef struct { + uchar vet_dest[6]; /* Destination node */ + uchar vet_src[6]; /* Source node */ + ushort vet_vlan_type; /* PROT_VLAN */ + ushort vet_tag; /* TAG of VLAN */ + ushort vet_type; /* protocol type */ +} VLAN_Ethernet_t; + +#define VLAN_ETHER_HDR_SIZE 18 /* VLAN Ethernet header size */ + +#define PROT_IP 0x0800 /* IP protocol */ +#define PROT_ARP 0x0806 /* IP ARP protocol */ +#define PROT_RARP 0x8035 /* IP ARP protocol */ +#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */ + +#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */ +#define IPPROTO_UDP 17 /* User Datagram Protocol */ + +/* + * Internet Protocol (IP) header. + */ +typedef struct { + uchar ip_hl_v; /* header length and version */ + uchar ip_tos; /* type of service */ + ushort ip_len; /* total length */ + ushort ip_id; /* identification */ + ushort ip_off; /* fragment offset field */ + uchar ip_ttl; /* time to live */ + uchar ip_p; /* protocol */ + ushort ip_sum; /* checksum */ + IPaddr_t ip_src; /* Source IP address */ + IPaddr_t ip_dst; /* Destination IP address */ + ushort udp_src; /* UDP source port */ + ushort udp_dst; /* UDP destination port */ + ushort udp_len; /* Length of UDP packet */ + ushort udp_xsum; /* Checksum */ +} IP_t; + +#define IP_HDR_SIZE_NO_UDP (sizeof (IP_t) - 8) +#define IP_HDR_SIZE (sizeof (IP_t)) + + +/* + * Address Resolution Protocol (ARP) header. + */ +typedef struct +{ + ushort ar_hrd; /* Format of hardware address */ +# define ARP_ETHER 1 /* Ethernet hardware address */ + ushort ar_pro; /* Format of protocol address */ + uchar ar_hln; /* Length of hardware address */ + uchar ar_pln; /* Length of protocol address */ + ushort ar_op; /* Operation */ +# define ARPOP_REQUEST 1 /* Request to resolve address */ +# define ARPOP_REPLY 2 /* Response to previous request */ + +# define RARPOP_REQUEST 3 /* Request to resolve address */ +# define RARPOP_REPLY 4 /* Response to previous request */ + + /* + * The remaining fields are variable in size, according to + * the sizes above, and are defined as appropriate for + * specific hardware/protocol combinations. + */ + uchar ar_data[0]; +} ARP_t; + +#define ARP_HDR_SIZE (8+20) /* Size assuming ethernet */ + +/* + * ICMP stuff (just enough to handle (host) redirect messages) + */ +#define ICMP_ECHO_REPLY 0 /* Echo reply */ +#define ICMP_REDIRECT 5 /* Redirect (change route) */ +#define ICMP_ECHO_REQUEST 8 /* Echo request */ + +/* Codes for REDIRECT. */ +#define ICMP_REDIR_NET 0 /* Redirect Net */ +#define ICMP_REDIR_HOST 1 /* Redirect Host */ + +typedef struct icmphdr { + uchar type; + uchar code; + ushort checksum; + union { + struct { + ushort id; + ushort sequence; + } echo; + ulong gateway; + struct { + ushort __unused; + ushort mtu; + } frag; + } un; +} ICMP_t; + + +/* + * Maximum packet size; used to allocate packet storage. + * TFTP packets can be 524 bytes + IP header + ethernet header. + * Lets be conservative, and go for 38 * 16. (Must also be + * a multiple of 32 bytes). + */ +/* + * AS.HARNOIS : Better to set PKTSIZE to maximum size because + * traffic type is not always controlled + * maximum packet size = 1518 + * maximum packet size and multiple of 32 bytes = 1536 + */ +#ifdef CFG_ATHRHDR_EN +#define PKTSIZE 1520 +#else +#define PKTSIZE 1518 +#endif +#define PKTSIZE_ALIGN 1536 +/*#define PKTSIZE 608*/ + +/* + * Maximum receive ring size; that is, the number of packets + * we can buffer before overflow happens. Basically, this just + * needs to be enough to prevent a packet being discarded while + * we are processing the previous one. + */ +#define RINGSZ 4 +#define RINGSZ_LOG2 2 + +/**********************************************************************/ +/* + * Globals. + * + * Note: + * + * All variables of type IPaddr_t are stored in NETWORK byte order + * (big endian). + */ + +/* net.c */ +/** BOOTP EXTENTIONS **/ +extern IPaddr_t NetOurGatewayIP; /* Our gateway IP addresse */ +extern IPaddr_t NetOurSubnetMask; /* Our subnet mask (0 = unknown)*/ +extern IPaddr_t NetOurDNSIP; /* Our Domain Name Server (0 = unknown)*/ +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +extern IPaddr_t NetOurDNS2IP; /* Our 2nd Domain Name Server (0 = unknown)*/ +#endif +extern char NetOurNISDomain[32]; /* Our NIS domain */ +extern char NetOurHostName[32]; /* Our hostname */ +extern char NetOurRootPath[64]; /* Our root path */ +extern ushort NetBootFileSize; /* Our boot file size in blocks */ +/** END OF BOOTP EXTENTIONS **/ +extern ulong NetBootFileXferSize; /* size of bootfile in bytes */ +extern uchar NetOurEther[6]; /* Our ethernet address */ +extern uchar NetServerEther[6]; /* Boot server enet address */ +extern IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */ +extern IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */ +extern volatile uchar * NetTxPacket; /* THE transmit packet */ +extern volatile uchar * NetRxPackets[PKTBUFSRX];/* Receive packets */ +extern volatile uchar * NetRxPkt; /* Current receive packet */ +extern int NetRxPktLen; /* Current rx packet length */ +extern unsigned NetIPID; /* IP ID (counting) */ +extern uchar NetBcastAddr[6]; /* Ethernet boardcast address */ +extern uchar NetEtherNullAddr[6]; + +#define VLAN_NONE 4095 /* untagged */ +#define VLAN_IDMASK 0x0fff /* mask of valid vlan id */ +extern ushort NetOurVLAN; /* Our VLAN */ +extern ushort NetOurNativeVLAN; /* Our Native VLAN */ + +extern uchar NetCDPAddr[6]; /* Ethernet CDP address */ +extern ushort CDPNativeVLAN; /* CDP returned native VLAN */ +extern ushort CDPApplianceVLAN; /* CDP returned appliance VLAN */ + +extern int NetState; /* Network loop state */ +#define NETLOOP_CONTINUE 1 +#define NETLOOP_RESTART 2 +#define NETLOOP_SUCCESS 3 +#define NETLOOP_FAIL 4 + +#ifdef CONFIG_NET_MULTI +extern int NetRestartWrap; /* Tried all network devices */ +#endif + +typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP } proto_t; + +/* Set active state */ +static inline __attribute__((always_inline)) int eth_init_state_only(bd_t *bis){ + eth_get_dev()->state = ETH_STATE_ACTIVE; + return 0; +} + + +/* Set passive state */ +static inline __attribute__((always_inline)) void eth_halt_state_only(void){ + eth_get_dev()->state = ETH_STATE_PASSIVE; +} + +static inline void eth_set_last_protocol(int protocol){ +#ifdef CONFIG_NETCONSOLE + extern proto_t net_loop_last_protocol; + net_loop_last_protocol = protocol; +#endif +} + +static inline __attribute__((always_inline)) int eth_is_on_demand_init(void){ +#ifdef CONFIG_NETCONSOLE + extern proto_t net_loop_last_protocol; + return net_loop_last_protocol != NETCONS; +#else + return 1; +#endif +} + + +/* from net/net.c */ +extern char BootFile[128]; /* Boot File name */ + +#if (CONFIG_COMMANDS & CFG_CMD_PING) +extern IPaddr_t NetPingIP; /* the ip address to ping */ +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */ +extern int NetTimeOffset; /* offset time from UTC */ +#endif + +/* Initialize the network adapter */ +extern int NetLoop(proto_t); +extern int NetLoopHttpd(void); +extern void NetSendHttpd(void); + +/* Shutdown adapters and cleanup */ +extern void NetStop(void); + +/* Load failed. Start again. */ +extern void NetStartAgain(void); + +/* Get size of the ethernet header when we send */ +extern int NetEthHdrSize(void); + +/* Set ethernet header; returns the size of the header */ +extern int NetSetEther(volatile uchar *, uchar *, uint); + +/* Set IP header */ +extern void NetSetIP(volatile uchar *, IPaddr_t, int, int, int); + +/* Checksum */ +extern int NetCksumOk(uchar *, int); /* Return true if cksum OK */ +extern uint NetCksum(uchar *, int); /* Calculate the checksum */ + +/* Set callbacks */ +extern void NetSetHandler(rxhand_f *); /* Set RX packet handler */ +extern void NetSetTimeout(ulong, thand_f *);/* Set timeout handler */ + +/* Transmit "NetTxPacket" */ +extern void NetSendPacket(volatile uchar *, int); + +/* Transmit UDP packet, performing ARP request if needed */ +extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len); + +/* Processes a received packet */ +extern void NetReceive(volatile uchar *, int); + +/* Print an IP address on the console */ +extern void print_IPaddr (IPaddr_t); + +/* + * The following functions are a bit ugly, but necessary to deal with + * alignment restrictions on ARM. + * + * We're using inline functions, which had the smallest memory + * footprint in our tests. + */ +/* return IP *in network byteorder* */ +static inline IPaddr_t NetReadIP(void *from) +{ + IPaddr_t ip; + memcpy((void*)&ip, from, sizeof(ip)); + return ip; +} + +/* return ulong *in network byteorder* */ +static inline ulong NetReadLong(ulong *from) +{ + ulong l; + memcpy((void*)&l, (void*)from, sizeof(l)); + return l; +} + +/* write IP *in network byteorder* */ +static inline void NetWriteIP(void *to, IPaddr_t ip) +{ + memcpy(to, (void*)&ip, sizeof(ip)); +} + +/* copy IP */ +static inline void NetCopyIP(void *to, void *from) +{ + memcpy(to, from, sizeof(IPaddr_t)); +} + +/* copy ulong */ +static inline void NetCopyLong(ulong *to, ulong *from) +{ + memcpy((void*)to, (void*)from, sizeof(ulong)); +} + +/* Convert an IP address to a string */ +extern void ip_to_string (IPaddr_t x, char *s); + +/* Convert a string to ip address */ +extern IPaddr_t string_to_ip(char *s); + +/* Convert a VLAN id to a string */ +extern void VLAN_to_string (ushort x, char *s); + +/* Convert a string to a vlan id */ +extern ushort string_to_VLAN(char *s); + +/* read an IP address from a environment variable */ +extern IPaddr_t getenv_IPaddr (char *); + +/* read a VLAN id from an environment variable */ +extern ushort getenv_VLAN(char *); + +/* copy a filename (allow for "..." notation, limit length) */ +extern void copy_filename (char *dst, char *src, int size); + +/**********************************************************************/ + +#endif /* __NET_H__ */ diff --git a/u-boot/include/pci.h b/u-boot/include/pci.h new file mode 100755 index 0000000..6e09b16 --- /dev/null +++ b/u-boot/include/pci.h @@ -0,0 +1,376 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * aloong with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PCI_H +#define _PCI_H + +/* + * Under PCI, each device has 256 bytes of configuration address space, + * of which the first 64 bytes are standardized as follows: + */ +#define PCI_VENDOR_ID 0x00 /* 16 bits */ +#define PCI_DEVICE_ID 0x02 /* 16 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ + +#define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ +#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ +#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ +#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ +#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ +#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ +#define PCI_STATUS_DEVSEL_FAST 0x000 +#define PCI_STATUS_DEVSEL_MEDIUM 0x200 +#define PCI_STATUS_DEVSEL_SLOW 0x400 +#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ +#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ +#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ +#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ +#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ + +#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 + revision */ +#define PCI_REVISION_ID 0x08 /* Revision ID */ +#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ +#define PCI_CLASS_DEVICE 0x0a /* Device class */ +#define PCI_CLASS_CODE 0x0b /* Device class code */ +#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ + +#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ +#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ +#define PCI_HEADER_TYPE 0x0e /* 8 bits */ +#define PCI_HEADER_TYPE_NORMAL 0 +#define PCI_HEADER_TYPE_BRIDGE 1 +#define PCI_HEADER_TYPE_CARDBUS 2 + +#define PCI_BIST 0x0f /* 8 bits */ +#define PCI_BIST_CODE_MASK 0x0f /* Return result */ +#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ +#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ + +/* + * Base addresses specify locations in memory or I/O space. + * Decoded size can be determined by writing a value of + * 0xffffffff to the register, and reading it back. Only + * 1 bits are decoded. + */ +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 +#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ +#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ +#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ +#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ +#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) +#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) +/* bit 1 is reserved if address_space = 1 */ + +/* Header type 0 (normal devices) */ +#define PCI_CARDBUS_CIS 0x28 +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c +#define PCI_SUBSYSTEM_ID 0x2e +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 +#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) + +#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ + +/* 0x35-0x3b are reserved */ +#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ +#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ +#define PCI_MIN_GNT 0x3e /* 8 bits */ +#define PCI_MAX_LAT 0x3f /* 8 bits */ + +/* Header type 1 (PCI-to-PCI bridges) */ +#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ +#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ +#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ +#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ +#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ +#define PCI_IO_LIMIT 0x1d +#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ +#define PCI_IO_RANGE_TYPE_16 0x00 +#define PCI_IO_RANGE_TYPE_32 0x01 +#define PCI_IO_RANGE_MASK ~0x0f +#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ +#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ +#define PCI_MEMORY_LIMIT 0x22 +#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f +#define PCI_MEMORY_RANGE_MASK ~0x0f +#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ +#define PCI_PREF_MEMORY_LIMIT 0x26 +#define PCI_PREF_RANGE_TYPE_MASK 0x0f +#define PCI_PREF_RANGE_TYPE_32 0x00 +#define PCI_PREF_RANGE_TYPE_64 0x01 +#define PCI_PREF_RANGE_MASK ~0x0f +#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ +#define PCI_PREF_LIMIT_UPPER32 0x2c +#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ +#define PCI_IO_LIMIT_UPPER16 0x32 +/* 0x34 same as for htype 0 */ +/* 0x35-0x3b is reserved */ +#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_BRIDGE_CONTROL 0x3e +#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ +#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ +#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ +#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ +#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ +#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ +#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ + +/* From 440ep */ +#define PCI_ERREN 0x48 /* Error Enable */ +#define PCI_ERRSTS 0x49 /* Error Status */ +#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ +#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ +#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ +#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ +#define PCI_CAPID 0x58 /* Capability Identifier */ +#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ +#define PCI_PMC 0x5A /* Power Management Capabilities */ +#define PCI_PMCSR 0x5C /* Power Management Control Status */ +#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ +#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ +#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ + +/* Header type 2 (CardBus bridges) */ +#define PCI_CB_CAPABILITY_LIST 0x14 +/* 0x15 reserved */ +#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ +#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ +#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ +#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ +#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ +#define PCI_CB_MEMORY_BASE_0 0x1c +#define PCI_CB_MEMORY_LIMIT_0 0x20 +#define PCI_CB_MEMORY_BASE_1 0x24 +#define PCI_CB_MEMORY_LIMIT_1 0x28 +#define PCI_CB_IO_BASE_0 0x2c +#define PCI_CB_IO_BASE_0_HI 0x2e +#define PCI_CB_IO_LIMIT_0 0x30 +#define PCI_CB_IO_LIMIT_0_HI 0x32 +#define PCI_CB_IO_BASE_1 0x34 +#define PCI_CB_IO_BASE_1_HI 0x36 +#define PCI_CB_IO_LIMIT_1 0x38 +#define PCI_CB_IO_LIMIT_1_HI 0x3a +#define PCI_CB_IO_RANGE_MASK ~0x03 +/* 0x3c-0x3d are same as for htype 0 */ +#define PCI_CB_BRIDGE_CONTROL 0x3e +#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ +#define PCI_CB_BRIDGE_CTL_SERR 0x02 +#define PCI_CB_BRIDGE_CTL_ISA 0x04 +#define PCI_CB_BRIDGE_CTL_VGA 0x08 +#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 +#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ +#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ +#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 +#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 +#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 +#define PCI_CB_SUBSYSTEM_ID 0x42 +#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ +/* 0x48-0x7f reserved */ + +/* Capability lists */ + +#define PCI_CAP_LIST_ID 0 /* Capability ID */ +#define PCI_CAP_ID_PM 0x01 /* Power Management */ +#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ +#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ +#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ +#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ +#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ +#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ +#define PCI_CAP_SIZEOF 4 + +/* Power Management Registers */ + +#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ +#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ +#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ +#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ +#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ +#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ +#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ +#define PCI_PM_CTRL 4 /* PM control and status register */ +#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ +#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ +#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ +#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ +#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ +#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ +#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ +#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ +#define PCI_PM_DATA_REGISTER 7 /* (??) */ +#define PCI_PM_SIZEOF 8 + +/* AGP registers */ + +#define PCI_AGP_VERSION 2 /* BCD version number */ +#define PCI_AGP_RFU 3 /* Rest of capability flags */ +#define PCI_AGP_STATUS 4 /* Status register */ +#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ +#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ +#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ +#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ +#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ +#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ +#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ +#define PCI_AGP_COMMAND 8 /* Control register */ +#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ +#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ +#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ +#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ +#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ +#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ +#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ +#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ +#define PCI_AGP_SIZEOF 12 + +/* Slot Identification */ + +#define PCI_SID_ESR 2 /* Expansion Slot Register */ +#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ +#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ +#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ + +/* Message Signalled Interrupts registers */ + +#define PCI_MSI_FLAGS 2 /* Various flags */ +#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ +#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ +#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ +#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ +#define PCI_MSI_RFU 3 /* Rest of capability flags */ +#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ +#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ +#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ +#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ + +#define PCI_MAX_PCI_DEVICES 32 +#define PCI_MAX_PCI_FUNCTIONS 8 + +/* Include the ID list */ + +#include + +struct pci_region { + unsigned long bus_start; /* Start on the bus */ + unsigned long phys_start; /* Start in physical address space */ + unsigned long size; /* Size */ + unsigned long flags; /* Resource flags */ + + unsigned long bus_lower; +}; + +#define PCI_REGION_MEM 0x00000000 /* PCI memory space */ +#define PCI_REGION_IO 0x00000001 /* PCI IO space */ +#define PCI_REGION_TYPE 0x00000001 +#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ + +#define PCI_REGION_MEMORY 0x00000100 /* System memory */ +#define PCI_REGION_RO 0x00000200 /* Read-only memory */ + +typedef int pci_dev_t; + +#define PCI_BUS(d) (((d) >> 16) & 0xff) +#define PCI_DEV(d) (((d) >> 11) & 0x1f) +#define PCI_FUNC(d) (((d) >> 8) & 0x7) +#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) + +#define PCI_ANY_ID (~0) + +struct pci_controller; + +struct pci_config_table { + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ + unsigned int class; /* Class ID, or PCI_ANY_ID */ + unsigned int bus; /* Bus number, or PCI_ANY_ID */ + unsigned int dev; /* Device number, or PCI_ANY_ID */ + unsigned int func; /* Function number, or PCI_ANY_ID */ + + void (*config_device)(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); + unsigned long priv[3]; +}; + +#define MAX_PCI_REGIONS 7 + +/* + * Structure of a PCI controller (host bridge) + */ +struct pci_controller { + struct pci_controller *next; + + int first_busno; + int last_busno; + + volatile unsigned int *cfg_addr; + volatile unsigned char *cfg_data; + + struct pci_region regions[MAX_PCI_REGIONS]; + int region_count; + + struct pci_config_table *config_table; + + void (*fixup_irq)(struct pci_controller *, pci_dev_t); + + /* Low-level architecture-dependent routines */ + int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); + int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); + int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); + int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); + int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); + int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); + + /* Used by auto config */ + struct pci_region *pci_mem, *pci_io, *pci_prefetch; + + /* Used by ppc405 autoconfig*/ + struct pci_region *pci_fb; + int current_busno; +}; + +#endif /* _PCI_H */ diff --git a/u-boot/include/pci_ids.h b/u-boot/include/pci_ids.h new file mode 100755 index 0000000..777a450 --- /dev/null +++ b/u-boot/include/pci_ids.h @@ -0,0 +1,2049 @@ +/* + * PCI Class, Vendor and Device IDs + * + * Please keep sorted. + */ + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_3D 0x0302 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 +#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_SCANNER 0x0903 +#define PCI_CLASS_INPUT_GAMEPORT 0x0904 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a80 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_BASE_CLASS_SATELLITE 0x0f +#define PCI_CLASS_SATELLITE_TV 0x0f00 +#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 +#define PCI_CLASS_SATELLITE_VOICE 0x0f03 +#define PCI_CLASS_SATELLITE_DATA 0x0f04 + +#define PCI_BASE_CLASS_CRYPT 0x10 +#define PCI_CLASS_CRYPT_NETWORK 0x1000 +#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 +#define PCI_CLASS_CRYPT_OTHER 0x1080 + +#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 +#define PCI_CLASS_SP_DPIO 0x1100 +#define PCI_CLASS_SP_OTHER 0x1180 + +#define PCI_CLASS_OTHERS 0xff + +/* Vendors and devices. Sort key: vendor first, device next. */ + +#define PCI_VENDOR_ID_DYNALINK 0x0675 +#define PCI_DEVICE_ID_DYNALINK_IS64PH 0x1702 + +#define PCI_VENDOR_ID_BERKOM 0x0871 +#define PCI_DEVICE_ID_BERKOM_A1T 0xffa1 +#define PCI_DEVICE_ID_BERKOM_T_CONCEPT 0xffa2 +#define PCI_DEVICE_ID_BERKOM_A4T 0xffa4 +#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO 0xffa8 + +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 +#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 +#define PCI_DEVICE_ID_COMPAQ_6010 0x6010 +#define PCI_DEVICE_ID_COMPAQ_TACHYON 0xa0fc +#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 +#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33 +#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 +#define PCI_DEVICE_ID_COMPAQ_CISS 0xb060 +#define PCI_DEVICE_ID_COMPAQ_CISSB 0xb178 +#define PCI_DEVICE_ID_COMPAQ_CISSC 0x0046 +#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 + +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_VENDOR_ID_LSI_LOGIC 0x1000 +#define PCI_DEVICE_ID_NCR_53C810 0x0001 +#define PCI_DEVICE_ID_NCR_53C820 0x0002 +#define PCI_DEVICE_ID_NCR_53C825 0x0003 +#define PCI_DEVICE_ID_NCR_53C815 0x0004 +#define PCI_DEVICE_ID_LSI_53C810AP 0x0005 +#define PCI_DEVICE_ID_NCR_53C860 0x0006 +#define PCI_DEVICE_ID_LSI_53C1510 0x000a +#define PCI_DEVICE_ID_NCR_53C896 0x000b +#define PCI_DEVICE_ID_NCR_53C895 0x000c +#define PCI_DEVICE_ID_NCR_53C885 0x000d +#define PCI_DEVICE_ID_NCR_53C875 0x000f +#define PCI_DEVICE_ID_NCR_53C1510 0x0010 +#define PCI_DEVICE_ID_LSI_53C895A 0x0012 +#define PCI_DEVICE_ID_LSI_53C875A 0x0013 +#define PCI_DEVICE_ID_LSI_53C1010_33 0x0020 +#define PCI_DEVICE_ID_LSI_53C1010_66 0x0021 +#define PCI_DEVICE_ID_LSI_53C1030 0x0030 +#define PCI_DEVICE_ID_LSI_53C1035 0x0040 +#define PCI_DEVICE_ID_NCR_53C875J 0x008f +#define PCI_DEVICE_ID_LSI_FC909 0x0621 +#define PCI_DEVICE_ID_LSI_FC929 0x0622 +#define PCI_DEVICE_ID_LSI_FC929_LAN 0x0623 +#define PCI_DEVICE_ID_LSI_FC919 0x0624 +#define PCI_DEVICE_ID_LSI_FC919_LAN 0x0625 +#define PCI_DEVICE_ID_LSI_FC929X 0x0626 +#define PCI_DEVICE_ID_LSI_FC919X 0x0628 +#define PCI_DEVICE_ID_NCR_YELLOWFIN 0x0701 +#define PCI_DEVICE_ID_LSI_61C102 0x0901 +#define PCI_DEVICE_ID_LSI_63C815 0x1000 + +#define PCI_VENDOR_ID_ATI 0x1002 +/* Mach64 */ +#define PCI_DEVICE_ID_ATI_68800 0x4158 +#define PCI_DEVICE_ID_ATI_215CT222 0x4354 +#define PCI_DEVICE_ID_ATI_210888CX 0x4358 +#define PCI_DEVICE_ID_ATI_215ET222 0x4554 +/* Mach64 / Rage */ +#define PCI_DEVICE_ID_ATI_215GB 0x4742 +#define PCI_DEVICE_ID_ATI_215GD 0x4744 +#define PCI_DEVICE_ID_ATI_215GI 0x4749 +#define PCI_DEVICE_ID_ATI_215GP 0x4750 +#define PCI_DEVICE_ID_ATI_215GQ 0x4751 +#define PCI_DEVICE_ID_ATI_215XL 0x4752 +#define PCI_DEVICE_ID_ATI_215GT 0x4754 +#define PCI_DEVICE_ID_ATI_215GTB 0x4755 +#define PCI_DEVICE_ID_ATI_215_IV 0x4756 +#define PCI_DEVICE_ID_ATI_215_IW 0x4757 +#define PCI_DEVICE_ID_ATI_215_IZ 0x475A +#define PCI_DEVICE_ID_ATI_210888GX 0x4758 +#define PCI_DEVICE_ID_ATI_215_LB 0x4c42 +#define PCI_DEVICE_ID_ATI_215_LD 0x4c44 +#define PCI_DEVICE_ID_ATI_215_LG 0x4c47 +#define PCI_DEVICE_ID_ATI_215_LI 0x4c49 +#define PCI_DEVICE_ID_ATI_215_LM 0x4c4D +#define PCI_DEVICE_ID_ATI_215_LN 0x4c4E +#define PCI_DEVICE_ID_ATI_215_LR 0x4c52 +#define PCI_DEVICE_ID_ATI_215_LS 0x4c53 +#define PCI_DEVICE_ID_ATI_264_LT 0x4c54 +/* Mach64 VT */ +#define PCI_DEVICE_ID_ATI_264VT 0x5654 +#define PCI_DEVICE_ID_ATI_264VU 0x5655 +#define PCI_DEVICE_ID_ATI_264VV 0x5656 +/* Rage128 Pro GL */ +#define PCI_DEVICE_ID_ATI_Rage128_PA 0x5041 +#define PCI_DEVICE_ID_ATI_Rage128_PB 0x5042 +#define PCI_DEVICE_ID_ATI_Rage128_PC 0x5043 +#define PCI_DEVICE_ID_ATI_Rage128_PD 0x5044 +#define PCI_DEVICE_ID_ATI_Rage128_PE 0x5045 +#define PCI_DEVICE_ID_ATI_RAGE128_PF 0x5046 +/* Rage128 Pro VR */ +#define PCI_DEVICE_ID_ATI_RAGE128_PG 0x5047 +#define PCI_DEVICE_ID_ATI_RAGE128_PH 0x5048 +#define PCI_DEVICE_ID_ATI_RAGE128_PI 0x5049 +#define PCI_DEVICE_ID_ATI_RAGE128_PJ 0x504A +#define PCI_DEVICE_ID_ATI_RAGE128_PK 0x504B +#define PCI_DEVICE_ID_ATI_RAGE128_PL 0x504C +#define PCI_DEVICE_ID_ATI_RAGE128_PM 0x504D +#define PCI_DEVICE_ID_ATI_RAGE128_PN 0x504E +#define PCI_DEVICE_ID_ATI_RAGE128_PO 0x504F +#define PCI_DEVICE_ID_ATI_RAGE128_PP 0x5050 +#define PCI_DEVICE_ID_ATI_RAGE128_PQ 0x5051 +#define PCI_DEVICE_ID_ATI_RAGE128_PR 0x5052 +#define PCI_DEVICE_ID_ATI_RAGE128_TR 0x5452 +#define PCI_DEVICE_ID_ATI_RAGE128_PS 0x5053 +#define PCI_DEVICE_ID_ATI_RAGE128_PT 0x5054 +#define PCI_DEVICE_ID_ATI_RAGE128_PU 0x5055 +#define PCI_DEVICE_ID_ATI_RAGE128_PV 0x5056 +#define PCI_DEVICE_ID_ATI_RAGE128_PW 0x5057 +#define PCI_DEVICE_ID_ATI_RAGE128_PX 0x5058 +/* Rage128 GL */ +#define PCI_DEVICE_ID_ATI_RAGE128_RE 0x5245 +#define PCI_DEVICE_ID_ATI_RAGE128_RF 0x5246 +#define PCI_DEVICE_ID_ATI_RAGE128_RG 0x534b +#define PCI_DEVICE_ID_ATI_RAGE128_RH 0x534c +#define PCI_DEVICE_ID_ATI_RAGE128_RI 0x534d +/* Rage128 VR */ +#define PCI_DEVICE_ID_ATI_RAGE128_RK 0x524b +#define PCI_DEVICE_ID_ATI_RAGE128_RL 0x524c +#define PCI_DEVICE_ID_ATI_RAGE128_RM 0x5345 +#define PCI_DEVICE_ID_ATI_RAGE128_RN 0x5346 +#define PCI_DEVICE_ID_ATI_RAGE128_RO 0x5347 +/* Rage128 M3 */ +#define PCI_DEVICE_ID_ATI_RAGE128_LE 0x4c45 +#define PCI_DEVICE_ID_ATI_RAGE128_LF 0x4c46 +/* Rage128 Pro Ultra */ +#define PCI_DEVICE_ID_ATI_RAGE128_U1 0x5446 +#define PCI_DEVICE_ID_ATI_RAGE128_U2 0x544C +#define PCI_DEVICE_ID_ATI_RAGE128_U3 0x5452 +/* Rage M4 */ +#define PCI_DEVICE_ID_ATI_RADEON_LE 0x4d45 +#define PCI_DEVICE_ID_ATI_RADEON_LF 0x4d46 +/* Radeon R100 */ +#define PCI_DEVICE_ID_ATI_RADEON_QD 0x5144 +#define PCI_DEVICE_ID_ATI_RADEON_QE 0x5145 +#define PCI_DEVICE_ID_ATI_RADEON_QF 0x5146 +#define PCI_DEVICE_ID_ATI_RADEON_QG 0x5147 +/* Radeon RV100 (VE) */ +#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 +#define PCI_DEVICE_ID_ATI_RADEON_QZ 0x515a +/* Radeon R200 (8500) */ +#define PCI_DEVICE_ID_ATI_RADEON_QL 0x514c +#define PCI_DEVICE_ID_ATI_RADEON_QN 0x514e +#define PCI_DEVICE_ID_ATI_RADEON_QO 0x514f +#define PCI_DEVICE_ID_ATI_RADEON_Ql 0x516c +#define PCI_DEVICE_ID_ATI_RADEON_BB 0x4242 +/* Radeon R200 (9100) */ +#define PCI_DEVICE_ID_ATI_RADEON_QM 0x514d +/* Radeon RV200 (7500) */ +#define PCI_DEVICE_ID_ATI_RADEON_QW 0x5157 +#define PCI_DEVICE_ID_ATI_RADEON_QX 0x5158 +/* Radeon RV250 (9000) */ +#define PCI_DEVICE_ID_ATI_RADEON_Id 0x4964 +#define PCI_DEVICE_ID_ATI_RADEON_Ie 0x4965 +#define PCI_DEVICE_ID_ATI_RADEON_If 0x4966 +#define PCI_DEVICE_ID_ATI_RADEON_Ig 0x4967 +/* Radeon RV280 (9200) */ +#define PCI_DEVICE_ID_ATI_RADEON_Y_ 0x5960 +#define PCI_DEVICE_ID_ATI_RADEON_Ya 0x5961 +#define PCI_DEVICE_ID_ATI_RADEON_Yd 0x5964 +/* Radeon R300 (9700) */ +#define PCI_DEVICE_ID_ATI_RADEON_ND 0x4e44 +#define PCI_DEVICE_ID_ATI_RADEON_NE 0x4e45 +#define PCI_DEVICE_ID_ATI_RADEON_NF 0x4e46 +#define PCI_DEVICE_ID_ATI_RADEON_NG 0x4e47 +#define PCI_DEVICE_ID_ATI_RADEON_AE 0x4145 +#define PCI_DEVICE_ID_ATI_RADEON_AF 0x4146 +/* Radeon R300 (9500) */ +#define PCI_DEVICE_ID_ATI_RADEON_AD 0x4144 +/* Radeon R350 (9800) */ +#define PCI_DEVICE_ID_ATI_RADEON_NH 0x4e48 +#define PCI_DEVICE_ID_ATI_RADEON_NI 0x4e49 +/* Radeon RV350 (9600) */ +#define PCI_DEVICE_ID_ATI_RADEON_AP 0x4150 +#define PCI_DEVICE_ID_ATI_RADEON_AR 0x4152 +/* Radeon M6 */ +#define PCI_DEVICE_ID_ATI_RADEON_LY 0x4c59 +#define PCI_DEVICE_ID_ATI_RADEON_LZ 0x4c5a +/* Radeon M7 */ +#define PCI_DEVICE_ID_ATI_RADEON_LW 0x4c57 +#define PCI_DEVICE_ID_ATI_RADEON_LX 0x4c58 +/* Radeon M9 */ +#define PCI_DEVICE_ID_ATI_RADEON_Ld 0x4c64 +#define PCI_DEVICE_ID_ATI_RADEON_Le 0x4c65 +#define PCI_DEVICE_ID_ATI_RADEON_Lf 0x4c66 +#define PCI_DEVICE_ID_ATI_RADEON_Lg 0x4c67 +/* RadeonIGP */ +#define PCI_DEVICE_ID_ATI_RADEON_IGP 0xCAB0 +/* ATI IXP Chipset */ +#define PCI_DEVICE_ID_ATI_IXP_IDE 0x4349 + +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_DEVICE_ID_VLSI_82C592 0x0005 +#define PCI_DEVICE_ID_VLSI_82C593 0x0006 +#define PCI_DEVICE_ID_VLSI_82C594 0x0007 +#define PCI_DEVICE_ID_VLSI_82C597 0x0009 +#define PCI_DEVICE_ID_VLSI_82C541 0x000c +#define PCI_DEVICE_ID_VLSI_82C543 0x000d +#define PCI_DEVICE_ID_VLSI_82C532 0x0101 +#define PCI_DEVICE_ID_VLSI_82C534 0x0102 +#define PCI_DEVICE_ID_VLSI_82C535 0x0104 +#define PCI_DEVICE_ID_VLSI_82C147 0x0105 +#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 + +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_DEVICE_ID_ADL_2301 0x2301 + +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_DEVICE_ID_NS_87415 0x0002 +#define PCI_DEVICE_ID_NS_87560_LIO 0x000e +#define PCI_DEVICE_ID_NS_87560_USB 0x0012 +#define PCI_DEVICE_ID_NS_83815 0x0020 +#define PCI_DEVICE_ID_NS_83820 0x0022 +#define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 +#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 +#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 +#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 +#define PCI_DEVICE_ID_NS_87410 0xd001 + +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 +#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 +#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 +#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 +#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 + +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 +#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 + +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_DEVICE_ID_DEC_BRD 0x0001 +#define PCI_DEVICE_ID_DEC_TULIP 0x0002 +#define PCI_DEVICE_ID_DEC_TGA 0x0004 +#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 +#define PCI_DEVICE_ID_DEC_TGA2 0x000D +#define PCI_DEVICE_ID_DEC_FDDI 0x000F +#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 +#define PCI_DEVICE_ID_DEC_21142 0x0019 +#define PCI_DEVICE_ID_DEC_21052 0x0021 +#define PCI_DEVICE_ID_DEC_21150 0x0022 +#define PCI_DEVICE_ID_DEC_21152 0x0024 +#define PCI_DEVICE_ID_DEC_21153 0x0025 +#define PCI_DEVICE_ID_DEC_21154 0x0026 +#define PCI_DEVICE_ID_DEC_21285 0x1065 +#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 + +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 +#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 +#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 +#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 +#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac +#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 +#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc +#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 +#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 +#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 +#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 +#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 + +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a +#define PCI_DEVICE_ID_IBM_TR 0x0018 +#define PCI_DEVICE_ID_IBM_82G2675 0x001d +#define PCI_DEVICE_ID_IBM_MCA 0x0020 +#define PCI_DEVICE_ID_IBM_82351 0x0022 +#define PCI_DEVICE_ID_IBM_PYTHON 0x002d +#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e +#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e +#define PCI_DEVICE_ID_IBM_MPIC 0x0046 +#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d +#define PCI_DEVICE_ID_IBM_CHUKAR 0x0096 +#define PCI_DEVICE_ID_IBM_CPC700 0x00f9 +#define PCI_DEVICE_ID_IBM_CPC710_PCI64 0x00fc +#define PCI_DEVICE_ID_IBM_CPC710_PCI32 0x0105 +#define PCI_DEVICE_ID_IBM_405GP 0x0156 +#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd +#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff + +#define PCI_VENDOR_ID_COMPEX2 0x101a /* pci.ids says "AT&T GIS (NCR)" */ +#define PCI_DEVICE_ID_COMPEX2_100VG 0x0005 + +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_DEVICE_ID_WD_7197 0x3296 +#define PCI_DEVICE_ID_WD_90C 0xc24a + +#define PCI_VENDOR_ID_AMI 0x101e +#define PCI_DEVICE_ID_AMI_MEGARAID3 0x1960 +#define PCI_DEVICE_ID_AMI_MEGARAID 0x9010 +#define PCI_DEVICE_ID_AMI_MEGARAID2 0x9060 + +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 +#define PCI_DEVICE_ID_AMD_SERENADE 0x36c0 +#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 +#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 +#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C +#define PCI_DEVICE_ID_AMD_FE_GATE_700D 0x700D +#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E +#define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F +#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 +#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 +#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403 +#define PCI_DEVICE_ID_AMD_COBRA_7404 0x7404 +#define PCI_DEVICE_ID_AMD_VIPER_7408 0x7408 +#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 +#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B +#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C +#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 +#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 +#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 +#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 +#define PCI_DEVICE_ID_AMD_OPUS_7440 0x7440 +# define PCI_DEVICE_ID_AMD_VIPER_7440 PCI_DEVICE_ID_AMD_OPUS_7440 +#define PCI_DEVICE_ID_AMD_OPUS_7441 0x7441 +# define PCI_DEVICE_ID_AMD_VIPER_7441 PCI_DEVICE_ID_AMD_OPUS_7441 +#define PCI_DEVICE_ID_AMD_OPUS_7443 0x7443 +# define PCI_DEVICE_ID_AMD_VIPER_7443 PCI_DEVICE_ID_AMD_OPUS_7443 +#define PCI_DEVICE_ID_AMD_OPUS_7448 0x7448 +# define PCI_DEVICE_ID_AMD_VIPER_7448 PCI_DEVICE_ID_AMD_OPUS_7448 +#define PCI_DEVICE_ID_AMD_OPUS_7449 0x7449 +# define PCI_DEVICE_ID_AMD_VIPER_7449 PCI_DEVICE_ID_AMD_OPUS_7449 +#define PCI_DEVICE_ID_AMD_8111_LAN 0x7462 +#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 +#define PCI_DEVICE_ID_AMD_8111_AC97 0x746d +#define PCI_DEVICE_ID_AMD_8131_APIC 0x7450 + +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 +#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001 +#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 +#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 +#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 +#define PCI_DEVICE_ID_TRIDENT_939A 0x939A +#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 +#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 +#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 +#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 +#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 +#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 +#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 +#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 +#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 +#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 +#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 + +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_DEVICE_ID_AI_M1435 0x1435 + +#define PCI_VENDOR_ID_DELL 0x1028 + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 +#define PCI_DEVICE_ID_MATROX_MIL 0x0519 +#define PCI_DEVICE_ID_MATROX_MYS 0x051A +#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f +#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 +#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 +#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 +#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 +#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 +#define PCI_DEVICE_ID_MATROX_G400 0x0525 +#define PCI_DEVICE_ID_MATROX_G550 0x2527 +#define PCI_DEVICE_ID_MATROX_VIA 0x4536 + +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_DEVICE_ID_CT_65545 0x00d8 +#define PCI_DEVICE_ID_CT_65548 0x00dc +#define PCI_DEVICE_ID_CT_65550 0x00e0 +#define PCI_DEVICE_ID_CT_65554 0x00e4 +#define PCI_DEVICE_ID_CT_65555 0x00e5 +#define PCI_DEVICE_ID_CT_69000 0x00c0 +#define PCI_DEVICE_ID_CT_69030 0x0c30 + +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_DEVICE_ID_MIRO_36050 0x5601 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e +#define PCI_DEVICE_ID_NEC_PCX2 0x0046 +#define PCI_DEVICE_ID_NEC_NILE4 0x005a +#define PCI_DEVICE_ID_NEC_VRC5476 0x009b +#define PCI_DEVICE_ID_NEC_VRC4173 0x00a5 +#define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6 + +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_DEVICE_ID_FD_36C70 0x0000 + +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 +#define PCI_DEVICE_ID_SI_6202 0x0002 +#define PCI_DEVICE_ID_SI_503 0x0008 +#define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_180 0x0180 +#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 +#define PCI_DEVICE_ID_SI_6205 0x0205 +#define PCI_DEVICE_ID_SI_501 0x0406 +#define PCI_DEVICE_ID_SI_496 0x0496 +#define PCI_DEVICE_ID_SI_300 0x0300 +#define PCI_DEVICE_ID_SI_315H 0x0310 +#define PCI_DEVICE_ID_SI_315 0x0315 +#define PCI_DEVICE_ID_SI_315PRO 0x0325 +#define PCI_DEVICE_ID_SI_530 0x0530 +#define PCI_DEVICE_ID_SI_540 0x0540 +#define PCI_DEVICE_ID_SI_550 0x0550 +#define PCI_DEVICE_ID_SI_540_VGA 0x5300 +#define PCI_DEVICE_ID_SI_550_VGA 0x5315 +#define PCI_DEVICE_ID_SI_601 0x0601 +#define PCI_DEVICE_ID_SI_620 0x0620 +#define PCI_DEVICE_ID_SI_630 0x0630 +#define PCI_DEVICE_ID_SI_633 0x0633 +#define PCI_DEVICE_ID_SI_635 0x0635 +#define PCI_DEVICE_ID_SI_640 0x0640 +#define PCI_DEVICE_ID_SI_645 0x0645 +#define PCI_DEVICE_ID_SI_646 0x0646 +#define PCI_DEVICE_ID_SI_648 0x0648 +#define PCI_DEVICE_ID_SI_650 0x0650 +#define PCI_DEVICE_ID_SI_651 0x0651 +#define PCI_DEVICE_ID_SI_652 0x0652 +#define PCI_DEVICE_ID_SI_655 0x0655 +#define PCI_DEVICE_ID_SI_730 0x0730 +#define PCI_DEVICE_ID_SI_733 0x0733 +#define PCI_DEVICE_ID_SI_630_VGA 0x6300 +#define PCI_DEVICE_ID_SI_730_VGA 0x7300 +#define PCI_DEVICE_ID_SI_735 0x0735 +#define PCI_DEVICE_ID_SI_740 0x0740 +#define PCI_DEVICE_ID_SI_745 0x0745 +#define PCI_DEVICE_ID_SI_746 0x0746 +#define PCI_DEVICE_ID_SI_748 0x0748 +#define PCI_DEVICE_ID_SI_750 0x0750 +#define PCI_DEVICE_ID_SI_751 0x0751 +#define PCI_DEVICE_ID_SI_752 0x0752 +#define PCI_DEVICE_ID_SI_755 0x0755 +#define PCI_DEVICE_ID_SI_900 0x0900 +#define PCI_DEVICE_ID_SI_5107 0x5107 +#define PCI_DEVICE_ID_SI_5300 0x5300 +#define PCI_DEVICE_ID_SI_5511 0x5511 +#define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5518 0x5518 +#define PCI_DEVICE_ID_SI_5571 0x5571 +#define PCI_DEVICE_ID_SI_5581 0x5581 +#define PCI_DEVICE_ID_SI_5582 0x5582 +#define PCI_DEVICE_ID_SI_5591 0x5591 +#define PCI_DEVICE_ID_SI_5596 0x5596 +#define PCI_DEVICE_ID_SI_5597 0x5597 +#define PCI_DEVICE_ID_SI_5598 0x5598 +#define PCI_DEVICE_ID_SI_5600 0x5600 +#define PCI_DEVICE_ID_SI_6300 0x6300 +#define PCI_DEVICE_ID_SI_6306 0x6306 +#define PCI_DEVICE_ID_SI_6326 0x6326 +#define PCI_DEVICE_ID_SI_7001 0x7001 +#define PCI_DEVICE_ID_SI_7016 0x7016 + +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_DEVICE_ID_HP_DONNER_GFX 0x1008 +#define PCI_DEVICE_ID_HP_TACHYON 0x1028 +#define PCI_DEVICE_ID_HP_TACHLITE 0x1029 +#define PCI_DEVICE_ID_HP_J2585A 0x1030 +#define PCI_DEVICE_ID_HP_J2585B 0x1031 +#define PCI_DEVICE_ID_HP_SAS 0x1048 +#define PCI_DEVICE_ID_HP_DIVA1 0x1049 +#define PCI_DEVICE_ID_HP_DIVA2 0x104A +#define PCI_DEVICE_ID_HP_SP2_0 0x104B +#define PCI_DEVICE_ID_HP_PCI_LBA 0x1054 +#define PCI_DEVICE_ID_HP_REO_SBA 0x10f0 +#define PCI_DEVICE_ID_HP_REO_IOC 0x10f1 +#define PCI_DEVICE_ID_HP_ZX1_SBA 0x1229 +#define PCI_DEVICE_ID_HP_ZX1_IOC 0x122a +#define PCI_DEVICE_ID_HP_PCIX_LBA 0x122e +#define PCI_DEVICE_ID_HP_SX1000_IOC 0x127c + +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 +#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 + +#define PCI_VENDOR_ID_ASUSTEK 0x1043 +#define PCI_DEVICE_ID_ASUSTEK_0675 0x0675 + +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 + +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_DEVICE_ID_OPTI_92C178 0xc178 +#define PCI_DEVICE_ID_OPTI_82C557 0xc557 +#define PCI_DEVICE_ID_OPTI_82C558 0xc558 +#define PCI_DEVICE_ID_OPTI_82C621 0xc621 +#define PCI_DEVICE_ID_OPTI_82C700 0xc700 +#define PCI_DEVICE_ID_OPTI_82C701 0xc701 +#define PCI_DEVICE_ID_OPTI_82C814 0xc814 +#define PCI_DEVICE_ID_OPTI_82C822 0xc822 +#define PCI_DEVICE_ID_OPTI_82C861 0xc861 +#define PCI_DEVICE_ID_OPTI_82C825 0xd568 + +#define PCI_VENDOR_ID_ELSA 0x1048 +#define PCI_DEVICE_ID_ELSA_MICROLINK 0x1000 +#define PCI_DEVICE_ID_ELSA_QS3000 0x3000 + +#define PCI_VENDOR_ID_SGS 0x104a +#define PCI_DEVICE_ID_SGS_2000 0x0008 +#define PCI_DEVICE_ID_SGS_1764 0x0009 + +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 + +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 +#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 +#define PCI_DEVICE_ID_TI_1130 0xac12 +#define PCI_DEVICE_ID_TI_1031 0xac13 +#define PCI_DEVICE_ID_TI_1131 0xac15 +#define PCI_DEVICE_ID_TI_1250 0xac16 +#define PCI_DEVICE_ID_TI_1220 0xac17 +#define PCI_DEVICE_ID_TI_1221 0xac19 +#define PCI_DEVICE_ID_TI_1210 0xac1a +#define PCI_DEVICE_ID_TI_1410 0xac50 +#define PCI_DEVICE_ID_TI_1450 0xac1b +#define PCI_DEVICE_ID_TI_1225 0xac1c +#define PCI_DEVICE_ID_TI_1251A 0xac1d +#define PCI_DEVICE_ID_TI_1211 0xac1e +#define PCI_DEVICE_ID_TI_1251B 0xac1f +#define PCI_DEVICE_ID_TI_4410 0xac41 +#define PCI_DEVICE_ID_TI_4451 0xac42 +#define PCI_DEVICE_ID_TI_1420 0xac51 +#define PCI_DEVICE_ID_TI_1520 0xac55 +#define PCI_DEVICE_ID_TI_1510 0xac56 + +#define PCI_VENDOR_ID_SONY 0x104d +#define PCI_DEVICE_ID_SONY_CXD3222 0x8039 + +#define PCI_VENDOR_ID_OAK 0x104e +#define PCI_DEVICE_ID_OAK_OTI107 0x0107 + +/* Winbond have two vendor IDs! See 0x10ad as well */ +#define PCI_VENDOR_ID_WINBOND2 0x1050 +#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 +#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a +#define PCI_DEVICE_ID_WINBOND2_6692 0x6692 + +#define PCI_VENDOR_ID_ANIGMA 0x1051 +#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100 + +#define PCI_VENDOR_ID_EFAR 0x1055 +#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130 +#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460 +#define PCI_DEVICE_ID_EFAR_SLC90E66_2 0x9462 +#define PCI_DEVICE_ID_EFAR_SLC90E66_3 0x9463 + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507 +#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 +#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 +#define PCI_DEVICE_ID_MOTOROLA_MPC107 0x0004 +#define PCI_DEVICE_ID_MOTOROLA_MPC8540 0x0008 +#define PCI_DEVICE_ID_MOTOROLA_MPC8560 0x0009 +#define PCI_DEVICE_ID_MOTOROLA_MPC8265A 0x18c0 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 +#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 +#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803 +#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806 +#define PCI_DEVICE_ID_MOTOROLA_MPC190 0x6400 + +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_DEVICE_ID_PROMISE_20265 0x0d30 +#define PCI_DEVICE_ID_PROMISE_20267 0x4d30 +#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 +#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 +#define PCI_DEVICE_ID_PROMISE_20263 0x0D38 +#define PCI_DEVICE_ID_PROMISE_20268 0x4d68 +#define PCI_DEVICE_ID_PROMISE_20270 0x6268 +#define PCI_DEVICE_ID_PROMISE_20269 0x4d69 +#define PCI_DEVICE_ID_PROMISE_20271 0x6269 +#define PCI_DEVICE_ID_PROMISE_20275 0x1275 +#define PCI_DEVICE_ID_PROMISE_20276 0x5275 +#define PCI_DEVICE_ID_PROMISE_20277 0x7275 +#define PCI_DEVICE_ID_PROMISE_5300 0x5300 + +#define PCI_VENDOR_ID_N9 0x105d +#define PCI_DEVICE_ID_N9_I128 0x2309 +#define PCI_DEVICE_ID_N9_I128_2 0x2339 +#define PCI_DEVICE_ID_N9_I128_T2R 0x493d + +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 +#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 +#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a +#define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 +#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 +#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 +#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 +#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 + +#define PCI_VENDOR_ID_X 0x1061 +#define PCI_DEVICE_ID_X_AGX016 0x0001 + +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960_LA 0x0020 +#define PCI_DEVICE_ID_MYLEX_DAC960_LP 0x0050 +#define PCI_DEVICE_ID_MYLEX_DAC960_BA 0xBA56 + +#define PCI_VENDOR_ID_PICOP 0x1066 +#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 +#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 +#define PCI_DEVICE_ID_APPLE_GC 0x0002 +#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e +#define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018 +#define PCI_DEVICE_ID_APPLE_KL_USB 0x0019 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC 0x0021 +#define PCI_DEVICE_ID_APPLE_KEYLARGO 0x0022 +#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024 +#define PCI_DEVICE_ID_APPLE_KEYLARGO_P 0x0025 +#define PCI_DEVICE_ID_APPLE_KL_USB_P 0x0026 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027 +#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d +#define PCI_DEVICE_ID_APPLE_UNI_N_FW2 0x0030 +#define PCI_DEVICE_ID_APPLE_TIGON3 0x1645 + +#define PCI_VENDOR_ID_YAMAHA 0x1073 +#define PCI_DEVICE_ID_YAMAHA_724 0x0004 +#define PCI_DEVICE_ID_YAMAHA_724F 0x000d +#define PCI_DEVICE_ID_YAMAHA_740 0x000a +#define PCI_DEVICE_ID_YAMAHA_740C 0x000c +#define PCI_DEVICE_ID_YAMAHA_744 0x0010 +#define PCI_DEVICE_ID_YAMAHA_754 0x0012 + +#define PCI_VENDOR_ID_NEXGEN 0x1074 +#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 + +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 +#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 +#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_DEVICE_ID_CYRIX_5510 0x0000 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 +#define PCI_DEVICE_ID_CYRIX_5520 0x0002 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 +#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 +#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 + +#define PCI_VENDOR_ID_LEADTEK 0x107d +#define PCI_DEVICE_ID_LEADTEK_805 0x0000 + +#define PCI_VENDOR_ID_INTERPHASE 0x107e +#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 +#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 +#define PCI_DEVICE_ID_INTERPHASE_5575 0x0008 + +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 +#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 + +#define PCI_VENDOR_ID_FOREX 0x1083 + +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 +#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 +#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 + +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_DEVICE_ID_SUN_EBUS 0x1000 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 +#define PCI_DEVICE_ID_SUN_RIO_EBUS 0x1100 +#define PCI_DEVICE_ID_SUN_RIO_GEM 0x1101 +#define PCI_DEVICE_ID_SUN_RIO_1394 0x1102 +#define PCI_DEVICE_ID_SUN_RIO_USB 0x1103 +#define PCI_DEVICE_ID_SUN_GEM 0x2bad +#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 +#define PCI_DEVICE_ID_SUN_PBM 0x8000 +#define PCI_DEVICE_ID_SUN_SCHIZO 0x8001 +#define PCI_DEVICE_ID_SUN_SABRE 0xa000 +#define PCI_DEVICE_ID_SUN_HUMMINGBIRD 0xa001 +#define PCI_DEVICE_ID_SUN_TOMATILLO 0xa801 + +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_DEVICE_ID_SII_1210SA 0x0240 + +#define PCI_DEVICE_ID_CMD_640 0x0640 +#define PCI_DEVICE_ID_CMD_643 0x0643 +#define PCI_DEVICE_ID_CMD_646 0x0646 +#define PCI_DEVICE_ID_CMD_647 0x0647 +#define PCI_DEVICE_ID_CMD_648 0x0648 +#define PCI_DEVICE_ID_CMD_649 0x0649 +#define PCI_DEVICE_ID_CMD_670 0x0670 + +#define PCI_DEVICE_ID_SII_680 0x0680 +#define PCI_DEVICE_ID_SII_3112 0x3112 + +#define PCI_VENDOR_ID_VISION 0x1098 +#define PCI_DEVICE_ID_VISION_QD8500 0x0001 +#define PCI_DEVICE_ID_VISION_QD8580 0x0002 + +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 +#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 +#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e +#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 +#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 + +#define PCI_VENDOR_ID_SIERRA 0x10a8 +#define PCI_DEVICE_ID_SIERRA_STB 0x0000 + +#define PCI_VENDOR_ID_SGI 0x10a9 +#define PCI_DEVICE_ID_SGI_IOC3 0x0003 +#define PCI_DEVICE_ID_SGI_IOC4 0x100a + +#define PCI_VENDOR_ID_ACC 0x10aa +#define PCI_DEVICE_ID_ACC_2056 0x0000 + +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_DEVICE_ID_WINBOND_83769 0x0001 +#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 +#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 + +#define PCI_VENDOR_ID_DATABOOK 0x10b3 +#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 + +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_DEVICE_ID_PLX_R685 0x1030 +#define PCI_DEVICE_ID_PLX_ROMULUS 0x106a +#define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 +#define PCI_DEVICE_ID_PLX_1077 0x1077 +#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 +#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151 +#define PCI_DEVICE_ID_PLX_R753 0x1152 +#define PCI_DEVICE_ID_PLX_9050 0x9050 +#define PCI_DEVICE_ID_PLX_9060 0x9060 +#define PCI_DEVICE_ID_PLX_9060ES 0x906E +#define PCI_DEVICE_ID_PLX_9060SD 0x906D +#define PCI_DEVICE_ID_PLX_9080 0x9080 +#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 + +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_DEVICE_ID_MADGE_MK2 0x0002 +#define PCI_DEVICE_ID_MADGE_C155S 0x1001 + +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_DEVICE_ID_3COM_3C985 0x0001 +#define PCI_DEVICE_ID_3COM_3C339 0x3390 +#define PCI_DEVICE_ID_3COM_3C590 0x5900 +#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 +#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 +#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 +#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 +#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 +#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 +#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 +#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 +#define PCI_DEVICE_ID_3COM_3CR990 0x9900 +#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902 +#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903 +#define PCI_DEVICE_ID_3COM_3CR990B 0x9904 +#define PCI_DEVICE_ID_3COM_3CR990_FX 0x9905 +#define PCI_DEVICE_ID_3COM_3CR990SVR95 0x9908 +#define PCI_DEVICE_ID_3COM_3CR990SVR97 0x9909 +#define PCI_DEVICE_ID_3COM_3CR990SVR 0x990a + +#define PCI_VENDOR_ID_SMC 0x10b8 +#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 + +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_DEVICE_ID_AL_M1445 0x1445 +#define PCI_DEVICE_ID_AL_M1449 0x1449 +#define PCI_DEVICE_ID_AL_M1451 0x1451 +#define PCI_DEVICE_ID_AL_M1461 0x1461 +#define PCI_DEVICE_ID_AL_M1489 0x1489 +#define PCI_DEVICE_ID_AL_M1511 0x1511 +#define PCI_DEVICE_ID_AL_M1513 0x1513 +#define PCI_DEVICE_ID_AL_M1521 0x1521 +#define PCI_DEVICE_ID_AL_M1523 0x1523 +#define PCI_DEVICE_ID_AL_M1531 0x1531 +#define PCI_DEVICE_ID_AL_M1533 0x1533 +#define PCI_DEVICE_ID_AL_M1535 0x1535 +#define PCI_DEVICE_ID_AL_M1541 0x1541 +#define PCI_DEVICE_ID_AL_M1621 0x1621 +#define PCI_DEVICE_ID_AL_M1631 0x1631 +#define PCI_DEVICE_ID_AL_M1641 0x1641 +#define PCI_DEVICE_ID_AL_M1644 0x1644 +#define PCI_DEVICE_ID_AL_M1647 0x1647 +#define PCI_DEVICE_ID_AL_M1651 0x1651 +#define PCI_DEVICE_ID_AL_M1543 0x1543 +#define PCI_DEVICE_ID_AL_M3307 0x3307 +#define PCI_DEVICE_ID_AL_M4803 0x5215 +#define PCI_DEVICE_ID_AL_M5219 0x5219 +#define PCI_DEVICE_ID_AL_M5229 0x5229 +#define PCI_DEVICE_ID_AL_M5237 0x5237 +#define PCI_DEVICE_ID_AL_M5243 0x5243 +#define PCI_DEVICE_ID_AL_M5451 0x5451 +#define PCI_DEVICE_ID_AL_M7101 0x7101 + +#define PCI_VENDOR_ID_MITSUBISHI 0x10ba + +#define PCI_VENDOR_ID_SURECOM 0x10bd +#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 + +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 + +#define PCI_VENDOR_ID_ASP 0x10cd +#define PCI_DEVICE_ID_ASP_ABP940 0x1200 +#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 +#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 + +#define PCI_VENDOR_ID_MACRONIX 0x10d9 +#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 +#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 + +#define PCI_VENDOR_ID_TCONRAD 0x10da +#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508 + +#define PCI_VENDOR_ID_CERN 0x10dc +#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 +#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 +#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 +#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 + +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 +#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 +#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 +#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C +#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D +#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE 0x0065 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE 0x0085 +#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA 0x008e +#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3 0x00d1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE 0x00d5 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S 0x00e1 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA 0x00e3 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE 0x00e5 +#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2 0x00ee +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 +#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX 0x0110 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2 0x0111 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 +#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4 +#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc +#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201 +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202 +#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC 0x0203 + +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_DEVICE_ID_IMS_8849 0x8849 +#define PCI_DEVICE_ID_IMS_TT128 0x9128 +#define PCI_DEVICE_ID_IMS_TT3D 0x9135 + +#define PCI_VENDOR_ID_TEKRAM2 0x10e1 +#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c + +#define PCI_VENDOR_ID_TUNDRA 0x10e3 +#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 + +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 +#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 +#define PCI_DEVICE_ID_AMCC_S5933 0x807d +#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c + +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_DEVICE_ID_INTERG_1680 0x1680 +#define PCI_DEVICE_ID_INTERG_1682 0x1682 +#define PCI_DEVICE_ID_INTERG_2000 0x2000 +#define PCI_DEVICE_ID_INTERG_2010 0x2010 +#define PCI_DEVICE_ID_INTERG_5000 0x5000 +#define PCI_DEVICE_ID_INTERG_5050 0x5050 + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_8029 0x8029 +#define PCI_DEVICE_ID_REALTEK_8129 0x8129 +#define PCI_DEVICE_ID_REALTEK_8139 0x8139 +#define PCI_DEVICE_ID_REALTEK_8169 0x8169 + +#define PCI_VENDOR_ID_XILINX 0x10ee +#define PCI_DEVICE_ID_TURBOPAM 0x4020 + +#define PCI_VENDOR_ID_TRUEVISION 0x10fa +#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c + +#define PCI_VENDOR_ID_INIT 0x1101 +#define PCI_DEVICE_ID_INIT_320P 0x9100 +#define PCI_DEVICE_ID_INIT_360P 0x9500 + +#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ +#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002 + +#define PCI_VENDOR_ID_ECTIVA 0x1102 /* duplicate: CREATIVE */ +#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938 + +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_DEVICE_ID_TTI_HPT343 0x0003 +#define PCI_DEVICE_ID_TTI_HPT366 0x0004 +#define PCI_DEVICE_ID_TTI_HPT372 0x0005 +#define PCI_DEVICE_ID_TTI_HPT302 0x0006 +#define PCI_DEVICE_ID_TTI_HPT371 0x0007 +#define PCI_DEVICE_ID_TTI_HPT374 0x0008 +#define PCI_DEVICE_ID_TTI_HPT372N 0x0009 /* appoarently a 372N variant? */ + +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_8363_0 0x0305 +#define PCI_DEVICE_ID_VIA_8371_0 0x0391 +#define PCI_DEVICE_ID_VIA_8501_0 0x0501 +#define PCI_DEVICE_ID_VIA_82C505 0x0505 +#define PCI_DEVICE_ID_VIA_82C561 0x0561 +#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 +#define PCI_DEVICE_ID_VIA_82C576 0x0576 +#define PCI_DEVICE_ID_VIA_82C585 0x0585 +#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 +#define PCI_DEVICE_ID_VIA_82C595 0x0595 +#define PCI_DEVICE_ID_VIA_82C596 0x0596 +#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 +#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 +#define PCI_DEVICE_ID_VIA_8601_0 0x0601 +#define PCI_DEVICE_ID_VIA_8605_0 0x0605 +#define PCI_DEVICE_ID_VIA_82C680 0x0680 +#define PCI_DEVICE_ID_VIA_82C686 0x0686 +#define PCI_DEVICE_ID_VIA_82C691 0x0691 +#define PCI_DEVICE_ID_VIA_82C693 0x0693 +#define PCI_DEVICE_ID_VIA_82C693_1 0x0698 +#define PCI_DEVICE_ID_VIA_82C926 0x0926 +#define PCI_DEVICE_ID_VIA_82C576_1 0x1571 +#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 +#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 +#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 +#define PCI_DEVICE_ID_VIA_6305 0x3044 +#define PCI_DEVICE_ID_VIA_82C596_3 0x3050 +#define PCI_DEVICE_ID_VIA_82C596B_3 0x3051 +#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 +#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 +#define PCI_DEVICE_ID_VIA_8233_5 0x3059 +#define PCI_DEVICE_ID_VIA_8233_7 0x3065 +#define PCI_DEVICE_ID_VIA_82C686_6 0x3068 +#define PCI_DEVICE_ID_VIA_8233_0 0x3074 +#define PCI_DEVICE_ID_VIA_8633_0 0x3091 +#define PCI_DEVICE_ID_VIA_8367_0 0x3099 +#define PCI_DEVICE_ID_VIA_8622 0x3102 +#define PCI_DEVICE_ID_VIA_8233C_0 0x3109 +#define PCI_DEVICE_ID_VIA_8361 0x3112 +#define PCI_DEVICE_ID_VIA_8375 0x3116 +#define PCI_DEVICE_ID_VIA_CLE266 0x3123 +#define PCI_DEVICE_ID_VIA_8233A 0x3147 +#define PCI_DEVICE_ID_VIA_P4M266 0x3148 +#define PCI_DEVICE_ID_VIA_8237_SATA 0x3149 +#define PCI_DEVICE_ID_VIA_P4X333 0x3168 +#define PCI_DEVICE_ID_VIA_8235 0x3177 +#define PCI_DEVICE_ID_VIA_8377_0 0x3189 +#define PCI_DEVICE_ID_VIA_K8T400M_0 0x3188 +#define PCI_DEVICE_ID_VIA_8237 0x3227 +#define PCI_DEVICE_ID_VIA_86C100A 0x6100 +#define PCI_DEVICE_ID_VIA_8231 0x8231 +#define PCI_DEVICE_ID_VIA_8231_4 0x8235 +#define PCI_DEVICE_ID_VIA_8365_1 0x8305 +#define PCI_DEVICE_ID_VIA_8371_1 0x8391 +#define PCI_DEVICE_ID_VIA_8501_1 0x8501 +#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 +#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 +#define PCI_DEVICE_ID_VIA_8601_1 0x8601 +#define PCI_DEVICE_ID_VIA_8505_1 0x8605 +#define PCI_DEVICE_ID_VIA_8633_1 0xB091 +#define PCI_DEVICE_ID_VIA_8367_1 0xB099 + +#define PCI_VENDOR_ID_SIEMENS 0x110A +#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 + +#define PCI_VENDOR_ID_SMC2 0x1113 +#define PCI_DEVICE_ID_SMC2_1211TX 0x1211 + +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 +#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 +#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 +#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 +#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 +#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 +#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 +#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 +#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 +#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 +#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a +#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b +#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c +#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 + +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 +#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 + +#define PCI_VENDOR_ID_IDT 0x111d +#define PCI_DEVICE_ID_IDT_IDT77201 0x0001 + +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 +#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 + +#define PCI_VENDOR_ID_IMAGINGTECH 0x112f +#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 + +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 +#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 +#define PCI_DEVICE_ID_PHILIPS_SAA9730 0x9730 + +#define PCI_VENDOR_ID_EICON 0x1133 +#define PCI_DEVICE_ID_EICON_DIVA20PRO 0xe001 +#define PCI_DEVICE_ID_EICON_DIVA20 0xe002 +#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003 +#define PCI_DEVICE_ID_EICON_DIVA20_U 0xe004 +#define PCI_DEVICE_ID_EICON_DIVA201 0xe005 +#define PCI_DEVICE_ID_EICON_DIVA202 0xe00b +#define PCI_DEVICE_ID_EICON_MAESTRA 0xe010 +#define PCI_DEVICE_ID_EICON_MAESTRAQ 0xe012 +#define PCI_DEVICE_ID_EICON_MAESTRAQ_U 0xe013 +#define PCI_DEVICE_ID_EICON_MAESTRAP 0xe014 + +#define PCI_VENDOR_ID_CYCLONE 0x113c +#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 + +#define PCI_VENDOR_ID_ALLIANCE 0x1142 +#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 +#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 +#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 +#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d + +#define PCI_VENDOR_ID_SYSKONNECT 0x1148 +#define PCI_DEVICE_ID_SYSKONNECT_FP 0x4000 +#define PCI_DEVICE_ID_SYSKONNECT_TR 0x4200 +#define PCI_DEVICE_ID_SYSKONNECT_GE 0x4300 +#define PCI_DEVICE_ID_SYSKONNECT_YU 0x4320 +#define PCI_DEVICE_ID_SYSKONNECT_9DXX 0x4400 +#define PCI_DEVICE_ID_SYSKONNECT_9MXX 0x4500 + +#define PCI_VENDOR_ID_VMIC 0x114a +#define PCI_DEVICE_ID_VMIC_VME 0x7587 + +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_DEVICE_ID_DIGI_EPC 0x0002 +#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 +#define PCI_DEVICE_ID_DIGI_XEM 0x0004 +#define PCI_DEVICE_ID_DIGI_XR 0x0005 +#define PCI_DEVICE_ID_DIGI_CX 0x0006 +#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 +#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a +#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E 0x0070 +#define PCI_DEVICE_ID_DIGI_DF_M_E 0x0071 +#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A 0x0072 +#define PCI_DEVICE_ID_DIGI_DF_M_A 0x0073 + +#define PCI_VENDOR_ID_MUTECH 0x1159 +#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 + +#define PCI_VENDOR_ID_XIRCOM 0x115d +#define PCI_DEVICE_ID_XIRCOM_X3201_ETH 0x0003 +#define PCI_DEVICE_ID_XIRCOM_X3201_MDM 0x0103 + +#define PCI_VENDOR_ID_RENDITION 0x1163 +#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 +#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 + +#define PCI_VENDOR_ID_SERVERWORKS 0x1166 +#define PCI_DEVICE_ID_SERVERWORKS_HE 0x0008 +#define PCI_DEVICE_ID_SERVERWORKS_LE 0x0009 +#define PCI_DEVICE_ID_SERVERWORKS_CIOB30 0x0010 +#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011 +#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217 +#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB +#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227 +#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230 + +#define PCI_VENDOR_ID_SBE 0x1176 +#define PCI_DEVICE_ID_SBE_WANXL100 0x0301 +#define PCI_DEVICE_ID_SBE_WANXL200 0x0302 +#define PCI_DEVICE_ID_SBE_WANXL400 0x0104 + +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_DEVICE_ID_TOSHIBA_PICCOLO 0x0102 +#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f + +#define PCI_VENDOR_ID_TOSHIBA_2 0x102f +#define PCI_DEVICE_ID_TOSHIBA_TX3927 0x000a +#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030 +#define PCI_DEVICE_ID_TOSHIBA_TX4927 0x0180 + +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 +#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 +#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 +#define PCI_DEVICE_ID_RICOH_RL5C476 0x0476 +#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 + +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 +#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 +#define PCI_DEVICE_ID_ARTOP_ATP860 0x0006 +#define PCI_DEVICE_ID_ARTOP_ATP860R 0x0007 +#define PCI_DEVICE_ID_ARTOP_ATP865 0x0008 +#define PCI_DEVICE_ID_ARTOP_ATP865R 0x0009 +#define PCI_DEVICE_ID_ARTOP_AEC7610 0x8002 +#define PCI_DEVICE_ID_ARTOP_AEC7612UW 0x8010 +#define PCI_DEVICE_ID_ARTOP_AEC7612U 0x8020 +#define PCI_DEVICE_ID_ARTOP_AEC7612S 0x8030 +#define PCI_DEVICE_ID_ARTOP_AEC7612D 0x8040 +#define PCI_DEVICE_ID_ARTOP_AEC7612SUW 0x8050 +#define PCI_DEVICE_ID_ARTOP_8060 0x8060 + +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 +#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 + +#define PCI_VENDOR_ID_OMEGA 0x119b +#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 + +#define PCI_VENDOR_ID_FUJITSU_ME 0x119e +#define PCI_DEVICE_ID_FUJITSU_FS155 0x0001 +#define PCI_DEVICE_ID_FUJITSU_FS50 0x0003 + +#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 +#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 + +#define PCI_VENDOR_ID_GALILEO 0x11ab +#define PCI_DEVICE_ID_GALILEO_GT64011 0x4146 +#define PCI_DEVICE_ID_GALILEO_GT64111 0x4146 +#define PCI_DEVICE_ID_GALILEO_GT96100 0x9652 +#define PCI_DEVICE_ID_GALILEO_GT96100A 0x9653 + +#define PCI_VENDOR_ID_LITEON 0x11ad +#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 + +#define PCI_VENDOR_ID_V3 0x11b0 +#define PCI_DEVICE_ID_V3_V960 0x0001 +#define PCI_DEVICE_ID_V3_V350 0x0001 +#define PCI_DEVICE_ID_V3_V961 0x0002 +#define PCI_DEVICE_ID_V3_V351 0x0002 + +#define PCI_VENDOR_ID_NP 0x11bc +#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 + +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 +#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 + +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 +#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 +#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 +#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004 + +#define PCI_VENDOR_ID_AURAVISION 0x11d1 +#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 + +#define PCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 +#define PCI_DEVICE_ID_AD1889JS 0x1889 + +#define PCI_VENDOR_ID_IKON 0x11d5 +#define PCI_DEVICE_ID_IKON_10115 0x0115 +#define PCI_DEVICE_ID_IKON_10117 0x0117 + +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_DEVICE_ID_ZORAN_36057 0x6057 +#define PCI_DEVICE_ID_ZORAN_36120 0x6120 + +#define PCI_VENDOR_ID_KINETIC 0x11f4 +#define PCI_DEVICE_ID_KINETIC_2915 0x2915 + +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 +#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 + +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_DEVICE_ID_RP32INTF 0x0001 +#define PCI_DEVICE_ID_RP8INTF 0x0002 +#define PCI_DEVICE_ID_RP16INTF 0x0003 +#define PCI_DEVICE_ID_RP4QUAD 0x0004 +#define PCI_DEVICE_ID_RP8OCTA 0x0005 +#define PCI_DEVICE_ID_RP8J 0x0006 +#define PCI_DEVICE_ID_RPP4 0x000A +#define PCI_DEVICE_ID_RPP8 0x000B +#define PCI_DEVICE_ID_RP8M 0x000C + +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 +#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 +#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 +#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 +#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 +#define PCI_DEVICE_ID_PC300_RX_2 0x0300 +#define PCI_DEVICE_ID_PC300_RX_1 0x0301 +#define PCI_DEVICE_ID_PC300_TE_2 0x0310 +#define PCI_DEVICE_ID_PC300_TE_1 0x0311 + +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 + +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_DEVICE_ID_O2_6729 0x6729 +#define PCI_DEVICE_ID_O2_6730 0x673a +#define PCI_DEVICE_ID_O2_6832 0x6832 +#define PCI_DEVICE_ID_O2_6836 0x6836 + +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 +#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 +#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 +#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 + +#define PCI_VENDOR_ID_SIGMADES 0x1236 +#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 + +#define PCI_VENDOR_ID_CCUBE 0x123f + +#define PCI_VENDOR_ID_AVM 0x1244 +#define PCI_DEVICE_ID_AVM_B1 0x0700 +#define PCI_DEVICE_ID_AVM_C4 0x0800 +#define PCI_DEVICE_ID_AVM_A1 0x0a00 +#define PCI_DEVICE_ID_AVM_A1_V2 0x0e00 +#define PCI_DEVICE_ID_AVM_C2 0x1100 +#define PCI_DEVICE_ID_AVM_T1 0x1200 + +#define PCI_VENDOR_ID_DIPIX 0x1246 + +#define PCI_VENDOR_ID_STALLION 0x124d +#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 +#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 +#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 + +#define PCI_VENDOR_ID_OPTIBASE 0x1255 +#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 +#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 +#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 +#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 +#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 + +#define PCI_VENDOR_ID_ESS 0x125d +#define PCI_DEVICE_ID_ESS_ESS1968 0x1968 +#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969 +#define PCI_DEVICE_ID_ESS_ESS1978 0x1978 + +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_DEVICE_ID_SATSAGEM_NICCY 0x1016 +#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 +#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b + +#define PCI_VENDOR_ID_SMI 0x126f +#define PCI_DEVICE_ID_SMI_710 0x0710 +#define PCI_DEVICE_ID_SMI_712 0x0712 +#define PCI_DEVICE_ID_SMI_810 0x0810 + +#define PCI_VENDOR_ID_HUGHES 0x1273 +#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 + +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 +#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 +#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 + +#define PCI_VENDOR_ID_ROCKWELL 0x127A + +#define PCI_VENDOR_ID_DAVICOM 0x1282 +#define PCI_DEVICE_ID_DAVICOM_DM9102A 0x9102 + +#define PCI_VENDOR_ID_ITE 0x1283 +#define PCI_DEVICE_ID_ITE_IT8172G 0x8172 +#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 +#define PCI_DEVICE_ID_ITE_IT8181 0x8181 +#define PCI_DEVICE_ID_ITE_8872 0x8872 + +#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 + +/* formerly Platform Tech */ +#define PCI_VENDOR_ID_ESS_OLD 0x1285 +#define PCI_DEVICE_ID_ESS_ESS0100 0x0100 + +#define PCI_VENDOR_ID_ALTEON 0x12ae +#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 + +#define PCI_VENDOR_ID_USR 0x12B9 + +#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B + +#define PCI_VENDOR_ID_PICTUREL 0x12c5 +#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 + +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 + +#define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8 0x0021 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16 0x0011 +#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC 0x0041 +#define PCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4 0xF001 +#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8 0xF010 + +#define PCI_VENDOR_ID_AUREAL 0x12eb +#define PCI_DEVICE_ID_AUREAL_VORTEX_1 0x0001 +#define PCI_DEVICE_ID_AUREAL_VORTEX_2 0x0002 + +#define PCI_VENDOR_ID_CBOARDS 0x1307 +#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 + +#define PCI_VENDOR_ID_SIIG 0x131f +#define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 +#define PCI_DEVICE_ID_SIIG_1S_10x_650 0x1001 +#define PCI_DEVICE_ID_SIIG_1S_10x_850 0x1002 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 +#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 +#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 +#define PCI_DEVICE_ID_SIIG_2S_10x_550 0x1030 +#define PCI_DEVICE_ID_SIIG_2S_10x_650 0x1031 +#define PCI_DEVICE_ID_SIIG_2S_10x_850 0x1032 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 +#define PCI_DEVICE_ID_SIIG_4S_10x_550 0x1050 +#define PCI_DEVICE_ID_SIIG_4S_10x_650 0x1051 +#define PCI_DEVICE_ID_SIIG_4S_10x_850 0x1052 +#define PCI_DEVICE_ID_SIIG_1S_20x_550 0x2000 +#define PCI_DEVICE_ID_SIIG_1S_20x_650 0x2001 +#define PCI_DEVICE_ID_SIIG_1S_20x_850 0x2002 +#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 +#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 +#define PCI_DEVICE_ID_SIIG_2S_20x_550 0x2030 +#define PCI_DEVICE_ID_SIIG_2S_20x_650 0x2031 +#define PCI_DEVICE_ID_SIIG_2S_20x_850 0x2032 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 +#define PCI_DEVICE_ID_SIIG_4S_20x_550 0x2050 +#define PCI_DEVICE_ID_SIIG_4S_20x_650 0x2051 +#define PCI_DEVICE_ID_SIIG_4S_20x_850 0x2052 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 + +#define PCI_VENDOR_ID_DOMEX 0x134a +#define PCI_DEVICE_ID_DOMEX_DMX3191D 0x0001 + +#define PCI_VENDOR_ID_QUATECH 0x135C +#define PCI_DEVICE_ID_QUATECH_QSC100 0x0010 +#define PCI_DEVICE_ID_QUATECH_DSC100 0x0020 +#define PCI_DEVICE_ID_QUATECH_DSC200 0x0030 +#define PCI_DEVICE_ID_QUATECH_QSC200 0x0040 +#define PCI_DEVICE_ID_QUATECH_ESC100D 0x0050 +#define PCI_DEVICE_ID_QUATECH_ESC100M 0x0060 + +#define PCI_VENDOR_ID_SEALEVEL 0x135e +#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 +#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 +#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 + +#define PCI_VENDOR_ID_HYPERCOPE 0x1365 +#define PCI_DEVICE_ID_HYPERCOPE_PLX 0x9050 +#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO 0x0104 +#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO 0x0106 +#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO 0x0107 +#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2 0x0108 +#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS 0x0109 + +#define PCI_VENDOR_ID_KAWASAKI 0x136b +#define PCI_DEVICE_ID_MCHIP_KL5A72002 0xff01 + +#define PCI_VENDOR_ID_LMC 0x1376 +#define PCI_DEVICE_ID_LMC_HSSI 0x0003 +#define PCI_DEVICE_ID_LMC_DS3 0x0004 +#define PCI_DEVICE_ID_LMC_SSI 0x0005 +#define PCI_DEVICE_ID_LMC_T1 0x0006 + +#define PCI_VENDOR_ID_NETGEAR 0x1385 +#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a +#define PCI_DEVICE_ID_NETGEAR_GA622 0x622a + +#define PCI_VENDOR_ID_APPLICOM 0x1389 +#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001 +#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002 +#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003 + +#define PCI_VENDOR_ID_MOXA 0x1393 +#define PCI_DEVICE_ID_MOXA_C104 0x1040 +#define PCI_DEVICE_ID_MOXA_C168 0x1680 +#define PCI_DEVICE_ID_MOXA_CP204J 0x2040 +#define PCI_DEVICE_ID_MOXA_C218 0x2180 +#define PCI_DEVICE_ID_MOXA_C320 0x3200 + +#define PCI_VENDOR_ID_CCD 0x1397 +#define PCI_DEVICE_ID_CCD_2BD0 0x2bd0 +#define PCI_DEVICE_ID_CCD_B000 0xb000 +#define PCI_DEVICE_ID_CCD_B006 0xb006 +#define PCI_DEVICE_ID_CCD_B007 0xb007 +#define PCI_DEVICE_ID_CCD_B008 0xb008 +#define PCI_DEVICE_ID_CCD_B009 0xb009 +#define PCI_DEVICE_ID_CCD_B00A 0xb00a +#define PCI_DEVICE_ID_CCD_B00B 0xb00b +#define PCI_DEVICE_ID_CCD_B00C 0xb00c +#define PCI_DEVICE_ID_CCD_B100 0xb100 + +#define PCI_VENDOR_ID_3WARE 0x13C1 +#define PCI_DEVICE_ID_3WARE_1000 0x1000 + +#define PCI_VENDOR_ID_ABOCOM 0x13D1 +#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 + +#define PCI_VENDOR_ID_CMEDIA 0x13f6 +#define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 +#define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 +#define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 +#define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 + +#define PCI_VENDOR_ID_LAVA 0x1407 +#define PCI_DEVICE_ID_LAVA_DSERIAL 0x0100 /* 2x 16550 */ +#define PCI_DEVICE_ID_LAVA_QUATRO_A 0x0101 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUATRO_B 0x0102 /* 2x 16550, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_A 0x0180 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_OCTO_B 0x0181 /* 4x 16550A, half of 8 port */ +#define PCI_DEVICE_ID_LAVA_PORT_PLUS 0x0200 /* 2x 16650 */ +#define PCI_DEVICE_ID_LAVA_QUAD_A 0x0201 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_QUAD_B 0x0202 /* 2x 16650, half of 4 port */ +#define PCI_DEVICE_ID_LAVA_SSERIAL 0x0500 /* 1x 16550 */ +#define PCI_DEVICE_ID_LAVA_PORT_650 0x0600 /* 1x 16650 */ +#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ +#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR 0x8800 + +#define PCI_VENDOR_ID_TIMEDIA 0x1409 +#define PCI_DEVICE_ID_TIMEDIA_1889 0x7168 + +#define PCI_VENDOR_ID_OXSEMI 0x1415 +#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403 +#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501 +#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511 +#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513 +#define PCI_DEVICE_ID_OXSEMI_16PCI952 0x9521 + +#define PCI_VENDOR_ID_AIRONET 0x14b9 +#define PCI_DEVICE_ID_AIRONET_4800_1 0x0001 +#define PCI_DEVICE_ID_AIRONET_4800 0x4500 /* values switched? see */ +#define PCI_DEVICE_ID_AIRONET_4500 0x4800 /* drivers/net/aironet4500_card.c */ + +#define PCI_VENDOR_ID_TITAN 0x14D2 +#define PCI_DEVICE_ID_TITAN_010L 0x8001 +#define PCI_DEVICE_ID_TITAN_100L 0x8010 +#define PCI_DEVICE_ID_TITAN_110L 0x8011 +#define PCI_DEVICE_ID_TITAN_200L 0x8020 +#define PCI_DEVICE_ID_TITAN_210L 0x8021 +#define PCI_DEVICE_ID_TITAN_400L 0x8040 +#define PCI_DEVICE_ID_TITAN_800L 0x8080 +#define PCI_DEVICE_ID_TITAN_100 0xA001 +#define PCI_DEVICE_ID_TITAN_200 0xA005 +#define PCI_DEVICE_ID_TITAN_400 0xA003 +#define PCI_DEVICE_ID_TITAN_800B 0xA004 + +#define PCI_VENDOR_ID_PANACOM 0x14d4 +#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 +#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 + +#define PCI_VENDOR_ID_AFAVLAB 0x14db +#define PCI_DEVICE_ID_AFAVLAB_P028 0x2180 + +#define PCI_VENDOR_ID_BROADCOM 0x14e4 +#define PCI_DEVICE_ID_TIGON3_5700 0x1644 +#define PCI_DEVICE_ID_TIGON3_5701 0x1645 +#define PCI_DEVICE_ID_TIGON3_5702 0x1646 +#define PCI_DEVICE_ID_TIGON3_5703 0x1647 +#define PCI_DEVICE_ID_TIGON3_5704 0x1648 +#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649 +#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d +#define PCI_DEVICE_ID_TIGON3_5705 0x1653 +#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 +#define PCI_DEVICE_ID_TIGON3_5705M 0x165d +#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e +#define PCI_DEVICE_ID_TIGON3_5705F 0x166e +#define PCI_DEVICE_ID_TIGON3_5782 0x1696 +#define PCI_DEVICE_ID_TIGON3_5788 0x169c +#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 +#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 +#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 +#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 +#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 +#define PCI_DEVICE_ID_TIGON3_5901 0x170d +#define PCI_DEVICE_ID_TIGON3_5901_2 0x170e +#define PCI_DEVICE_ID_BCM4401 0x4401 + +#define PCI_VENDOR_ID_ENE 0x1524 +#define PCI_DEVICE_ID_ENE_1211 0x1211 +#define PCI_DEVICE_ID_ENE_1225 0x1225 +#define PCI_DEVICE_ID_ENE_1410 0x1410 +#define PCI_DEVICE_ID_ENE_1420 0x1420 + +#define PCI_VENDOR_ID_SYBA 0x1592 +#define PCI_DEVICE_ID_SYBA_2P_EPP 0x0782 +#define PCI_DEVICE_ID_SYBA_1P_ECP 0x0783 + +#define PCI_VENDOR_ID_MORETON 0x15aa +#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000 + +#define PCI_VENDOR_ID_ZOLTRIX 0x15b0 +#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0 + +#define PCI_VENDOR_ID_PDC 0x15e9 +#define PCI_DEVICE_ID_PDC_ADMA100 0x1841 + +#define PCI_VENDOR_ID_ALTIMA 0x173b +#define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 +#define PCI_DEVICE_ID_ALTIMA_AC1001 0x03e9 +#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea +#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb + +#define PCI_VENDOR_ID_SYMPHONY 0x1c1c +#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 + +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 + +#define PCI_VENDOR_ID_HINT 0x3388 +#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 +#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 +#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 +#define PCI_DEVICE_ID_3DLABS_MX 0x0006 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2 0x0007 +#define PCI_DEVICE_ID_3DLABS_GAMMA 0x0008 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009 + +#define PCI_VENDOR_ID_AVANCE 0x4005 +#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 +#define PCI_DEVICE_ID_AVANCE_2302 0x2302 + +#define PCI_VENDOR_ID_AKS 0x416c +#define PCI_DEVICE_ID_AKS_ALADDINCARD 0x0100 +#define PCI_DEVICE_ID_AKS_CPC 0x0200 + +#define PCI_VENDOR_ID_REDCREEK 0x4916 +#define PCI_DEVICE_ID_RC45 0x1960 + +#define PCI_VENDOR_ID_NETVIN 0x4a14 +#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 + +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 +#define PCI_DEVICE_ID_S3_ViRGE 0x5631 +#define PCI_DEVICE_ID_S3_TRIO 0x8811 +#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 +#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 +#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d +#define PCI_DEVICE_ID_S3_868 0x8880 +#define PCI_DEVICE_ID_S3_928 0x88b0 +#define PCI_DEVICE_ID_S3_864_1 0x88c0 +#define PCI_DEVICE_ID_S3_864_2 0x88c1 +#define PCI_DEVICE_ID_S3_964_1 0x88d0 +#define PCI_DEVICE_ID_S3_964_2 0x88d1 +#define PCI_DEVICE_ID_S3_968 0x88f0 +#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 +#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 +#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 +#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 +#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 +#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 +#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 +#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 + +#define PCI_VENDOR_ID_DUNORD 0x5544 +#define PCI_DEVICE_ID_DUNORD_I3000 0x0001 +#define PCI_VENDOR_ID_GENROCO 0x5555 +#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003 + +#define PCI_VENDOR_ID_DCI 0x6666 +#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 +#define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_21145 0x0039 +#define PCI_DEVICE_ID_INTEL_21152BB 0xb152 +#define PCI_DEVICE_ID_INTEL_82375 0x0482 +#define PCI_DEVICE_ID_INTEL_82424 0x0483 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 +#define PCI_DEVICE_ID_INTEL_82430 0x0486 +#define PCI_DEVICE_ID_INTEL_82434 0x04a3 +#define PCI_DEVICE_ID_INTEL_I960 0x0960 +#define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_82542 0x1000 +#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001 +#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004 +#define PCI_DEVICE_ID_INTEL_82544EI_COPPER 0x1008 +#define PCI_DEVICE_ID_INTEL_82544EI_FIBER 0x1009 +#define PCI_DEVICE_ID_INTEL_82544GC_COPPER 0x100C +#define PCI_DEVICE_ID_INTEL_82544GC_LOM 0x100D +#define PCI_DEVICE_ID_INTEL_82540EM 0x100E +#define PCI_DEVICE_ID_INTEL_82545EM_COPPER 0x100F +#define PCI_DEVICE_ID_INTEL_82546EB_COPPER 0x1010 +#define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011 +#define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012 +#define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015 +#define PCI_DEVICE_ID_INTEL_82559 0x1030 + +#define PCI_DEVICE_ID_INTEL_82562ET 0x1031 + +#define PCI_DEVICE_ID_INTEL_82815_MC 0x1130 + +#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 +#define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_7205_0 0x255d +#define PCI_DEVICE_ID_INTEL_82596 0x1226 +#define PCI_DEVICE_ID_INTEL_82865 0x1227 +#define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82437 0x122d +#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 +#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 +#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_82380FB 0x124b +#define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960 +#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30 +#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 +#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 +#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410 +#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411 +#define PCI_DEVICE_ID_INTEL_82801AA_2 0x2412 +#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413 +#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 +#define PCI_DEVICE_ID_INTEL_82801AA_6 0x2416 +#define PCI_DEVICE_ID_INTEL_82801AA_8 0x2418 +#define PCI_DEVICE_ID_INTEL_82801AB_0 0x2420 +#define PCI_DEVICE_ID_INTEL_82801AB_1 0x2421 +#define PCI_DEVICE_ID_INTEL_82801AB_2 0x2422 +#define PCI_DEVICE_ID_INTEL_82801AB_3 0x2423 +#define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 +#define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 +#define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 +#define PCI_DEVICE_ID_INTEL_82801BA_0 0x2440 +#define PCI_DEVICE_ID_INTEL_82801BA_1 0x2442 +#define PCI_DEVICE_ID_INTEL_82801BA_2 0x2443 +#define PCI_DEVICE_ID_INTEL_82801BA_3 0x2444 +#define PCI_DEVICE_ID_INTEL_82801BA_4 0x2445 +#define PCI_DEVICE_ID_INTEL_82801BA_5 0x2446 +#define PCI_DEVICE_ID_INTEL_82801BA_6 0x2448 +#define PCI_DEVICE_ID_INTEL_82801BA_7 0x2449 +#define PCI_DEVICE_ID_INTEL_82801BA_8 0x244a +#define PCI_DEVICE_ID_INTEL_82801BA_9 0x244b +#define PCI_DEVICE_ID_INTEL_82801BA_10 0x244c +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e +#define PCI_DEVICE_ID_INTEL_82801E_0 0x2450 +#define PCI_DEVICE_ID_INTEL_82801E_2 0x2452 +#define PCI_DEVICE_ID_INTEL_82801E_3 0x2453 +#define PCI_DEVICE_ID_INTEL_82801E_9 0x2459 +#define PCI_DEVICE_ID_INTEL_82801E_11 0x245B +#define PCI_DEVICE_ID_INTEL_82801E_14 0x245D +#define PCI_DEVICE_ID_INTEL_82801E_15 0x245E +#define PCI_DEVICE_ID_INTEL_82801CA_0 0x2480 +#define PCI_DEVICE_ID_INTEL_82801CA_2 0x2482 +#define PCI_DEVICE_ID_INTEL_82801CA_3 0x2483 +#define PCI_DEVICE_ID_INTEL_82801CA_4 0x2484 +#define PCI_DEVICE_ID_INTEL_82801CA_5 0x2485 +#define PCI_DEVICE_ID_INTEL_82801CA_6 0x2486 +#define PCI_DEVICE_ID_INTEL_82801CA_7 0x2487 +#define PCI_DEVICE_ID_INTEL_82801CA_10 0x248a +#define PCI_DEVICE_ID_INTEL_82801CA_11 0x248b +#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c +#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0 +#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2 +#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3 +#define PCI_DEVICE_ID_INTEL_82801DB_4 0x24c4 +#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5 +#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6 +#define PCI_DEVICE_ID_INTEL_82801DB_7 0x24c7 +#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca +#define PCI_DEVICE_ID_INTEL_82801DB_11 0x24cb +#define PCI_DEVICE_ID_INTEL_82801DB_12 0x24cc +#define PCI_DEVICE_ID_INTEL_82801DB_13 0x24cd +#define PCI_DEVICE_ID_INTEL_82801EB_0 0x24d0 +#define PCI_DEVICE_ID_INTEL_82801EB_1 0x24d1 +#define PCI_DEVICE_ID_INTEL_82801EB_2 0x24d2 +#define PCI_DEVICE_ID_INTEL_82801EB_3 0x24d3 +#define PCI_DEVICE_ID_INTEL_82801EB_4 0x24d4 +#define PCI_DEVICE_ID_INTEL_82801EB_5 0x24d5 +#define PCI_DEVICE_ID_INTEL_82801EB_6 0x24d6 +#define PCI_DEVICE_ID_INTEL_82801EB_7 0x24d7 +#define PCI_DEVICE_ID_INTEL_82801DB_10 0x24ca +#define PCI_DEVICE_ID_INTEL_82801EB_11 0x24db +#define PCI_DEVICE_ID_INTEL_82801EB_13 0x24dd +#define PCI_DEVICE_ID_INTEL_ESB_0 0x25a0 +#define PCI_DEVICE_ID_INTEL_ESB_1 0x25a1 +#define PCI_DEVICE_ID_INTEL_ESB_2 0x25a2 +#define PCI_DEVICE_ID_INTEL_ESB_3 0x25a3 +#define PCI_DEVICE_ID_INTEL_ESB_31 0x25b0 +#define PCI_DEVICE_ID_INTEL_ESB_4 0x25a4 +#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6 +#define PCI_DEVICE_ID_INTEL_ESB_6 0x25a7 +#define PCI_DEVICE_ID_INTEL_ESB_7 0x25a9 +#define PCI_DEVICE_ID_INTEL_ESB_8 0x25aa +#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab +#define PCI_DEVICE_ID_INTEL_ESB_11 0x25ac +#define PCI_DEVICE_ID_INTEL_ESB_12 0x25ad +#define PCI_DEVICE_ID_INTEL_ESB_13 0x25ae +#define PCI_DEVICE_ID_INTEL_ICH6_0 0x2640 +#define PCI_DEVICE_ID_INTEL_ICH6_1 0x2641 +#define PCI_DEVICE_ID_INTEL_ICH6_2 0x266f +#define PCI_DEVICE_ID_INTEL_ICH6_3 0x266e +#define PCI_DEVICE_ID_INTEL_82850_HB 0x2530 +#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 +#define PCI_DEVICE_ID_INTEL_80310 0x530d +#define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 +#define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 +#define PCI_DEVICE_ID_INTEL_82810_MC3 0x7122 +#define PCI_DEVICE_ID_INTEL_82810_IG3 0x7123 +#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 +#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 +#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 +#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 +#define PCI_DEVICE_ID_INTEL_82443MX_0 0x7198 +#define PCI_DEVICE_ID_INTEL_82443MX_1 0x7199 +#define PCI_DEVICE_ID_INTEL_82443MX_2 0x719a +#define PCI_DEVICE_ID_INTEL_82443MX_3 0x719b +#define PCI_DEVICE_ID_INTEL_82443GX_0 0x71a0 +#define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1 +#define PCI_DEVICE_ID_INTEL_82443GX_2 0x71a2 +#define PCI_DEVICE_ID_INTEL_82372FB_0 0x7600 +#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 +#define PCI_DEVICE_ID_INTEL_82372FB_2 0x7602 +#define PCI_DEVICE_ID_INTEL_82372FB_3 0x7603 +#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 +#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 +#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca +#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb + +#define PCI_VENDOR_ID_COMPUTONE 0x8e0e +#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 +#define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 +#define PCI_SUBVENDOR_ID_COMPUTONE 0x8e0e +#define PCI_SUBDEVICE_ID_COMPUTONE_PG4 0x0001 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG8 0x0002 +#define PCI_SUBDEVICE_ID_COMPUTONE_PG6 0x0003 + +#define PCI_VENDOR_ID_KTI 0x8e2e +#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 + +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 +#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 +#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 +#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 +#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 +#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 +#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 +#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 +#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 +#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 +#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 +#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 +#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 +#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 +#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 +#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 +#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 +#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 +#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 +#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 +#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 +#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 +#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 +#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 +#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 +#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 + +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 +#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 +#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 +#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f +#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 +#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 +#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f +#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 +#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 +#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 +#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f +#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 +#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 +#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 +#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf + +#define PCI_VENDOR_ID_ATRONICS 0x907f +#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 + +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 + +#define PCI_VENDOR_ID_NETMOS 0x9710 +#define PCI_DEVICE_ID_NETMOS_9735 0x9735 +#define PCI_DEVICE_ID_NETMOS_9835 0x9835 + +#define PCI_SUBVENDOR_ID_EXSYS 0xd84d +#define PCI_SUBDEVICE_ID_EXSYS_4014 0x4014 +#define PCI_SUBDEVICE_ID_EXSYS_4055 0x4055 + +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_DEVICE_ID_TIGERJET_300 0x0001 +#define PCI_DEVICE_ID_TIGERJET_100 0x0002 + +#define PCI_VENDOR_ID_ARK 0xedd8 +#define PCI_DEVICE_ID_ARK_STING 0xa091 +#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 +#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 + +#define PCI_VENDOR_ID_MICROGATE 0x13c0 +#define PCI_DEVICE_ID_MICROGATE_USC 0x0010 +#define PCI_DEVICE_ID_MICROGATE_SCC 0x0020 +#define PCI_DEVICE_ID_MICROGATE_SCA 0x0030 diff --git a/u-boot/include/rtc.h b/u-boot/include/rtc.h new file mode 100755 index 0000000..a742077 --- /dev/null +++ b/u-boot/include/rtc.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Generic RTC interface. + */ +#ifndef _RTC_H_ +#define _RTC_H_ + +/* + * The struct used to pass data from the generic interface code to + * the hardware dependend low-level code ande vice versa. Identical + * to struct rtc_time used by the Linux kernel. + * + * Note that there are small but significant differences to the + * common "struct time": + * + * struct time: struct rtc_time: + * tm_mon 0 ... 11 1 ... 12 + * tm_year years since 1900 years since 0 + */ + +struct rtc_time { + int tm_sec; + int tm_min; + int tm_hour; + int tm_mday; + int tm_mon; + int tm_year; + int tm_wday; + int tm_yday; + int tm_isdst; +}; + +void rtc_get(struct rtc_time *); +void rtc_set(struct rtc_time *); +void rtc_reset(void); + +void GregorianDay(struct rtc_time *); +void to_tm(int, struct rtc_time *); +unsigned long mktime(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int); + +#endif /* _RTC_H_ */ diff --git a/u-boot/include/serial.h b/u-boot/include/serial.h new file mode 100755 index 0000000..c8abb72 --- /dev/null +++ b/u-boot/include/serial.h @@ -0,0 +1,37 @@ +#ifndef __SERIAL_H__ +#define __SERIAL_H__ + +#define NAMESIZE 16 +#define CTLRSIZE 8 + +struct serial_device { + char name[NAMESIZE]; + char ctlr[CTLRSIZE]; + + int (*init) (void); + void (*setbrg) (void); + int (*getc) (void); + int (*tstc) (void); + void (*putc) (const char c); + void (*puts) (const char *s); + + struct serial_device *next; +}; + +extern struct serial_device serial_smc_device; +extern struct serial_device serial_scc_device; +extern struct serial_device * default_serial_console (void); + +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ + || defined(CONFIG_405EP) +extern struct serial_device serial0_device; +extern struct serial_device serial1_device; +#endif + + +extern void serial_initialize(void); +extern void serial_devices_init(void); +extern int serial_assign(char * name); +extern void serial_reinit_all(void); + +#endif diff --git a/u-boot/include/tpLinuxTag.h b/u-boot/include/tpLinuxTag.h new file mode 100755 index 0000000..425560a --- /dev/null +++ b/u-boot/include/tpLinuxTag.h @@ -0,0 +1,60 @@ + +/************************************************************************************** +* File Name : tpLinuxTag.h +* +* Description: add tag with validation system to the firmware image file to be uploaded +* via http +* +* Created : 16Sep07, Liang Qiming +**************************************************************************************/ + +#ifndef _TP_LINUX_TAG_H_ +#define _TP_LINUX_TAG_H_ + +/* + * File tag (head) structure all is in clear text + * except validationTokens (crc, md5, sha1, etc). + * + * Total: 128 unsigned chars + */ +#define TAG_LEN 512 +#define SIG_LEN 24 +#define SIG_LEN_2 12 // Original second SIG = 20 is now devided into 14 for SIG_LEN_2 and 6 for CHIP_ID +#define CHIP_ID_LEN 8 +#define TOKEN_LEN 20 +#define BOARD_ID_LEN 16 + +/* + * TAG for downloadable image (kernel plus file system) + * integer in the structure is stored in Network-Byte order (BIG-endian) + */ +typedef struct _tplink_image_header_t { + unsigned long tagVersion; + char signiture_1[SIG_LEN]; // text line for company info + char signiture_2[SIG_LEN_2]; // additional info (can be version number) + char chipId[CHIP_ID_LEN]; // chip id + char boardId[BOARD_ID_LEN]; // board id + unsigned long productId; // product id + unsigned long productVer; // product version + unsigned long reserved1; // reserved for future + + unsigned char imageValidationToken[TOKEN_LEN]; // image validation token - md5 checksum + unsigned char kernelValidationToken[TOKEN_LEN]; // kernel+tag validation token - md5 checksum + + unsigned long kernelTextAddr; // text section address of kernel + unsigned long kernelEntryPoint; // entry point address of kernel + + unsigned long totalImageLen; // the sum of kernelLen+rootfsLen+tagLen + + unsigned long kernelAddress; // starting address (offset from the beginning of FILE_TAG) of kernel image + unsigned long kernelLen; // length of kernel image + + unsigned long rootfsAddress; // starting address (offset) of filesystem image + unsigned long rootfsLen; // length of filesystem image + + unsigned long bootloaderAddress; // starting address (offset) of boot loader image + unsigned long bootloaderLen; // length of boot loader image + +} tplink_image_header_t; + +#endif /* ifndef _TP_LINUX_TAG_H_ */ diff --git a/u-boot/include/version.h b/u-boot/include/version.h new file mode 100755 index 0000000..b56d2e9 --- /dev/null +++ b/u-boot/include/version.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __VERSION_H__ +#define __VERSION_H__ + +#include "version_autogenerated.h" + +#endif /* __VERSION_H__ */ diff --git a/u-boot/include/zlib.h b/u-boot/include/zlib.h new file mode 100755 index 0000000..e441494 --- /dev/null +++ b/u-boot/include/zlib.h @@ -0,0 +1,434 @@ +/* + * This file is derived from zlib.h and zconf.h from the zlib-0.95 + * distribution by Jean-loup Gailly and Mark Adler, with some additions + * by Paul Mackerras to aid in implementing Deflate compression and + * decompression for PPP packets. + */ + +/* + * ==FILEVERSION 960122== + * + * This marker is used by the Linux installation script to determine + * whether an up-to-date version of this file is already installed. + */ + +/* zlib.h -- interface of the 'zlib' general purpose compression library + version 0.95, Aug 16th, 1995. + + Copyright (C) 1995 Jean-loup Gailly and Mark Adler + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + + Jean-loup Gailly Mark Adler + gzip@prep.ai.mit.edu madler@alumni.caltech.edu + */ + +#ifndef _ZLIB_H +#define _ZLIB_H + +/* #include "zconf.h" */ /* included directly here */ + +/* zconf.h -- configuration of the zlib compression library + * Copyright (C) 1995 Jean-loup Gailly. + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +/* From: zconf.h,v 1.12 1995/05/03 17:27:12 jloup Exp */ + +/* + The library does not install any signal handler. It is recommended to + add at least a handler for SIGSEGV when decompressing; the library checks + the consistency of the input data whenever possible but may go nuts + for some forms of corrupted input. + */ + +/* + * Compile with -DMAXSEG_64K if the alloc function cannot allocate more + * than 64k bytes at a time (needed on systems with 16-bit int). + * Compile with -DUNALIGNED_OK if it is OK to access shorts or ints + * at addresses which are not a multiple of their size. + * Under DOS, -DFAR=far or -DFAR=__far may be needed. + */ + +#ifndef STDC +# if defined(MSDOS) || defined(__STDC__) || defined(__cplusplus) +# define STDC +# endif +#endif + +#ifdef __MWERKS__ /* Metrowerks CodeWarrior declares fileno() in unix.h */ +# include +#endif + +/* Maximum value for memLevel in deflateInit2 */ +#ifndef MAX_MEM_LEVEL +# ifdef MAXSEG_64K +# define MAX_MEM_LEVEL 8 +# else +# define MAX_MEM_LEVEL 9 +# endif +#endif + +#ifndef FAR +# define FAR +#endif + +/* Maximum value for windowBits in deflateInit2 and inflateInit2 */ +#ifndef MAX_WBITS +# define MAX_WBITS 15 /* 32K LZ77 window */ +#endif + +/* The memory requirements for deflate are (in bytes): + 1 << (windowBits+2) + 1 << (memLevel+9) + that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values) + plus a few kilobytes for small objects. For example, if you want to reduce + the default memory requirements from 256K to 128K, compile with + make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7" + Of course this will generally degrade compression (there's no free lunch). + + The memory requirements for inflate are (in bytes) 1 << windowBits + that is, 32K for windowBits=15 (default value) plus a few kilobytes + for small objects. +*/ + + /* Type declarations */ + +#ifndef OF /* function prototypes */ +# ifdef STDC +# define OF(args) args +# else +# define OF(args) () +# endif +#endif + +typedef unsigned char Byte; /* 8 bits */ +typedef unsigned int uInt; /* 16 bits or more */ +typedef unsigned long uLong; /* 32 bits or more */ + +typedef Byte FAR Bytef; +typedef char FAR charf; +typedef int FAR intf; +typedef uInt FAR uIntf; +typedef uLong FAR uLongf; + +#ifdef STDC + typedef void FAR *voidpf; + typedef void *voidp; +#else + typedef Byte FAR *voidpf; + typedef Byte *voidp; +#endif + +/* end of original zconf.h */ + +#define ZLIB_VERSION "0.95P" + +/* + The 'zlib' compression library provides in-memory compression and + decompression functions, including integrity checks of the uncompressed + data. This version of the library supports only one compression method + (deflation) but other algorithms may be added later and will have the same + stream interface. + + For compression the application must provide the output buffer and + may optionally provide the input buffer for optimization. For decompression, + the application must provide the input buffer and may optionally provide + the output buffer for optimization. + + Compression can be done in a single step if the buffers are large + enough (for example if an input file is mmap'ed), or can be done by + repeated calls of the compression function. In the latter case, the + application must provide more input and/or consume the output + (providing more output space) before each call. +*/ + +typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size)); +typedef void (*free_func) OF((voidpf opaque, voidpf address, uInt nbytes)); + +typedef void (*cb_func) OF((Bytef *buf, uInt len)); + +struct internal_state; + +typedef struct z_stream_s { + Bytef *next_in; /* next input byte */ + uInt avail_in; /* number of bytes available at next_in */ + uLong total_in; /* total nb of input bytes read so far */ + + Bytef *next_out; /* next output byte should be put there */ + uInt avail_out; /* remaining free space at next_out */ + uLong total_out; /* total nb of bytes output so far */ + + char *msg; /* last error message, NULL if no error */ + struct internal_state FAR *state; /* not visible by applications */ + + alloc_func zalloc; /* used to allocate the internal state */ + free_func zfree; /* used to free the internal state */ + voidp opaque; /* private data object passed to zalloc and zfree */ + + Byte data_type; /* best guess about the data type: ascii or binary */ + + cb_func outcb; /* called regularly just before blocks of output */ + +} z_stream; + +/* + The application must update next_in and avail_in when avail_in has + dropped to zero. It must update next_out and avail_out when avail_out + has dropped to zero. The application must initialize zalloc, zfree and + opaque before calling the init function. All other fields are set by the + compression library and must not be updated by the application. + + The opaque value provided by the application will be passed as the first + parameter for calls of zalloc and zfree. This can be useful for custom + memory management. The compression library attaches no meaning to the + opaque value. + + zalloc must return Z_NULL if there is not enough memory for the object. + On 16-bit systems, the functions zalloc and zfree must be able to allocate + exactly 65536 bytes, but will not be required to allocate more than this + if the symbol MAXSEG_64K is defined (see zconf.h). WARNING: On MSDOS, + pointers returned by zalloc for objects of exactly 65536 bytes *must* + have their offset normalized to zero. The default allocation function + provided by this library ensures this (see zutil.c). To reduce memory + requirements and avoid any allocation of 64K objects, at the expense of + compression ratio, compile the library with -DMAX_WBITS=14 (see zconf.h). + + The fields total_in and total_out can be used for statistics or + progress reports. After compression, total_in holds the total size of + the uncompressed data and may be saved for use in the decompressor + (particularly if the decompressor wants to decompress everything in + a single step). +*/ + + /* constants */ + +#define Z_NO_FLUSH 0 +#define Z_PARTIAL_FLUSH 1 +#define Z_FULL_FLUSH 2 +#define Z_SYNC_FLUSH 3 /* experimental: partial_flush + byte align */ +#define Z_FINISH 4 +#define Z_PACKET_FLUSH 5 +/* See deflate() below for the usage of these constants */ + +#define Z_OK 0 +#define Z_STREAM_END 1 +#define Z_ERRNO (-1) +#define Z_STREAM_ERROR (-2) +#define Z_DATA_ERROR (-3) +#define Z_MEM_ERROR (-4) +#define Z_BUF_ERROR (-5) +/* error codes for the compression/decompression functions */ + +#define Z_BEST_SPEED 1 +#define Z_BEST_COMPRESSION 9 +#define Z_DEFAULT_COMPRESSION (-1) +/* compression levels */ + +#define Z_FILTERED 1 +#define Z_HUFFMAN_ONLY 2 +#define Z_DEFAULT_STRATEGY 0 + +#define Z_BINARY 0 +#define Z_ASCII 1 +#define Z_UNKNOWN 2 +/* Used to set the data_type field */ + +#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */ + +extern char *zlib_version; +/* The application can compare zlib_version and ZLIB_VERSION for consistency. + If the first character differs, the library code actually used is + not compatible with the zlib.h header file used by the application. + */ + + /* basic functions */ + +extern int inflateInit OF((z_stream *strm)); +/* + Initializes the internal stream state for decompression. The fields + zalloc and zfree must be initialized before by the caller. If zalloc and + zfree are set to Z_NULL, inflateInit updates them to use default allocation + functions. + + inflateInit returns Z_OK if success, Z_MEM_ERROR if there was not + enough memory. msg is set to null if there is no error message. + inflateInit does not perform any decompression: this will be done by + inflate(). +*/ + + +extern int inflate OF((z_stream *strm, int flush)); +/* + Performs one or both of the following actions: + + - Decompress more input starting at next_in and update next_in and avail_in + accordingly. If not all input can be processed (because there is not + enough room in the output buffer), next_in is updated and processing + will resume at this point for the next call of inflate(). + + - Provide more output starting at next_out and update next_out and avail_out + accordingly. inflate() always provides as much output as possible + (until there is no more input data or no more space in the output buffer). + + Before the call of inflate(), the application should ensure that at least + one of the actions is possible, by providing more input and/or consuming + more output, and updating the next_* and avail_* values accordingly. + The application can consume the uncompressed output when it wants, for + example when the output buffer is full (avail_out == 0), or after each + call of inflate(). + + If the parameter flush is set to Z_PARTIAL_FLUSH or Z_PACKET_FLUSH, + inflate flushes as much output as possible to the output buffer. The + flushing behavior of inflate is not specified for values of the flush + parameter other than Z_PARTIAL_FLUSH, Z_PACKET_FLUSH or Z_FINISH, but the + current implementation actually flushes as much output as possible + anyway. For Z_PACKET_FLUSH, inflate checks that once all the input data + has been consumed, it is expecting to see the length field of a stored + block; if not, it returns Z_DATA_ERROR. + + inflate() should normally be called until it returns Z_STREAM_END or an + error. However if all decompression is to be performed in a single step + (a single call of inflate), the parameter flush should be set to + Z_FINISH. In this case all pending input is processed and all pending + output is flushed; avail_out must be large enough to hold all the + uncompressed data. (The size of the uncompressed data may have been saved + by the compressor for this purpose.) The next operation on this stream must + be inflateEnd to deallocate the decompression state. The use of Z_FINISH + is never required, but can be used to inform inflate that a faster routine + may be used for the single inflate() call. + + inflate() returns Z_OK if some progress has been made (more input + processed or more output produced), Z_STREAM_END if the end of the + compressed data has been reached and all uncompressed output has been + produced, Z_DATA_ERROR if the input data was corrupted, Z_STREAM_ERROR if + the stream structure was inconsistent (for example if next_in or next_out + was NULL), Z_MEM_ERROR if there was not enough memory, Z_BUF_ERROR if no + progress is possible or if there was not enough room in the output buffer + when Z_FINISH is used. In the Z_DATA_ERROR case, the application may then + call inflateSync to look for a good compression block. */ + + +extern int inflateEnd OF((z_stream *strm)); +/* + All dynamically allocated data structures for this stream are freed. + This function discards any unprocessed input and does not flush any + pending output. + + inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state + was inconsistent. In the error case, msg may be set but then points to a + static string (which must not be deallocated). +*/ + + /* advanced functions */ + +extern int inflateInit2 OF((z_stream *strm, + int windowBits)); +/* + This is another version of inflateInit with more compression options. The + fields next_out, zalloc and zfree must be initialized before by the caller. + + The windowBits parameter is the base two logarithm of the maximum window + size (the size of the history buffer). It should be in the range 8..15 for + this version of the library (the value 16 will be allowed soon). The + default value is 15 if inflateInit is used instead. If a compressed stream + with a larger window size is given as input, inflate() will return with + the error code Z_DATA_ERROR instead of trying to allocate a larger window. + + If next_out is not null, the library will use this buffer for the history + buffer; the buffer must either be large enough to hold the entire output + data, or have at least 1<Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return result; } \ + BufferLim = Buffer + size; if (size == 0) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } }} +#else + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { return result; } \ + BufferLim = Buffer + size; if (size == 0) { return LZMA_RESULT_DATA_ERROR; } }} +#endif + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#if 0 +#define RC_TEST { if (Buffer == BufferLim) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } } +#else +#define RC_TEST { if (Buffer == BufferLim) { return LZMA_RESULT_DATA_ERROR; } } +#endif + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + { +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("ERROR: %s, %d\n", __FILE__, __LINE__); +#endif + return LZMA_RESULT_DATA_ERROR; + } + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + { +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("ERROR: %s, %d\n", __FILE__, __LINE__); +#endif + return LZMA_RESULT_DATA_ERROR; + } + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("ERROR: %s, %d\n", __FILE__, __LINE__); +#endif + return LZMA_RESULT_DATA_ERROR; + } + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("ERROR: %s, %d\n", __FILE__, __LINE__); +#endif + return LZMA_RESULT_DATA_ERROR; + } + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} + +#endif /* CONFIG_LZMA */ diff --git a/u-boot/lib_bootstrap/LzmaDecode.h b/u-boot/lib_bootstrap/LzmaDecode.h new file mode 100755 index 0000000..2870eeb --- /dev/null +++ b/u-boot/lib_bootstrap/LzmaDecode.h @@ -0,0 +1,113 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +#include "LzmaTypes.h" + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb UInt16 +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/u-boot/lib_bootstrap/LzmaTypes.h b/u-boot/lib_bootstrap/LzmaTypes.h new file mode 100755 index 0000000..288c5e4 --- /dev/null +++ b/u-boot/lib_bootstrap/LzmaTypes.h @@ -0,0 +1,45 @@ +/* +LzmaTypes.h + +Types for LZMA Decoder + +This file written and distributed to public domain by Igor Pavlov. +This file is part of LZMA SDK 4.40 (2006-05-01) +*/ + +#ifndef __LZMATYPES_H +#define __LZMATYPES_H + +#ifndef _7ZIP_BYTE_DEFINED +#define _7ZIP_BYTE_DEFINED +typedef unsigned char Byte; +#endif + +#ifndef _7ZIP_UINT16_DEFINED +#define _7ZIP_UINT16_DEFINED +typedef unsigned short UInt16; +#endif + +#ifndef _7ZIP_UINT32_DEFINED +#define _7ZIP_UINT32_DEFINED +#ifdef _LZMA_UINT32_IS_ULONG +typedef unsigned long UInt32; +#else +typedef unsigned int UInt32; +#endif +#endif + +/* #define _LZMA_SYSTEM_SIZE_T */ +/* Use system's size_t. You can use it to enable 64-bit sizes supporting */ + +#ifndef _7ZIP_SIZET_DEFINED +#define _7ZIP_SIZET_DEFINED +#ifdef _LZMA_SYSTEM_SIZE_T +#include +typedef size_t SizeT; +#else +typedef UInt32 SizeT; +#endif +#endif + +#endif diff --git a/u-boot/lib_bootstrap/LzmaWrapper.c b/u-boot/lib_bootstrap/LzmaWrapper.c new file mode 100755 index 0000000..fd5d047 --- /dev/null +++ b/u-boot/lib_bootstrap/LzmaWrapper.c @@ -0,0 +1,223 @@ +/****************************************************************************** +** +** FILE NAME : LzmaWrapper.c +** PROJECT : bootloader +** MODULES : U-boot +** +** DATE : 2 Nov 2006 +** AUTHOR : Lin Mars +** DESCRIPTION : LZMA decoder support for U-boot 1.1.5 +** COPYRIGHT : Copyright (c) 2006 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from +** LZMA v4.43 SDK +*******************************************************************************/ +#define LZMA_NO_STDIO +#ifndef LZMA_NO_STDIO +#include +#include +#include +#endif + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_LZMA + +#include "LzmaDecode.h" +#include "LzmaWrapper.h" + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF +static const char *kCantReadMessage = "Can not read from source buffer"; +static const char *kCantAllocateMessage = "Not enough buffer for decompression"; +#endif + +static size_t rpos=0; + +static int MyReadFileAndCheck(unsigned char *src, void *dest, size_t size){ + if (size == 0) + return 0; + memcpy(dest, src + rpos, size); + rpos += size; + return 1; +} + +int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len){ + /* We use two 32-bit integers to construct 64-bit integer for file size. + You can remove outSizeHigh, if you don't need >= 4GB supporting, + or you can use UInt64 outSize, if your compiler supports 64-bit integers*/ + UInt32 outSize = 0; + UInt32 outSizeHigh = 0; + SizeT outSizeFull; + unsigned char *outStream; + + int waitEOS = 1; + /* waitEOS = 1, if there is no uncompressed size in headers, + so decoder will wait EOS (End of Stream Marker) in compressed stream */ + + SizeT compressedSize; + unsigned char *inStream; + + CLzmaDecoderState state; /* it's about 24-80 bytes structure, if int is 32-bit */ + unsigned char properties[LZMA_PROPERTIES_SIZE]; + + int res; + + if (sizeof(UInt32) < 4) + { +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("LZMA decoder needs correct UInt32\n"); +#endif + return LZMA_RESULT_DATA_ERROR; + } + + { + long length=s_len; + if ((long)(SizeT)length != length) + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("Too big compressed stream\n"); +#endif + return LZMA_RESULT_DATA_ERROR; + } + compressedSize = (SizeT)(length - (LZMA_PROPERTIES_SIZE + 8)); + } + + /* Read LZMA properties for compressed stream */ + + if (!MyReadFileAndCheck(source, properties, sizeof(properties))) + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("%s\n", kCantReadMessage); +#endif + return LZMA_RESULT_DATA_ERROR; + } + + /* Read uncompressed size */ + { + int i; + for (i = 0; i < 8; i++) + { + unsigned char b; + if (!MyReadFileAndCheck(source, &b, 1)) + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("%s\n", kCantReadMessage); +#endif + return LZMA_RESULT_DATA_ERROR; + } + if (b != 0xFF) + waitEOS = 0; + if (i < 4) + outSize += (UInt32)(b) << (i * 8); + else + outSizeHigh += (UInt32)(b) << ((i - 4) * 8); + } + + if (waitEOS) + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("Stream with EOS marker is not supported"); +#endif + return LZMA_RESULT_DATA_ERROR; + } + outSizeFull = (SizeT)outSize; + if (sizeof(SizeT) >= 8) + outSizeFull |= (((SizeT)outSizeHigh << 16) << 16); + else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize) + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("Too big uncompressed stream"); +#endif + return LZMA_RESULT_DATA_ERROR; + } + } + + /* Decode LZMA properties and allocate memory */ + if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("Incorrect stream properties"); +#endif + return LZMA_RESULT_DATA_ERROR; + } + state.Probs = (CProb *)malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb)); + + if (outSizeFull == 0) + outStream = 0; + else + { + if (outSizeFull > (int)d_len) + outStream = 0; + else + outStream = dest; + } + + if (compressedSize == 0) + inStream = 0; + else + { + if ((compressedSize+rpos) > s_len ) + inStream = 0; + else + inStream = source + rpos; + } + + if (state.Probs == 0 + || (outStream == 0 && outSizeFull != 0) + || (inStream == 0 && compressedSize != 0) + ) + { + free(state.Probs); + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("%s\n", kCantAllocateMessage); +#endif + return LZMA_RESULT_DATA_ERROR; + } + + /* Decompress */ + { + SizeT inProcessed; + SizeT outProcessed; + res = LzmaDecode(&state, + inStream, compressedSize, &inProcessed, + outStream, outSizeFull, &outProcessed); + if (res != 0) + { + +#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF + printf("\nDecoding error = %d\n", res); +#endif + res = 1; + } + else + { + *d_len = outProcessed; + } + } + + free(state.Probs); + return res; +} + +#endif /* CONFIG_LZMA */ diff --git a/u-boot/lib_bootstrap/Makefile b/u-boot/lib_bootstrap/Makefile new file mode 100755 index 0000000..bdcc7a1 --- /dev/null +++ b/u-boot/lib_bootstrap/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libbootstrap.a + +OBJS = bootstrap_board.o LzmaDecode.o string.o crc32.o LzmaWrapper.o time.o + +CFLAGS += -DCONFIG_LZMA=1 + +all: .depend $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + #echo "make libbootstrap.a with HEAD_SIZE $(HEAD_SIZE)" + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/lib_bootstrap/bootstrap_board.c b/u-boot/lib_bootstrap/bootstrap_board.c new file mode 100755 index 0000000..35a8f40 --- /dev/null +++ b/u-boot/lib_bootstrap/bootstrap_board.c @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "LzmaWrapper.h" + +//#define DEBUG_ENABLE_BOOTSTRAP_PRINTF + +DECLARE_GLOBAL_DATA_PTR; + +#if (((CFG_ENV_ADDR+CFG_ENV_SIZE) < BOOTSTRAP_CFG_MONITOR_BASE) || (CFG_ENV_ADDR >= (BOOTSTRAP_CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || defined(CFG_ENV_IS_IN_NVRAM) +#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) +#else +#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN +#endif + +#undef DEBUG + +extern void bootstrap_relocate_code(ulong addr_sp, gd_t *gd, ulong addr_moni); + +extern int timer_init(void); + +extern ulong uboot_end_data_bootstrap; +extern ulong uboot_end_bootstrap; + +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +static ulong mem_malloc_start; +static ulong mem_malloc_end; +static ulong mem_malloc_brk; + +/* + * The Malloc area is immediately below the monitor copy in DRAM + */ +static void mem_malloc_init(ulong dest_addr){ +// ulong dest_addr = BOOTSTRAP_CFG_MONITOR_BASE + gd->reloc_off; + + mem_malloc_end = dest_addr; + mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + + memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); +} + +void *malloc(unsigned int size){ + if(size < (mem_malloc_end - mem_malloc_start)){ + mem_malloc_start += size; + + return((void *)(mem_malloc_start - size)); + } + + return(NULL); +} + +void *realloc(void *src, unsigned int size){ + return(NULL); +} + +void free(void *src){ + return; +} + +static int init_func_ram(void){ + if((gd->ram_size = initdram()) > 0){ + return(0); + } + return(1); +} + +/* + * Breath some life into the board... + * + * The first part of initialization is running from Flash memory; + * its main purpose is to initialize the RAM so that we + * can relocate the monitor code to RAM. + */ + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ +typedef int(init_fnc_t)(void); + +init_fnc_t *init_sequence[] = { timer_init, + serial_init, + init_func_ram, + NULL, }; + +void bootstrap_board_init_f(ulong bootflag){ + gd_t gd_data, *id; + bd_t *bd; + init_fnc_t **init_fnc_ptr; + ulong addr, addr_sp, len = (ulong)&uboot_end_bootstrap - BOOTSTRAP_CFG_MONITOR_BASE; + ulong *s; + + /* Pointer is writable since we allocated a register for it. + */ + gd = &gd_data; + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset((void *)gd, 0, sizeof(gd_t)); + + for(init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr){ + if((*init_fnc_ptr)() != 0){ + hang(); + } + } + + /* + * Now that we have DRAM mapped and working, we can + * relocate the code and continue running from DRAM. + */ + addr = CFG_SDRAM_BASE + gd->ram_size; + + /* + * We can reserve some RAM "on top" here. + * round down to next 4 kB limit. + */ + addr &= ~(4096 - 1); + + /* + * Reserve memory for U-Boot code, data & bss + * round down to next 16 kB limit + */ + addr -= len; + addr &= ~(16 * 1024 - 1); + + /* + * Reserve memory for malloc() arena. + */ + addr_sp = addr - TOTAL_MALLOC_LEN; + + /* + * (permanently) allocate a Board Info struct + * and a permanent copy of the "global" data + */ + addr_sp -= sizeof(bd_t); + bd = (bd_t *)addr_sp; + gd->bd = bd; + + addr_sp -= sizeof(gd_t); + id = (gd_t *)addr_sp; + + /* + * Reserve memory for boot params. + */ + addr_sp -= CFG_BOOTPARAMS_LEN; + bd->bi_boot_params = addr_sp; + + /* + * Finally, we set up a new (bigger) stack. + * + * Leave some safety gap for SP, force alignment on 16 byte boundary + * Clear initial stack frame + */ + addr_sp -= 16; + addr_sp &= ~0xF; + s = (ulong *)addr_sp; + *s-- = 0; + *s-- = 0; + addr_sp = (ulong)s; + + /* + * Save local variables to board info struct + */ + bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ + bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ + bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ + + memcpy(id, (void *)gd, sizeof(gd_t)); + + bootstrap_relocate_code(addr_sp, id, addr); + + /* NOTREACHED - relocate_code() does not return */ +} + +/************************************************************************ + * + * This is the next part if the initialization sequence: we are now + * running from RAM and have a "normal" C environment, i. e. global + * data can be written, BSS has been cleared, the stack size in not + * that critical any more, etc. + * + ************************************************************************ + */ +void bootstrap_board_init_r(gd_t *id, ulong dest_addr){ + int i; + ulong addr; + ulong data, len, checksum; + image_header_t header; + image_header_t *hdr = &header; + unsigned int destLen; + int (*fn)(int); + + /* initialize malloc() area */ + mem_malloc_init(dest_addr); + + addr = (ulong)((char *)(BOOTSTRAP_CFG_MONITOR_BASE + ((ulong)&uboot_end_data_bootstrap - dest_addr))); + memmove(&header, (char *)addr, sizeof(image_header_t)); + + if(ntohl(hdr->ih_magic) != IH_MAGIC){ + return; + } + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if(crc32(0, (unsigned char *)data, len) != checksum){ + return; + } + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + /* + * If we've got less than 4 MB of malloc() space, + * use slower decompression algorithm which requires + * at most 2300 KB of memory. + */ + destLen = 0x0; + +#ifdef CONFIG_LZMA + i = lzma_inflate((unsigned char *)data, len, (unsigned char*)ntohl(hdr->ih_load), (int *)&destLen); + + if(i != LZMA_RESULT_OK){ + //do_reset(cmdtp, flag, argc, argv); + return; + } +#endif + + fn = (void *)ntohl(hdr->ih_load); + + (*fn)(gd->ram_size); + + hang(); +} + +void hang(void){ + for(;;); +} diff --git a/u-boot/lib_bootstrap/crc32.c b/u-boot/lib_bootstrap/crc32.c new file mode 100755 index 0000000..378318c --- /dev/null +++ b/u-boot/lib_bootstrap/crc32.c @@ -0,0 +1,158 @@ +/* + * This file is derived from crc32.c from the zlib-1.1.3 distribution + * by Jean-loup Gailly and Mark Adler. + */ + +/* crc32.c -- compute the CRC-32 of a data stream + * Copyright (C) 1995-1998 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */ +#include /* to get command definitions like CFG_CMD_JFFS2 */ +#endif + +#include "zlib.h" + +#define local static +#define ZEXPORT /* empty */ +unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); + +#ifdef DYNAMIC_CRC_TABLE + +local int crc_table_empty = 1; +local uLongf crc_table[256]; +local void make_crc_table OF((void)); + +/* + Generate a table for a byte-wise 32-bit CRC calculation on the polynomial: + x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1. + + Polynomials over GF(2) are represented in binary, one bit per coefficient, + with the lowest powers in the most significant bit. Then adding polynomials + is just exclusive-or, and multiplying a polynomial by x is a right shift by + one. If we call the above polynomial p, and represent a byte as the + polynomial q, also with the lowest power in the most significant bit (so the + byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p, + where a mod b means the remainder after dividing a by b. + + This calculation is done using the shift-register method of multiplying and + taking the remainder. The register is initialized to zero, and for each + incoming bit, x^32 is added mod p to the register if the bit is a one (where + x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by + x (which is shifting right by one and adding x^32 mod p if the bit shifted + out is a one). We start with the highest power (least significant bit) of + q and repeat for all eight bits of q. + + The table is simply the CRC of all possible eight bit values. This is all + the information needed to generate CRC's on data a byte at a time for all + combinations of CRC register values and incoming bytes. +*/ +local void make_crc_table(){ + uLong c; + int n, k; + uLong poly; /* polynomial exclusive-or pattern */ + /* terms of polynomial defining this crc (except x^32): */ + static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26}; + + /* make exclusive-or pattern from polynomial (0xedb88320L) */ + poly = 0L; + for (n = 0; n < sizeof(p)/sizeof(Byte); n++) + poly |= 1L << (31 - p[n]); + + for (n = 0; n < 256; n++) + { + c = (uLong)n; + for (k = 0; k < 8; k++) + c = c & 1 ? poly ^ (c >> 1) : c >> 1; + crc_table[n] = c; + } + crc_table_empty = 0; +} +#else +/* ======================================================================== + * Table of CRC-32's of all single-byte values (made by make_crc_table) + */ +local const uLongf crc_table[256] = { + 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, + 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L, + 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, + 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, + 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L, + 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, + 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, + 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL, + 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, + 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL, + 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, + 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, + 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L, + 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, + 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, + 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L, + 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, + 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L, + 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, + 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, + 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL, + 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, + 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L, + 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL, + 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, + 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L, + 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, + 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, + 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L, + 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, + 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, + 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L, + 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, + 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL, + 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, + 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, + 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL, + 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, + 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, + 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L, + 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, + 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L, + 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, + 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, + 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L, + 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, + 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, + 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L, + 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, + 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L, + 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, + 0x2d02ef8dL +}; +#endif + +/* ========================================================================= */ +#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8); +#define DO2(buf) DO1(buf); DO1(buf); +#define DO4(buf) DO2(buf); DO2(buf); +#define DO8(buf) DO4(buf); DO4(buf); + +/* ========================================================================= */ +uLong ZEXPORT crc32(crc, buf, len) + uLong crc; + const Bytef *buf; + uInt len; +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) + make_crc_table(); +#endif + crc = crc ^ 0xffffffffL; + while (len >= 8) + { + DO8(buf); + len -= 8; + } + if (len) do { + DO1(buf); + } while (--len); + return crc ^ 0xffffffffL; +} diff --git a/u-boot/lib_bootstrap/string.c b/u-boot/lib_bootstrap/string.c new file mode 100755 index 0000000..6675571 --- /dev/null +++ b/u-boot/lib_bootstrap/string.c @@ -0,0 +1,310 @@ +/* + * linux/lib/string.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* + * stupid library routines.. The optimized versions should generally be found + * as inline code in + * + * These are buggy as well.. + * + * * Fri Jun 25 1999, Ingo Oeser + * - Added strsep() which will replace strtok() soon (because strsep() is + * reentrant and should be faster). Use only strsep() in new code, please. + */ + +#include +#include +#include +#include + +#ifndef __HAVE_ARCH_STRCPY +/** + * strcpy - Copy a %NUL terminated string + * @dest: Where to copy the string to + * @src: Where to copy the string from + */ +char * strcpy(char * dest,const char *src){ + char *tmp = dest; + + while ((*dest++ = *src++) != '\0') + /* nothing */; + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRNCPY +/** + * strncpy - Copy a length-limited, %NUL-terminated string + * @dest: Where to copy the string to + * @src: Where to copy the string from + * @count: The maximum number of bytes to copy + * + * Note that unlike userspace strncpy, this does not %NUL-pad the buffer. + * However, the result is not %NUL-terminated if the source exceeds + * @count bytes. + */ +char * strncpy(char * dest,const char *src,size_t count){ + char *tmp = dest; + + while (count-- && (*dest++ = *src++) != '\0') + /* nothing */; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCAT +/** + * strcat - Append one %NUL-terminated string to another + * @dest: The string to be appended to + * @src: The string to append to it + */ +char * strcat(char * dest, const char * src){ + char *tmp = dest; + + while (*dest) + dest++; + while ((*dest++ = *src++) != '\0') + ; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCMP +/** + * strcmp - Compare two strings + * @cs: One string + * @ct: Another string + */ +int strcmp(const char * cs,const char * ct){ + register signed char __res; + + while (1) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRNCMP +/** + * strncmp - Compare two length-limited strings + * @cs: One string + * @ct: Another string + * @count: The maximum number of bytes to compare + */ +int strncmp(const char * cs,const char * ct,size_t count){ + register signed char __res = 0; + + while (count) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count--; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRCHR +/** + * strchr - Find the first occurrence of a character in a string + * @s: The string to be searched + * @c: The character to search for + */ +char * strchr(const char * s, int c){ + for(; *s != (char) c; ++s) + if (*s == '\0') + return NULL; + return (char *) s; +} +#endif + +#ifndef __HAVE_ARCH_STRLEN +/** + * strlen - Find the length of a string + * @s: The string to be sized + */ +size_t strlen(const char * s){ + const char *sc; + + for (sc = s; *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRNLEN +/** + * strnlen - Find the length of a length-limited string + * @s: The string to be sized + * @count: The maximum number of bytes to search + */ +size_t strnlen(const char * s, size_t count){ + const char *sc; + + for (sc = s; count-- && *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRSPN +/** + * strspn - Calculate the length of the initial substring of @s which only + * contain letters in @accept + * @s: The string to be searched + * @accept: The string to search for + */ +size_t strspn(const char *s, const char *accept){ + const char *p; + const char *a; + size_t count = 0; + + for (p = s; *p != '\0'; ++p) { + for (a = accept; *a != '\0'; ++a) { + if (*p == *a) + break; + } + if (*a == '\0') + return count; + ++count; + } + + return count; +} +#endif + +#ifndef __HAVE_ARCH_STRPBRK +/** + * strpbrk - Find the first occurrence of a set of characters + * @cs: The string to be searched + * @ct: The characters to search for + */ +char * strpbrk(const char * cs,const char * ct){ + const char *sc1,*sc2; + + for( sc1 = cs; *sc1 != '\0'; ++sc1) { + for( sc2 = ct; *sc2 != '\0'; ++sc2) { + if (*sc1 == *sc2) + return (char *) sc1; + } + } + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_MEMSET +/** + * memset - Fill a region of memory with the given value + * @s: Pointer to the start of the area. + * @c: The byte to fill the area with + * @count: The size of the area. + * + * Do not use memset() to access IO space, use memset_io() instead. + */ +void * memset(void * s,int c,size_t count){ + char *xs = (char *) s; + + while (count--) + *xs++ = c; + + return s; +} +#endif + +#ifndef __HAVE_ARCH_MEMCPY +/** + * memcpy - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * You should not use this function to access IO space, use memcpy_toio() + * or memcpy_fromio() instead. + */ +void * memcpy(void * dest,const void *src,size_t count){ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMMOVE +/** + * memmove - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * Unlike memcpy(), memmove() copes with overlapping areas. + */ +void * memmove(void * dest,const void *src,size_t count){ + char *tmp, *s; + + if (dest <= src) { + tmp = (char *) dest; + s = (char *) src; + while (count--) + *tmp++ = *s++; + } + else { + tmp = (char *) dest + count; + s = (char *) src + count; + while (count--) + *--tmp = *--s; + } + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMCMP +/** + * memcmp - Compare two areas of memory + * @cs: One area of memory + * @ct: Another area of memory + * @count: The size of the area. + */ +int memcmp(const void * cs,const void * ct,size_t count){ + const unsigned char *su1, *su2; + int res = 0; + + for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + return res; +} +#endif + +#ifndef __HAVE_ARCH_STRSTR +/** + * strstr - Find the first substring in a %NUL terminated string + * @s1: The string to be searched + * @s2: The string to search for + */ +char * strstr(const char * s1,const char * s2){ + int l1, l2; + + l2 = strlen(s2); + if (!l2) + return (char *) s1; + l1 = strlen(s1); + while (l1 >= l2) { + l1--; + if (!memcmp(s1,s2,l2)) + return (char *) s1; + s1++; + } + return NULL; +} +#endif diff --git a/u-boot/lib_bootstrap/time.c b/u-boot/lib_bootstrap/time.c new file mode 100755 index 0000000..a00d9b8 --- /dev/null +++ b/u-boot/lib_bootstrap/time.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +static inline void mips_compare_set(u32 v){ + asm volatile ("mtc0 %0, $11" : : "r" (v)); +} + +static inline void mips_count_set(u32 v){ + asm volatile ("mtc0 %0, $9" : : "r" (v)); +} + +static inline u32 mips_count_get(void){ + u32 count; + + asm volatile ("mfc0 %0, $9" : "=r" (count) :); + return(count); +} + +/* + * timer without interrupts + */ +int timer_init(void){ + mips_compare_set(0); + mips_count_set(0); + + return(0); +} + +ulong get_timer(ulong base){ + return(mips_count_get() - base); +} + +void udelay(unsigned long usec){ + ulong tmo; + ulong start = get_timer(0); + + tmo = usec * (CFG_HZ / 1000000); + while ((ulong) ((mips_count_get() - start)) < tmo) + /*NOP*/; +} diff --git a/u-boot/lib_generic/LzmaDecode.c b/u-boot/lib_generic/LzmaDecode.c new file mode 100755 index 0000000..95400d3 --- /dev/null +++ b/u-boot/lib_generic/LzmaDecode.c @@ -0,0 +1,600 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifdef CONFIG_LZMA + +#include "LzmaDecode.h" + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { return result; } \ + BufferLim = Buffer + size; if (size == 0) { return LZMA_RESULT_DATA_ERROR; } }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) { return LZMA_RESULT_DATA_ERROR; } } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + { + //printf("ERROR: %s, %d\n", __FILE__, __LINE__); + return LZMA_RESULT_DATA_ERROR; + } + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + { + //printf("ERROR: %s, %d\n", __FILE__, __LINE__); + return LZMA_RESULT_DATA_ERROR; + } + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + { + //printf("ERROR: %s, %d\n", __FILE__, __LINE__); + return LZMA_RESULT_DATA_ERROR; + } + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + { + //printf("ERROR: %s, %d\n", __FILE__, __LINE__); + return LZMA_RESULT_DATA_ERROR; + } + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} + +#endif /* CONFIG_LZMA */ diff --git a/u-boot/lib_generic/LzmaDecode.h b/u-boot/lib_generic/LzmaDecode.h new file mode 100755 index 0000000..2870eeb --- /dev/null +++ b/u-boot/lib_generic/LzmaDecode.h @@ -0,0 +1,113 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +#include "LzmaTypes.h" + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb UInt16 +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/u-boot/lib_generic/LzmaTypes.h b/u-boot/lib_generic/LzmaTypes.h new file mode 100755 index 0000000..288c5e4 --- /dev/null +++ b/u-boot/lib_generic/LzmaTypes.h @@ -0,0 +1,45 @@ +/* +LzmaTypes.h + +Types for LZMA Decoder + +This file written and distributed to public domain by Igor Pavlov. +This file is part of LZMA SDK 4.40 (2006-05-01) +*/ + +#ifndef __LZMATYPES_H +#define __LZMATYPES_H + +#ifndef _7ZIP_BYTE_DEFINED +#define _7ZIP_BYTE_DEFINED +typedef unsigned char Byte; +#endif + +#ifndef _7ZIP_UINT16_DEFINED +#define _7ZIP_UINT16_DEFINED +typedef unsigned short UInt16; +#endif + +#ifndef _7ZIP_UINT32_DEFINED +#define _7ZIP_UINT32_DEFINED +#ifdef _LZMA_UINT32_IS_ULONG +typedef unsigned long UInt32; +#else +typedef unsigned int UInt32; +#endif +#endif + +/* #define _LZMA_SYSTEM_SIZE_T */ +/* Use system's size_t. You can use it to enable 64-bit sizes supporting */ + +#ifndef _7ZIP_SIZET_DEFINED +#define _7ZIP_SIZET_DEFINED +#ifdef _LZMA_SYSTEM_SIZE_T +#include +typedef size_t SizeT; +#else +typedef UInt32 SizeT; +#endif +#endif + +#endif diff --git a/u-boot/lib_generic/LzmaWrapper.c b/u-boot/lib_generic/LzmaWrapper.c new file mode 100755 index 0000000..076e8ab --- /dev/null +++ b/u-boot/lib_generic/LzmaWrapper.c @@ -0,0 +1,179 @@ +/****************************************************************************** + ** + ** FILE NAME : LzmaWrapper.c + ** PROJECT : bootloader + ** MODULES : U-boot + ** + ** DATE : 2 Nov 2006 + ** AUTHOR : Lin Mars + ** DESCRIPTION : LZMA decoder support for U-boot 1.1.5 + ** COPYRIGHT : Copyright (c) 2006 + ** Infineon Technologies AG + ** Am Campeon 1-12, 85579 Neubiberg, Germany + ** + ** This program is free software; you can redistribute it and/or modify + ** it under the terms of the GNU General Public License as published by + ** the Free Software Foundation; either version 2 of the License, or + ** (at your option) any later version. + ** + ** HISTORY + ** $Date $Author $Comment + ** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from + ** LZMA v4.43 SDK + *******************************************************************************/ +#define LZMA_NO_STDIO +#ifndef LZMA_NO_STDIO +#include +#include +#include +#endif + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_LZMA + +#include "LzmaDecode.h" +#include "LzmaWrapper.h" + +//static const char *kCantReadMessage = "can not read from source buffer"; +//static const char *kCantAllocateMessage = "not enough buffer for decompression"; + +static size_t rpos = 0; + +static int MyReadFileAndCheck(unsigned char *src, void *dest, size_t size) { + if (size == 0) return 0; + memcpy(dest, src + rpos, size); + rpos += size; + return 1; +} + +int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len) { + /* We use two 32-bit integers to construct 64-bit integer for file size. + You can remove outSizeHigh, if you don't need >= 4GB supporting, + or you can use UInt64 outSize, if your compiler supports 64-bit integers*/ + UInt32 outSize = 0; + UInt32 outSizeHigh = 0; + SizeT outSizeFull; + unsigned char *outStream; + + int waitEOS = 1; + /* waitEOS = 1, if there is no uncompressed size in headers, + so decoder will wait EOS (End of Stream Marker) in compressed stream */ + + SizeT compressedSize; + unsigned char *inStream; + + CLzmaDecoderState state; /* it's about 24-80 bytes structure, if int is 32-bit */ + unsigned char properties[LZMA_PROPERTIES_SIZE]; + + int res; + + if (sizeof(UInt32) < 4) { + //printf("## Error: LZMA decoder needs correct UInt32\n"); + return LZMA_RESULT_DATA_ERROR; + } + + long length = s_len; + + if ((long) (SizeT) length != length) { + //printf("## Error: too big compressed stream\n"); + return LZMA_RESULT_DATA_ERROR; + } + + compressedSize = (SizeT) (length - (LZMA_PROPERTIES_SIZE + 8)); + + /* Read LZMA properties for compressed stream */ + + if (!MyReadFileAndCheck(source, properties, sizeof(properties))) { + //printf("## Error: %s\n", kCantReadMessage); + return LZMA_RESULT_DATA_ERROR; + } + + /* Read uncompressed size */ + + int i; + + for (i = 0; i < 8; i++) { + unsigned char b; + if (!MyReadFileAndCheck(source, &b, 1)) { + //printf("## Error: %s\n", kCantReadMessage); + return LZMA_RESULT_DATA_ERROR; + } + if (b != 0xFF) waitEOS = 0; + if (i < 4) + outSize += (UInt32) (b) << (i * 8); + else + outSizeHigh += (UInt32) (b) << ((i - 4) * 8); + } + + if (waitEOS) { + //printf("## Error: stream with EOS marker is not supported\n"); + return LZMA_RESULT_DATA_ERROR; + } + + outSizeFull = (SizeT) outSize; + + if (sizeof(SizeT) >= 8){ + outSizeFull |= (((SizeT) outSizeHigh << 16) << 16); + } else if (outSizeHigh != 0 || (UInt32) (SizeT) outSize != outSize) { + //printf("## Error: too big uncompressed stream\n"); + return LZMA_RESULT_DATA_ERROR; + } + + + /* Decode LZMA properties and allocate memory */ + if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) { + //printf("## Error: incorrect stream properties\n"); + return LZMA_RESULT_DATA_ERROR; + } + + state.Probs = (CProb *) malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb)); + + if (outSizeFull == 0){ + outStream = 0; + } else { + if (outSizeFull > *d_len){ + outStream = 0; + } else{ + outStream = dest; + } + } + + if (compressedSize == 0){ + inStream = 0; + } else { + if ((compressedSize + rpos) > s_len){ + inStream = 0; + } else{ + inStream = source + rpos; + } + } + + if (state.Probs == 0 || (outStream == 0 && outSizeFull != 0) || (inStream == 0 && compressedSize != 0)) { + free(state.Probs); + //printf("## Error: %s\n", kCantAllocateMessage); + return LZMA_RESULT_DATA_ERROR; + } + + /* Decompress */ + SizeT inProcessed; + SizeT outProcessed; + res = LzmaDecode(&state, inStream, compressedSize, &inProcessed, outStream, outSizeFull, &outProcessed); + + if (res != 0) { + //printf("\n## Error: decoding error = %d\n", res); + res = 1; + } else { + *d_len = outProcessed; + } + + free(state.Probs); + return res; +} + +#endif /* CONFIG_LZMA */ diff --git a/u-boot/lib_generic/Makefile b/u-boot/lib_generic/Makefile new file mode 100755 index 0000000..4fe3648 --- /dev/null +++ b/u-boot/lib_generic/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libgeneric.a + +OBJS = crc32.o ctype.o display_options.o ldiv.o string.o vsprintf.o LzmaWrapper.o LzmaDecode.o + +CFLAGS += -DCONFIG_LZMA=1 + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/lib_generic/crc32.c b/u-boot/lib_generic/crc32.c new file mode 100755 index 0000000..b9d15ab --- /dev/null +++ b/u-boot/lib_generic/crc32.c @@ -0,0 +1,172 @@ +/* + * This file is derived from crc32.c from the zlib-1.1.3 distribution + * by Jean-loup Gailly and Mark Adler. + */ + +/* crc32.c -- compute the CRC-32 of a data stream + * Copyright (C) 1995-1998 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */ +#include /* to get command definitions like CFG_CMD_JFFS2 */ +#endif + +#include "zlib.h" + +#define local static +#define ZEXPORT /* empty */ +unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); + +#ifdef DYNAMIC_CRC_TABLE + +local int crc_table_empty = 1; +local uLongf crc_table[256]; +local void make_crc_table OF((void)); + +/* + Generate a table for a byte-wise 32-bit CRC calculation on the polynomial: + x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1. + + Polynomials over GF(2) are represented in binary, one bit per coefficient, + with the lowest powers in the most significant bit. Then adding polynomials + is just exclusive-or, and multiplying a polynomial by x is a right shift by + one. If we call the above polynomial p, and represent a byte as the + polynomial q, also with the lowest power in the most significant bit (so the + byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p, + where a mod b means the remainder after dividing a by b. + + This calculation is done using the shift-register method of multiplying and + taking the remainder. The register is initialized to zero, and for each + incoming bit, x^32 is added mod p to the register if the bit is a one (where + x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by + x (which is shifting right by one and adding x^32 mod p if the bit shifted + out is a one). We start with the highest power (least significant bit) of + q and repeat for all eight bits of q. + + The table is simply the CRC of all possible eight bit values. This is all + the information needed to generate CRC's on data a byte at a time for all + combinations of CRC register values and incoming bytes. +*/ +local void make_crc_table() +{ + uLong c; + int n, k; + uLong poly; /* polynomial exclusive-or pattern */ + /* terms of polynomial defining this crc (except x^32): */ + static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26}; + + /* make exclusive-or pattern from polynomial (0xedb88320L) */ + poly = 0L; + for (n = 0; n < sizeof(p)/sizeof(Byte); n++) + poly |= 1L << (31 - p[n]); + + for (n = 0; n < 256; n++) + { + c = (uLong)n; + for (k = 0; k < 8; k++) + c = c & 1 ? poly ^ (c >> 1) : c >> 1; + crc_table[n] = c; + } + crc_table_empty = 0; +} +#else +/* ======================================================================== + * Table of CRC-32's of all single-byte values (made by make_crc_table) + */ +local const uLongf crc_table[256] = { + 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, + 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L, + 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, + 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, + 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L, + 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, + 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, + 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL, + 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, + 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL, + 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, + 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, + 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L, + 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, + 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, + 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L, + 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, + 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L, + 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, + 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, + 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL, + 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, + 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L, + 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL, + 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, + 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L, + 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, + 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, + 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L, + 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, + 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, + 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L, + 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, + 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL, + 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, + 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, + 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL, + 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, + 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, + 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L, + 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, + 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L, + 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, + 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, + 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L, + 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, + 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, + 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L, + 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, + 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L, + 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, + 0x2d02ef8dL +}; +#endif + +#if 0 +/* ========================================================================= + * This function can be used by asm versions of crc32() + */ +const uLongf * ZEXPORT get_crc_table() +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) make_crc_table(); +#endif + return (const uLongf *)crc_table; +} +#endif + +/* ========================================================================= */ +#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8); +#define DO2(buf) DO1(buf); DO1(buf); +#define DO4(buf) DO2(buf); DO2(buf); +#define DO8(buf) DO4(buf); DO4(buf); + +/* ========================================================================= */ +uLong ZEXPORT crc32(crc, buf, len) + uLong crc; + const Bytef *buf; + uInt len; +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) + make_crc_table(); +#endif + crc = crc ^ 0xffffffffL; + while (len >= 8) + { + DO8(buf); + len -= 8; + } + if (len) do { + DO1(buf); + } while (--len); + return crc ^ 0xffffffffL; +} diff --git a/u-boot/lib_generic/ctype.c b/u-boot/lib_generic/ctype.c new file mode 100755 index 0000000..6ed0468 --- /dev/null +++ b/u-boot/lib_generic/ctype.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * linux/lib/ctype.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +#include + +unsigned char _ctype[] = { +_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ +_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ +_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ +_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ +_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ +_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ +_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ +_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ +_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ +_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ +_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ +_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */ +_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */ +_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ diff --git a/u-boot/lib_generic/display_options.c b/u-boot/lib_generic/display_options.c new file mode 100755 index 0000000..65ed7ee --- /dev/null +++ b/u-boot/lib_generic/display_options.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * print sizes as "xxx kB", "xxx.y kB", "xxx MB" or "xxx.y MB" as needed; + * allow for optional trailing string (like "\n") + */ +void print_size(ulong size, const char *s){ + ulong m, n; + ulong d = 1 << 20; /* 1 MB */ + char c = 'M'; + + if (size < d) { /* print in kB */ + c = 'k'; + d = 1 << 10; + } + + n = size / d; + + m = (10 * (size - (n * d)) + (d / 2) ) / d; + + if (m >= 10) { + m -= 10; + n += 1; + } + + printf ("%ld", n); + if (m) { + printf (".%ld", m); + } + printf (" %cB%s", c, s); +} diff --git a/u-boot/lib_generic/ldiv.c b/u-boot/lib_generic/ldiv.c new file mode 100755 index 0000000..5d231a2 --- /dev/null +++ b/u-boot/lib_generic/ldiv.c @@ -0,0 +1,55 @@ +/* Copyright (C) 1992, 1997 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with the GNU C Library; see the file COPYING.LIB. If not, + write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +typedef struct { + long quot; + long rem; +} ldiv_t; +/* Return the `ldiv_t' representation of NUMER over DENOM. */ +ldiv_t +ldiv (long int numer, long int denom) +{ + ldiv_t result; + + result.quot = numer / denom; + result.rem = numer % denom; + + /* The ANSI standard says that |QUOT| <= |NUMER / DENOM|, where + NUMER / DENOM is to be computed in infinite precision. In + other words, we should always truncate the quotient towards + zero, never -infinity. Machine division and remainer may + work either way when one or both of NUMER or DENOM is + negative. If only one is negative and QUOT has been + truncated towards -infinity, REM will have the same sign as + DENOM and the opposite sign of NUMER; if both are negative + and QUOT has been truncated towards -infinity, REM will be + positive (will have the opposite sign of NUMER). These are + considered `wrong'. If both are NUM and DENOM are positive, + RESULT will always be positive. This all boils down to: if + NUMER >= 0, but REM < 0, we got the wrong answer. In that + case, to get the right answer, add 1 to QUOT and subtract + DENOM from REM. */ + + if (numer >= 0 && result.rem < 0) + { + ++result.quot; + result.rem -= denom; + } + + return result; +} diff --git a/u-boot/lib_generic/string.c b/u-boot/lib_generic/string.c new file mode 100755 index 0000000..6675571 --- /dev/null +++ b/u-boot/lib_generic/string.c @@ -0,0 +1,310 @@ +/* + * linux/lib/string.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* + * stupid library routines.. The optimized versions should generally be found + * as inline code in + * + * These are buggy as well.. + * + * * Fri Jun 25 1999, Ingo Oeser + * - Added strsep() which will replace strtok() soon (because strsep() is + * reentrant and should be faster). Use only strsep() in new code, please. + */ + +#include +#include +#include +#include + +#ifndef __HAVE_ARCH_STRCPY +/** + * strcpy - Copy a %NUL terminated string + * @dest: Where to copy the string to + * @src: Where to copy the string from + */ +char * strcpy(char * dest,const char *src){ + char *tmp = dest; + + while ((*dest++ = *src++) != '\0') + /* nothing */; + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRNCPY +/** + * strncpy - Copy a length-limited, %NUL-terminated string + * @dest: Where to copy the string to + * @src: Where to copy the string from + * @count: The maximum number of bytes to copy + * + * Note that unlike userspace strncpy, this does not %NUL-pad the buffer. + * However, the result is not %NUL-terminated if the source exceeds + * @count bytes. + */ +char * strncpy(char * dest,const char *src,size_t count){ + char *tmp = dest; + + while (count-- && (*dest++ = *src++) != '\0') + /* nothing */; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCAT +/** + * strcat - Append one %NUL-terminated string to another + * @dest: The string to be appended to + * @src: The string to append to it + */ +char * strcat(char * dest, const char * src){ + char *tmp = dest; + + while (*dest) + dest++; + while ((*dest++ = *src++) != '\0') + ; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCMP +/** + * strcmp - Compare two strings + * @cs: One string + * @ct: Another string + */ +int strcmp(const char * cs,const char * ct){ + register signed char __res; + + while (1) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRNCMP +/** + * strncmp - Compare two length-limited strings + * @cs: One string + * @ct: Another string + * @count: The maximum number of bytes to compare + */ +int strncmp(const char * cs,const char * ct,size_t count){ + register signed char __res = 0; + + while (count) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count--; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRCHR +/** + * strchr - Find the first occurrence of a character in a string + * @s: The string to be searched + * @c: The character to search for + */ +char * strchr(const char * s, int c){ + for(; *s != (char) c; ++s) + if (*s == '\0') + return NULL; + return (char *) s; +} +#endif + +#ifndef __HAVE_ARCH_STRLEN +/** + * strlen - Find the length of a string + * @s: The string to be sized + */ +size_t strlen(const char * s){ + const char *sc; + + for (sc = s; *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRNLEN +/** + * strnlen - Find the length of a length-limited string + * @s: The string to be sized + * @count: The maximum number of bytes to search + */ +size_t strnlen(const char * s, size_t count){ + const char *sc; + + for (sc = s; count-- && *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRSPN +/** + * strspn - Calculate the length of the initial substring of @s which only + * contain letters in @accept + * @s: The string to be searched + * @accept: The string to search for + */ +size_t strspn(const char *s, const char *accept){ + const char *p; + const char *a; + size_t count = 0; + + for (p = s; *p != '\0'; ++p) { + for (a = accept; *a != '\0'; ++a) { + if (*p == *a) + break; + } + if (*a == '\0') + return count; + ++count; + } + + return count; +} +#endif + +#ifndef __HAVE_ARCH_STRPBRK +/** + * strpbrk - Find the first occurrence of a set of characters + * @cs: The string to be searched + * @ct: The characters to search for + */ +char * strpbrk(const char * cs,const char * ct){ + const char *sc1,*sc2; + + for( sc1 = cs; *sc1 != '\0'; ++sc1) { + for( sc2 = ct; *sc2 != '\0'; ++sc2) { + if (*sc1 == *sc2) + return (char *) sc1; + } + } + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_MEMSET +/** + * memset - Fill a region of memory with the given value + * @s: Pointer to the start of the area. + * @c: The byte to fill the area with + * @count: The size of the area. + * + * Do not use memset() to access IO space, use memset_io() instead. + */ +void * memset(void * s,int c,size_t count){ + char *xs = (char *) s; + + while (count--) + *xs++ = c; + + return s; +} +#endif + +#ifndef __HAVE_ARCH_MEMCPY +/** + * memcpy - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * You should not use this function to access IO space, use memcpy_toio() + * or memcpy_fromio() instead. + */ +void * memcpy(void * dest,const void *src,size_t count){ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMMOVE +/** + * memmove - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * Unlike memcpy(), memmove() copes with overlapping areas. + */ +void * memmove(void * dest,const void *src,size_t count){ + char *tmp, *s; + + if (dest <= src) { + tmp = (char *) dest; + s = (char *) src; + while (count--) + *tmp++ = *s++; + } + else { + tmp = (char *) dest + count; + s = (char *) src + count; + while (count--) + *--tmp = *--s; + } + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMCMP +/** + * memcmp - Compare two areas of memory + * @cs: One area of memory + * @ct: Another area of memory + * @count: The size of the area. + */ +int memcmp(const void * cs,const void * ct,size_t count){ + const unsigned char *su1, *su2; + int res = 0; + + for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + return res; +} +#endif + +#ifndef __HAVE_ARCH_STRSTR +/** + * strstr - Find the first substring in a %NUL terminated string + * @s1: The string to be searched + * @s2: The string to search for + */ +char * strstr(const char * s1,const char * s2){ + int l1, l2; + + l2 = strlen(s2); + if (!l2) + return (char *) s1; + l1 = strlen(s1); + while (l1 >= l2) { + l1--; + if (!memcmp(s1,s2,l2)) + return (char *) s1; + s1++; + } + return NULL; +} +#endif diff --git a/u-boot/lib_generic/vsprintf.c b/u-boot/lib_generic/vsprintf.c new file mode 100755 index 0000000..e6e0638 --- /dev/null +++ b/u-boot/lib_generic/vsprintf.c @@ -0,0 +1,363 @@ +/* + * linux/lib/vsprintf.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ +/* + * Wirzenius wrote this portably, Torvalds fucked it up :-) + */ + +#include +#include +#include +#include +#include +#include + +/*cmd_boot.c*/ +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base){ + unsigned long result = 0,value; + + if (*cp == '0') { + cp++; + if ((*cp == 'x') && isxdigit(cp[1])) { + base = 16; + cp++; + } + if (!base) { + base = 8; + } + } + if (!base) { + base = 10; + } + while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) + ? toupper(*cp) : *cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } + if (endp) + *endp = (char *)cp; + return result; +} + +long simple_strtol(const char *cp,char **endp,unsigned int base){ + if(*cp=='-') + return -simple_strtoul(cp+1,endp,base); + return simple_strtoul(cp,endp,base); +} + +#ifdef CFG_64BIT_STRTOUL +unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base) +{ + unsigned long long result = 0, value; + + if (*cp == '0') { + cp++; + if ((*cp == 'x') && isxdigit (cp[1])) { + base = 16; + cp++; + } + if (!base) { + base = 8; + } + } + if (!base) { + base = 10; + } + while (isxdigit (*cp) && (value = isdigit (*cp) + ? *cp - '0' + : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) { + result = result * base + value; + cp++; + } + if (endp) + *endp = (char *) cp; + return result; +} +#endif /* CFG_64BIT_STRTOUL */ + +/* we use this so that we can do without the ctype library */ +#define is_digit(c) ((c) >= '0' && (c) <= '9') + +static int skip_atoi(const char **s){ + int i=0; + + while (is_digit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} + +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SPECIAL 32 /* 0x */ +#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ + +#define do_div(n,base) ({ \ + int __res; \ + __res = ((unsigned long) n) % (unsigned) base; \ + n = ((unsigned long) n) / (unsigned) base; \ + __res; \ +}) + +#ifdef CFG_64BIT_VSPRINTF +static char * number(char * str, long long num, int base, int size, int precision ,int type) +#else +static char * number(char * str, long num, int base, int size, int precision ,int type) +#endif +{ + char c,sign,tmp[66]; + const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; + int i; + + if (type & LARGE) + digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + if (type & LEFT) + type &= ~ZEROPAD; + if (base < 2 || base > 36) + return 0; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) { + if (num < 0) { + sign = '-'; + num = -num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (type & SPECIAL) { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } + i = 0; + if (num == 0) + tmp[i++]='0'; + else while (num != 0) + tmp[i++] = digits[do_div(num,base)]; + if (i > precision) + precision = i; + size -= precision; + if (!(type&(ZEROPAD+LEFT))) + while(size-->0) + *str++ = ' '; + if (sign) + *str++ = sign; + if (type & SPECIAL) { + if (base==8) + *str++ = '0'; + else if (base==16) { + *str++ = '0'; + *str++ = digits[33]; + } + } + if (!(type & LEFT)) + while (size-- > 0) + *str++ = c; + while (i < precision--) + *str++ = '0'; + while (i-- > 0) + *str++ = tmp[i]; + while (size-- > 0) + *str++ = ' '; + return str; +} + +/* Forward decl. needed for IP address printing stuff... */ +int sprintf(char * buf, const char *fmt, ...); + +int vsprintf(char *buf, const char *fmt, va_list args){ + int len; +#ifdef CFG_64BIT_VSPRINTF + unsigned long long num; +#else + unsigned long num; +#endif + int i, base; + char * str; + const char *s; + + int flags; /* flags to number() */ + + int field_width; /* width of output field */ + int precision; /* min. # of digits for integers; max + number of chars for from string */ + int qualifier; /* 'h', 'l', or 'q' for integer fields */ + + for (str=buf ; *fmt ; ++fmt) { + if (*fmt != '%') { + *str++ = *fmt; + continue; + } + + /* process flags */ + flags = 0; + repeat: + ++fmt; /* this also skips first '%' */ + switch (*fmt) { + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } + + /* get field width */ + field_width = -1; + if (is_digit(*fmt)) + field_width = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + field_width = va_arg(args, int); + if (field_width < 0) { + field_width = -field_width; + flags |= LEFT; + } + } + + /* get the precision */ + precision = -1; + if (*fmt == '.') { + ++fmt; + if (is_digit(*fmt)) + precision = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + precision = va_arg(args, int); + } + if (precision < 0) + precision = 0; + } + + /* get the conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'q') { + qualifier = *fmt; + ++fmt; + } + + /* default base */ + base = 10; + + switch (*fmt) { + case 'c': + if (!(flags & LEFT)) + while (--field_width > 0) + *str++ = ' '; + *str++ = (unsigned char) va_arg(args, int); + while (--field_width > 0) + *str++ = ' '; + continue; + + case 's': + s = va_arg(args, char *); + if (!s) + s = ""; + + len = strnlen(s, precision); + + if (!(flags & LEFT)) + while (len < field_width--) + *str++ = ' '; + for (i = 0; i < len; ++i) + *str++ = *s++; + while (len < field_width--) + *str++ = ' '; + continue; + + case 'p': + if (field_width == -1) { + field_width = 2*sizeof(void *); + flags |= ZEROPAD; + } + str = number(str, + (unsigned long) va_arg(args, void *), 16, + field_width, precision, flags); + continue; + + + case 'n': + if (qualifier == 'l') { + long * ip = va_arg(args, long *); + *ip = (str - buf); + } else { + int * ip = va_arg(args, int *); + *ip = (str - buf); + } + continue; + + case '%': + *str++ = '%'; + continue; + + /* integer number formats - set up the flags and "break" */ + case 'o': + base = 8; + break; + + case 'X': + flags |= LARGE; + case 'x': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + case 'u': + break; + + default: + *str++ = '%'; + if (*fmt) + *str++ = *fmt; + else + --fmt; + continue; + } +#ifdef CFG_64BIT_VSPRINTF + if (qualifier == 'q') /* "quad" for 64 bit variables */ + num = va_arg(args, unsigned long long); + else +#endif + if (qualifier == 'l') + num = va_arg(args, unsigned long); + else if (qualifier == 'h') { + num = (unsigned short) va_arg(args, int); + if (flags & SIGN) + num = (short) num; + } else if (flags & SIGN) + num = va_arg(args, int); + else + num = va_arg(args, unsigned int); + str = number(str, num, base, field_width, precision, flags); + } + *str = '\0'; + return str-buf; +} + +int sprintf(char * buf, const char *fmt, ...){ + va_list args; + int i; + + va_start(args, fmt); + i=vsprintf(buf,fmt,args); + va_end(args); + return i; +} diff --git a/u-boot/lib_mips/Makefile b/u-boot/lib_mips/Makefile new file mode 100755 index 0000000..d5980e6 --- /dev/null +++ b/u-boot/lib_mips/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = + +COBJS = board.o time.o mips_linux.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/lib_mips/board.c b/u-boot/lib_mips/board.c new file mode 100755 index 0000000..790fcfe --- /dev/null +++ b/u-boot/lib_mips/board.c @@ -0,0 +1,423 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +//#define BOARD_DEBUG + +#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || defined(CFG_ENV_IS_IN_NVRAM) +#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) +#else +#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN +#endif + +extern ulong uboot_end_data; +extern ulong uboot_end; + +extern int timer_init(void); + +extern void all_led_on(void); +extern void all_led_off(void); + +ulong monitor_flash_len; + +const char version_string[] = U_BOOT_VERSION" (" __DATE__ ")"; + +// Begin and End of memory area for malloc(), and current "brk" +static ulong mem_malloc_start; +static ulong mem_malloc_end; +static ulong mem_malloc_brk; + +// The Malloc area is immediately below the monitor copy in DRAM +static void mem_malloc_init(void){ + ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off; + + mem_malloc_end = dest_addr; + mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + + memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start); +} + +void *sbrk(ptrdiff_t increment){ + ulong old = mem_malloc_brk; + ulong new = old + increment; + + if((new < mem_malloc_start) || (new > mem_malloc_end)){ + return(NULL); + } + mem_malloc_brk = new; + return((void *)old); +} + +static int display_banner(void){ + printf("\n\n*****************************************\n* %s *\n*****************************************\n\n", version_string); + return(0); +} + +static int init_baudrate(void){ + gd->baudrate = CONFIG_BAUDRATE; + return(0); +} + +#ifndef COMPRESSED_UBOOT +static int init_func_ram(void){ + puts("DRAM: "); + + if((gd->ram_size = initdram()) > 0){ + print_size (gd->ram_size, "\n"); + + return(0); + } + + puts("## Error on RAM initialization!\n"); + return(1); +} +#endif + +/* + * Breath some life into the board... + * + * The first part of initialization is running from Flash memory; + * its main purpose is to initialize the RAM so that we + * can relocate the monitor code to RAM. + */ + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ +typedef int(init_fnc_t)(void); + +#ifndef COMPRESSED_UBOOT +init_fnc_t *init_sequence[] = { timer_init, + env_init, /* initialize environment */ + init_baudrate, /* initialze baudrate settings */ + serial_init, /* serial communications setup */ + console_init_f, + display_banner, /* say that we are here */ + checkboard, + init_func_ram, + NULL, }; +#else +init_fnc_t *init_sequence[] = { env_init, /* initialize environment */ + init_baudrate, /* initialze baudrate settings */ + console_init_f, /* initialize console */ + display_banner, /* say that we are here -> print baner */ + NULL, }; +#endif + +/* + * + * BOARD INITIALIZATION + * + */ +void board_init_f(ulong bootflag){ + gd_t gd_data, *id; + bd_t *bd; + init_fnc_t **init_fnc_ptr; + ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE; + ulong *s; + + // Pointer is writable since we allocated a register for it. + gd = &gd_data; + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset((void *)gd, 0, sizeof(gd_t)); + + // loop trough init_sequence + for(init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr){ + if((*init_fnc_ptr)() != 0){ + hang(); + } + } + +#ifdef COMPRESSED_UBOOT + // print BOARD_CUSTOM_STRING + puts(BOARD_CUSTOM_STRING"\n\n"); + + // count ram size and print it + gd->ram_size = bootflag; + puts("DRAM: "); + print_size(gd->ram_size, "\n"); +#endif + + /* + * Now that we have DRAM mapped and working, we can + * relocate the code and continue running from DRAM. + */ + addr = CFG_SDRAM_BASE + gd->ram_size; + + /* + * We can reserve some RAM "on top" here. + */ + + /* + * round down to next 4 kB limit. + */ + addr &= ~(4096 - 1); + +#ifdef BOARD_DEBUG + printf("Top of RAM usable for U-Boot at: %08lX\n", addr); +#endif + + /* + * Reserve memory for U-Boot code, data & bss + * round down to next 16 kB limit + */ + addr -= len; + addr &= ~(16 * 1024 - 1); + +#ifdef BOARD_DEBUG + printf("Reserving %ldk for U-Boot at: %08lX\n", len >> 10, addr); +#endif + + /* + * Reserve memory for malloc() arena. + */ + addr_sp = addr - TOTAL_MALLOC_LEN; + +#ifdef BOARD_DEBUG + printf("Reserving %dk for malloc() at: %08lX\n", TOTAL_MALLOC_LEN >> 10, addr_sp); +#endif + + /* + * (permanently) allocate a Board Info struct + * and a permanent copy of the "global" data + */ + addr_sp -= sizeof(bd_t); + bd = (bd_t *)addr_sp; + gd->bd = bd; + +#ifdef BOARD_DEBUG + printf("Reserving %d Bytes for Board Info at: %08lX\n", sizeof(bd_t), addr_sp); +#endif + + addr_sp -= sizeof(gd_t); + id = (gd_t *)addr_sp; + +#ifdef BOARD_DEBUG + printf("Reserving %d Bytes for Global Data at: %08lX\n", sizeof(gd_t), addr_sp); +#endif + + /* Reserve memory for boot params. + */ + addr_sp -= CFG_BOOTPARAMS_LEN; + bd->bi_boot_params = addr_sp; + +#ifdef BOARD_DEBUG + printf("Reserving %dk for boot params() at: %08lX\n", CFG_BOOTPARAMS_LEN >> 10, addr_sp); +#endif + + /* + * Finally, we set up a new (bigger) stack. + * + * Leave some safety gap for SP, force alignment on 16 byte boundary + * Clear initial stack frame + */ + addr_sp -= 16; + addr_sp &= ~0xF; + s = (ulong *)addr_sp; + *s-- = 0; + *s-- = 0; + addr_sp = (ulong)s; + +#ifdef BOARD_DEBUG + printf("Stack Pointer at: %08lX\n", addr_sp); +#endif + + /* + * Save local variables to board info struct + */ + bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */ + bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ + bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ + + memcpy(id, (void *)gd, sizeof(gd_t)); + + relocate_code(addr_sp, id, addr); + /* NOTREACHED - relocate_code() does not return */ +} + +/************************************************************************ + * + * This is the next part if the initialization sequence: we are now + * running from RAM and have a "normal" C environment, i. e. global + * data can be written, BSS has been cleared, the stack size in not + * that critical any more, etc. + * + ************************************************************************ + */ +void board_init_r(gd_t *id, ulong dest_addr){ + cmd_tbl_t *cmdtp; + ulong size; + extern void malloc_bin_reloc(void); +#ifndef CFG_ENV_IS_NOWHERE + extern char * env_name_spec; +#endif + bd_t *bd; + int i; + char *s; + unsigned char buffer[6]; + + gd = id; + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + +#ifdef BOARD_DEBUG + printf("Now running in RAM - U-Boot at: %08lX\n", dest_addr); +#endif + + gd->reloc_off = dest_addr - CFG_MONITOR_BASE; + + monitor_flash_len = (ulong)&uboot_end_data - dest_addr; + + /* + * We have to relocate the command table manually + */ + for(cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++){ + ulong addr; + + addr = (ulong)(cmdtp->cmd) + gd->reloc_off; + + cmdtp->cmd = (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; + + addr = (ulong)(cmdtp->name) + gd->reloc_off; + cmdtp->name = (char *)addr; + + if(cmdtp->usage){ + addr = (ulong)(cmdtp->usage) + gd->reloc_off; + cmdtp->usage = (char *)addr; + } +#ifdef CFG_LONGHELP + if(cmdtp->help){ + addr = (ulong)(cmdtp->help) + gd->reloc_off; + cmdtp->help = (char *)addr; + } +#endif + } + + /* there are some other pointer constants we must deal with */ +#ifndef CFG_ENV_IS_NOWHERE + env_name_spec += gd->reloc_off; +#endif + + /* configure available FLASH banks */ + size = flash_init(); + + puts("\n\n"); + + bd = gd->bd; + bd->bi_flashstart = CFG_FLASH_BASE; + bd->bi_flashsize = size; + +#if CFG_MONITOR_BASE == CFG_FLASH_BASE + bd->bi_flashoffset = monitor_flash_len; /* reserved area for U-Boot */ +#else + bd->bi_flashoffset = 0; +#endif + + /* initialize malloc() area */ + mem_malloc_init(); + malloc_bin_reloc(); + + /* relocate environment function pointers etc. */ + env_relocate(); + + /* board MAC address */ + memcpy(buffer, (void *)(CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6); + + for(i = 0; i < 6; ++i){ + bd->bi_enetaddr[i] = buffer[i]; + } + + /* IP Address */ + bd->bi_ip_addr = getenv_IPaddr("ipaddr"); + +#if defined(CONFIG_PCI) + /* + * Do pci configuration + */ + pci_init(); +#endif + + /** leave this here (after malloc(), environment and PCI are working) **/ + /* Initialize devices */ + devices_init(); + + jumptable_init(); + + /* Initialize the console (after the relocation and devices init) */ + console_init_r(); + /** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/ + + /* Initialize from environment */ + if((s = getenv("loadaddr")) != NULL){ + load_addr = simple_strtoul(s, NULL, 16); + } + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + if((s = getenv("bootfile")) != NULL){ + copy_filename(BootFile, s, sizeof(BootFile)); + } +#endif /* CFG_CMD_NET */ + + /* blink all available LEDs */ + printf("LED on during eth initialization...\n\n"); + all_led_on(); + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + eth_initialize(gd->bd); +#endif + + all_led_off(); + + /* main_loop() can return to retry autoboot, if so just run it again. */ + for(;;){ + main_loop(); + } + + /* NOTREACHED - no way out of command loop except booting */ +} + +void hang(void){ + puts("## ERROR ##\n"); + for(;;); +} diff --git a/u-boot/lib_mips/mips_linux.c b/u-boot/lib_mips/mips_linux.c new file mode 100755 index 0000000..2ce2d46 --- /dev/null +++ b/u-boot/lib_mips/mips_linux.c @@ -0,0 +1,226 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +//#define DEBUG + +#ifdef CONFIG_AR7240 +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define LINUX_MAX_ENVS 512 // was 256 +#define LINUX_MAX_ARGS 512 // was 256 + +/* from cmd_bootm.c */ +extern image_header_t header; + +/* from cpu.c */ +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +static int linux_argc; +static char ** linux_argv; + +static char ** linux_env; +static char * linux_env_p; +static int linux_env_idx; + +static void linux_params_init(ulong start, char * commandline); +static void linux_env_set(char * env_name, char * env_val); + +#ifdef CONFIG_WASP_SUPPORT +void wasp_set_cca(void){ + /* set cache coherency attribute */ + asm("mfc0 $t0, $16\n" /* CP0_CONFIG == 16 */ + "li $t1, ~7\n" + "and $t0, $t0, $t1\n" + "ori $t0, 3\n" /* CONF_CM_CACHABLE_NONCOHERENT */ + "mtc0 $t0, $16\n" /* CP0_CONFIG == 16 */ + "nop\n": : ); +} +#endif + +void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ + //ulong initrd_start = 0, initrd_end = 0; +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) + int flash_size_mbytes; + void(*theKernel)(int, char **, char **, int); +#else + void(*theKernel)(int, char **, char **, int *); +#endif + image_header_t *hdr = &header; + char *commandline = getenv("bootargs"); + char env_buf[12]; + +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) + theKernel = (void (*)(int, char **, char **, int))ntohl(hdr->ih_ep); +#else + theKernel = (void (*)(int, char **, char **, int *))ntohl(hdr->ih_ep); +#endif + +#ifdef DEBUG + printf("## Bootargs: %s\n", commandline); + printf("## Transferring control to Linux (at address %08lx) ...\n", (ulong)theKernel); +#endif + + linux_params_init(UNCACHED_SDRAM(gd->bd->bi_boot_params), commandline); + + sprintf(env_buf, "%lu", gd->ram_size >> 20); + +#ifdef DEBUG + printf("## Giving linux memsize in MB, %lu\n", gd->ram_size >> 20); +#endif + + linux_env_set("memsize", env_buf); + + //sprintf(env_buf, "0x%08X", (uint)UNCACHED_SDRAM(initrd_start)); + //linux_env_set("initrd_start", env_buf); + + //sprintf(env_buf, "0x%X", (uint)(initrd_end - initrd_start)); + //linux_env_set("initrd_size", env_buf); + + sprintf(env_buf, "0x%08X", (uint)(gd->bd->bi_flashstart)); + linux_env_set("flash_start", env_buf); + + sprintf(env_buf, "0x%X", (uint)(gd->bd->bi_flashsize)); + linux_env_set("flash_size", env_buf); + + // we assume that the kernel is in place + printf("Starting kernel...\n\n"); + +#ifdef CONFIG_WASP_SUPPORT + wasp_set_cca(); +#endif + +#if defined(CONFIG_AR7100) || defined(CONFIG_AR7240) + // Pass the flash size as expected by current Linux kernel for AR7100 + flash_size_mbytes = gd->bd->bi_flashsize/(1024 * 1024); + theKernel(linux_argc, linux_argv, linux_env, flash_size_mbytes); +#else + theKernel(linux_argc, linux_argv, linux_env, 0); +#endif +} + +static void linux_params_init(ulong start, char *line){ + char *next, *quote, *argp; + char memstr[32]; + + linux_argc = 1; + linux_argv = (char **)start; + linux_argv[0] = 0; + argp = (char *)(linux_argv + LINUX_MAX_ARGS); + + next = line; + + if(strstr(line, "mem=")){ + memstr[0] = 0; + } else { + memstr[0] = 1; + } + + while(line && *line && linux_argc < LINUX_MAX_ARGS){ + quote = strchr(line, '"'); + next = strchr(line, ' '); + + while(next != NULL && quote != NULL && quote < next){ + /* we found a left quote before the next blank + * now we have to find the matching right quote + */ + next = strchr(quote + 1, '"'); + if(next != NULL){ + quote = strchr(next + 1, '"'); + next = strchr(next + 1, ' '); + } + } + + if(next == NULL){ + next = line + strlen(line); + } + + linux_argv[linux_argc] = argp; + memcpy(argp, line, next - line); + argp[next - line] = 0; +#if defined(CONFIG_AR7240) +#define REVSTR "REVISIONID" +#define PYTHON "python" +#define VIRIAN "virian" + if(strcmp(argp, REVSTR) == 0){ + if(is_ar7241() || is_ar7242()){ + strcpy(argp, VIRIAN); + } else { + strcpy(argp, PYTHON); + } + } +#endif + + argp += next - line + 1; + linux_argc++; + + if(*next){ + next++; + } + + line = next; + } + +#if defined(CONFIG_AR9100) || defined(CONFIG_AR7240) + /* Add mem size to command line */ + if(memstr[0]){ + sprintf(memstr, "mem=%luM", gd->ram_size >> 20); + memcpy(argp, memstr, strlen(memstr)+1); + linux_argv[linux_argc] = argp; + linux_argc++; + argp += strlen(memstr) + 1; + } +#endif + + linux_env = (char **)(((ulong)argp + 15) & ~15); + linux_env[0] = 0; + linux_env_p = (char *)(linux_env + LINUX_MAX_ENVS); + linux_env_idx = 0; +} + +static void linux_env_set(char *env_name, char *env_val){ + if(linux_env_idx < LINUX_MAX_ENVS - 1){ + linux_env[linux_env_idx] = linux_env_p; + + strcpy(linux_env_p, env_name); + linux_env_p += strlen(env_name); + + strcpy(linux_env_p, "="); + linux_env_p += 1; + + strcpy(linux_env_p, env_val); + linux_env_p += strlen(env_val); + + linux_env_p++; + linux_env[++linux_env_idx] = 0; + } +} diff --git a/u-boot/lib_mips/time.c b/u-boot/lib_mips/time.c new file mode 100755 index 0000000..03ed468 --- /dev/null +++ b/u-boot/lib_mips/time.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +static inline void mips_compare_set(u32 v){ + asm volatile ("mtc0 %0, $11" : : "r" (v)); +} + +static inline void mips_count_set(u32 v){ + asm volatile ("mtc0 %0, $9" : : "r" (v)); +} + +static inline u32 mips_count_get(void){ + u32 count; + + asm volatile ("mfc0 %0, $9" : "=r" (count) :); + return count; +} + +/* + * timer without interrupts + */ +int timer_init(void){ + mips_compare_set(0); + mips_count_set(0); + + return 0; +} + +ulong get_timer(ulong base){ + return mips_count_get() - base; +} + +void udelay(unsigned long usec){ + ulong tmo; + ulong start = get_timer(0); + + tmo = usec * (CFG_HZ / 1000000); + while ((ulong)((mips_count_get() - start)) < tmo) + /*NOP*/; +} diff --git a/u-boot/mips_config.mk b/u-boot/mips_config.mk new file mode 100755 index 0000000..d8aa5fa --- /dev/null +++ b/u-boot/mips_config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ diff --git a/u-boot/mkconfig b/u-boot/mkconfig new file mode 100755 index 0000000..294cb99 --- /dev/null +++ b/u-boot/mkconfig @@ -0,0 +1,67 @@ +#!/bin/sh -e + +# Script to create header files and links to configure +# U-Boot for a specific board. +# +# Parameters: Target Architecture CPU Board [VENDOR] [SOC] +# +# (C) 2002 DENX Software Engineering, Wolfgang Denk +# + +APPEND=no # Default: Create new config file + +while [ $# -gt 0 ] ; do + case "$1" in + --) shift ; break ;; + -a) shift ; APPEND=yes ;; + *) break ;; + esac +done + +[ $# -lt 4 ] && exit 1 +[ $# -gt 6 ] && exit 1 + +cd ./include + +# +# Create link to architecture specific headers +# +rm -f asm +ln -s asm-$2 asm +rm -f asm-$2/arch + +if [ -z "$6" -o "$6" = "NULL" ] ; then + ln -s arch-$3 asm-$2/arch +else + ln -s arch-$6 asm-$2/arch +fi + +if [ "$2" = "arm" ] ; then + rm -f asm-$2/proc + ln -s proc-armv asm-$2/proc +fi + +# +# Create include file for Make +# +echo "ARCH = $2" > config.mk +echo "CPU = $3" >> config.mk +echo "BOARD = $4" >> config.mk + +[ "$5" ] && [ "$5" != "NULL" ] && echo "VENDOR = $5" >> config.mk + +[ "$6" ] && [ "$6" != "NULL" ] && echo "SOC = $6" >> config.mk + +# +# Create board specific header file +# +if [ "$APPEND" = "yes" ] # Append to existing config file +then + echo >> config.h +else + > config.h # Create new config file +fi +echo "/* Automatically generated - do not edit */" >>config.h +echo "#include " >>config.h + +exit 0 diff --git a/u-boot/net/Makefile b/u-boot/net/Makefile new file mode 100755 index 0000000..bc7e846 --- /dev/null +++ b/u-boot/net/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libnet.a + +OBJS = net.o tftp.o rarp.o eth.o bootp.o sntp.o httpd.o + +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/net/bootp.c b/u-boot/net/bootp.c new file mode 100755 index 0000000..f2fce9c --- /dev/null +++ b/u-boot/net/bootp.c @@ -0,0 +1,1087 @@ +/* + * Based on LiMon - BOOTP. + * + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + * Copyright 2000 Roland Borde + * Copyright 2000 Paolo Scaffardi + * Copyright 2000-2004 Wolfgang Denk, wd@denx.de + */ + +//#define DEBUG 1 + +#include +#include +#include +#include "bootp.h" +#include "tftp.h" +#include "nfs.h" + +#define CONFIG_BOOTP_RANDOM_DELAY +#define BOOTP_VENDOR_MAGIC 0x63825363 /* RFC1048 Magic Cookie */ + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +#define TIMEOUT 5 /* Seconds before trying BOOTP again */ + +#ifndef CONFIG_NET_RETRY_COUNT + #define TIMEOUT_COUNT 5 /* # of timeouts before giving up */ +#else + #define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT) +#endif + +#define PORT_BOOTPS 67 /* BOOTP server UDP port */ +#define PORT_BOOTPC 68 /* BOOTP client UDP port */ + +#ifndef CONFIG_DHCP_MIN_EXT_LEN /* minimal length of extension list */ + #define CONFIG_DHCP_MIN_EXT_LEN 64 +#endif + +ulong BootpID; +int BootpTry; + +#ifdef CONFIG_BOOTP_RANDOM_DELAY +ulong seed1, seed2; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +dhcp_state_t dhcp_state = INIT; +unsigned long dhcp_leasetime = 0; +IPaddr_t NetDHCPServerIP = 0; +static void DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len); + +/* For Debug */ +#if 0 +static char *dhcpmsg2str(int type){ + switch(type){ + case 1: + return("DHCPDISCOVER"); + break; + case 2: + return("DHCPOFFER"); + break; + case 3: + return("DHCPREQUEST"); + break; + case 4: + return("DHCPDECLINE"); + break; + case 5: + return("DHCPACK"); + break; + case 6: + return("DHCPNACK"); + break; + case 7: + return("DHCPRELEASE"); + break; + default: + return("UNKNOWN/INVALID MSG TYPE"); + break; + } +} +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) +extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ +extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL */ +#endif + +#endif /* CFG_CMD_DHCP */ + +static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len){ + Bootp_t *bp = (Bootp_t *) pkt; + int retval = 0; + + if(dest != PORT_BOOTPC || src != PORT_BOOTPS){ + retval = -1; + } else if(len < sizeof (Bootp_t) - OPT_SIZE){ + retval = -2; + } else if(bp->bp_op != OP_BOOTREQUEST && + bp->bp_op != OP_BOOTREPLY && + bp->bp_op != DHCP_OFFER && + bp->bp_op != DHCP_ACK && + bp->bp_op != DHCP_NAK){ + retval = -3; + } else if(bp->bp_htype != HWT_ETHER){ + retval = -4; + } else if(bp->bp_hlen != HWL_ETHER){ + retval = -5; + } else if(NetReadLong((ulong*)&bp->bp_id) != BootpID){ + retval = -6; + } + +#ifdef DEBUG + printf("Filtering pkt = %d\n", retval); +#endif + + return(retval); +} + +/* + * Copy parameters of interest from BOOTP_REPLY/DHCP_OFFER packet + */ +static void BootpCopyNetParams(Bootp_t *bp){ + IPaddr_t tmp_ip; + + NetCopyIP(&NetOurIP, &bp->bp_yiaddr); + NetCopyIP(&tmp_ip, &bp->bp_siaddr); + + if(tmp_ip != 0){ + NetCopyIP(&NetServerIP, &bp->bp_siaddr); + } + + memcpy(NetServerEther, ((Ethernet_t *)NetRxPkt)->et_src, 6); + + if(strlen(bp->bp_file) > 0){ + copy_filename(BootFile, bp->bp_file, sizeof(BootFile)); + } + +#ifdef DEBUG + printf("Bootfile: %s\n", BootFile); +#endif + + /* + * Propagate to environment: + * don't delete exising entry when BOOTP / DHCP reply does + * not contain a new value + */ + if(*BootFile){ + setenv("bootfile", BootFile); + } +} + +static int truncate_sz(const char *name, int maxlen, int curlen){ + if(curlen >= maxlen){ + printf("** Warning: %s is too long (%d - max: %d) - truncated\n", name, curlen, maxlen); + curlen = maxlen - 1; + } + + return(curlen); +} + +#if !(CONFIG_COMMANDS & CFG_CMD_DHCP) + +static void BootpVendorFieldProcess(u8 * ext){ + int size = *(ext + 1); + + NetBootFileSize = 0; + + switch(*ext){ + /* Fixed length fields */ + case 1: /* Subnet mask */ + if (NetOurSubnetMask == 0){ + NetCopyIP(&NetOurSubnetMask, (IPaddr_t *)(ext + 2)); + } + break; + + case 2: /* Time offset - Not yet supported */ + break; + + /* Variable length fields */ + case 3: /* Gateways list */ + if(NetOurGatewayIP == 0){ + NetCopyIP(&NetOurGatewayIP, (IPaddr_t *)(ext + 2)); + } + break; + + case 4: /* Time server - Not yet supported */ + break; + + case 5: /* IEN-116 name server - Not yet supported */ + break; + + case 6: + if(NetOurDNSIP == 0){ + NetCopyIP(&NetOurDNSIP, (IPaddr_t *)(ext + 2)); + } +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) + if((NetOurDNS2IP == 0) && (size > 4)){ + NetCopyIP(&NetOurDNS2IP, (IPaddr_t *)(ext + 2 + 4)); + } +#endif + break; + + case 7: /* Log server - Not yet supported */ + break; + + case 8: /* Cookie/Quote server - Not yet supported */ + break; + + case 9: /* LPR server - Not yet supported */ + break; + + case 10: /* Impress server - Not yet supported */ + break; + + case 11: /* RPL server - Not yet supported */ + break; + + case 12: /* Host name */ + if(NetOurHostName[0] == 0){ + size = truncate_sz("Host Name", sizeof(NetOurHostName), size); + memcpy(&NetOurHostName, ext + 2, size); + NetOurHostName[size] = 0; + } + break; + + case 13: /* Boot file size */ + if(size == 2){ + NetBootFileSize = ntohs(*(ushort *)(ext + 2)); + } else if(size == 4){ + NetBootFileSize = ntohl(*(ulong *)(ext + 2)); + } + break; + + case 14: /* Merit dump file - Not yet supported */ + break; + + case 15: /* Domain name - Not yet supported */ + break; + + case 16: /* Swap server - Not yet supported */ + break; + + case 17: /* Root path */ + if(NetOurRootPath[0] == 0){ + size = truncate_sz("Root Path", sizeof(NetOurRootPath), size); + memcpy(&NetOurRootPath, ext + 2, size); + NetOurRootPath[size] = 0; + } + break; + + case 18: /* Extension path - Not yet supported */ + /* + * This can be used to send the information of the + * vendor area in another file that the client can + * access via TFTP. + */ + break; + + /* IP host layer fields */ + case 40: /* NIS Domain name */ + if(NetOurNISDomain[0] == 0){ + size = truncate_sz("NIS Domain Name", sizeof(NetOurNISDomain), size); + memcpy(&NetOurNISDomain, ext + 2, size); + NetOurNISDomain[size] = 0; + } + break; + + /* Application layer fields */ + case 43: /* Vendor specific info - Not yet supported */ + /* + * Binary information to exchange specific + * product information. + */ + break; + /* Reserved (custom) fields (128..254) */ + } + +} + +static void BootpVendorProcess(u8 * ext, int size){ + u8 *end = ext + size; + + while((ext < end) && (*ext != 0xff)){ + if(*ext == 0){ + ext++; + } else { + u8 *opt = ext; + + ext += ext[1] + 2; + if(ext <= end){ + BootpVendorFieldProcess(opt); + } + } + } + +#ifdef DEBUG + puts("[BOOTP] Received fields: \n"); + + if(NetOurSubnetMask){ + puts("NetOurSubnetMask : "); + print_IPaddr(NetOurSubnetMask); + putc('\n'); + } + + if(NetOurGatewayIP){ + puts("NetOurGatewayIP : "); + print_IPaddr(NetOurGatewayIP); + putc('\n'); + } + + if(NetBootFileSize){ + printf("NetBootFileSize : %d\n", NetBootFileSize); + } + + if(NetOurHostName[0]){ + printf("NetOurHostName : %s\n", NetOurHostName); + } + + if(NetOurRootPath[0]){ + printf("NetOurRootPath : %s\n", NetOurRootPath); + } + + if(NetOurNISDomain[0]){ + printf("NetOurNISDomain : %s\n", NetOurNISDomain); + } + + if(NetBootFileSize){ + printf("NetBootFileSize: %d\n", NetBootFileSize); + } +#endif /* DEBUG_BOOTP_EXT */ +} + +/* + * Handle a BOOTP received packet. + */ +static void BootpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len){ + Bootp_t *bp; + char *s; + +#ifdef DEBUG + printf("got BOOTP packet (src=%d, dst=%d, len=%d want_len=%d)\n", src, dest, len, sizeof(Bootp_t)); +#endif + + bp = (Bootp_t *)pkt; + + if(BootpCheckPkt(pkt, dest, src, len)){ /* Filter out pkts we don't want */ + return; + } + + /* + * Got a good BOOTP reply. Copy the data into our variables. + */ + BootpCopyNetParams(bp); /* Store net parameters from reply */ + + /* Retrieve extended information (we must parse the vendor area) */ + if(NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)){ + BootpVendorProcess((uchar *)&bp->bp_vend[4], len); + } + + NetSetTimeout(0, (thand_f *)0); + +#ifdef DEBUG + printf("Got good BOOTP\n"); +#endif + + if((s = getenv("autoload")) != NULL){ + if(*s == 'n'){ + /* + * Just use BOOTP to configure system; + * Do not use TFTP to load the bootfile. + */ + NetState = NETLOOP_SUCCESS; + return; +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + } else if(strcmp(s, "NFS") == 0){ + /* + * Use NFS to load the bootfile. + */ + NfsStart(); + return; +#endif + } + } + + TftpStart(); +} +#endif /* !CFG_CMD_DHCP */ + +/* + * Timeout on BOOTP/DHCP request. + */ +static void BootpTimeout(void){ + if(BootpTry >= TIMEOUT_COUNT){ + puts("\n## Error: retry count exceeded, starting again!\n\n"); + NetStartAgain(); + } else { + NetSetTimeout(TIMEOUT * CFG_HZ, BootpTimeout); + BootpRequest(); + } +} + +/* + * Initialize BOOTP extension fields in the request. + */ +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +static int DhcpExtended(u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t RequestedIP){ + u8 *start = e; + u8 *cnt; + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) + u8 *x; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME) + char *hostname; +#endif + + *e++ = 99; /* RFC1048 Magic Cookie */ + *e++ = 130; + *e++ = 83; + *e++ = 99; + + *e++ = 53; /* DHCP Message Type */ + *e++ = 1; + *e++ = message_type; + + *e++ = 57; /* Maximum DHCP Message Size */ + *e++ = 2; + *e++ = (576 - 312 + OPT_SIZE) >> 8; + *e++ = (576 - 312 + OPT_SIZE) & 0xff; + + if(ServerID){ + int tmp = ntohl(ServerID); + + *e++ = 54; /* ServerID */ + *e++ = 4; + *e++ = tmp >> 24; + *e++ = tmp >> 16; + *e++ = tmp >> 8; + *e++ = tmp & 0xff; + } + + if(RequestedIP){ + int tmp = ntohl(RequestedIP); + + *e++ = 50; /* Requested IP */ + *e++ = 4; + *e++ = tmp >> 24; + *e++ = tmp >> 16; + *e++ = tmp >> 8; + *e++ = tmp & 0xff; + } + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME) + if((hostname = getenv("hostname"))){ + int hostnamelen = strlen (hostname); + + *e++ = 12; /* Hostname */ + *e++ = hostnamelen; + + memcpy(e, hostname, hostnamelen); + e += hostnamelen; + } +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) + if((x = dhcp_vendorex_prep (e))){ + return(x - start); + } +#endif + + *e++ = 55; /* Parameter Request List */ + cnt = e++; /* Pointer to count of requested items */ + *cnt = 0; + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SUBNETMASK) + *e++ = 1; /* Subnet Mask */ + *cnt += 1; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) + *e++ = 2; + *cnt += 1; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_GATEWAY) + *e++ = 3; /* Router Option */ + *cnt += 1; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS) + *e++ = 6; /* DNS Server(s) */ + *cnt += 1; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_HOSTNAME) + *e++ = 12; /* Hostname */ + *cnt += 1; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTFILESIZE) + *e++ = 13; /* Boot File Size */ + *cnt += 1; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTPATH) + *e++ = 17; /* Boot path */ + *cnt += 1; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NISDOMAIN) + *e++ = 40; /* NIS Domain name request */ + *cnt += 1; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) + *e++ = 42; + *cnt += 1; +#endif + *e++ = 255; /* End of the list */ + + /* Pad to minimal length */ +#ifdef CONFIG_DHCP_MIN_EXT_LEN + while((e - start) <= CONFIG_DHCP_MIN_EXT_LEN){ + *e++ = 0; + } +#endif + + return(e - start); +} + +#else /* CFG_CMD_DHCP */ + +/* + * Warning: no field size check - change CONFIG_BOOTP_MASK at your own risk! + */ +static int BootpExtended(u8 * e){ + u8 *start = e; + + *e++ = 99; /* RFC1048 Magic Cookie */ + *e++ = 130; + *e++ = 83; + *e++ = 99; + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + *e++ = 53; /* DHCP Message Type */ + *e++ = 1; + *e++ = DHCP_DISCOVER; + + *e++ = 57; /* Maximum DHCP Message Size */ + *e++ = 2; + *e++ = (576 - 312 + OPT_SIZE) >> 16; + *e++ = (576 - 312 + OPT_SIZE) & 0xff; +#endif /* CFG_CMD_DHCP */ + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SUBNETMASK) + *e++ = 1; /* Subnet mask request */ + *e++ = 4; + e += 4; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_GATEWAY) + *e++ = 3; /* Default gateway request */ + *e++ = 4; + e += 4; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS) + *e++ = 6; /* Domain Name Server */ + *e++ = 4; + e += 4; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_HOSTNAME) + *e++ = 12; /* Host name request */ + *e++ = 32; + e += 32; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTFILESIZE) + *e++ = 13; /* Boot file size */ + *e++ = 2; + e += 2; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTPATH) + *e++ = 17; /* Boot path */ + *e++ = 32; + e += 32; +#endif + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NISDOMAIN) + *e++ = 40; /* NIS Domain name request */ + *e++ = 32; + e += 32; +#endif + + *e++ = 255; /* End of the list */ + + return(e - start); +} +#endif /* CFG_CMD_DHCP */ + +void BootpRequest(void){ + volatile uchar *pkt, *iphdr; + Bootp_t *bp; + int ext_len, pktlen, iplen; + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + dhcp_state = INIT; +#endif + +#ifdef CONFIG_BOOTP_RANDOM_DELAY /* Random BOOTP delay */ + unsigned char bi_enetaddr[6]; + int reg; + char *e,*s; + char tmp[64]; + ulong tst1, tst2, sum, m_mask, m_value = 0; + + if(BootpTry == 0){ + /* get our mac */ + reg = getenv_r("ethaddr", tmp, sizeof(tmp)); + s = (reg > 0) ? tmp : NULL; + + for (reg = 0; reg < 6; ++reg) { + bi_enetaddr[reg] = s ? simple_strtoul(s, &e, 16) : 0; + if(s){ + s = (*e) ? e+1 : e; + } + } + +#ifdef DEBUG + puts("BootpRequest => Our Mac: "); + + for(reg = 0; reg < 6; reg++){ + printf("%x%c", bi_enetaddr[reg], reg == 5 ? '\n' : ':'); + } +#endif /* DEBUG */ + + /* Mac-Manipulation 2 get seed1 */ + tst1=0; + tst2=0; + + for(reg = 2; reg < 6; reg++){ + tst1 = tst1 << 8; + tst1 = tst1 | bi_enetaddr[reg]; + } + + for(reg = 0; reg < 2; reg++){ + tst2 = tst2 | bi_enetaddr[reg]; + tst2 = tst2 << 8; + } + + seed1 = tst1^tst2; + + /* Mirror seed1*/ + m_mask=0x1; + + for(reg = 1;reg <= 32; reg++){ + m_value |= (m_mask & seed1); + seed1 = seed1 >> 1; + m_value = m_value << 1; + } + + seed1 = m_value; + seed2 = 0xB78D0945; + } + + /* Random Number Generator */ + for(reg = 0; reg <= 0; reg++){ + sum = seed1 + seed2; + + if(sum < seed1 || sum < seed2){ + sum++; + } + + seed2 = seed1; + seed1 = sum; + + if(BootpTry<=2){ /* Start with max 1024 * 1ms */ + sum = sum >> (22-BootpTry); + } else { /*After 3rd BOOTP request max 8192 * 1ms */ + sum = sum >> 19; + } + } + + printf("\nRandom delay: %ld ms...\n", sum); + + for(reg = 0; reg < sum; reg++){ + udelay(1000); /* Wait 1ms */ + } +#endif /* CONFIG_BOOTP_RANDOM_DELAY */ + + printf("Sending DHCP discover... %d\n", ++BootpTry); + + pkt = NetTxPacket; + memset((void*)pkt, 0, PKTSIZE); + + pkt += NetSetEther(pkt, NetBcastAddr, PROT_IP); + + /* + * Next line results in incorrect packet size being transmitted, resulting + * in errors in some DHCP servers, reporting missing bytes. Size must be + * set in packet header after extension length has been determined. + * C. Hallinan, DS4.COM, Inc. + */ + /* NetSetIP(pkt, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, sizeof (Bootp_t)); */ + iphdr = pkt; /* We need this later for NetSetIP() */ + pkt += IP_HDR_SIZE; + + bp = (Bootp_t *)pkt; + + bp->bp_op = OP_BOOTREQUEST; + bp->bp_htype = HWT_ETHER; + bp->bp_hlen = HWL_ETHER; + bp->bp_hops = 0; + bp->bp_secs = htons(get_timer(0) / CFG_HZ); + + NetWriteIP(&bp->bp_ciaddr, 0); + NetWriteIP(&bp->bp_yiaddr, 0); + NetWriteIP(&bp->bp_siaddr, 0); + NetWriteIP(&bp->bp_giaddr, 0); + + memcpy(bp->bp_chaddr, NetOurEther, 6); + + copy_filename(bp->bp_file, BootFile, sizeof(bp->bp_file)); + + /* Request additional information from the BOOTP/DHCP server */ +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + ext_len = DhcpExtended((u8 *)bp->bp_vend, DHCP_DISCOVER, 0, 0); +#else + ext_len = BootpExtended((u8 *)bp->bp_vend); +#endif /* CFG_CMD_DHCP */ + + /* + * Bootp ID is the lower 4 bytes of our ethernet address + * plus the current time in HZ. + */ + BootpID = ((ulong)NetOurEther[2] << 24) + | ((ulong)NetOurEther[3] << 16) + | ((ulong)NetOurEther[4] << 8) + | (ulong)NetOurEther[5]; + + BootpID += get_timer(0); + BootpID = htonl(BootpID); + + NetCopyLong(&bp->bp_id, &BootpID); + + /* + * Calculate proper packet lengths taking into account the + * variable size of the options field + */ + pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + ext_len; + iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + ext_len; + + NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen); + NetSetTimeout(SELECT_TIMEOUT * CFG_HZ, BootpTimeout); + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + dhcp_state = SELECTING; + NetSetHandler(DhcpHandler); +#else + NetSetHandler(BootpHandler); +#endif /* CFG_CMD_DHCP */ + + NetSendPacket(NetTxPacket, pktlen); +} + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +static void DhcpOptionsProcess(uchar * popt, Bootp_t *bp){ + uchar *end = popt + BOOTP_HDR_SIZE; + int oplen, size; + + while(popt < end && *popt != 0xff){ + oplen = *(popt + 1); + + switch(*popt){ + case 1: + NetCopyIP(&NetOurSubnetMask, (popt + 2)); + break; + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) + case 2: /* Time offset */ + NetCopyLong(&NetTimeOffset, (ulong *)(popt + 2)); + NetTimeOffset = ntohl(NetTimeOffset); + break; +#endif + + case 3: + NetCopyIP(&NetOurGatewayIP, (popt + 2)); + break; + + case 6: + NetCopyIP(&NetOurDNSIP, (popt + 2)); +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) + if(*(popt + 1) > 4){ + NetCopyIP(&NetOurDNS2IP, (popt + 2 + 4)); + } +#endif + break; + + case 12: + size = truncate_sz("Host Name", sizeof(NetOurHostName), oplen); + memcpy(&NetOurHostName, popt + 2, size); + NetOurHostName[size] = 0; + break; + + case 15: /* Ignore Domain Name Option */ + break; + + case 17: + size = truncate_sz("Root Path", sizeof(NetOurRootPath), oplen); + memcpy(&NetOurRootPath, popt + 2, size); + NetOurRootPath[size] = 0; + break; + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) + case 42: /* NTP server IP */ + NetCopyIP(&NetNtpServerIP, (popt + 2)); + break; +#endif + + case 51: + NetCopyLong(&dhcp_leasetime, (ulong *)(popt + 2)); + break; + + case 53: /* Ignore Message Type Option */ + break; + + case 54: + NetCopyIP(&NetDHCPServerIP, (popt + 2)); + break; + + case 58: /* Ignore Renewal Time Option */ + break; + + case 59: /* Ignore Rebinding Time Option */ + break; + + case 66: /* Ignore TFTP server name */ + break; + + case 67: /* vendor opt bootfile */ + /* + * I can't use dhcp_vendorex_proc here because I need + * to write into the bootp packet - even then I had to + * pass the bootp packet pointer into here as the + * second arg + */ + size = truncate_sz("Opt Boot File", sizeof(bp->bp_file), oplen); + + if(bp->bp_file[0] == '\0' && size > 0){ + /* + * only use vendor boot file if we didn't + * receive a boot file in the main non-vendor + * part of the packet - god only knows why + * some vendors chose not to use this perfectly + * good spot to store the boot file (join on + * Tru64 Unix) it seems mind bogglingly crazy + * to me + */ + printf("** Warning: using vendor optional boot file\n"); + memcpy(bp->bp_file, popt + 2, size); + bp->bp_file[size] = '\0'; + } + break; + + default: +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) + if(dhcp_vendorex_proc(popt)){ + break; + } +#endif + printf("** Warning: unhandled DHCP option in OFFER/ACK: %d\n", *popt); + break; + } + + popt += oplen + 2; /* Process next option */ + } +} + +static int DhcpMessageType(unsigned char *popt){ + if(NetReadLong((ulong*)popt) != htonl(BOOTP_VENDOR_MAGIC)){ + return(-1); + } + + popt += 4; + + while(*popt != 0xff){ + if(*popt == 53){ /* DHCP Message Type */ + return(*(popt + 2)); + } + + popt += *(popt + 1) + 2; /* Scan through all options */ + } + + return(-1); +} + +static void DhcpSendRequestPkt(Bootp_t *bp_offer){ + volatile uchar *pkt, *iphdr; + Bootp_t *bp; + int pktlen, iplen, extlen; + IPaddr_t OfferedIP; + +#ifdef DEBUG + puts("DhcpSendRequestPkt: Sending DHCPREQUEST\n"); +#endif + + pkt = NetTxPacket; + memset((void*)pkt, 0, PKTSIZE); + + pkt += NetSetEther(pkt, NetBcastAddr, PROT_IP); + + iphdr = pkt; /* We'll need this later to set proper pkt size */ + pkt += IP_HDR_SIZE; + + bp = (Bootp_t *)pkt; + + bp->bp_op = OP_BOOTREQUEST; + bp->bp_htype = HWT_ETHER; + bp->bp_hlen = HWL_ETHER; + bp->bp_hops = 0; + bp->bp_secs = htons(get_timer(0) / CFG_HZ); + + NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_ciaddr); /* both in network byte order */ + NetCopyIP(&bp->bp_yiaddr, &bp_offer->bp_yiaddr); + NetCopyIP(&bp->bp_siaddr, &bp_offer->bp_siaddr); + NetCopyIP(&bp->bp_giaddr, &bp_offer->bp_giaddr); + + memcpy(bp->bp_chaddr, NetOurEther, 6); + + /* + * ID is the id of the OFFER packet + */ + NetCopyLong(&bp->bp_id, &bp_offer->bp_id); + + /* + * Copy options from OFFER packet if present + */ + NetCopyIP(&OfferedIP, &bp->bp_yiaddr); + extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP); + + pktlen = BOOTP_SIZE - sizeof(bp->bp_vend) + extlen; + iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen; + + NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen); + +#ifdef DEBUG + printf("Transmitting DHCPREQUEST packet: len = %d\n", pktlen); +#endif + + NetSendPacket(NetTxPacket, pktlen); +} + +/* + * Handle DHCP received packets. + */ +static void DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len){ + Bootp_t *bp = (Bootp_t *)pkt; + char tmp[22]; + +#ifdef DEBUG + printf("DHCPHandler: got packet: (src=%d, dst=%d, len=%d) state: %d\n", src, dest, len, dhcp_state); +#endif + + if(BootpCheckPkt(pkt, dest, src, len)){ /* Filter out pkts we don't want */ + return; + } + +#ifdef DEBUG + printf("DHCPHandler: got DHCP packet: (src=%d, dst=%d, len=%d) state: %d\n", src, dest, len, dhcp_state); +#endif + + switch(dhcp_state){ + case SELECTING: + /* + * Wait an appropriate time for any potential DHCPOFFER packets + * to arrive. Then select one, and generate DHCPREQUEST response. + * If filename is in format we recognize, assume it is a valid + * OFFER from a server we want. + */ +#ifdef DEBUG + printf("DHCP: state=SELECTING bp_file: \"%s\"\n", bp->bp_file); +#endif + +#ifdef CFG_BOOTFILE_PREFIX + if(strncmp(bp->bp_file, CFG_BOOTFILE_PREFIX, strlen(CFG_BOOTFILE_PREFIX)) == 0 ){ +#endif /* CFG_BOOTFILE_PREFIX */ + +#ifdef DEBUG + puts("TRANSITIONING TO REQUESTING STATE\n"); +#endif + + dhcp_state = REQUESTING; + + if(NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)){ + DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp); + } + + BootpCopyNetParams(bp); /* Store net params from reply */ + + NetSetTimeout(TIMEOUT * CFG_HZ, BootpTimeout); + DhcpSendRequestPkt(bp); + +#ifdef CFG_BOOTFILE_PREFIX + } +#endif /* CFG_BOOTFILE_PREFIX */ + + return; + break; + + case REQUESTING: +#ifdef DEBUG + puts("DHCP State: REQUESTING\n"); +#endif + + if(DhcpMessageType((u8 *)bp->bp_vend) == DHCP_ACK ){ + char *s; + + if(NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC)){ + DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp); + } + + BootpCopyNetParams(bp); /* Store net params from reply */ + + dhcp_state = BOUND; + + puts("\nReceived DHCP offer!\n New IP: "); + print_IPaddr(NetOurIP); + putc('\n'); + + // save our new IP to env + if(NetOurIP){ + ip_to_string(NetOurIP, tmp); + setenv("ipaddr", tmp); + } + + puts(" Server IP: "); + print_IPaddr(NetServerIP); + putc('\n'); + + // save new server IP to env + if(NetServerIP){ + ip_to_string(NetServerIP, tmp); + setenv("serverip", tmp); + } + + /* Obey the 'autoload' setting */ + if((s = getenv("autoload")) != NULL){ + if(*s == 'n'){ + /* + * Just use BOOTP to configure system; + * Do not use TFTP to load the bootfile. + */ + NetState = NETLOOP_SUCCESS; + return; +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + } else if(strcmp(s, "NFS") == 0){ + /* + * Use NFS to load the bootfile. + */ + NfsStart(); + return; +#endif + } + } + + TftpStart(); + return; + } + break; + + default: + puts("## Error: DHCP in INVALID STATE\n"); + break; + } + +} + +void DhcpRequest(void){ + BootpRequest(); +} +#endif /* CFG_CMD_DHCP */ + +#endif /* CFG_CMD_NET */ diff --git a/u-boot/net/bootp.h b/u-boot/net/bootp.h new file mode 100755 index 0000000..0b31639 --- /dev/null +++ b/u-boot/net/bootp.h @@ -0,0 +1,95 @@ +/* + * Copied from LiMon - BOOTP. + * + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + * Copyright 2000 Paolo Scaffardi + */ + +#ifndef __BOOTP_H__ +#define __BOOTP_H__ + +#ifndef __NET_H__ +#include +#endif /* __NET_H__ */ + +/**********************************************************************/ + +/* + * BOOTP header. + */ +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) +#define OPT_SIZE 312 /* Minimum DHCP Options size per RFC2131 - results in 576 byte pkt */ +#else +#define OPT_SIZE 64 +#endif + +typedef struct +{ + uchar bp_op; /* Operation */ +# define OP_BOOTREQUEST 1 +# define OP_BOOTREPLY 2 + uchar bp_htype; /* Hardware type */ +# define HWT_ETHER 1 + uchar bp_hlen; /* Hardware address length */ +# define HWL_ETHER 6 + uchar bp_hops; /* Hop count (gateway thing) */ + ulong bp_id; /* Transaction ID */ + ushort bp_secs; /* Seconds since boot */ + ushort bp_spare1; /* Alignment */ + IPaddr_t bp_ciaddr; /* Client IP address */ + IPaddr_t bp_yiaddr; /* Your (client) IP address */ + IPaddr_t bp_siaddr; /* Server IP address */ + IPaddr_t bp_giaddr; /* Gateway IP address */ + uchar bp_chaddr[16]; /* Client hardware address */ + char bp_sname[64]; /* Server host name */ + char bp_file[128]; /* Boot file name */ + char bp_vend[OPT_SIZE]; /* Vendor information */ +} Bootp_t; + +#define BOOTP_HDR_SIZE sizeof (Bootp_t) +#define BOOTP_SIZE (ETHER_HDR_SIZE + IP_HDR_SIZE + BOOTP_HDR_SIZE) + +/**********************************************************************/ +/* + * Global functions and variables. + */ + +/* bootp.c */ +extern ulong BootpID; /* ID of cur BOOTP request */ +extern char BootFile[128]; /* Boot file name */ +extern int BootpTry; +#ifdef CONFIG_BOOTP_RANDOM_DELAY +ulong seed1, seed2; /* seed for random BOOTP delay */ +#endif + + +/* Send a BOOTP request */ +extern void BootpRequest (void); + +/****************** DHCP Support *********************/ +extern void DhcpRequest(void); + +/* DHCP States */ +typedef enum { INIT, + INIT_REBOOT, + REBOOTING, + SELECTING, + REQUESTING, + REBINDING, + BOUND, + RENEWING } dhcp_state_t; + +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 + +#define SELECT_TIMEOUT 3 /* Seconds to wait for offers */ + +/**********************************************************************/ + +#endif /* __BOOTP_H__ */ diff --git a/u-boot/net/eth.c b/u-boot/net/eth.c new file mode 100755 index 0000000..93b14a1 --- /dev/null +++ b/u-boot/net/eth.c @@ -0,0 +1,323 @@ +/* + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +extern int ag7240_enet_initialize(bd_t * bis); + +/* +static struct eth_device *eth_devices, *eth_current; + +struct eth_device *eth_get_dev(void){ + return eth_current; +} +*/ + +static struct eth_device *eth_devices; +struct eth_device *eth_current; + + +struct eth_device *eth_get_dev_by_name(char *devname){ + struct eth_device *dev, *target_dev; + + if(!eth_devices){ + return NULL; + } + + dev = eth_devices; + target_dev = NULL; + + do { + if(strcmp(devname, dev->name) == 0){ + target_dev = dev; + break; + } + dev = dev->next; + } while(dev != eth_devices); + + return(target_dev); +} + +int eth_get_dev_index(void){ + struct eth_device *dev; + int num = 0; + + if (!eth_devices){ + return(-1); + } + + for(dev = eth_devices; dev; dev = dev->next){ + if(dev == eth_current){ + break; + } + ++num; + } + + if(dev){ + return(num); + } + + return(0); +} + +int eth_register(struct eth_device* dev){ + struct eth_device *d; + + if(!eth_devices){ + eth_current = eth_devices = dev; +#ifdef CONFIG_NET_MULTI + /* update current ethernet name */ + char *act = getenv("ethact"); + if(act == NULL || strcmp(act, eth_current->name) != 0){ + setenv("ethact", eth_current->name); + } +#endif + } else { + for (d = eth_devices; d->next != eth_devices; d = d->next); + d->next = dev; + } + + dev->state = ETH_STATE_INIT; + dev->next = eth_devices; + + return(0); +} + +int eth_initialize(bd_t *bis){ + char enetvar[32]; + int i, eth_number = 0; + char *tmp = NULL, *end = NULL; + + eth_devices = NULL; + eth_current = NULL; + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_init(); +#endif + + // ag7240 initialization + ag7240_enet_initialize(bis); + + if(!eth_devices){ + puts("## Error: no ethernet found\n"); + } else { + struct eth_device *dev = eth_devices; + char *ethprime = getenv("ethprime"); + + do { + /* + if (eth_number) { + puts(", "); + } + + printf("%s", dev->name); + */ + + if(ethprime && strcmp(dev->name, ethprime) == 0){ + eth_current = dev; + //puts(" [PRIME]"); + } + + sprintf(enetvar, eth_number ? "eth%daddr" : "ethaddr", eth_number); + tmp = getenv(enetvar); + + for(i = 0; i < 6; i++){ + if(tmp){ + tmp = (*end) ? end + 1 : end; + } + } + + eth_number++; + dev = dev->next; + + } while(dev != eth_devices); + +#ifdef CONFIG_NET_MULTI + /* update current ethernet name */ + if(eth_current){ + char *act = getenv("ethact"); + if(act == NULL || strcmp(act, eth_current->name) != 0){ + setenv("ethact", eth_current->name); + } + } else { + setenv("ethact", NULL); + } +#endif + + //putc('\n'); + } + + return(eth_number); +} + +void eth_set_enetaddr(int num, char *addr){ + struct eth_device *dev; + unsigned char enetaddr[6]; + char *end; + int i; + + //debug("eth_set_enetaddr(num=%d, addr=%s)\n", num, addr); + + if(!eth_devices){ + return; + } + + for(i = 0; i < 6; i++){ + enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0; + if (addr){ + addr = (*end) ? end + 1 : end; + } + } + + dev = eth_devices; + while(num-- > 0){ + dev = dev->next; + + if(dev == eth_devices){ + return; + } + } + + //debug("Setting new HW address on %s\nNew Address is %02X:%02X:%02X:%02X:%02X:%02X\n", dev->name, enetaddr[0], enetaddr[1], enetaddr[2], enetaddr[3], enetaddr[4], enetaddr[5]); + memcpy(dev->enetaddr, enetaddr, 6); +} + +int eth_init(bd_t *bis){ + struct eth_device* old_current; + + if (!eth_current){ + return(0); + } + + old_current = eth_current; + + do { +#if !defined(CFG_ATHRS26_PHY) && !defined(CFG_ATHRHDR_EN) + //debug("Trying %s\n", eth_current->name); +#endif + if(eth_current->init(eth_current, bis)){ + eth_current->state = ETH_STATE_ACTIVE; + return(1); + } + + //debug("FAIL\n"); + + eth_try_another(0); + } while(old_current != eth_current); + + return(0); +} + +void eth_halt(void){ + if(!eth_current){ + return; + } + + eth_current->halt(eth_current); + eth_current->state = ETH_STATE_PASSIVE; +} + +int eth_send(volatile void *packet, int length){ + if(!eth_current){ + return(-1); + } + + return(eth_current->send(eth_current, packet, length)); +} + +int eth_rx(void){ + if(!eth_current){ + return(-1); + } + + return(eth_current->recv(eth_current)); +} + +void eth_try_another(int first_restart){ + static struct eth_device *first_failed = NULL; + + if(!eth_current){ + return; + } + + if(first_restart){ + first_failed = eth_current; + } + + eth_current = eth_current->next; + +#ifdef CONFIG_NET_MULTI + /* update current ethernet name */ + char *act = getenv("ethact"); + if(act == NULL || strcmp(act, eth_current->name) != 0){ + setenv("ethact", eth_current->name); + } +#endif + + if (first_failed == eth_current){ + NetRestartWrap = 1; + } +} + +#ifdef CONFIG_NET_MULTI +void eth_set_current(void){ + + char *act; + struct eth_device* old_current; + + if (!eth_current){ + return; + } + + act = getenv("ethact"); + + if(act != NULL){ + old_current = eth_current; + do { + if(strcmp(eth_current->name, act) == 0){ + return; + } + eth_current = eth_current->next; + } while(old_current != eth_current); + } + + setenv("ethact", eth_current->name); +} +#endif + +char *eth_get_name(void){ + return(eth_current ? eth_current->name : "unknown"); +} +#elif (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI) + +int eth_initialize(bd_t *bis){ +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_init(); +#endif + return 0; +} +#endif diff --git a/u-boot/net/httpd.c b/u-boot/net/httpd.c new file mode 100755 index 0000000..866b9cf --- /dev/null +++ b/u-boot/net/httpd.c @@ -0,0 +1,143 @@ +/* + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + * Copyright 2000, 2001 DENX Software Engineering, Wolfgang Denk, wd@denx.de + */ + +#include +#include +#include +#include +#include "httpd.h" + +#include "../httpd/uipopt.h" +#include "../httpd/uip.h" +#include "../httpd/uip_arp.h" + +extern flash_info_t flash_info[]; + +static int arptimer = 0; + +void HttpdHandler(void){ + int i; + + for(i = 0; i < UIP_CONNS; i++){ + uip_periodic(i); + + if(uip_len > 0){ + uip_arp_out(); + NetSendHttpd(); + } + } + + if(++arptimer == 20){ + uip_arp_timer(); + arptimer = 0; + } +} + +// start http daemon +void HttpdStart(void){ + uip_init(); + httpd_init(); +} + +int do_http_upgrade(const ulong size, const int upgrade_type){ + char buf[96]; // erase 0xXXXXXXXX +0xXXXXXXXX; cp.b 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX (68 signs) + flash_info_t *info = &flash_info[0]; + + if(upgrade_type == WEBFAILSAFE_UPGRADE_TYPE_UBOOT){ + + printf("\n\n****************************\n* U-BOOT UPGRADING *\n* DO NOT POWER OFF DEVICE! *\n****************************\n\n"); + sprintf(buf, + "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", + WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS, + WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES, + WEBFAILSAFE_UPLOAD_RAM_ADDRESS, + WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS, + WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES); + + } else if(upgrade_type == WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE){ + + printf("\n\n****************************\n* FIRMWARE UPGRADING *\n* DO NOT POWER OFF DEVICE! *\n****************************\n\n"); + sprintf(buf, + "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", + WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS, + size, + WEBFAILSAFE_UPLOAD_RAM_ADDRESS, + WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS, + size); + + } else if(upgrade_type == WEBFAILSAFE_UPGRADE_TYPE_ART){ + + // TODO: add option to change ART partition offset, + // for those who want to use OFW on router with replaced/bigger FLASH + printf("\n\n****************************\n* ART UPGRADING *\n* DO NOT POWER OFF DEVICE! *\n****************************\n\n"); + sprintf(buf, + "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", + WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + (info->size - WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES), + WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES, + WEBFAILSAFE_UPLOAD_RAM_ADDRESS, + WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + (info->size - WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES), + WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES); + + } else { + return(-1); + } + + printf("Executing: %s\n\n", buf); + return(run_command(buf, 0)); + + return(-1); +} + +// info about current progress of failsafe mode +int do_http_progress(const int state){ + unsigned char i = 0; + + /* toggle LED's here */ + switch(state){ + case WEBFAILSAFE_PROGRESS_START: + + // blink LED fast 10 times + for(i = 0; i < 10; ++i){ + all_led_on(); + milisecdelay(25); + all_led_off(); + milisecdelay(25); + } + + printf("HTTP server is ready!\n\n"); + break; + + case WEBFAILSAFE_PROGRESS_TIMEOUT: + //printf("Waiting for request...\n"); + break; + + case WEBFAILSAFE_PROGRESS_UPLOAD_READY: + printf("HTTP upload is done! Upgrading...\n"); + break; + + case WEBFAILSAFE_PROGRESS_UPGRADE_READY: + printf("HTTP ugrade is done! Rebooting...\n\n"); + break; + + case WEBFAILSAFE_PROGRESS_UPGRADE_FAILED: + printf("## Error: HTTP ugrade failed!\n\n"); + + // blink LED fast for 4 sec + for(i = 0; i < 80; ++i){ + all_led_on(); + milisecdelay(25); + all_led_off(); + milisecdelay(25); + } + + // wait 1 sec + milisecdelay(1000); + + break; + } + + return(0); +} diff --git a/u-boot/net/httpd.h b/u-boot/net/httpd.h new file mode 100644 index 0000000..c119d31 --- /dev/null +++ b/u-boot/net/httpd.h @@ -0,0 +1,13 @@ +#ifndef _NET_HTTPD_H__ +#define _NET_HTTPD_H__ + +void HttpdStart(void); +void HttpdHandler(void); + +/* board specific implementation */ +extern int do_http_upgrade(const ulong size, const int upgrade_type); +extern int do_http_progress(const int state); +extern void all_led_on(void); +extern void all_led_off(void); + +#endif diff --git a/u-boot/net/net.c b/u-boot/net/net.c new file mode 100755 index 0000000..b27f79d --- /dev/null +++ b/u-boot/net/net.c @@ -0,0 +1,1588 @@ +/* + * Copied from Linux Monitor (LiMon) - Networking. + * + * Copyright 1994 - 2000 Neil Russell. + * (See License) + * Copyright 2000 Roland Borde + * Copyright 2000 Paolo Scaffardi + * Copyright 2000-2002 Wolfgang Denk, wd@denx.de + */ + +/* + * General Desription: + * + * The user interface supports commands for BOOTP, RARP, and TFTP. + * Also, we support ARP internally. Depending on available data, + * these interact as follows: + * + * BOOTP: + * + * Prerequisites: - own ethernet address + * We want: - own IP address + * - TFTP server IP address + * - name of bootfile + * Next step: ARP + * + * RARP: + * + * Prerequisites: - own ethernet address + * We want: - own IP address + * - TFTP server IP address + * Next step: ARP + * + * ARP: + * + * Prerequisites: - own ethernet address + * - own IP address + * - TFTP server IP address + * We want: - TFTP server ethernet address + * Next step: TFTP + * + * DHCP: + * + * Prerequisites: - own ethernet address + * We want: - IP, Netmask, ServerIP, Gateway IP + * - bootfilename, lease time + * Next step: - TFTP + * + * TFTP: + * + * Prerequisites: - own ethernet address + * - own IP address + * - TFTP server IP address + * - TFTP server ethernet address + * - name of bootfile (if unknown, we use a default name + * derived from our own IP address) + * We want: - load the boot file + * Next step: none + * + * NFS: + * + * Prerequisites: - own ethernet address + * - own IP address + * - name of bootfile (if unknown, we use a default name + * derived from our own IP address) + * We want: - load the boot file + * Next step: none + * + * SNTP: + * + * Prerequisites: - own ethernet address + * - own IP address + * We want: - network time + * Next step: none + */ + +#include +#include +#include +#include "bootp.h" +#include "tftp.h" +#include "rarp.h" +#include "nfs.h" +#include "httpd.h" + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +#include "sntp.h" +#endif + +#include "../httpd/uipopt.h" +#include "../httpd/uip.h" +#include "../httpd/uip_arp.h" + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +DECLARE_GLOBAL_DATA_PTR; + +#define ARP_TIMEOUT 5 /* Seconds before trying ARP again */ + +#ifndef CONFIG_NET_RETRY_COUNT + #define ARP_TIMEOUT_COUNT 5 /* # of timeouts before giving up */ +#else + #define ARP_TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT) +#endif + +unsigned char *webfailsafe_data_pointer = NULL; +int webfailsafe_is_running = 0; +int webfailsafe_ready_for_upgrade = 0; +int webfailsafe_upgrade_type = WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE; + +void NetReceiveHttpd(volatile uchar * inpkt, int len); + +extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/** BOOTP EXTENTIONS **/ +IPaddr_t NetOurSubnetMask = 0; /* Our subnet mask (0=unknown) */ +IPaddr_t NetOurGatewayIP = 0; /* Our gateways IP address */ +IPaddr_t NetOurDNSIP = 0; /* Our DNS IP address */ + +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +IPaddr_t NetOurDNS2IP = 0; /* Our 2nd DNS IP address */ +#endif + +char NetOurNISDomain[32] = {0,}; /* Our NIS domain */ +char NetOurHostName[32] = {0,}; /* Our hostname */ +char NetOurRootPath[64] = {0,}; /* Our bootpath */ +ushort NetBootFileSize = 0; /* Our bootfile size in blocks */ +/** END OF BOOTP EXTENTIONS **/ + +ulong NetBootFileXferSize; /* The actual transferred size of the bootfile (in bytes) */ +uchar NetOurEther[6]; /* Our ethernet address */ +uchar NetServerEther[6] = {0, 0, 0, 0, 0, 0}; /* Boot server enet address */ +IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */ +IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */ +volatile uchar *NetRxPkt; /* Current receive packet */ +int NetRxPktLen; /* Current rx packet length */ +unsigned NetIPID; /* IP packet ID */ + +uchar NetBcastAddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; /* Ethernet bcast address */ +uchar NetEtherNullAddr[6] = {0, 0, 0, 0, 0, 0}; + +int NetState; /* Network loop state */ + +#ifdef CONFIG_NET_MULTI +int NetRestartWrap = 0; /* Tried all network devices */ +static int NetRestarted = 0; /* Network loop restarted */ +static int NetDevExists = 0; /* At least one device configured */ +#endif + +/* XXX in both little & big endian machines 0xFFFF == ntohs(-1) */ +ushort NetOurVLAN = 0xFFFF; /* default is without VLAN */ +ushort NetOurNativeVLAN = 0xFFFF; /* ditto */ + +char BootFile[128]; /* Boot File name */ + +#if (CONFIG_COMMANDS & CFG_CMD_PING) +IPaddr_t NetPingIP; /* the ip address to ping */ +static void PingStart(void); +#endif /* CFG_CMD_PING */ + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +IPaddr_t NetNtpServerIP; /* NTP server IP address */ +int NetTimeOffset = 0; /* offset time from UTC */ +#endif /* CFG_CMD_SNTP */ + +#ifdef CONFIG_NETCONSOLE +void NcStart(void); +int nc_input_packet(uchar *pkt, unsigned dest, unsigned src, unsigned len); +#endif /* CONFIG_NETCONSOLE */ + +volatile uchar PktBuf[(PKTBUFSRX + 1) * PKTSIZE_ALIGN + PKTALIGN]; +volatile uchar *NetRxPackets[PKTBUFSRX]; /* Receive packets */ + +static rxhand_f *packetHandler; /* Current RX packet handler */ +static thand_f *timeHandler; /* Current timeout handler */ +static ulong timeStart; /* Time base value */ +static ulong timeDelta; /* Current timeout value */ +volatile uchar *NetTxPacket = 0; /* THE transmit packet */ + +static int net_check_prereq(proto_t protocol); + +/**********************************************************************/ + +IPaddr_t NetArpWaitPacketIP; +IPaddr_t NetArpWaitReplyIP; + +uchar *NetArpWaitPacketMAC; /* MAC address of waiting packet's destination */ +uchar *NetArpWaitTxPacket; /* THE transmit packet */ +uchar NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN]; +ulong NetArpWaitTimerStart; + +int NetArpWaitTry; +int NetArpWaitTxPacketSize; + +void ArpRequest(void){ + int i; + volatile uchar *pkt; + ARP_t *arp; + +#ifdef ET_DEBUG + printf("ARP broadcast %d\n", NetArpWaitTry); +#endif + + pkt = NetTxPacket; + pkt += NetSetEther(pkt, NetBcastAddr, PROT_ARP); + + arp = (ARP_t *)pkt; + + arp->ar_hrd = htons(ARP_ETHER); + arp->ar_pro = htons(PROT_IP); + arp->ar_hln = 6; + arp->ar_pln = 4; + arp->ar_op = htons(ARPOP_REQUEST); + + memcpy(&arp->ar_data[0], NetOurEther, 6); /* source ET addr */ + NetWriteIP((uchar *)&arp->ar_data[6], NetOurIP); /* source IP addr */ + + for(i = 10; i < 16; ++i){ + arp->ar_data[i] = 0; /* dest ET addr = 0 */ + } + + if((NetArpWaitPacketIP & NetOurSubnetMask) != (NetOurIP & NetOurSubnetMask)){ + if(NetOurGatewayIP == 0){ + puts("## Warning: gatewayip needed but not set\n"); + NetArpWaitReplyIP = NetArpWaitPacketIP; + } else { + NetArpWaitReplyIP = NetOurGatewayIP; + } + } else { + NetArpWaitReplyIP = NetArpWaitPacketIP; + } + + NetWriteIP((uchar *)&arp->ar_data[16], NetArpWaitReplyIP); + (void)eth_send(NetTxPacket, (pkt - NetTxPacket) + ARP_HDR_SIZE); +} + +void ArpTimeoutCheck(void){ + ulong t; + + if(!NetArpWaitPacketIP){ + return; + } + + t = get_timer(0); + + /* check for arp timeout */ + if((t - NetArpWaitTimerStart) > ARP_TIMEOUT * CFG_HZ){ + NetArpWaitTry++; + + if(NetArpWaitTry >= ARP_TIMEOUT_COUNT){ + puts("## Error: ARP retry count exceeded, starting again\n"); + NetArpWaitTry = 0; + NetStartAgain(); + } else { + NetArpWaitTimerStart = t; + ArpRequest(); + } + } +} + +/**********************************************************************/ +/* + * Main network processing loop. + */ +int NetLoop(proto_t protocol){ + bd_t *bd = gd->bd; + +#ifdef CONFIG_NET_MULTI + NetRestarted = 0; + NetDevExists = 0; +#endif + + /* XXX problem with bss workaround */ + NetArpWaitPacketMAC = NULL; + NetArpWaitTxPacket = NULL; + NetArpWaitPacketIP = 0; + NetArpWaitReplyIP = 0; + NetArpWaitTxPacket = NULL; + NetTxPacket = NULL; + + if(!NetTxPacket){ + int i; + /* + * Setup packet buffers, aligned correctly. + */ + NetTxPacket = &PktBuf[0] + (PKTALIGN - 1); + NetTxPacket -= (ulong)NetTxPacket % PKTALIGN; + + for(i = 0; i < PKTBUFSRX; i++){ + NetRxPackets[i] = NetTxPacket + (i + 1) * PKTSIZE_ALIGN; + } + } + + if(!NetArpWaitTxPacket){ + NetArpWaitTxPacket = &NetArpWaitPacketBuf[0] + (PKTALIGN - 1); + NetArpWaitTxPacket -= (ulong)NetArpWaitTxPacket % PKTALIGN; + NetArpWaitTxPacketSize = 0; + } + + if(eth_is_on_demand_init() || protocol != NETCONS){ + eth_halt(); +#ifdef CONFIG_NET_MULTI + eth_set_current(); +#endif + if(!eth_init(bd)){ + eth_halt(); + return(-1); + } + } else { + eth_init_state_only(bd); + } + + /* restart label */ + restart: + +#ifdef CONFIG_NET_MULTI + memcpy(NetOurEther, eth_get_dev()->enetaddr, 6); +#else + memcpy(NetOurEther, bd->bi_enetaddr, 6); +#endif + + NetState = NETLOOP_CONTINUE; + + /* + * Start the ball rolling with the given start function. From + * here on, this code is a state machine driven by received + * packets and timer events. + */ + + switch(protocol){ +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + case NFS: +#endif +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case PING: +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) + case SNTP: +#endif + case NETCONS: + case TFTP: + NetCopyIP(&NetOurIP, &bd->bi_ip_addr); + + NetOurGatewayIP = getenv_IPaddr("gatewayip"); + NetOurSubnetMask = getenv_IPaddr("netmask"); + NetOurVLAN = getenv_VLAN("vlan"); + NetOurNativeVLAN = getenv_VLAN("nvlan"); + + switch(protocol){ +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + case NFS: +#endif + case NETCONS: + case TFTP: + NetServerIP = getenv_IPaddr("serverip"); + break; +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case PING: + /* nothing */ + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) + case SNTP: + /* nothing */ + break; +#endif + default: + break; + } + + break; + + case BOOTP: + case RARP: + /* + * initialize our IP addr to 0 in order to accept ANY + * IP addr assigned to us by the BOOTP / RARP server + */ + NetOurIP = 0; + NetServerIP = getenv_IPaddr("serverip"); + NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */ + NetOurNativeVLAN = getenv_VLAN("nvlan"); + + case CDP: + NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */ + NetOurNativeVLAN = getenv_VLAN("nvlan"); + break; + + default: + break; + } + + switch(net_check_prereq(protocol)){ + case 1: + /* network not configured */ + eth_halt(); + return(-1); + +#ifdef CONFIG_NET_MULTI + case 2: + /* network device not configured */ + break; +#endif /* CONFIG_NET_MULTI */ + + case 0: +#ifdef CONFIG_NET_MULTI + NetDevExists = 1; +#endif + switch(protocol){ + case TFTP: + /* always use ARP to get server ethernet address */ + TftpStart(); + break; + +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) + case DHCP: + /* Start with a clean slate... */ + BootpTry = 0; + NetOurIP = 0; + NetServerIP = getenv_IPaddr("serverip"); + DhcpRequest(); /* Basically same as BOOTP */ + break; + +#endif /* CFG_CMD_DHCP */ + +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case PING: + PingStart(); + break; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + case NFS: + NfsStart(); + break; +#endif + +#ifdef CONFIG_NETCONSOLE + case NETCONS: + NcStart(); + break; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) + case SNTP: + SntpStart(); + break; +#endif + + default: + break; + } + + NetBootFileXferSize = 0; + break; + } + + /* + * Main packet reception loop. Loop receiving packets until + * someone sets `NetState' to a state that terminates. + */ + for(;;){ + /* + * Check the ethernet for a new packet. The ethernet + * receive routine will process it. + */ + eth_rx(); + + /* + * Abort if ctrl-c was pressed. + */ + if(ctrlc()){ + eth_halt(); + + /* Invalidate the last protocol */ + eth_set_last_protocol(BOOTP); + + puts("\nAbort\n"); + return(-1); + } + + ArpTimeoutCheck(); + + /* + * Check for a timeout, and run the timeout handler + * if we have one. + */ + if(timeHandler && ((get_timer(0) - timeStart) > timeDelta)){ + thand_f *x; + x = timeHandler; + timeHandler = (thand_f *)0; + (*x)(); + } + + switch(NetState){ + + case NETLOOP_RESTART: +#ifdef CONFIG_NET_MULTI + NetRestarted = 1; +#endif + goto restart; + + case NETLOOP_SUCCESS: + if(NetBootFileXferSize > 0){ + char buf[10]; + printf("\nBytes transferred: %ld (0x%lx)\n", NetBootFileXferSize, NetBootFileXferSize); + + sprintf(buf, "%lx", NetBootFileXferSize); + setenv("filesize", buf); + + sprintf(buf, "%lX", (unsigned long)load_addr); + setenv("fileaddr", buf); + } + + if(protocol != NETCONS){ + eth_halt(); + } else { + eth_halt_state_only(); + } + + eth_set_last_protocol(protocol); + + return(NetBootFileXferSize); + + case NETLOOP_FAIL: + /* Invalidate the last protocol */ + eth_set_last_protocol(BOOTP); + return(-1); + } + } +} + +/**********************************************************************/ + +static void startAgainTimeout(void){ + NetState = NETLOOP_RESTART; +} + +static void startAgainHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len){ + /* Totally ignore the packet */ +} + +void NetStartAgain(void){ + char *nretry; + int noretry = 0, once = 0; + + if((nretry = getenv("netretry")) != NULL){ + noretry = (strcmp(nretry, "no") == 0); + once = (strcmp(nretry, "once") == 0); + } + + if(noretry){ + eth_halt(); + NetState = NETLOOP_FAIL; + return; + } + +#ifndef CONFIG_NET_MULTI + NetSetTimeout(10 * CFG_HZ, startAgainTimeout); + NetSetHandler(startAgainHandler); +#else /* !CONFIG_NET_MULTI*/ + eth_halt(); + eth_try_another(!NetRestarted); + eth_init(gd->bd); + + if(NetRestartWrap){ + NetRestartWrap = 0; + if(NetDevExists && !once){ + NetSetTimeout(10 * CFG_HZ, startAgainTimeout); + NetSetHandler(startAgainHandler); + } else { + NetState = NETLOOP_FAIL; + } + } else { + NetState = NETLOOP_RESTART; + } +#endif /* CONFIG_NET_MULTI */ +} + +/**********************************************************************/ +/* + * Miscelaneous bits. + */ + +void NetSetHandler(rxhand_f * f){ + packetHandler = f; +} + +void NetSetTimeout(ulong iv, thand_f * f){ + if(iv == 0){ + timeHandler = (thand_f *)0; + } else { + timeHandler = f; + timeStart = get_timer(0); + timeDelta = iv; + } +} + +void NetSendPacket(volatile uchar * pkt, int len){ + (void)eth_send(pkt, len); +} + +int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len){ + uchar *pkt; + + /* convert to new style broadcast */ + if(dest == 0){ + dest = 0xFFFFFFFF; + } + + /* if broadcast, make the ether address a broadcast and don't do ARP */ + if(dest == 0xFFFFFFFF){ + ether = NetBcastAddr; + } + + /* if MAC address was not discovered yet, save the packet and do an ARP request */ + if(memcmp(ether, NetEtherNullAddr, 6) == 0){ + +#ifdef ET_DEBUG + printf("Sending ARP for %08lx\n", dest); +#endif + NetArpWaitPacketIP = dest; + NetArpWaitPacketMAC = ether; + + pkt = NetArpWaitTxPacket; + pkt += NetSetEther(pkt, NetArpWaitPacketMAC, PROT_IP); + + NetSetIP(pkt, dest, dport, sport, len); + memcpy(pkt + IP_HDR_SIZE, (uchar *)NetTxPacket + (pkt - (uchar *)NetArpWaitTxPacket) + IP_HDR_SIZE, len); + + /* size of the waiting packet */ + NetArpWaitTxPacketSize = (pkt - NetArpWaitTxPacket) + IP_HDR_SIZE + len; + + /* and do the ARP request */ + NetArpWaitTry = 1; + NetArpWaitTimerStart = get_timer(0); + ArpRequest(); + + return(1); /* waiting */ + } + +#ifdef ET_DEBUG + printf("Sending UDP to %08lx/%02x:%02x:%02x:%02x:%02x:%02x\n", dest, ether[0], ether[1], ether[2], ether[3], ether[4], ether[5]); +#endif + + pkt = (uchar *)NetTxPacket; + pkt += NetSetEther(pkt, ether, PROT_IP); + NetSetIP(pkt, dest, dport, sport, len); + (void)eth_send(NetTxPacket, (pkt - NetTxPacket) + IP_HDR_SIZE + len); + + return(0); /* transmitted */ +} + +#if (CONFIG_COMMANDS & CFG_CMD_PING) +static ushort PingSeqNo; + +int PingSend(void){ + static uchar mac[6]; + volatile IP_t *ip; + volatile ushort *s; + uchar *pkt; + + /* XXX always send arp request */ + + memcpy(mac, NetEtherNullAddr, 6); + +#ifdef ET_DEBUG + printf("Sending ARP for %08lx\n", NetPingIP); +#endif + + NetArpWaitPacketIP = NetPingIP; + NetArpWaitPacketMAC = mac; + + pkt = NetArpWaitTxPacket; + pkt += NetSetEther(pkt, mac, PROT_IP); + + ip = (volatile IP_t *)pkt; + + /* + * Construct an IP and ICMP header. (need to set no fragment bit - XXX) + */ + ip->ip_hl_v = 0x45; /* IP_HDR_SIZE / 4 (not including UDP) */ + ip->ip_tos = 0; + ip->ip_len = htons(IP_HDR_SIZE_NO_UDP + 8); + ip->ip_id = htons(NetIPID++); + ip->ip_off = htons(0x4000); /* No fragmentation */ + ip->ip_ttl = 255; + ip->ip_p = 0x01; /* ICMP */ + ip->ip_sum = 0; + + NetCopyIP((void*)&ip->ip_src, &NetOurIP); /* already in network byte order */ + NetCopyIP((void*)&ip->ip_dst, &NetPingIP); /* - "" - */ + + ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2); + + s = &ip->udp_src; /* XXX ICMP starts here */ + + s[0] = htons(0x0800); /* echo-request, code */ + s[1] = 0; /* checksum */ + s[2] = 0; /* identifier */ + s[3] = htons(PingSeqNo++); /* sequence number */ + s[1] = ~NetCksum((uchar *)s, 8/2); + + /* size of the waiting packet */ + NetArpWaitTxPacketSize = (pkt - NetArpWaitTxPacket) + IP_HDR_SIZE_NO_UDP + 8; + + /* and do the ARP request */ + NetArpWaitTry = 1; + NetArpWaitTimerStart = get_timer(0); + ArpRequest(); + + return(1); /* waiting */ +} + +static void PingTimeout(void){ + eth_halt(); + NetState = NETLOOP_FAIL; /* we did not get the reply */ +} + +static void PingHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len){ + IPaddr_t tmp; + volatile IP_t *ip = (volatile IP_t *)pkt; + + tmp = NetReadIP((void *)&ip->ip_src); + + if(tmp != NetPingIP){ + return; + } + + NetState = NETLOOP_SUCCESS; +} + +static void PingStart(void){ +#if defined(CONFIG_NET_MULTI) + printf("Using %s device\n", eth_get_name()); +#endif /* CONFIG_NET_MULTI */ + + NetSetTimeout(10 * CFG_HZ, PingTimeout); + NetSetHandler(PingHandler); + + PingSend(); +} +#endif /* CFG_CMD_PING */ + +void NetReceive(volatile uchar * inpkt, int len){ + Ethernet_t *et; + IP_t *ip; + ARP_t *arp; + IPaddr_t tmp; + int x; + uchar *pkt; + ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid; + +#ifdef ET_DEBUG + printf("Packet received\n"); +#endif + + if(webfailsafe_is_running){ + NetReceiveHttpd(inpkt, len); + return; + } + + NetRxPkt = inpkt; + NetRxPktLen = len; + et = (Ethernet_t *)inpkt; + + /* too small packet? */ + if(len < ETHER_HDR_SIZE){ + return; + } + + myvlanid = ntohs(NetOurVLAN); + + if(myvlanid == (ushort)-1){ + myvlanid = VLAN_NONE; + } + + mynvlanid = ntohs(NetOurNativeVLAN); + + if(mynvlanid == (ushort)-1){ + mynvlanid = VLAN_NONE; + } + + x = ntohs(et->et_protlen); + +#ifdef ET_DEBUG + printf("Packet received\n"); +#endif + + if(x < 1514){ + /* + * Got a 802 packet. Check the other protocol field. + */ + x = ntohs(et->et_prot); + + ip = (IP_t *)(inpkt + E802_HDR_SIZE); + len -= E802_HDR_SIZE; + + } else if(x != PROT_VLAN){ /* normal packet */ + ip = (IP_t *)(inpkt + ETHER_HDR_SIZE); + len -= ETHER_HDR_SIZE; + + } else { /* VLAN packet */ + VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)et; + +#ifdef ET_DEBUG + printf("VLAN packet received\n"); +#endif + /* too small packet? */ + if(len < VLAN_ETHER_HDR_SIZE){ + return; + } + + /* if no VLAN active */ + if((ntohs(NetOurVLAN) & VLAN_IDMASK) == VLAN_NONE){ + return; + } + + cti = ntohs(vet->vet_tag); + vlanid = cti & VLAN_IDMASK; + x = ntohs(vet->vet_type); + + ip = (IP_t *)(inpkt + VLAN_ETHER_HDR_SIZE); + len -= VLAN_ETHER_HDR_SIZE; + } + +#ifdef ET_DEBUG + printf("Receive from protocol 0x%x\n", x); +#endif + + if((myvlanid & VLAN_IDMASK) != VLAN_NONE){ + if(vlanid == VLAN_NONE){ + vlanid = (mynvlanid & VLAN_IDMASK); + } + /* not matched? */ + if(vlanid != (myvlanid & VLAN_IDMASK)){ + return; + } + } + + switch(x){ + + case PROT_ARP: + /* + * We have to deal with two types of ARP packets: + * - REQUEST packets will be answered by sending our + * IP address - if we know it. + * - REPLY packates are expected only after we asked + * for the TFTP server's or the gateway's ethernet + * address; so if we receive such a packet, we set + * the server ethernet address + */ +#ifdef ET_DEBUG + puts("Got ARP\n"); +#endif + arp = (ARP_t *)ip; + + if(len < ARP_HDR_SIZE){ + printf("## Error: bad length %d < %d\n", len, ARP_HDR_SIZE); + return; + } + + if(ntohs(arp->ar_hrd) != ARP_ETHER){ + return; + } + + if(ntohs(arp->ar_pro) != PROT_IP){ + return; + } + + if(arp->ar_hln != 6){ + return; + } + + if(arp->ar_pln != 4){ + return; + } + + if(NetOurIP == 0){ + return; + } + + if(NetReadIP(&arp->ar_data[16]) != NetOurIP){ + return; + } + + switch(ntohs(arp->ar_op)){ + case ARPOP_REQUEST: /* reply with our IP address */ +#ifdef ET_DEBUG + puts("Got ARP REQUEST, return our IP\n"); +#endif + pkt = (uchar *)et; + pkt += NetSetEther(pkt, et->et_src, PROT_ARP); + arp->ar_op = htons(ARPOP_REPLY); + memcpy(&arp->ar_data[10], &arp->ar_data[0], 6); + NetCopyIP(&arp->ar_data[16], &arp->ar_data[6]); + memcpy(&arp->ar_data[0], NetOurEther, 6); + NetCopyIP(&arp->ar_data[6], &NetOurIP); + (void)eth_send((uchar *)et, (pkt - (uchar *)et) + ARP_HDR_SIZE); + + return; + + case ARPOP_REPLY: /* arp reply */ + /* are we waiting for a reply */ + if(!NetArpWaitPacketIP || !NetArpWaitPacketMAC){ + break; + } +#ifdef ET_DEBUG + printf("Got ARP REPLY, set server/gtwy eth addr (%02x:%02x:%02x:%02x:%02x:%02x)\n", arp->ar_data[0], arp->ar_data[1], arp->ar_data[2], arp->ar_data[3], arp->ar_data[4], arp->ar_data[5]); +#endif + + tmp = NetReadIP(&arp->ar_data[6]); + + /* matched waiting packet's address */ + if(tmp == NetArpWaitReplyIP){ +#ifdef ET_DEBUG + puts("Got it\n"); +#endif + /* save address for later use */ + memcpy(NetArpWaitPacketMAC, &arp->ar_data[0], 6); + +#ifdef CONFIG_NETCONSOLE + (*packetHandler)(0,0,0,0); +#endif + /* modify header, and transmit it */ + memcpy(((Ethernet_t *)NetArpWaitTxPacket)->et_dest, NetArpWaitPacketMAC, 6); + (void)eth_send(NetArpWaitTxPacket, NetArpWaitTxPacketSize); + + /* no arp request pending now */ + NetArpWaitPacketIP = 0; + NetArpWaitTxPacketSize = 0; + NetArpWaitPacketMAC = NULL; + + } + + return; + default: +#ifdef ET_DEBUG + printf("## Error: unexpected ARP opcode 0x%x\n", ntohs(arp->ar_op)); +#endif + return; + } + break; + + case PROT_RARP: +#ifdef ET_DEBUG + puts("Got RARP\n"); +#endif + arp = (ARP_t *)ip; + if(len < ARP_HDR_SIZE){ + printf("## Error: bad length %d < %d\n", len, ARP_HDR_SIZE); + return; + } + + if((ntohs(arp->ar_op) != RARPOP_REPLY) || (ntohs(arp->ar_hrd) != ARP_ETHER) || (ntohs(arp->ar_pro) != PROT_IP) || (arp->ar_hln != 6) || (arp->ar_pln != 4)){ + puts("## Error: invalid RARP header\n"); + } else { + NetCopyIP(&NetOurIP, &arp->ar_data[16]); + if(NetServerIP == 0){ + NetCopyIP(&NetServerIP, &arp->ar_data[6]); + } + memcpy(NetServerEther, &arp->ar_data[0], 6); + (*packetHandler)(0, 0, 0, 0); + } + + break; + + case PROT_IP: +#ifdef ET_DEBUG + puts("Got IP\n"); +#endif + if(len < IP_HDR_SIZE){ + debug("## Error: len bad %d < %d\n", len, IP_HDR_SIZE); + return; + } + + if(len < ntohs(ip->ip_len)){ + printf("## Error: len bad %d < %d\n", len, ntohs(ip->ip_len)); + return; + } + + len = ntohs(ip->ip_len); +#ifdef ET_DEBUG + printf("Len=%d, v=%02x\n", len, ip->ip_hl_v & 0xff); +#endif + if((ip->ip_hl_v & 0xf0) != 0x40){ + return; + } + + if(ip->ip_off & htons(0x1fff)){ /* Can't deal w/ fragments */ + return; + } + + if(!NetCksumOk((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2)){ +#ifdef ET_DEBUG + puts("\n## Error: checksum bad\n"); +#endif + return; + } + + tmp = NetReadIP(&ip->ip_dst); + + if(NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF){ + return; + } + /* + * watch for ICMP host redirects + * + * There is no real handler code (yet). We just watch + * for ICMP host redirect messages. In case anybody + * sees these messages: please contact me + * (wd@denx.de), or - even better - send me the + * necessary fixes :-) + * + * Note: in all cases where I have seen this so far + * it was a problem with the router configuration, + * for instance when a router was configured in the + * BOOTP reply, but the TFTP server was on the same + * subnet. So this is probably a warning that your + * configuration might be wrong. But I'm not really + * sure if there aren't any other situations. + */ + if(ip->ip_p == IPPROTO_ICMP){ + ICMP_t *icmph = (ICMP_t *) & (ip->udp_src); + + switch(icmph->type){ + case ICMP_REDIRECT: + if(icmph->code != ICMP_REDIR_HOST){ + return; + } + + puts(" ICMP Host Redirect to "); + print_IPaddr(icmph->un.gateway); + putc(' '); + + return; +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case ICMP_ECHO_REPLY: + /* + * IP header OK. Pass the packet to the current handler. + */ + /* XXX point to ip packet */ + (*packetHandler)((uchar *)ip, 0, 0, 0); + return; +#endif + default: + return; + } + } else if(ip->ip_p != IPPROTO_UDP){ /* Only UDP packets */ + return; + } + +#ifdef CONFIG_UDP_CHECKSUM + if(ip->udp_xsum != 0){ + ulong xsum; + ushort *sumptr; + ushort sumlen; + + xsum = ip->ip_p; + xsum += (ntohs(ip->udp_len)); + xsum += (ntohl(ip->ip_src) >> 16) & 0x0000ffff; + xsum += (ntohl(ip->ip_src) >> 0) & 0x0000ffff; + xsum += (ntohl(ip->ip_dst) >> 16) & 0x0000ffff; + xsum += (ntohl(ip->ip_dst) >> 0) & 0x0000ffff; + + sumlen = ntohs(ip->udp_len); + sumptr = (ushort *)&(ip->udp_src); + + while(sumlen > 1){ + ushort sumdata; + + sumdata = *sumptr++; + xsum += ntohs(sumdata); + sumlen -= 2; + } + + if(sumlen > 0){ + ushort sumdata; + + sumdata = *(unsigned char *)sumptr; + sumdata = (sumdata << 8) & 0xff00; + xsum += sumdata; + } + + while((xsum >> 16) != 0){ + xsum = (xsum & 0x0000ffff) + ((xsum >> 16) & 0x0000ffff); + } + + if((xsum != 0x00000000) && (xsum != 0x0000ffff)){ + printf("## Error: UDP wrong checksum %08x %08x\n", xsum, ntohs(ip->udp_xsum)); + return; + } + } +#endif + +#ifdef CONFIG_NETCONSOLE + nc_input_packet((uchar *)ip +IP_HDR_SIZE, ntohs(ip->udp_dst), ntohs(ip->udp_src), ntohs(ip->udp_len) - 8); +#endif + /* + * IP header OK. Pass the packet to the current handler. + */ + (*packetHandler)((uchar *)ip + IP_HDR_SIZE, ntohs(ip->udp_dst), ntohs(ip->udp_src), ntohs(ip->udp_len) - 8); + break; + } +} + +/**********************************************************************/ + +static int net_check_prereq(proto_t protocol){ + switch(protocol){ + /* Fall through */ +#if (CONFIG_COMMANDS & CFG_CMD_PING) + case PING: + if(NetPingIP == 0){ + puts("## Error: ping address not given\n"); + return(1); + } + goto common; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) + case SNTP: + if(NetNtpServerIP == 0){ + puts("## Error: NTP server address not given\n"); + return(1); + } + goto common; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + case NFS: +#endif + case NETCONS: + case TFTP: + if(NetServerIP == 0){ + puts("## Error: serverip not set\n"); + return(1); + } +#if (CONFIG_COMMANDS & (CFG_CMD_PING | CFG_CMD_SNTP)) + common: +#endif + if(NetOurIP == 0){ + puts("## Error: ipaddr not set\n"); + return(1); + } + /* Fall through */ + + case DHCP: + case RARP: + case BOOTP: + case CDP: + if(memcmp(NetOurEther, "\0\0\0\0\0\0", 6) == 0){ +#ifdef CONFIG_NET_MULTI + extern int eth_get_dev_index(void); + int num = eth_get_dev_index(); + + switch(num){ + case -1: + puts("## Error: no ethernet found\n"); + return(1); + case 0: + puts("## Error: ethaddr not set\n"); + break; + default: + printf("## Error: eth%daddr not set\n", num); + break; + } + + NetStartAgain(); + return(2); +#else + puts("## Error: ethaddr not set\n"); + return(1); +#endif + } + /* Fall through */ + default: + return(0); + } + + return(0); /* OK */ +} +/**********************************************************************/ + +int NetCksumOk(uchar * ptr, int len){ + return(!((NetCksum(ptr, len) + 1) & 0xfffe)); +} + +unsigned NetCksum(uchar * ptr, int len){ + ulong xsum; + ushort *p = (ushort *)ptr; + + xsum = 0; + + while(len-- > 0){ + xsum += *p++; + } + + xsum = (xsum & 0xffff) + (xsum >> 16); + xsum = (xsum & 0xffff) + (xsum >> 16); + + return(xsum & 0xffff); +} + +int NetEthHdrSize(void){ + ushort myvlanid; + + myvlanid = ntohs(NetOurVLAN); + + if(myvlanid == (ushort) -1){ + myvlanid = VLAN_NONE; + } + + return(((myvlanid & VLAN_IDMASK) == VLAN_NONE) ? ETHER_HDR_SIZE : VLAN_ETHER_HDR_SIZE); +} + +int NetSetEther(volatile uchar * xet, uchar * addr, uint prot){ + Ethernet_t *et = (Ethernet_t *)xet; + ushort myvlanid; + + myvlanid = ntohs(NetOurVLAN); + + if(myvlanid == (ushort) -1){ + myvlanid = VLAN_NONE; + } + + memcpy(et->et_dest, addr, 6); + memcpy(et->et_src, NetOurEther, 6); + + if((myvlanid & VLAN_IDMASK) == VLAN_NONE){ + et->et_protlen = htons(prot); + + return(ETHER_HDR_SIZE); + } else { + VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)xet; + + vet->vet_vlan_type = htons(PROT_VLAN); + vet->vet_tag = htons((0 << 5) | (myvlanid & VLAN_IDMASK)); + vet->vet_type = htons(prot); + return(VLAN_ETHER_HDR_SIZE); + } +} + +void NetSetIP(volatile uchar * xip, IPaddr_t dest, int dport, int sport, int len){ + volatile IP_t *ip = (IP_t *)xip; + + /* + * If the data is an odd number of bytes, zero the + * byte after the last byte so that the checksum + * will work. + */ + if(len & 1){ + xip[IP_HDR_SIZE + len] = 0; + } + + /* + * Construct an IP and UDP header. + * (need to set no fragment bit - XXX) + */ + ip->ip_hl_v = 0x45; /* IP_HDR_SIZE / 4 (not including UDP) */ + ip->ip_tos = 0; + ip->ip_len = htons(IP_HDR_SIZE + len); + ip->ip_id = htons(NetIPID++); + ip->ip_off = htons(0x4000); /* No fragmentation */ + ip->ip_ttl = 255; + ip->ip_p = 17; /* UDP */ + ip->ip_sum = 0; + + NetCopyIP((void*)&ip->ip_src, &NetOurIP); /* already in network byte order */ + NetCopyIP((void*)&ip->ip_dst, &dest); /* - "" - */ + + ip->udp_src = htons(sport); + ip->udp_dst = htons(dport); + ip->udp_len = htons(8 + len); + ip->udp_xsum = 0; + ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2); +} + +void copy_filename(char *dst, char *src, int size){ + if(*src && (*src == '"')){ + ++src; + --size; + } + + while((--size > 0) && *src && (*src != '"')){ + *dst++ = *src++; + } + *dst = '\0'; +} + +#endif /* CFG_CMD_NET */ + +void ip_to_string(IPaddr_t x, char *s){ + x = ntohl(x); + sprintf(s, "%d.%d.%d.%d", (int)((x >> 24) & 0xff), (int)((x >> 16) & 0xff), (int)((x >> 8) & 0xff), (int)((x >> 0) & 0xff)); +} + +IPaddr_t string_to_ip(char *s){ + IPaddr_t addr; + char *e; + int i; + + if(s == NULL){ + return(0); + } + + for(addr = 0, i = 0; i < 4; ++i){ + ulong val = s ? simple_strtoul(s, &e, 10) : 0; + addr <<= 8; + addr |= (val & 0xFF); + if(s){ + s = (*e) ? e + 1 : e; + } + } + + return(htonl(addr)); +} + +void VLAN_to_string(ushort x, char *s){ + x = ntohs(x); + + if(x == (ushort) -1){ + x = VLAN_NONE; + } + + if(x == VLAN_NONE){ + strcpy(s, "none"); + } else { + sprintf(s, "%d", x & VLAN_IDMASK); + } +} + +ushort string_to_VLAN(char *s){ + ushort id; + + if(s == NULL){ + return(htons(VLAN_NONE)); + } + + if(*s < '0' || *s > '9'){ + id = VLAN_NONE; + } else { + id = (ushort) simple_strtoul(s, NULL, 10); + } + + return(htons(id)); +} + +void print_IPaddr(IPaddr_t x){ + char tmp[16]; + + ip_to_string(x, tmp); + + puts(tmp); +} + +IPaddr_t getenv_IPaddr(char *var){ + return(string_to_ip(getenv(var))); +} + +ushort getenv_VLAN(char *var){ + return(string_to_VLAN(getenv(var))); +} + + +/********************************************************************************** + * HTTPD section + */ + +#define BUF ((struct uip_eth_hdr *)&uip_buf[0]) + +void NetSendHttpd(void){ + volatile uchar *tmpbuf = NetTxPacket; + int i; + + for(i = 0; i < 40 + UIP_LLH_LEN; i++){ + tmpbuf[i] = uip_buf[i]; + } + + for(; i < uip_len; i++){ + tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN]; + } + + eth_send(NetTxPacket, uip_len); +} + +void NetReceiveHttpd(volatile uchar * inpkt, int len){ + memcpy(uip_buf, (const void *)inpkt, len); + uip_len = len; + + if(BUF->type == htons(UIP_ETHTYPE_IP)){ + uip_arp_ipin(); + uip_input(); + + if(uip_len > 0){ + uip_arp_out(); + NetSendHttpd(); + } + } else if(BUF->type == htons(UIP_ETHTYPE_ARP)){ + uip_arp_arpin(); + + if(uip_len > 0){ + NetSendHttpd(); + } + } +} + +/* ************************************* + * + * HTTP web server for web failsafe mode + * + ***************************************/ +int NetLoopHttpd(void){ + bd_t *bd = gd->bd; + unsigned short int ip[2]; + unsigned char ethinit_attempt = 0; + struct uip_eth_addr eaddr; + +#ifdef CONFIG_NET_MULTI + NetRestarted = 0; + NetDevExists = 0; +#endif + + /* XXX problem with bss workaround */ + NetArpWaitPacketMAC = NULL; + NetArpWaitTxPacket = NULL; + NetArpWaitPacketIP = 0; + NetArpWaitReplyIP = 0; + NetArpWaitTxPacket = NULL; + NetTxPacket = NULL; + + if(!NetTxPacket){ + int i; + // Setup packet buffers, aligned correctly. + NetTxPacket = &PktBuf[0] + (PKTALIGN - 1); + NetTxPacket -= (ulong)NetTxPacket % PKTALIGN; + + for(i = 0; i < PKTBUFSRX; i++){ + NetRxPackets[i] = NetTxPacket + (i + 1) * PKTSIZE_ALIGN; + } + } + + if(!NetArpWaitTxPacket){ + NetArpWaitTxPacket = &NetArpWaitPacketBuf[0] + (PKTALIGN - 1); + NetArpWaitTxPacket -= (ulong)NetArpWaitTxPacket % PKTALIGN; + NetArpWaitTxPacketSize = 0; + } + + // restart label + restart: + + eth_halt(); + +#ifdef CONFIG_NET_MULTI + eth_set_current(); +#endif + + while(ethinit_attempt < 10){ + if(eth_init(bd)){ + ethinit_attempt = 0; + break; + } else { + ethinit_attempt++; + eth_halt(); + milisecdelay(1000); + } + } + + if(ethinit_attempt > 0){ + eth_halt(); + printf("## Error: couldn't initialize eth (cable disconnected?)!\n\n"); + return(-1); + } + + // get MAC address +#ifdef CONFIG_NET_MULTI + memcpy(NetOurEther, eth_get_dev()->enetaddr, 6); +#else + eth_getenv_enetaddr("ethaddr", NetOurEther); +#endif + + eaddr.addr[0] = NetOurEther[0]; + eaddr.addr[1] = NetOurEther[1]; + eaddr.addr[2] = NetOurEther[2]; + eaddr.addr[3] = NetOurEther[3]; + eaddr.addr[4] = NetOurEther[4]; + eaddr.addr[5] = NetOurEther[5]; + + // set MAC address + uip_setethaddr(eaddr); + + // set ip and other addresses + // TODO: do we need this with uIP stack? + NetCopyIP(&NetOurIP, &bd->bi_ip_addr); + + NetOurGatewayIP = getenv_IPaddr("gatewayip"); + NetOurSubnetMask = getenv_IPaddr("netmask"); + NetOurVLAN = getenv_VLAN("vlan"); + NetOurNativeVLAN = getenv_VLAN("nvlan"); + + // start server... + printf("HTTP server is starting at IP: %ld.%ld.%ld.%ld\n", (bd->bi_ip_addr & 0xff000000) >> 24, (bd->bi_ip_addr & 0x00ff0000) >> 16, (bd->bi_ip_addr & 0x0000ff00) >> 8, (bd->bi_ip_addr & 0x000000ff)); + + HttpdStart(); + + // set local host ip address + ip[0] = ((bd->bi_ip_addr & 0xFFFF0000) >> 16); + ip[1] = (bd->bi_ip_addr & 0x0000FFFF); + + uip_sethostaddr(ip); + + // set network mask (255.255.255.0 -> local network) + ip[0] = ((0xFFFFFF00 & 0xFFFF0000) >> 16); + ip[1] = (0xFFFFFF00 & 0x0000FFFF); + + uip_setnetmask(ip); + + // should we also set default router ip address? + //uip_setdraddr(); + + // show current progress of the process + do_http_progress(WEBFAILSAFE_PROGRESS_START); + + webfailsafe_is_running = 1; + + // infinite loop + for(;;){ + + /* + * Check the ethernet for a new packet. + * The ethernet receive routine will process it. + */ + if(eth_rx() > 0){ + HttpdHandler(); + } + + // if CTRL+C was pressed -> return! + if(ctrlc()){ + eth_halt(); + + // reset global variables to default state + webfailsafe_is_running = 0; + webfailsafe_ready_for_upgrade = 0; + webfailsafe_upgrade_type = WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE; + + /* Invalidate the last protocol */ + eth_set_last_protocol(BOOTP); + + printf("\nWeb failsafe mode aborted!\n\n"); + return(-1); + } + + // until upload is not completed, get back to the start of the loop + if(!webfailsafe_ready_for_upgrade){ + continue; + } + + // stop eth interface + eth_halt(); + + // show progress + do_http_progress(WEBFAILSAFE_PROGRESS_UPLOAD_READY); + + // try to make upgrade! + if(do_http_upgrade(NetBootFileXferSize, webfailsafe_upgrade_type) >= 0){ + milisecdelay(500); + + do_http_progress(WEBFAILSAFE_PROGRESS_UPGRADE_READY); + + milisecdelay(500); + + /* reset the board */ + do_reset(NULL, 0, 0, NULL); + } + break; + } + + // reset global variables to default state + webfailsafe_is_running = 0; + webfailsafe_ready_for_upgrade = 0; + webfailsafe_upgrade_type = WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE; + + NetBootFileXferSize = 0; + + do_http_progress(WEBFAILSAFE_PROGRESS_UPGRADE_FAILED); + + // go to restart + goto restart; + + return(-1); +} diff --git a/u-boot/net/nfs.c b/u-boot/net/nfs.c new file mode 100755 index 0000000..553f3d3 --- /dev/null +++ b/u-boot/net/nfs.c @@ -0,0 +1,778 @@ +/* + * NFS support driver - based on etherboot and U-BOOT's tftp.c + * + * Masami Komiya 2004 + * + */ + +/* NOTE: the NFS code is heavily inspired by the NetBSD netboot code (read: + * large portions are copied verbatim) as distributed in OSKit 0.97. A few + * changes were necessary to adapt the code to Etherboot and to fix several + * inconsistencies. Also the RPC message preparation is done "by hand" to + * avoid adding netsprintf() which I find hard to understand and use. */ + +/* NOTE 2: Etherboot does not care about things beyond the kernel image, so + * it loads the kernel image off the boot server (ARP_SERVER) and does not + * access the client root disk (root-path in dhcpd.conf), which would use + * ARP_ROOTSERVER. The root disk is something the operating system we are + * about to load needs to use. This is different from the OSKit 0.97 logic. */ + +/* NOTE 3: Symlink handling introduced by Anselm M Hoffmeister, 2003-July-14 + * If a symlink is encountered, it is followed as far as possible (recursion + * possible, maximum 16 steps). There is no clearing of ".."'s inside the + * path, so please DON'T DO THAT. thx. */ + +#include +#include +#include +#include +#include "nfs.h" +#include "bootp.h" + +/*#define NFS_DEBUG*/ + +#if ((CONFIG_COMMANDS & CFG_CMD_NET) && (CONFIG_COMMANDS & CFG_CMD_NFS)) + +#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */ +#define NFS_TIMEOUT 60 + +static int fs_mounted = 0; +static unsigned long rpc_id = 0; +static int nfs_offset = -1; +static int nfs_len; + +static char dirfh[NFS_FHSIZE]; /* file handle of directory */ +static char filefh[NFS_FHSIZE]; /* file handle of kernel image */ + +static int NfsDownloadState; +static IPaddr_t NfsServerIP; +static int NfsSrvMountPort; +static int NfsSrvNfsPort; +static int NfsOurPort; +static int NfsTimeoutCount; +static int NfsState; +#define STATE_PRCLOOKUP_PROG_MOUNT_REQ 1 +#define STATE_PRCLOOKUP_PROG_NFS_REQ 2 +#define STATE_MOUNT_REQ 3 +#define STATE_UMOUNT_REQ 4 +#define STATE_LOOKUP_REQ 5 +#define STATE_READ_REQ 6 +#define STATE_READLINK_REQ 7 + +static char default_filename[64]; +static char *nfs_filename; +static char *nfs_path; +static char nfs_path_buff[2048]; + +static __inline__ int +store_block (uchar * src, unsigned offset, unsigned len) +{ + ulong newsize = offset + len; +#ifdef CFG_DIRECT_FLASH_NFS + int i, rc = 0; + + for (i=0; i= flash_info[i].start[0]) { + rc = 1; + break; + } + } + + if (rc) { /* Flash is destination for this packet */ + rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len); + if (rc) { + flash_perror (rc); + return -1; + } + } else +#endif /* CFG_DIRECT_FLASH_NFS */ + { + (void)memcpy ((void *)(load_addr + offset), src, len); + } + + if (NetBootFileXferSize < (offset+len)) + NetBootFileXferSize = newsize; + return 0; +} + +static char* +basename (char *path) +{ + char *fname; + + fname = path + strlen(path) - 1; + while (fname >= path) { + if (*fname == '/') { + fname++; + break; + } + fname--; + } + return fname; +} + +static char* +dirname (char *path) +{ + char *fname; + + fname = basename (path); + --fname; + *fname = '\0'; + return path; +} + +/************************************************************************** +RPC_ADD_CREDENTIALS - Add RPC authentication/verifier entries +**************************************************************************/ +static long *rpc_add_credentials (long *p) +{ + int hl; + int hostnamelen; + char hostname[256]; + + strcpy (hostname, ""); + hostnamelen=strlen (hostname); + + /* Here's the executive summary on authentication requirements of the + * various NFS server implementations: Linux accepts both AUTH_NONE + * and AUTH_UNIX authentication (also accepts an empty hostname field + * in the AUTH_UNIX scheme). *BSD refuses AUTH_NONE, but accepts + * AUTH_UNIX (also accepts an empty hostname field in the AUTH_UNIX + * scheme). To be safe, use AUTH_UNIX and pass the hostname if we have + * it (if the BOOTP/DHCP reply didn't give one, just use an empty + * hostname). */ + + hl = (hostnamelen + 3) & ~3; + + /* Provide an AUTH_UNIX credential. */ + *p++ = htonl(1); /* AUTH_UNIX */ + *p++ = htonl(hl+20); /* auth length */ + *p++ = htonl(0); /* stamp */ + *p++ = htonl(hostnamelen); /* hostname string */ + if (hostnamelen & 3) { + *(p + hostnamelen / 4) = 0; /* add zero padding */ + } + memcpy (p, hostname, hostnamelen); + p += hl / 4; + *p++ = 0; /* uid */ + *p++ = 0; /* gid */ + *p++ = 0; /* auxiliary gid list */ + + /* Provide an AUTH_NONE verifier. */ + *p++ = 0; /* AUTH_NONE */ + *p++ = 0; /* auth length */ + + return p; +} + +/************************************************************************** +RPC_LOOKUP - Lookup RPC Port numbers +**************************************************************************/ +static void +rpc_req (int rpc_prog, int rpc_proc, uint32_t *data, int datalen) +{ + struct rpc_t pkt; + unsigned long id; + uint32_t *p; + int pktlen; + int sport; + + id = ++rpc_id; + pkt.u.call.id = htonl(id); + pkt.u.call.type = htonl(MSG_CALL); + pkt.u.call.rpcvers = htonl(2); /* use RPC version 2 */ + pkt.u.call.prog = htonl(rpc_prog); + pkt.u.call.vers = htonl(2); /* portmapper is version 2 */ + pkt.u.call.proc = htonl(rpc_proc); + p = (uint32_t *)&(pkt.u.call.data); + + if (datalen) + memcpy ((char *)p, (char *)data, datalen*sizeof(uint32_t)); + + pktlen = (char *)p + datalen*sizeof(uint32_t) - (char *)&pkt; + + memcpy ((char *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE, (char *)&pkt, pktlen); + + if (rpc_prog == PROG_PORTMAP) + sport = SUNRPC_PORT; + else if (rpc_prog == PROG_MOUNT) + sport = NfsSrvMountPort; + else + sport = NfsSrvNfsPort; + + NetSendUDPPacket (NetServerEther, NfsServerIP, sport, NfsOurPort, pktlen); +} + +/************************************************************************** +RPC_LOOKUP - Lookup RPC Port numbers +**************************************************************************/ +static void +rpc_lookup_req (int prog, int ver) +{ + uint32_t data[16]; + + data[0] = 0; data[1] = 0; /* auth credential */ + data[2] = 0; data[3] = 0; /* auth verifier */ + data[4] = htonl(prog); + data[5] = htonl(ver); + data[6] = htonl(17); /* IP_UDP */ + data[7] = 0; + + rpc_req (PROG_PORTMAP, PORTMAP_GETPORT, data, 8); +} + +/************************************************************************** +NFS_MOUNT - Mount an NFS Filesystem +**************************************************************************/ +static void +nfs_mount_req (char *path) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + int pathlen; + + pathlen = strlen (path); + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials((long *)p); + + *p++ = htonl(pathlen); + if (pathlen & 3) *(p + pathlen / 4) = 0; + memcpy (p, path, pathlen); + p += (pathlen + 3) / 4; + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_MOUNT, MOUNT_ADDENTRY, data, len); +} + +/************************************************************************** +NFS_UMOUNTALL - Unmount all our NFS Filesystems on the Server +**************************************************************************/ +static void +nfs_umountall_req (void) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + + if ((NfsSrvMountPort == -1) || (!fs_mounted)) { + /* Nothing mounted, nothing to umount */ + return; + } + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_MOUNT, MOUNT_UMOUNTALL, data, len); +} + +/*************************************************************************** + * NFS_READLINK (AH 2003-07-14) + * This procedure is called when read of the first block fails - + * this probably happens when it's a directory or a symlink + * In case of successful readlink(), the dirname is manipulated, + * so that inside the nfs() function a recursion can be done. + **************************************************************************/ +static void +nfs_readlink_req (void) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + + memcpy (p, filefh, NFS_FHSIZE); + p += (NFS_FHSIZE / 4); + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_NFS, NFS_READLINK, data, len); +} + +/************************************************************************** +NFS_LOOKUP - Lookup Pathname +**************************************************************************/ +static void +nfs_lookup_req (char *fname) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + int fnamelen; + + fnamelen = strlen (fname); + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + + memcpy (p, dirfh, NFS_FHSIZE); + p += (NFS_FHSIZE / 4); + *p++ = htonl(fnamelen); + if (fnamelen & 3) *(p + fnamelen / 4) = 0; + memcpy (p, fname, fnamelen); + p += (fnamelen + 3) / 4; + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_NFS, NFS_LOOKUP, data, len); +} + +/************************************************************************** +NFS_READ - Read File on NFS Server +**************************************************************************/ +static void +nfs_read_req (int offset, int readlen) +{ + uint32_t data[1024]; + uint32_t *p; + int len; + + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + + memcpy (p, filefh, NFS_FHSIZE); + p += (NFS_FHSIZE / 4); + *p++ = htonl(offset); + *p++ = htonl(readlen); + *p++ = 0; + + len = (uint32_t *)p - (uint32_t *)&(data[0]); + + rpc_req (PROG_NFS, NFS_READ, data, len); +} + +/************************************************************************** +RPC request dispatcher +**************************************************************************/ + +static void +NfsSend (void) +{ +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + switch (NfsState) { + case STATE_PRCLOOKUP_PROG_MOUNT_REQ: + rpc_lookup_req (PROG_MOUNT, 1); + break; + case STATE_PRCLOOKUP_PROG_NFS_REQ: + rpc_lookup_req (PROG_NFS, 2); + break; + case STATE_MOUNT_REQ: + nfs_mount_req (nfs_path); + break; + case STATE_UMOUNT_REQ: + nfs_umountall_req (); + break; + case STATE_LOOKUP_REQ: + nfs_lookup_req (nfs_filename); + break; + case STATE_READ_REQ: + nfs_read_req (nfs_offset, nfs_len); + break; + case STATE_READLINK_REQ: + nfs_readlink_req (); + break; + } +} + +/************************************************************************** +Handlers for the reply from server +**************************************************************************/ + +static int +rpc_lookup_reply (int prog, uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.astatus) { + return -1; + } + + switch (prog) { + case PROG_MOUNT: + NfsSrvMountPort = ntohl(rpc_pkt.u.reply.data[0]); + break; + case PROG_NFS: + NfsSrvNfsPort = ntohl(rpc_pkt.u.reply.data[0]); + break; + } + + return 0; +} + +static int +nfs_mount_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { + return -1; + } + + fs_mounted = 1; + memcpy (dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); + + return 0; +} + +static int +nfs_umountall_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus) { + return -1; + } + + fs_mounted = 0; + memset (dirfh, 0, sizeof(dirfh)); + + return 0; +} + +static int +nfs_lookup_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { + return -1; + } + + memcpy (filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); + + return 0; +} + +static int +nfs_readlink_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + int rlen; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { + return -1; + } + + rlen = ntohl (rpc_pkt.u.reply.data[1]); /* new path length */ + + if (*((char *)&(rpc_pkt.u.reply.data[2])) != '/') { + int pathlen; + strcat (nfs_path, "/"); + pathlen = strlen(nfs_path); + memcpy (nfs_path+pathlen, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen); + nfs_path[pathlen+rlen+1] = 0; + } else { + memcpy (nfs_path, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen); + nfs_path[rlen] = 0; + } + return 0; +} + +static int +nfs_read_reply (uchar *pkt, unsigned len) +{ + struct rpc_t rpc_pkt; + int rlen; + +#ifdef NFS_DEBUG_nop + printf ("%s\n", __FUNCTION__); +#endif + + memcpy ((uchar *)&rpc_pkt, pkt, sizeof(rpc_pkt.u.reply)); + + if (ntohl(rpc_pkt.u.reply.id) != rpc_id) + return -1; + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { + if (rpc_pkt.u.reply.rstatus) { + return -9999; + } + if (rpc_pkt.u.reply.astatus) { + return -9999; + } + return -ntohl(rpc_pkt.u.reply.data[0]);; + } + + if ((nfs_offset!=0) && !((nfs_offset) % (NFS_READ_SIZE/2*10*HASHES_PER_LINE))) { + puts ("\n\t "); + } + if (!(nfs_offset % ((NFS_READ_SIZE/2)*10))) { + putc ('#'); + } + + rlen = ntohl(rpc_pkt.u.reply.data[18]); + if ( store_block ((uchar *)pkt+sizeof(rpc_pkt.u.reply), nfs_offset, rlen) ) + return -9999; + + return rlen; +} + +/************************************************************************** +Interfaces of U-BOOT +**************************************************************************/ + +static void +NfsTimeout (void) +{ + puts ("Timeout\n"); + NetState = NETLOOP_FAIL; + return; +} + +static void +NfsHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len) +{ + int rlen; + +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + + if (dest != NfsOurPort) return; + + switch (NfsState) { + case STATE_PRCLOOKUP_PROG_MOUNT_REQ: + rpc_lookup_reply (PROG_MOUNT, pkt, len); + NfsState = STATE_PRCLOOKUP_PROG_NFS_REQ; + NfsSend (); + break; + + case STATE_PRCLOOKUP_PROG_NFS_REQ: + rpc_lookup_reply (PROG_NFS, pkt, len); + NfsState = STATE_MOUNT_REQ; + NfsSend (); + break; + + case STATE_MOUNT_REQ: + if (nfs_mount_reply(pkt, len)) { + puts ("*** ERROR: Cannot mount\n"); + /* just to be sure... */ + NfsState = STATE_UMOUNT_REQ; + NfsSend (); + } else { + NfsState = STATE_LOOKUP_REQ; + NfsSend (); + } + break; + + case STATE_UMOUNT_REQ: + if (nfs_umountall_reply(pkt, len)) { + puts ("*** ERROR: Cannot umount\n"); + NetState = NETLOOP_FAIL; + } else { + puts ("\ndone\n"); + NetState = NfsDownloadState; + } + break; + + case STATE_LOOKUP_REQ: + if (nfs_lookup_reply(pkt, len)) { + puts ("*** ERROR: File lookup fail\n"); + NfsState = STATE_UMOUNT_REQ; + NfsSend (); + } else { + NfsState = STATE_READ_REQ; + nfs_offset = 0; + nfs_len = NFS_READ_SIZE; + NfsSend (); + } + break; + + case STATE_READLINK_REQ: + if (nfs_readlink_reply(pkt, len)) { + puts ("*** ERROR: Symlink fail\n"); + NfsState = STATE_UMOUNT_REQ; + NfsSend (); + } else { +#ifdef NFS_DEBUG + printf ("Symlink --> %s\n", nfs_path); +#endif + nfs_filename = basename (nfs_path); + nfs_path = dirname (nfs_path); + + NfsState = STATE_MOUNT_REQ; + NfsSend (); + } + break; + + case STATE_READ_REQ: + rlen = nfs_read_reply (pkt, len); + NetSetTimeout (NFS_TIMEOUT * CFG_HZ, NfsTimeout); + if (rlen > 0) { + nfs_offset += rlen; + NfsSend (); + } + else if ((rlen == -NFSERR_ISDIR)||(rlen == -NFSERR_INVAL)) { + /* symbolic link */ + NfsState = STATE_READLINK_REQ; + NfsSend (); + } else { + if ( ! rlen ) NfsDownloadState = NETLOOP_SUCCESS; + NfsState = STATE_UMOUNT_REQ; + NfsSend (); + } + break; + } +} + + +void +NfsStart (void) +{ +#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); +#endif + NfsDownloadState = NETLOOP_FAIL; + + NfsServerIP = NetServerIP; + nfs_path = (char *)nfs_path_buff; + + if (nfs_path == NULL) { + NetState = NETLOOP_FAIL; + puts ("*** ERROR: Fail allocate memory\n"); + return; + } + + if (BootFile[0] == '\0') { + sprintf (default_filename, "/nfsroot/%02lX%02lX%02lX%02lX.img", + NetOurIP & 0xFF, + (NetOurIP >> 8) & 0xFF, + (NetOurIP >> 16) & 0xFF, + (NetOurIP >> 24) & 0xFF ); + strcpy (nfs_path, default_filename); + + printf ("** Warning: no boot file name; using '%s'\n", + nfs_path); + } else { + char *p=BootFile; + + p = strchr (p, ':'); + + if (p != NULL) { + NfsServerIP = string_to_ip (BootFile); + ++p; + strcpy (nfs_path, p); + } else { + strcpy (nfs_path, BootFile); + } + } + + nfs_filename = basename (nfs_path); + nfs_path = dirname (nfs_path); + +#if defined(CONFIG_NET_MULTI) + printf ("Using %s device\n", eth_get_name()); +#endif + + puts ("File transfer via NFS from server "); print_IPaddr (NfsServerIP); + puts ("; our IP address is "); print_IPaddr (NetOurIP); + + /* Check if we need to send across this subnet */ + if (NetOurGatewayIP && NetOurSubnetMask) { + IPaddr_t OurNet = NetOurIP & NetOurSubnetMask; + IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask; + + if (OurNet != ServerNet) { + puts ("; sending through gateway "); + print_IPaddr (NetOurGatewayIP) ; + } + } + printf ("\nFilename '%s/%s'.", nfs_path, nfs_filename); + + if (NetBootFileSize) { + printf (" Size is 0x%x Bytes = ", NetBootFileSize<<9); + print_size (NetBootFileSize<<9, ""); + } + printf ("\nLoad address: 0x%lx\n" + "Loading: *\b", load_addr); + + NetSetTimeout (NFS_TIMEOUT * CFG_HZ, NfsTimeout); + NetSetHandler (NfsHandler); + + NfsTimeoutCount = 0; + NfsState = STATE_PRCLOOKUP_PROG_MOUNT_REQ; + + /*NfsOurPort = 4096 + (get_ticks() % 3072);*/ + /*FIX ME !!!*/ + NfsOurPort = 1000; + + /* zero out server ether in case the server ip has changed */ + memset (NetServerEther, 0, 6); + + NfsSend (); +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NFS */ diff --git a/u-boot/net/nfs.h b/u-boot/net/nfs.h new file mode 100755 index 0000000..712afa0 --- /dev/null +++ b/u-boot/net/nfs.h @@ -0,0 +1,74 @@ +/* + * (C) Masami Komiya 2004 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +#ifndef __NFS_H__ +#define __NFS_H__ + +#define SUNRPC_PORT 111 + +#define PROG_PORTMAP 100000 +#define PROG_NFS 100003 +#define PROG_MOUNT 100005 + +#define MSG_CALL 0 +#define MSG_REPLY 1 + +#define PORTMAP_GETPORT 3 + +#define MOUNT_ADDENTRY 1 +#define MOUNT_UMOUNTALL 4 + +#define NFS_LOOKUP 4 +#define NFS_READLINK 5 +#define NFS_READ 6 + +#define NFS_FHSIZE 32 + +#define NFSERR_PERM 1 +#define NFSERR_NOENT 2 +#define NFSERR_ACCES 13 +#define NFSERR_ISDIR 21 +#define NFSERR_INVAL 22 + +/* Block size used for NFS read accesses. A RPC reply packet (including all + * headers) must fit within a single Ethernet frame to avoid fragmentation. + * Chosen to be a power of two, as most NFS servers are optimized for this. */ +#define NFS_READ_SIZE 1024 + +#define NFS_MAXLINKDEPTH 16 + +struct rpc_t { + union { + uint8_t data[2048]; + struct { + uint32_t id; + uint32_t type; + uint32_t rpcvers; + uint32_t prog; + uint32_t vers; + uint32_t proc; + uint32_t data[1]; + } call; + struct { + uint32_t id; + uint32_t type; + uint32_t rstatus; + uint32_t verifier; + uint32_t v2; + uint32_t astatus; + uint32_t data[19]; + } reply; + } u; +}; +extern void NfsStart (void); /* Begin NFS */ + + +/**********************************************************************/ + +#endif /* __NFS_H__ */ diff --git a/u-boot/net/rarp.c b/u-boot/net/rarp.c new file mode 100755 index 0000000..1ba60e8 --- /dev/null +++ b/u-boot/net/rarp.c @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include "nfs.h" +#include "bootp.h" +#include "rarp.h" +#include "tftp.h" + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#define TIMEOUT 5 /* Seconds before trying BOOTP again */ +#ifndef CONFIG_NET_RETRY_COUNT +# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */ +#else +# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT) +#endif + + +int RarpTry; + +/* + * Handle a RARP received packet. + */ +static void +RarpHandler(uchar * dummi0, unsigned dummi1, unsigned dummi2, unsigned dummi3) +{ + char *s; +#ifdef DEBUG + puts ("Got good RARP\n"); +#endif + if ((s = getenv("autoload")) != NULL) { + if (*s == 'n') { + /* + * Just use RARP to configure system; + * Do not use TFTP/NFS to to load the bootfile. + */ + NetState = NETLOOP_SUCCESS; + return; +#if (CONFIG_COMMANDS & CFG_CMD_NFS) + } else if ((s != NULL) && !strcmp(s, "NFS")) { + NfsStart(); + return; +#endif + } + } + TftpStart (); +} + + +/* + * Timeout on BOOTP request. + */ +static void +RarpTimeout(void) +{ + if (RarpTry >= TIMEOUT_COUNT) { + puts ("\nRetry count exceeded; starting again\n"); + NetStartAgain (); + } else { + NetSetTimeout (TIMEOUT * CFG_HZ, RarpTimeout); + RarpRequest (); + } +} + + +void +RarpRequest (void) +{ + int i; + volatile uchar *pkt; + ARP_t * rarp; + + printf("RARP broadcast %d\n", ++RarpTry); + pkt = NetTxPacket; + + pkt += NetSetEther(pkt, NetBcastAddr, PROT_RARP); + + rarp = (ARP_t *)pkt; + + rarp->ar_hrd = htons (ARP_ETHER); + rarp->ar_pro = htons (PROT_IP); + rarp->ar_hln = 6; + rarp->ar_pln = 4; + rarp->ar_op = htons (RARPOP_REQUEST); + memcpy (&rarp->ar_data[0], NetOurEther, 6); /* source ET addr */ + memcpy (&rarp->ar_data[6], &NetOurIP, 4); /* source IP addr */ + memcpy (&rarp->ar_data[10], NetOurEther, 6); /* dest ET addr = source ET addr ??*/ + /* dest. IP addr set to broadcast */ + for (i = 0; i <= 3; i++) { + rarp->ar_data[16 + i] = 0xff; + } + + NetSendPacket(NetTxPacket, (pkt - NetTxPacket) + ARP_HDR_SIZE); + + NetSetTimeout(TIMEOUT * CFG_HZ, RarpTimeout); + NetSetHandler(RarpHandler); +} + +#endif /* CFG_CMD_NET */ diff --git a/u-boot/net/rarp.h b/u-boot/net/rarp.h new file mode 100755 index 0000000..0c16d46 --- /dev/null +++ b/u-boot/net/rarp.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __RARP_H__ +#define __RARP_H__ + +#ifndef __NET_H__ +#include +#endif /* __NET_H__ */ + + +/**********************************************************************/ +/* + * Global functions and variables. + */ + +extern int RarpTry; + +extern void RarpRequest (void); /* Send a RARP request */ + +/**********************************************************************/ + +#endif /* __RARP_H__ */ diff --git a/u-boot/net/sntp.c b/u-boot/net/sntp.c new file mode 100755 index 0000000..e06c411 --- /dev/null +++ b/u-boot/net/sntp.c @@ -0,0 +1,95 @@ +/* + * SNTP support driver + * + * Masami Komiya 2005 + * + */ +#include +#include +#include +#include +#include "sntp.h" + +#if ((CONFIG_COMMANDS & CFG_CMD_NET) && (CONFIG_COMMANDS & CFG_CMD_SNTP)) + +//#define DEBUG + +#define SNTP_TIMEOUT 10 + +static int SntpOurPort; + +static void SntpSend(void){ + struct sntp_pkt_t pkt; + int pktlen = SNTP_PACKET_LEN; + int sport; + +#ifdef DEBUG + printf("%s\n", __FUNCTION__); +#endif + + memset(&pkt, 0, sizeof(pkt)); + + pkt.li = NTP_LI_NOLEAP; + pkt.vn = NTP_VERSION; + pkt.mode = NTP_MODE_CLIENT; + + memcpy((char *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE, (char *)&pkt, pktlen); + + SntpOurPort = 10000 + (get_timer(0) % 4096); + sport = NTP_SERVICE_PORT; + + puts("Sending SNTP request...\n"); + + NetSendUDPPacket(NetServerEther, NetNtpServerIP, sport, SntpOurPort, pktlen); +} + +static void SntpTimeout(void){ + puts("## Error: timeout\n"); + NetState = NETLOOP_FAIL; + + return; +} + +static void SntpHandler(uchar *pkt, unsigned dest, unsigned src, unsigned len){ + struct sntp_pkt_t *rpktp = (struct sntp_pkt_t *)pkt; + struct rtc_time tm; + ulong seconds; + +#ifdef DEBUG + printf("%s\n", __FUNCTION__); +#endif + + if(dest != SntpOurPort){ + return; + } + + /* + * As the RTC's used in U-Boot supports second resolution only + * we simply ignore the sub-second field. + */ + memcpy(&seconds, &rpktp->transmit_timestamp, sizeof(ulong)); + + to_tm(ntohl(seconds) - 2208988800UL + NetTimeOffset, &tm); + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + // TODO: find out how to use RTC on + //rtc_set(&tm); +#endif + printf("Got SNTP response: %4d-%02d-%02d %2d:%02d:%02d\n\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); + NetState = NETLOOP_SUCCESS; +} + +void SntpStart(void){ +#ifdef DEBUG + printf("%s\n", __FUNCTION__); +#endif + + NetSetTimeout(SNTP_TIMEOUT * CFG_HZ, SntpTimeout); + NetSetHandler(SntpHandler); + + memset(NetServerEther, 0, 6); + + SntpSend(); +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_SNTP */ diff --git a/u-boot/net/sntp.h b/u-boot/net/sntp.h new file mode 100755 index 0000000..8a097bf --- /dev/null +++ b/u-boot/net/sntp.h @@ -0,0 +1,61 @@ +/* + * (C) Masami Komiya 2005 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2, or (at + * your option) any later version. + */ + +#ifndef __SNTP_H__ +#define __SNTP_H__ + +#define NTP_SERVICE_PORT 123 +#define SNTP_PACKET_LEN 48 + + +/* Leap Indicator */ +#define NTP_LI_NOLEAP 0x0 +#define NTP_LI_61SECS 0x1 +#define NTP_LI_59SECS 0x2 +#define NTP_LI_ALARM 0x3 + +/* Version */ + +#define NTP_VERSION 4 + +/* Mode */ +#define NTP_MODE_RESERVED 0 +#define NTP_MODE_SYMACTIVE 1 /* Symmetric Active */ +#define NTP_MODE_SYMPASSIVE 2 /* Symmetric Passive */ +#define NTP_MODE_CLIENT 3 +#define NTP_MODE_SERVER 4 +#define NTP_MODE_BROADCAST 5 +#define NTP_MODE_NTPCTRL 6 /* Reserved for NTP control message */ +#define NTP_MODE_PRIVATE 7 /* Reserved for private use */ + +struct sntp_pkt_t { +#if __LITTLE_ENDIAN + uchar mode:3; + uchar vn:3; + uchar li:2; +#else + uchar li:2; + uchar vn:3; + uchar mode:3; +#endif + uchar stratum; + uchar poll; + uchar precision; + uint root_delay; + uint root_dispersion; + uint reference_id; + unsigned long long reference_timestamp; + unsigned long long originate_timestamp; + unsigned long long receive_timestamp; + unsigned long long transmit_timestamp; +}; + +extern void SntpStart (void); /* Begin SNTP */ + +#endif /* __SNTP_H__ */ diff --git a/u-boot/net/tftp.c b/u-boot/net/tftp.c new file mode 100755 index 0000000..3695800 --- /dev/null +++ b/u-boot/net/tftp.c @@ -0,0 +1,388 @@ +/* + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + * Copyright 2000, 2001 DENX Software Engineering, Wolfgang Denk, wd@denx.de + */ + +#include +#include +#include +#include "tftp.h" +#include "bootp.h" + +#undef ET_DEBUG + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */ +#define TIMEOUT 5 /* Seconds to timeout for a lost pkt */ + +#ifndef CONFIG_NET_RETRY_COUNT + #define TIMEOUT_COUNT 10 /* # of timeouts before giving up */ +#else + #define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT * 2) +#endif + +/* (for checking the image size) */ +#define HASHES_PER_LINE 40 /* Number of "loading" hashes per line */ + +/* + * TFTP operations. + */ +#define TFTP_RRQ 1 +#define TFTP_WRQ 2 +#define TFTP_DATA 3 +#define TFTP_ACK 4 +#define TFTP_ERROR 5 +#define TFTP_OACK 6 + + +static int TftpServerPort; /* The UDP port at their end */ +static int TftpOurPort; /* The UDP port at our end */ +static int TftpTimeoutCount; +static int TftpState; + +static ulong TftpBlock; /* packet sequence number */ +static ulong TftpLastBlock; /* last packet sequence number received */ +static ulong TftpBlockWrap; /* count of sequence number wraparounds */ +static ulong TftpBlockWrapOffset; /* memory offset due to wrapping */ + +#define STATE_RRQ 1 +#define STATE_DATA 2 +#define STATE_TOO_LARGE 3 +#define STATE_BAD_MAGIC 4 +#define STATE_OACK 5 + +#define TFTP_BLOCK_SIZE 512 /* default TFTP block size */ +#define TFTP_SEQUENCE_SIZE ((ulong)(1<<16)) /* sequence number is 16 bit */ + +#define DEFAULT_NAME_LEN (8 + 4 + 1) + +static char default_filename[DEFAULT_NAME_LEN]; +static char *tftp_filename; + +#ifdef CFG_DIRECT_FLASH_TFTP + extern flash_info_t flash_info[]; +#endif + +static __inline__ void store_block(unsigned block, uchar * src, unsigned len){ + ulong offset = block * TFTP_BLOCK_SIZE + TftpBlockWrapOffset; + ulong newsize = offset + len; + +#ifdef CFG_DIRECT_FLASH_TFTP + int i, rc = 0; + + for(i=0; i= flash_info[i].start[0]){ + rc = 1; + break; + } + } + + if(rc){ /* Flash is destination for this packet */ + rc = flash_write((char *)src, (ulong)(load_addr+offset), len); + + if(rc){ + flash_perror(rc); + NetState = NETLOOP_FAIL; + return; + } + } else +#endif /* CFG_DIRECT_FLASH_TFTP */ + { + (void)memcpy((void *)(load_addr + offset), src, len); + } + + if(NetBootFileXferSize < newsize){ + NetBootFileXferSize = newsize; + } +} + +static void TftpSend(void); +static void TftpTimeout(void); + +/**********************************************************************/ + +static void TftpSend(void){ + volatile uchar *pkt; + volatile uchar *xp; + int len = 0; + volatile ushort *s; + + /* + * We will always be sending some sort of packet, so + * cobble together the packet headers now. + */ + pkt = NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE; + + switch(TftpState){ + case STATE_RRQ: + xp = pkt; + s = (ushort *)pkt; + *s++ = htons(TFTP_RRQ); + + pkt = (uchar *)s; + strcpy ((char *)pkt, tftp_filename); + + pkt += strlen(tftp_filename) + 1; + strcpy ((char *)pkt, "octet"); + + pkt += 5 /*strlen("octet")*/ + 1; + strcpy ((char *)pkt, "timeout"); + + pkt += 7 /*strlen("timeout")*/ + 1; + sprintf((char *)pkt, "%d", TIMEOUT); + #ifdef ET_DEBUG + printf("send option \"timeout %s\"\n", (char *)pkt); + #endif + pkt += strlen((char *)pkt) + 1; + len = pkt - xp; + break; + + case STATE_DATA: + case STATE_OACK: + xp = pkt; + s = (ushort *)pkt; + *s++ = htons(TFTP_ACK); + *s++ = htons(TftpBlock); + pkt = (uchar *)s; + len = pkt - xp; + break; + + case STATE_TOO_LARGE: + xp = pkt; + s = (ushort *)pkt; + *s++ = htons(TFTP_ERROR); + *s++ = htons(3); + pkt = (uchar *)s; + strcpy((char *)pkt, "File too large"); + pkt += 14 /*strlen("File too large")*/ + 1; + len = pkt - xp; + break; + + case STATE_BAD_MAGIC: + xp = pkt; + s = (ushort *)pkt; + *s++ = htons(TFTP_ERROR); + *s++ = htons(2); + pkt = (uchar *)s; + strcpy((char *)pkt, "File has bad magic"); + pkt += 18 /*strlen("File has bad magic")*/ + 1; + len = pkt - xp; + break; + } + + NetSendUDPPacket(NetServerEther, NetServerIP, TftpServerPort, TftpOurPort, len); +} + +static void TftpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len){ + ushort proto; + ushort *s; + + if(dest != TftpOurPort){ + return; + } + + if(TftpState != STATE_RRQ && src != TftpServerPort){ + return; + } + + if(len < 2){ + return; + } + + len -= 2; + + /* warning: don't use increment (++) in ntohs() macros!! */ + s = (ushort *)pkt; + proto = *s++; + pkt = (uchar *)s; + + switch(ntohs(proto)){ + case TFTP_RRQ: + case TFTP_WRQ: + case TFTP_ACK: + break; + + default: + break; + + case TFTP_OACK: + #ifdef ET_DEBUG + printf("Got OACK: %s %s\n", pkt, pkt+strlen(pkt)+1); + #endif + TftpState = STATE_OACK; + TftpServerPort = src; + TftpSend(); /* Send ACK */ + break; + + // TFTP DATA PACKET + case TFTP_DATA: + if(len < 2){ + return; + } + + len -= 2; + TftpBlock = ntohs(*(ushort *)pkt); + + /* + * RFC1350 specifies that the first data packet will + * have sequence number 1. If we receive a sequence + * number of 0 this means that there was a wrap + * around of the (16 bit) counter. + */ + if(TftpBlock == 0){ + TftpBlockWrap++; + TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE; + printf("\n %lu MB received\n ", TftpBlockWrapOffset>>20); + } else { + if(((TftpBlock - 1) % 10) == 0){ + putc('#'); + } else if((TftpBlock % (10 * HASHES_PER_LINE)) == 0){ + puts("\n "); + } + } + + #ifdef ET_DEBUG + if(TftpState == STATE_RRQ){ + puts("## Error: server did not acknowledge timeout option!\n"); + } + #endif + + if(TftpState == STATE_RRQ || TftpState == STATE_OACK){ + /* first block received */ + TftpState = STATE_DATA; + TftpServerPort = src; + TftpLastBlock = 0; + TftpBlockWrap = 0; + TftpBlockWrapOffset = 0; + + if(TftpBlock != 1){ /* Assertion */ + printf("\n## Error: first block is not block 1 (%ld), starting again!\n\n", TftpBlock); + NetStartAgain(); + break; + } + } + + if(TftpBlock == TftpLastBlock){ + /* + * Same block again; ignore it. + */ + break; + } + + TftpLastBlock = TftpBlock; + NetSetTimeout(TIMEOUT * CFG_HZ, TftpTimeout); + + store_block(TftpBlock - 1, pkt + 2, len); + + /* + * Acknoledge the block just received, which will prompt + * the server for the next one. + */ + TftpSend(); + + if(len < TFTP_BLOCK_SIZE){ + /* + * We received the whole thing. Try to + * run it. + */ + puts("\n\nTFTP transfer complete!\n"); + NetState = NETLOOP_SUCCESS; + } + + break; + + case TFTP_ERROR: + printf("\n## Error: '%s' (%d), starting again!\n\n", pkt + 2, ntohs(*(ushort *)pkt)); + NetStartAgain(); + break; + } +} + +static void TftpTimeout(void){ + if(++TftpTimeoutCount > TIMEOUT_COUNT){ + puts("\n\n## Error: retry count exceeded, starting again!\n\n"); + NetStartAgain(); + } else { + puts("T "); + NetSetTimeout(TIMEOUT * CFG_HZ, TftpTimeout); + TftpSend(); + } +} + +void TftpStart(void){ +#ifdef CONFIG_TFTP_PORT + char *ep; /* Environment pointer */ +#endif + + if(BootFile[0] == '\0'){ + sprintf(default_filename, "%02lX%02lX%02lX%02lX.img", NetOurIP & 0xFF, (NetOurIP >> 8) & 0xFF, (NetOurIP >> 16) & 0xFF, (NetOurIP >> 24) & 0xFF); + tftp_filename = default_filename; + + printf("** Warning: no boot file name, using: '%s'\n", tftp_filename); + } else { + tftp_filename = BootFile; + } + + puts("\nTFTP from IP: "); + print_IPaddr(NetServerIP); + + puts("\n Our IP: "); + print_IPaddr(NetOurIP); + + /* Check if we need to send across this subnet */ + if(NetOurGatewayIP && NetOurSubnetMask){ + IPaddr_t OurNet = NetOurIP & NetOurSubnetMask; + IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask; + + if(OurNet != ServerNet){ + puts("\n Gateway IP: "); + print_IPaddr(NetOurGatewayIP) ; + } + } + + printf("\n Filename: '%s'", tftp_filename); + + if(NetBootFileSize){ + printf("\n Size: 0x%x Bytes = ", NetBootFileSize<<9); + print_size(NetBootFileSize<<9, ""); + } + + printf("\nLoad address: 0x%lx", load_addr); + +#if defined(CONFIG_NET_MULTI) + printf("\n Using: %s", eth_get_name()); +#endif + + puts("\n\n Loading: *\b"); + + NetSetTimeout(TIMEOUT * CFG_HZ, TftpTimeout); + NetSetHandler(TftpHandler); + + TftpServerPort = WELL_KNOWN_PORT; + TftpTimeoutCount = 0; + TftpState = STATE_RRQ; + + /* Use a pseudo-random port unless a specific port is set */ + TftpOurPort = 1024 + (get_timer(0) % 3072); + +#ifdef CONFIG_TFTP_PORT + if((ep = getenv("tftpdstp")) != NULL){ + TftpServerPort = simple_strtol(ep, NULL, 10); + } + if((ep = getenv("tftpsrcp")) != NULL){ + TftpOurPort= simple_strtol(ep, NULL, 10); + } +#endif + + TftpBlock = 0; + + /* zero out server ether in case the server ip has changed */ + memset(NetServerEther, 0, 6); + + TftpSend(); +} + +#endif /* CFG_CMD_NET */ diff --git a/u-boot/net/tftp.h b/u-boot/net/tftp.h new file mode 100755 index 0000000..42678f7 --- /dev/null +++ b/u-boot/net/tftp.h @@ -0,0 +1,21 @@ +/* + * LiMon - BOOTP/TFTP. + * + * Copyright 1994, 1995, 2000 Neil Russell. + * (See License) + */ + +#ifndef __TFTP_H__ +#define __TFTP_H__ + +/**********************************************************************/ +/* + * Global functions and variables. + */ + +/* tftp.c */ +extern void TftpStart(void); /* Begin TFTP get */ + +/**********************************************************************/ + +#endif /* __TFTP_H__ */ diff --git a/u-boot/rtc/Makefile b/u-boot/rtc/Makefile new file mode 100755 index 0000000..883435b --- /dev/null +++ b/u-boot/rtc/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +#CFLAGS += -DDEBUG + +LIB = librtc.a + +OBJS = date.o + +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/rtc/date.c b/u-boot/rtc/date.c new file mode 100755 index 0000000..bc94742 --- /dev/null +++ b/u-boot/rtc/date.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for Philips PCF8563 RTC + */ + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) +#define FEBRUARY 2 +#define STARTOFTIME 1970 +#define SECDAY 86400L +#define SECYR (SECDAY * 365) +#define leapyear(year) ((year) % 4 == 0) +#define days_in_year(a) (leapyear(a) ? 366 : 365) +#define days_in_month(a) (month_days[(a) - 1]) + +static int month_days[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + +/* + * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) + */ +void GregorianDay(struct rtc_time * tm) { + int leapsToDate; + int lastYear; + int day; + int MonthOffset[] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 }; + + lastYear = tm->tm_year - 1; + + /* + * Number of leap corrections to apply up to end of last year + */ + leapsToDate = lastYear / 4 - lastYear / 100 + lastYear / 400; + + /* + * This year is a leap year if it is divisible by 4 except when it is + * divisible by 100 unless it is divisible by 400 + * + * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 will be + */ + if ((tm->tm_year % 4 == 0) && ((tm->tm_year % 100 != 0) || (tm->tm_year % 400 == 0)) && (tm->tm_mon > 2)) { + /* + * We are past Feb. 29 in a leap year + */ + day = 1; + } else { + day = 0; + } + + day += lastYear * 365 + leapsToDate + MonthOffset[tm->tm_mon - 1] + tm->tm_mday; + tm->tm_wday = day % 7; +} + +void to_tm(int tim, struct rtc_time * tm) { + register int i; + register long hms, day; + + day = tim / SECDAY; + hms = tim % SECDAY; + + /* Hours, minutes, seconds are easy */ + tm->tm_hour = hms / 3600; + tm->tm_min = (hms % 3600) / 60; + tm->tm_sec = (hms % 3600) % 60; + + /* Number of years in days */ + for (i = STARTOFTIME; day >= days_in_year(i); i++) { + day -= days_in_year(i); + } + tm->tm_year = i; + + /* Number of months in days left */ + if (leapyear(tm->tm_year)) { + days_in_month(FEBRUARY) = 29; + } + + for (i = 1; day >= days_in_month(i); i++) { + day -= days_in_month(i); + } + days_in_month(FEBRUARY) = 28; + tm->tm_mon = i; + + /* Days are what is left over (+1) from all that. */ + tm->tm_mday = day + 1; + + /* + * Determine the day of week + */ + GregorianDay(tm); +} + +/* Converts Gregorian date to seconds since 1970-01-01 00:00:00. + * Assumes input in normal date format, i.e. 1980-12-31 23:59:59 + * => year=1980, mon=12, day=31, hour=23, min=59, sec=59. + * + * [For the Julian calendar (which was used in Russia before 1917, + * Britain & colonies before 1752, anywhere else before 1582, + * and is still in use by some communities) leave out the + * -year/100+year/400 terms, and add 10.] + * + * This algorithm was first published by Gauss (I think). + * + * WARNING: this function will overflow on 2106-02-07 06:28:16 on + * machines were long is 32-bit! (However, as time_t is signed, we + * will already get problems at other places on 2038-01-19 03:14:08) + */ +unsigned long mktime(unsigned int year, unsigned int mon, unsigned int day, unsigned int hour, unsigned int min, unsigned int sec) { + if (0 >= (int) (mon -= 2)) { /* 1..12 -> 11,12,1..10 */ + mon += 12; /* Puts Feb last since it has leap day */ + year -= 1; + } + + return ((((unsigned long) (year / 4 - year / 100 + year / 400 + 367 * mon / 12 + day) + year * 365 - 719499) * 24 + hour /* now have hours */ + ) * 60 + min /* now have minutes */ + ) * 60 + sec; /* finally seconds */ +} + +#endif /* CFG_CMD_DATE */ diff --git a/u-boot/tools/Makefile b/u-boot/tools/Makefile new file mode 100755 index 0000000..150a130 --- /dev/null +++ b/u-boot/tools/Makefile @@ -0,0 +1,151 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +BINS = mkimage$(SFX) envcrc$(SFX) +OBJS = environment.o mkimage.o crc32.o envcrc.o + +#------------------------------------------------------------------------- + +HOSTARCH := $(shell uname -m | \ + sed -e s/i.86/i386/ \ + -e s/sun4u/sparc64/ \ + -e s/arm.*/arm/ \ + -e s/sa110/arm/ \ + -e s/powerpc/ppc/ \ + -e s/Power\ Macintosh/ppc/ \ + -e s/macppc/ppc/) + +HOSTOS := $(shell uname -s | tr A-Z a-z | \ + sed -e 's/\(cygwin\).*/cygwin/') + +TOOLSUBDIRS = + +# +# Mac OS X / Darwin's C preprocessor is Apple specific. It +# generates numerous errors and warnings. We want to bypass it +# and use GNU C's cpp. To do this we pass the -traditional-cpp +# option to the compiler. Note that the -traditional-cpp flag +# DOES NOT have the same semantics as GNU C's flag, all it does +# is invoke the GNU preprocessor in stock ANSI/ISO C fashion. +# +# Apple's linker is similar, thanks to the new 2 stage linking +# multiple symbol definitions are treated as errors, hence the +# -multiply_defined suppress option to turn off this error. +# +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +HOST_CFLAGS = -traditional-cpp -Wall +HOST_LDFLAGS =-multiply_defined suppress +HOST_ENVIRO_CFLAGS = -traditional-cpp + +else +ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc) +HOST_CFLAGS = -Wall -pedantic +HOST_LDFLAGS = +HOST_ENVIRO_CFLAGS = + +# +# Everyone else +# +else +HOST_CFLAGS = -Wall -pedantic +HOST_LDFLAGS = +HOST_ENVIRO_CFLAGS = +endif +endif + +# +# Cygwin needs .exe files :-( +# +ifeq ($(HOSTOS),cygwin) +SFX = .exe +else +SFX = +endif + +# +# Include this after HOSTOS HOSTARCH check +# so that we can act intelligently. +# +include $(TOPDIR)/config.mk + +# +# Use native tools and options +# +CPPFLAGS = -idirafter ../include -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC +CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O2 +AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS) +CC = $(HOSTCC) +STRIP = $(HOSTSTRIP) +MAKEDEPEND = makedepend + +all: .depend $(BINS) subdirs + +envcrc$(SFX): envcrc.o crc32.o environment.o + $(CC) $(CFLAGS) -o $@ $^ + +mkimage$(SFX): mkimage.o crc32.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + +envcrc.o: envcrc.c + $(CC) -g $(CFLAGS) -c $< + +crc32.o: crc32.c + $(CC) -g $(CFLAGS) -c $< + +mkimage.o: mkimage.c + $(CC) -g $(CFLAGS) -c $< + +subdirs: +ifeq ($(TOOLSUBDIRS),) + @: +else + @for dir in $(TOOLSUBDIRS) ; do \ + $(MAKE) \ + HOSTOS=$(HOSTOS) \ + HOSTARCH=$(HOSTARCH) \ + HOST_CFLAGS="$(HOST_CFLAGS)" \ + HOST_LDFLAGS="$(HOST_LDFLAGS)" \ + -C $$dir || exit 1 ; \ + done +endif + +environment.c: + @rm -f environment.c + ln -s ../common/environment.c environment.c + +environment.o: environment.c + $(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c $< + +crc32.c: + @rm -f crc32.c + ln -s ../lib_generic/crc32.c crc32.c + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/tools/envcrc.c b/u-boot/tools/envcrc.c new file mode 100755 index 0000000..7b77183 --- /dev/null +++ b/u-boot/tools/envcrc.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2001 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ /* Dirty trick to get only #defines */ +#endif +#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */ +#include +#undef __ASSEMBLY__ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_OFFSET +# define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +# endif +# if !defined(CFG_ENV_ADDR_REDUND) && defined(CFG_ENV_OFFSET_REDUND) +# define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + CFG_ENV_OFFSET_REDUND) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# if defined(CFG_ENV_ADDR_REDUND) && !defined(CFG_ENV_SIZE_REDUND) +# define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE +# endif +# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \ + ((CFG_ENV_ADDR + CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) +# define ENV_IS_EMBEDDED 1 +# endif +# if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND) +# define CFG_REDUNDAND_ENVIRONMENT 1 +# endif +#endif /* CFG_ENV_IS_IN_FLASH */ + +#ifdef CFG_REDUNDAND_ENVIRONMENT +# define ENV_HEADER_SIZE (sizeof(unsigned long) + 1) +#else +# define ENV_HEADER_SIZE (sizeof(unsigned long)) +#endif + +#define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE) + + +extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); + +#ifdef ENV_IS_EMBEDDED +extern unsigned int env_size; +extern unsigned char environment; +#endif /* ENV_IS_EMBEDDED */ + +int main (int argc, char **argv) +{ +#ifdef ENV_IS_EMBEDDED + int crc; + unsigned char *envptr = &environment, + *dataptr = envptr + ENV_HEADER_SIZE; + unsigned int datasize = ENV_SIZE; + + crc = crc32 (0, dataptr, datasize); + + /* Check if verbose mode is activated passing a parameter to the program */ + if (argc > 1) { + printf ("CRC32 from offset %08X to %08X of environment = %08X\n", + (unsigned int) (dataptr - envptr), + (unsigned int) (dataptr - envptr) + datasize, + crc); + } else { + printf ("0x%08X\n", crc); + } +#else + printf ("0\n"); +#endif + return EXIT_SUCCESS; +} diff --git a/u-boot/tools/mkimage.c b/u-boot/tools/mkimage.c new file mode 100755 index 0000000..9d15a50 --- /dev/null +++ b/u-boot/tools/mkimage.c @@ -0,0 +1,747 @@ +/* + * (C) Copyright 2000-2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#ifndef __WIN32__ +#include /* for host / network byte order conversions */ +#endif +#include +#include +#include +#include + +#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__) +#include +#endif + +#ifdef __WIN32__ +typedef unsigned int __u32; + +#define SWAP_LONG(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; + +#define ntohl(a) SWAP_LONG(a) +#define htonl(a) SWAP_LONG(a) +#endif /* __WIN32__ */ + +#ifndef O_BINARY /* should be define'd on __WIN32__ */ +#define O_BINARY 0 +#endif + +#include + +extern int errno; + +#ifndef MAP_FAILED +#define MAP_FAILED (-1) +#endif + +char *cmdname; + +extern unsigned long crc32 (unsigned long crc, const char *buf, unsigned int len); + +typedef struct table_entry { + int val; /* as defined in image.h */ + char *sname; /* short (input) name */ + char *lname; /* long (output) name */ +} table_entry_t; + +table_entry_t arch_name[] = { + { IH_CPU_INVALID, NULL, "Invalid CPU", }, + { IH_CPU_ALPHA, "alpha", "Alpha", }, + { IH_CPU_ARM, "arm", "ARM", }, + { IH_CPU_I386, "x86", "Intel x86", }, + { IH_CPU_IA64, "ia64", "IA64", }, + { IH_CPU_M68K, "m68k", "MC68000", }, + { IH_CPU_MICROBLAZE, "microblaze", "MicroBlaze", }, + { IH_CPU_MIPS, "mips", "MIPS", }, + { IH_CPU_MIPS64, "mips64", "MIPS 64 Bit", }, + { IH_CPU_NIOS, "nios", "NIOS", }, + { IH_CPU_NIOS2, "nios2", "NIOS II", }, + { IH_CPU_PPC, "ppc", "PowerPC", }, + { IH_CPU_S390, "s390", "IBM S390", }, + { IH_CPU_SH, "sh", "SuperH", }, + { IH_CPU_SPARC, "sparc", "SPARC", }, + { IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", }, + { IH_CPU_BLACKFIN, "blackfin", "Blackfin", }, + { -1, "", "", }, +}; + +table_entry_t os_name[] = { + { IH_OS_INVALID, NULL, "Invalid OS", }, + { IH_OS_4_4BSD, "4_4bsd", "4_4BSD", }, + { IH_OS_ARTOS, "artos", "ARTOS", }, + { IH_OS_DELL, "dell", "Dell", }, + { IH_OS_ESIX, "esix", "Esix", }, + { IH_OS_FREEBSD, "freebsd", "FreeBSD", }, + { IH_OS_IRIX, "irix", "Irix", }, + { IH_OS_LINUX, "linux", "Linux", }, + { IH_OS_LYNXOS, "lynxos", "LynxOS", }, + { IH_OS_NCR, "ncr", "NCR", }, + { IH_OS_NETBSD, "netbsd", "NetBSD", }, + { IH_OS_OPENBSD, "openbsd", "OpenBSD", }, + { IH_OS_PSOS, "psos", "pSOS", }, + { IH_OS_QNX, "qnx", "QNX", }, + { IH_OS_RTEMS, "rtems", "RTEMS", }, + { IH_OS_SCO, "sco", "SCO", }, + { IH_OS_SOLARIS, "solaris", "Solaris", }, + { IH_OS_SVR4, "svr4", "SVR4", }, + { IH_OS_U_BOOT, "u-boot", "U-Boot", }, + { IH_OS_VXWORKS, "vxworks", "VxWorks", }, + { -1, "", "", }, +}; + +table_entry_t type_name[] = { + { IH_TYPE_INVALID, NULL, "Invalid Image", }, + { IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image", }, + { IH_TYPE_FIRMWARE, "firmware", "Firmware", }, + { IH_TYPE_KERNEL, "kernel", "Kernel Image", }, + { IH_TYPE_MULTI, "multi", "Multi-File Image", }, + { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, + { IH_TYPE_SCRIPT, "script", "Script", }, + { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, + { -1, "", "", }, +}; + +table_entry_t comp_name[] = { + { IH_COMP_NONE, "none", "uncompressed", }, + { IH_COMP_BZIP2, "bzip2", "bzip2 compressed", }, + { IH_COMP_GZIP, "gzip", "gzip compressed", }, + { IH_COMP_LZMA, "lzma", "lzma compressed", }, + { -1, "", "", }, +}; + +static void copy_file (int, const char *, int); +static void usage (void); +static void print_header (image_header_t *); +static void print_type (image_header_t *); +static char *put_table_entry (table_entry_t *, char *, int); +static char *put_arch (int); +static char *put_type (int); +static char *put_os (int); +static char *put_comp (int); +static int get_table_entry (table_entry_t *, char *, char *); +static int get_arch(char *); +static int get_comp(char *); +static int get_os (char *); +static int get_type(char *); + + +char *datafile; +char *imagefile; + +int dflag = 0; +int eflag = 0; +int lflag = 0; +int vflag = 0; +int xflag = 0; +int opt_os = IH_OS_LINUX; +int opt_arch = IH_CPU_PPC; +int opt_type = IH_TYPE_KERNEL; +int opt_comp = IH_COMP_GZIP; + +image_header_t header; +image_header_t *hdr = &header; + +int +main (int argc, char **argv) +{ + int ifd; + uint32_t checksum; + uint32_t addr; + uint32_t ep; + struct stat sbuf; + unsigned char *ptr; + char *name = ""; + + cmdname = *argv; + + addr = ep = 0; + + while (--argc > 0 && **++argv == '-') { + while (*++*argv) { + switch (**argv) { + case 'l': + lflag = 1; + break; + case 'A': + if ((--argc <= 0) || + (opt_arch = get_arch(*++argv)) < 0) + usage (); + goto NXTARG; + case 'C': + if ((--argc <= 0) || + (opt_comp = get_comp(*++argv)) < 0) + usage (); + goto NXTARG; + case 'O': + if ((--argc <= 0) || + (opt_os = get_os(*++argv)) < 0) + usage (); + goto NXTARG; + case 'T': + if ((--argc <= 0) || + (opt_type = get_type(*++argv)) < 0) + usage (); + goto NXTARG; + + case 'a': + if (--argc <= 0) + usage (); + addr = strtoul (*++argv, (char **)&ptr, 16); + if (*ptr) { + fprintf (stderr, + "%s: invalid load address %s\n", + cmdname, *argv); + exit (EXIT_FAILURE); + } + goto NXTARG; + case 'd': + if (--argc <= 0) + usage (); + datafile = *++argv; + dflag = 1; + goto NXTARG; + case 'e': + if (--argc <= 0) + usage (); + ep = strtoul (*++argv, (char **)&ptr, 16); + if (*ptr) { + fprintf (stderr, + "%s: invalid entry point %s\n", + cmdname, *argv); + exit (EXIT_FAILURE); + } + eflag = 1; + goto NXTARG; + case 'n': + if (--argc <= 0) + usage (); + name = *++argv; + goto NXTARG; + case 'v': + vflag++; + break; + case 'x': + xflag++; + break; + default: + usage (); + } + } +NXTARG: ; + } + + if ((argc != 1) || ((lflag ^ dflag) == 0)) + usage(); + + if (!eflag) { + ep = addr; + /* If XIP, entry point must be after the U-Boot header */ + if (xflag) + ep += sizeof(image_header_t); + } + + /* + * If XIP, ensure the entry point is equal to the load address plus + * the size of the U-Boot header. + */ + if (xflag) { + if (ep != addr + sizeof(image_header_t)) { + fprintf (stderr, "%s: For XIP, the entry point must be the load addr + %lu\n", + cmdname, + (unsigned long)sizeof(image_header_t)); + exit (EXIT_FAILURE); + } + } + + imagefile = *argv; + + if (lflag) { + ifd = open(imagefile, O_RDONLY|O_BINARY); + } else { + ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666); + } + + if (ifd < 0) { + fprintf (stderr, "%s: Can't open %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (lflag) { + int len; + char *data; + /* + * list header information of existing image + */ + if (fstat(ifd, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if ((unsigned)sbuf.st_size < sizeof(image_header_t)) { + fprintf (stderr, + "%s: Bad size: \"%s\" is no valid image\n", + cmdname, imagefile); + exit (EXIT_FAILURE); + } + + ptr = (unsigned char *)mmap(0, sbuf.st_size, + PROT_READ, MAP_SHARED, ifd, 0); + if ((caddr_t)ptr == (caddr_t)-1) { + fprintf (stderr, "%s: Can't read %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + /* + * create copy of header so that we can blank out the + * checksum field for checking - this can't be done + * on the PROT_READ mapped data. + */ + memcpy (hdr, ptr, sizeof(image_header_t)); + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + fprintf (stderr, + "%s: Bad Magic Number: \"%s\" is no valid image\n", + cmdname, imagefile); + exit (EXIT_FAILURE); + } + + data = (char *)hdr; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = htonl(0); /* clear for re-calculation */ + + if (crc32 (0, data, len) != checksum) { + fprintf (stderr, + "*** Warning: \"%s\" has bad header checksum!\n", + imagefile); + } + + data = (char *)(ptr + sizeof(image_header_t)); + len = sbuf.st_size - sizeof(image_header_t) ; + + if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) { + fprintf (stderr, + "*** Warning: \"%s\" has corrupted data!\n", + imagefile); + } + + /* for multi-file images we need the data part, too */ + print_header ((image_header_t *)ptr); + + (void) munmap((void *)ptr, sbuf.st_size); + (void) close (ifd); + + exit (EXIT_SUCCESS); + } + + /* + * Must be -w then: + * + * write dummy header, to be fixed later + */ + memset (hdr, 0, sizeof(image_header_t)); + + if (write(ifd, hdr, sizeof(image_header_t)) != sizeof(image_header_t)) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (opt_type == IH_TYPE_MULTI || opt_type == IH_TYPE_SCRIPT) { + char *file = datafile; + uint32_t size; + + for (;;) { + char *sep = NULL; + + if (file) { + if ((sep = strchr(file, ':')) != NULL) { + *sep = '\0'; + } + + if (stat (file, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, file, strerror(errno)); + exit (EXIT_FAILURE); + } + size = htonl(sbuf.st_size); + } else { + size = 0; + } + + if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (!file) { + break; + } + + if (sep) { + *sep = ':'; + file = sep + 1; + } else { + file = NULL; + } + } + + file = datafile; + + for (;;) { + char *sep = strchr(file, ':'); + if (sep) { + *sep = '\0'; + copy_file (ifd, file, 1); + *sep++ = ':'; + file = sep; + } else { + copy_file (ifd, file, 0); + break; + } + } + } else { + copy_file (ifd, datafile, 0); + } + + /* We're a bit of paranoid */ +#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) + (void) fdatasync (ifd); +#else + (void) fsync (ifd); +#endif + + if (fstat(ifd, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + ptr = (unsigned char *)mmap(0, sbuf.st_size, + PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0); + if (ptr == (unsigned char *)MAP_FAILED) { + fprintf (stderr, "%s: Can't map %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + hdr = (image_header_t *)ptr; + + checksum = crc32 (0, + (const char *)(ptr + sizeof(image_header_t)), + sbuf.st_size - sizeof(image_header_t) + ); + + /* Build new header */ + hdr->ih_magic = htonl(IH_MAGIC); + hdr->ih_time = htonl(sbuf.st_mtime); + hdr->ih_size = htonl(sbuf.st_size - sizeof(image_header_t)); + hdr->ih_load = htonl(addr); + hdr->ih_ep = htonl(ep); + hdr->ih_dcrc = htonl(checksum); + hdr->ih_os = opt_os; + hdr->ih_arch = opt_arch; + hdr->ih_type = opt_type; + hdr->ih_comp = opt_comp; + + strncpy((char *)hdr->ih_name, name, IH_NMLEN); + + checksum = crc32(0,(const char *)hdr,sizeof(image_header_t)); + + hdr->ih_hcrc = htonl(checksum); + + print_header (hdr); + + (void) munmap((void *)ptr, sbuf.st_size); + + /* We're a bit of paranoid */ +#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) + (void) fdatasync (ifd); +#else + (void) fsync (ifd); +#endif + + if (close(ifd)) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + exit (EXIT_SUCCESS); +} + +static void +copy_file (int ifd, const char *datafile, int pad) +{ + int dfd; + struct stat sbuf; + unsigned char *ptr; + int tail; + int zero = 0; + int offset = 0; + int size; + + if (vflag) { + fprintf (stderr, "Adding Image %s\n", datafile); + } + + if ((dfd = open(datafile, O_RDONLY|O_BINARY)) < 0) { + fprintf (stderr, "%s: Can't open %s: %s\n", + cmdname, datafile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (fstat(dfd, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, datafile, strerror(errno)); + exit (EXIT_FAILURE); + } + + ptr = (unsigned char *)mmap(0, sbuf.st_size, + PROT_READ, MAP_SHARED, dfd, 0); + if (ptr == (unsigned char *)MAP_FAILED) { + fprintf (stderr, "%s: Can't read %s: %s\n", + cmdname, datafile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (xflag) { + unsigned char *p = NULL; + /* + * XIP: do not append the image_header_t at the + * beginning of the file, but consume the space + * reserved for it. + */ + + if ((unsigned)sbuf.st_size < sizeof(image_header_t)) { + fprintf (stderr, + "%s: Bad size: \"%s\" is too small for XIP\n", + cmdname, datafile); + exit (EXIT_FAILURE); + } + + for (p=ptr; p < ptr+sizeof(image_header_t); p++) { + if ( *p != 0xff ) { + fprintf (stderr, + "%s: Bad file: \"%s\" has invalid buffer for XIP\n", + cmdname, datafile); + exit (EXIT_FAILURE); + } + } + + offset = sizeof(image_header_t); + } + + size = sbuf.st_size - offset; + if (write(ifd, ptr + offset, size) != size) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + if (pad && ((tail = size % 4) != 0)) { + + if (write(ifd, (char *)&zero, 4-tail) != 4-tail) { + fprintf (stderr, "%s: Write error on %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + } + + (void) munmap((void *)ptr, sbuf.st_size); + (void) close (dfd); +} + +void +usage () +{ + fprintf (stderr, "Usage: %s -l image\n" + " -l ==> list image header information\n" + " %s [-x] -A arch -O os -T type -C comp " + "-a addr -e ep -n name -d data_file[:data_file...] image\n", + cmdname, cmdname); + fprintf (stderr, " -A ==> set architecture to 'arch'\n" + " -O ==> set operating system to 'os'\n" + " -T ==> set image type to 'type'\n" + " -C ==> set compression type 'comp'\n" + " -a ==> set load address to 'addr' (hex)\n" + " -e ==> set entry point to 'ep' (hex)\n" + " -n ==> set image name to 'name'\n" + " -d ==> use image data from 'datafile'\n" + " -x ==> set XIP (execute in place)\n" + ); + exit (EXIT_FAILURE); +} + +static void +print_header (image_header_t *hdr) +{ + time_t timestamp; + uint32_t size; + + timestamp = (time_t)ntohl(hdr->ih_time); + size = ntohl(hdr->ih_size); + + printf ("Image Name: %.*s\n", IH_NMLEN, hdr->ih_name); + printf ("Created: %s", ctime(×tamp)); + printf ("Image Type: "); print_type(hdr); + printf ("Data Size: %d Bytes = %.2f kB = %.2f MB\n", + size, (double)size / 1.024e3, (double)size / 1.048576e6 ); + printf ("Load Address: 0x%08X\n", ntohl(hdr->ih_load)); + printf ("Entry Point: 0x%08X\n", ntohl(hdr->ih_ep)); + + if (hdr->ih_type == IH_TYPE_MULTI || hdr->ih_type == IH_TYPE_SCRIPT) { + int i, ptrs; + uint32_t pos; + unsigned long *len_ptr = (unsigned long *) ( + (unsigned long)hdr + sizeof(image_header_t) + ); + + /* determine number of images first (to calculate image offsets) */ + for (i=0; len_ptr[i]; ++i) /* null pointer terminates list */ + ; + ptrs = i; /* null pointer terminates list */ + + pos = sizeof(image_header_t) + ptrs * sizeof(long); + printf ("Contents:\n"); + for (i=0; len_ptr[i]; ++i) { + size = ntohl(len_ptr[i]); + + printf (" Image %d: %8d Bytes = %4d kB = %d MB\n", + i, size, size>>10, size>>20); + if (hdr->ih_type == IH_TYPE_SCRIPT && i > 0) { + /* + * the user may need to know offsets + * if planning to do something with + * multiple files + */ + printf (" Offset = %08X\n", pos); + } + /* copy_file() will pad the first files to even word align */ + size += 3; + size &= ~3; + pos += size; + } + } +} + + +static void +print_type (image_header_t *hdr) +{ + printf ("%s %s %s (%s)\n", + put_arch (hdr->ih_arch), + put_os (hdr->ih_os ), + put_type (hdr->ih_type), + put_comp (hdr->ih_comp) + ); +} + +static char *put_arch (int arch) +{ + return (put_table_entry(arch_name, "Unknown Architecture", arch)); +} + +static char *put_os (int os) +{ + return (put_table_entry(os_name, "Unknown OS", os)); +} + +static char *put_type (int type) +{ + return (put_table_entry(type_name, "Unknown Image", type)); +} + +static char *put_comp (int comp) +{ + return (put_table_entry(comp_name, "Unknown Compression", comp)); +} + +static char *put_table_entry (table_entry_t *table, char *msg, int type) +{ + for (; table->val>=0; ++table) { + if (table->val == type) + return (table->lname); + } + return (msg); +} + +static int get_arch(char *name) +{ + return (get_table_entry(arch_name, "CPU", name)); +} + + +static int get_comp(char *name) +{ + return (get_table_entry(comp_name, "Compression", name)); +} + + +static int get_os (char *name) +{ + return (get_table_entry(os_name, "OS", name)); +} + + +static int get_type(char *name) +{ + return (get_table_entry(type_name, "Image", name)); +} + +static int get_table_entry (table_entry_t *table, char *msg, char *name) +{ + table_entry_t *t; + int first = 1; + + for (t=table; t->val>=0; ++t) { + if (t->sname && strcasecmp(t->sname, name)==0) + return (t->val); + } + fprintf (stderr, "\nInvalid %s Type - valid names are", msg); + for (t=table; t->val>=0; ++t) { + if (t->sname == NULL) + continue; + fprintf (stderr, "%c %s", (first) ? ':' : ',', t->sname); + first = 0; + } + fprintf (stderr, "\n"); + return (-1); +}