From: Kumar Gala <galak@kernel.crashing.org>
Date: Thu, 13 Jan 2011 07:54:01 +0000 (-0600)
Subject: powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)
X-Git-Tag: v2011.03-rc1~29^2~2
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=1d2c2a62e328db22c38e3dfb3c0a8a373333471b;p=oweals%2Fu-boot.git

powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)

CoreNet Platform Cache single-bit tag error scrubbing will cause tag
corruption.  Disable the feature to workaround the issue.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 4e2cb4a640..ae6af4f967 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -59,6 +59,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
 	puts("Work-around for Erratum ESDHC136 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
+	puts("Work-around for Erratum CPC-A002 enabled\n");
+#endif
+
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 354b222314..c822d871ae 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -142,6 +142,10 @@ static void enable_cpc(void)
 		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
 		size += CPC_CFG0_SZ_K(cpccfg0);
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
+		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
+#endif
+
 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 		/* Read back to sync write */
 		in_be32(&cpc->cpccsr0);
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 30c64ebb17..6b19ee8586 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1,7 +1,7 @@
 /*
  * MPC85xx Internal Memory Map
  *
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
@@ -1619,6 +1619,7 @@ typedef struct cpc_corenet {
 #define CPC_SRCR0_SRAMEN	0x00000001
 #define	CPC_ERRDIS_TMHITDIS  	0x00000080	/* multi-way hit disable */
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
+#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #endif /* CONFIG_SYS_FSL_CPC */
 
 /* Global Utilities Block */
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 4dd7faa1bb..950c8bcaf6 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -40,6 +40,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136
 
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
 
 #include "corenet_ds.h"