From: Piotr Dymacz <pepe2k@gmail.com>
Date: Tue, 29 Mar 2016 22:09:08 +0000 (+0200)
Subject: Fix mess with inline QC/A related functions
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=1522a406076be6652861bc534764c9d25035aa26;p=oweals%2Fu-boot_mod.git

Fix mess with inline QC/A related functions
---

diff --git a/u-boot/cpu/mips/ar7240/qca_common.c b/u-boot/cpu/mips/ar7240/qca_common.c
index 6c87659..483326c 100644
--- a/u-boot/cpu/mips/ar7240/qca_common.c
+++ b/u-boot/cpu/mips/ar7240/qca_common.c
@@ -14,7 +14,7 @@
 /*
  * Returns 1 if reference clock is 40 MHz
  */
-inline u32 qca_xtal_is_40mhz(void)
+u32 qca_xtal_is_40mhz(void)
 {
 	return ((qca_soc_reg_read(QCA_RST_BOOTSTRAP_REG) &
 			QCA_RST_BOOTSTRAP_REF_CLK_MASK) >> QCA_RST_BOOTSTRAP_REF_CLK_SHIFT);
diff --git a/u-boot/cpu/mips/ar7240/qca_dram.c b/u-boot/cpu/mips/ar7240/qca_dram.c
index 8b10802..ff938ad 100644
--- a/u-boot/cpu/mips/ar7240/qca_dram.c
+++ b/u-boot/cpu/mips/ar7240/qca_dram.c
@@ -123,7 +123,7 @@ u32 qca_dram_ddr_width(void)
 /*
  * Returns CAS latency, based on setting in DDR_CONFIG register
  */
-inline u32 qca_dram_cas_lat(void)
+u32 qca_dram_cas_lat(void)
 {
 #ifndef CONFIG_BOARD_DRAM_CAS_LATENCY
 	u32 reg;
@@ -144,7 +144,7 @@ inline u32 qca_dram_cas_lat(void)
 /*
  * Returns tRCD latency
  */
-inline u32 qca_dram_trcd_lat(void)
+u32 qca_dram_trcd_lat(void)
 {
 	u32 reg;
 
@@ -157,7 +157,7 @@ inline u32 qca_dram_trcd_lat(void)
 /*
  * Returns tRP latency
  */
-inline u32 qca_dram_trp_lat(void)
+u32 qca_dram_trp_lat(void)
 {
 	u32 reg;
 
@@ -170,7 +170,7 @@ inline u32 qca_dram_trp_lat(void)
 /*
  * Returns tRAS latency
  */
-inline u32 qca_dram_tras_lat(void)
+u32 qca_dram_tras_lat(void)
 {
 	u32 reg;
 
diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index 64290b0..c3164c2 100644
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -1618,23 +1618,23 @@
  * Functions
  */
 #ifndef __ASSEMBLY__
-inline u32 qca_xtal_is_40mhz(void);
-void   qca_soc_name_rev(char *buf);
-void   qca_full_chip_reset(void);
-void   qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
-void   qca_sf_bulk_erase(u32 bank);
-void   qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
-u32    qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
-u32    qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
-u32    qca_sf_jedec_id(u32 bank);
-u32    qca_dram_type(void);
-u32    qca_dram_size(void);
-u32    qca_dram_ddr_width(void);
-void   qca_dram_init(void);
-inline u32 qca_dram_cas_lat(void);
-inline u32 qca_dram_trcd_lat(void);
-inline u32 qca_dram_trp_lat(void);
-inline u32 qca_dram_tras_lat(void);
+u32  qca_dram_cas_lat(void);
+u32  qca_dram_ddr_width(void);
+void qca_dram_init(void);
+u32  qca_dram_size(void);
+u32  qca_dram_tras_lat(void);
+u32  qca_dram_trcd_lat(void);
+u32  qca_dram_trp_lat(void);
+u32  qca_dram_type(void);
+void qca_full_chip_reset(void);
+void qca_sf_bulk_erase(u32 bank);
+u32  qca_sf_jedec_id(u32 bank);
+u32  qca_sf_sect_erase(u32 bank, u32 address, u32 sect_size, u8 erase_cmd);
+u32  qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_cmd);
+void qca_sf_write_page(u32 bank, u32 address, u32 length, u8 *data);
+void qca_soc_name_rev(char *buf);
+void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk);
+u32  qca_xtal_is_40mhz(void);
 #endif /* !__ASSEMBLY__ */
 
 /*