From: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Date: Wed, 22 Jan 2020 15:01:45 +0000 (+0100)
Subject: x86: Move itss.h from Apollo Lake to the generic x86 include directory
X-Git-Tag: v2020.04-rc2~18^2~7
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=142c9751a6cb7e2f9d18847570bc01c5e991aeeb;p=oweals%2Fu-boot.git

x86: Move itss.h from Apollo Lake to the generic x86 include directory

The code in this file is not specific to Apollo Lake. According to
coreboot sources (where this code comes from), it is common to at least:
  * Apollo Lake
  * Cannon Lake
  * Ice Lake
  * Skylake

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

diff --git a/arch/x86/cpu/apollolake/itss.c b/arch/x86/cpu/apollolake/itss.c
index 95c9ebddc1..ff7a83d618 100644
--- a/arch/x86/cpu/apollolake/itss.c
+++ b/arch/x86/cpu/apollolake/itss.c
@@ -15,7 +15,7 @@
 #include <irq.h>
 #include <p2sb.h>
 #include <spl.h>
-#include <asm/arch/itss.h>
+#include <asm/itss.h>
 
 struct apl_itss_platdata {
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/arch/x86/include/asm/arch-apollolake/itss.h b/arch/x86/include/asm/arch-apollolake/itss.h
deleted file mode 100644
index c75d8fe8c2..0000000000
--- a/arch/x86/include/asm/arch-apollolake/itss.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Interrupt Timer Subsystem
- *
- * Copyright (C) 2017 Intel Corporation.
- * Copyright 2019 Google LLC
- *
- * Modified from coreboot itss.h
- */
-
-#ifndef _ASM_ARCH_ITSS_H
-#define _ASM_ARCH_ITSS_H
-
-#define GPIO_IRQ_START	50
-#define GPIO_IRQ_END	ITSS_MAX_IRQ
-
-#define ITSS_MAX_IRQ	119
-#define IRQS_PER_IPC	32
-#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC)
-
-/* Max PXRC registers in ITSS */
-#define MAX_PXRC_CONFIG	(PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
-
-/* PIRQA Routing Control Register */
-#define PCR_ITSS_PIRQA_ROUT	0x3100
-/* PIRQB Routing Control Register */
-#define PCR_ITSS_PIRQB_ROUT	0x3101
-/* PIRQC Routing Control Register */
-#define PCR_ITSS_PIRQC_ROUT	0x3102
-/* PIRQD Routing Control Register */
-#define PCR_ITSS_PIRQD_ROUT	0x3103
-/* PIRQE Routing Control Register */
-#define PCR_ITSS_PIRQE_ROUT	0x3104
-/* PIRQF Routing Control Register */
-#define PCR_ITSS_PIRQF_ROUT	0x3105
-/* PIRQG Routing Control Register */
-#define PCR_ITSS_PIRQG_ROUT	0x3106
-/* PIRQH Routing Control Register */
-#define PCR_ITSS_PIRQH_ROUT	0x3107
-/* ITSS Interrupt polarity control */
-#define PCR_ITSS_IPC0_CONF	0x3200
-/* ITSS Power reduction control */
-#define PCR_ITSS_ITSSPRC	0x3300
-
-#endif /* _ASM_ARCH_ITSS_H */
diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h
new file mode 100644
index 0000000000..c75d8fe8c2
--- /dev/null
+++ b/arch/x86/include/asm/itss.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Interrupt Timer Subsystem
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot itss.h
+ */
+
+#ifndef _ASM_ARCH_ITSS_H
+#define _ASM_ARCH_ITSS_H
+
+#define GPIO_IRQ_START	50
+#define GPIO_IRQ_END	ITSS_MAX_IRQ
+
+#define ITSS_MAX_IRQ	119
+#define IRQS_PER_IPC	32
+#define NUM_IPC_REGS	((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC)
+
+/* Max PXRC registers in ITSS */
+#define MAX_PXRC_CONFIG	(PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
+
+/* PIRQA Routing Control Register */
+#define PCR_ITSS_PIRQA_ROUT	0x3100
+/* PIRQB Routing Control Register */
+#define PCR_ITSS_PIRQB_ROUT	0x3101
+/* PIRQC Routing Control Register */
+#define PCR_ITSS_PIRQC_ROUT	0x3102
+/* PIRQD Routing Control Register */
+#define PCR_ITSS_PIRQD_ROUT	0x3103
+/* PIRQE Routing Control Register */
+#define PCR_ITSS_PIRQE_ROUT	0x3104
+/* PIRQF Routing Control Register */
+#define PCR_ITSS_PIRQF_ROUT	0x3105
+/* PIRQG Routing Control Register */
+#define PCR_ITSS_PIRQG_ROUT	0x3106
+/* PIRQH Routing Control Register */
+#define PCR_ITSS_PIRQH_ROUT	0x3107
+/* ITSS Interrupt polarity control */
+#define PCR_ITSS_IPC0_CONF	0x3200
+/* ITSS Power reduction control */
+#define PCR_ITSS_ITSSPRC	0x3300
+
+#endif /* _ASM_ARCH_ITSS_H */
diff --git a/drivers/pinctrl/intel/pinctrl.c b/drivers/pinctrl/intel/pinctrl.c
index 4875a3b0b5..5bf5d8b0e2 100644
--- a/drivers/pinctrl/intel/pinctrl.c
+++ b/drivers/pinctrl/intel/pinctrl.c
@@ -25,7 +25,7 @@
 #include <asm/intel_pinctrl.h>
 #include <asm/intel_pinctrl_defs.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/itss.h>
+#include <asm/itss.h>
 #include <dm/device-internal.h>
 #include <dt-bindings/gpio/gpio.h>