From: Bin Meng <bmeng.cn@gmail.com>
Date: Fri, 21 Apr 2017 14:24:31 +0000 (-0700)
Subject: x86: fsp: acpi: Pass different boot mode to FSP init
X-Git-Tag: v2017.07-rc1~254^2~25
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=1206723b6e597f1aa946b800fc59059db91908bc;p=oweals%2Fu-boot.git

x86: fsp: acpi: Pass different boot mode to FSP init

When ACPI S3 resume is turned on, we should pass different boot mode
to FSP init instead of default BOOT_FULL_CONFIG.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
---

diff --git a/arch/x86/include/asm/acpi_s3.h b/arch/x86/include/asm/acpi_s3.h
index 78c53ea2fb..ec052112f3 100644
--- a/arch/x86/include/asm/acpi_s3.h
+++ b/arch/x86/include/asm/acpi_s3.h
@@ -61,4 +61,22 @@ static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt)
 	return -EINVAL;
 }
 
+/**
+ * chipset_prev_sleep_state() - Get chipset previous sleep state
+ *
+ * This returns chipset previous sleep state from ACPI registers.
+ * Platform codes must supply this routine in order to support ACPI S3.
+ *
+ * @return ACPI_S0/S1/S2/S3/S4/S5.
+ */
+enum acpi_sleep_state chipset_prev_sleep_state(void);
+
+/**
+ * chipset_clear_sleep_state() - Clear chipset sleep state
+ *
+ * This clears chipset sleep state in ACPI registers.
+ * Platform codes must supply this routine in order to support ACPI S3.
+ */
+void chipset_clear_sleep_state(void);
+
 #endif /* __ASM_ACPI_S3_H__ */
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index 66a388d601..cc42cad20b 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <errno.h>
+#include <asm/acpi_s3.h>
 #include <asm/io.h>
 #include <asm/mrccache.h>
 #include <asm/post.h>
@@ -78,6 +79,10 @@ static __maybe_unused void *fsp_prepare_mrc_cache(void)
 int arch_fsp_init(void)
 {
 	void *nvs;
+	int boot_mode = BOOT_FULL_CONFIG;
+#ifdef CONFIG_HAVE_ACPI_RESUME
+	int prev_sleep_state = chipset_prev_sleep_state();
+#endif
 
 	if (!gd->arch.hob_list) {
 #ifdef CONFIG_ENABLE_MRC_CACHE
@@ -85,12 +90,31 @@ int arch_fsp_init(void)
 #else
 		nvs = NULL;
 #endif
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+		if (prev_sleep_state == ACPI_S3) {
+			if (nvs == NULL) {
+				/* If waking from S3 and no cache then */
+				debug("No MRC cache found in S3 resume path\n");
+				post_code(POST_RESUME_FAILURE);
+				/* Clear Sleep Type */
+				chipset_clear_sleep_state();
+				/* Reboot */
+				debug("Rebooting..\n");
+				reset_cpu(0);
+				/* Should not reach here.. */
+				panic("Reboot System");
+			}
+
+			boot_mode = BOOT_ON_S3_RESUME;
+		}
+#endif
 		/*
 		 * The first time we enter here, call fsp_init().
 		 * Note the execution does not return to this function,
 		 * instead it jumps to fsp_continue().
 		 */
-		fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, nvs);
+		fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, boot_mode, nvs);
 	} else {
 		/*
 		 * The second time we enter here, adjust the size of malloc()