From: Piotr Dymacz Date: Tue, 23 Feb 2016 08:57:49 +0000 (+0100) Subject: Adjust apu143.h config file for new PLL/clock and GPIO configuration code, minor... X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=0efe9d5ce8143ddbaad2c13708b9a1575f61163f;p=oweals%2Fu-boot_mod.git Adjust apu143.h config file for new PLL/clock and GPIO configuration code, minor changes for WR820 --- diff --git a/u-boot/include/configs/ap143.h b/u-boot/include/configs/ap143.h index 137a087..cfc13ce 100644 --- a/u-boot/include/configs/ap143.h +++ b/u-boot/include/configs/ap143.h @@ -7,6 +7,60 @@ #include #include +#include + +/* + * GPIO configuration + */ +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + /* LEDs */ + #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO GPIO13 + + /* Outputs, inputs */ + #define CONFIG_QCA_GPIO_MASK_OUTPUTS CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO + #define CONFIG_QCA_GPIO_MASK_INPUTS GPIO12 + + /* Initial states */ + #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO +#endif + +/* + * Miscellaneous configurable options + */ +#ifndef CONFIG_BOOTDELAY + #define CONFIG_BOOTDELAY 1 +#endif + +#define CFG_LONGHELP + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 600, 1200, 2400, 4800, 9600, 14400, \ + 19200, 28800, 38400, 56000, 57600, 115200 } + +#define CFG_ALT_MEMTEST +#define CFG_HUSH_PARSER +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size, was: def + 16 */ +#define CFG_MAXARGS 16 /* max number of command */ +#define CFG_MALLOC_LEN 512*1024 /* def: 128*1024 */ +#define CFG_BOOTPARAMS_LEN 512*1024 /* def: 128 */ +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x200000) /* RAM test start = CFG_SDRAM_BASE + 2 MB */ +#define CFG_MEMTEST_END (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001) /* RAM test end = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */ +#define CFG_RX_ETH_BUFFER 16 + +#if defined(CONFIG_SILENT_CONSOLE) + #define SILENT_ENV_VARIABLE "silent=1\0" +#else + #define SILENT_ENV_VARIABLE "" +#endif + +#define CFG_DCACHE_SIZE 32768 +#define CFG_ICACHE_SIZE 65536 +#define CFG_CACHELINE_SIZE 32 /* * FLASH and environment organization @@ -14,6 +68,7 @@ #define CFG_MAX_FLASH_BANKS 1 #define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash #define CFG_FLASH_SECTOR_SIZE 64 * 1024 + /* * We boot from this flash */ @@ -34,7 +89,7 @@ */ #undef CONFIG_BOOTARGS #if defined(CONFIG_FOR_TPLINK_WR820N_CH) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)" + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)" #endif /* @@ -46,21 +101,38 @@ #undef CONFIG_LOADADDR #define CONFIG_LOADADDR 0x80800000 -#define CFG_LOAD_ADDR 0x9F020000 -#define UPDATE_SCRIPT_FW_ADDR "0x9F020000" -#define CONFIG_BOOTCOMMAND "bootm 0x9F020000" +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define CFG_LOAD_ADDR 0x9F020000 + #define UPDATE_SCRIPT_FW_ADDR "0x9F020000" + #define CONFIG_BOOTCOMMAND "bootm 0x9F020000" +#endif + #define CONFIG_IPADDR 192.168.1.1 #define CONFIG_SERVERIP 192.168.1.2 -#undef CFG_PLL_FREQ -#undef CFG_HZ +/* + * PLL/Clocks configuration + */ +#ifdef CFG_HZ + #undef CFG_HZ +#endif +#define CFG_HZ bd->bi_cfg_hz + +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200 + #define CFG_HZ_FALLBACK (550000000LU/2) +#endif -// CPU-RAM-AHB frequency setting -#define CFG_HZ_FALLBACK (400000000LU/2) +/* + * For PLL/clocks recovery use reset button by default + */ +#ifdef GPIO_RST_BUTTON_BIT + #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN GPIO_RST_BUTTON_BIT +#endif -#define CFG_HZ bd->bi_cfg_hz -#define AR7240_SPI_CONTROL 0x43 -#define AR7240_SPI_CONTROL_DEFAULT AR7240_SPI_CONTROL +#ifdef GPIO_RST_BUTTON_IS_ACTIVE_LOW + #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1 +#endif /* * Address and size of Primary Environment Sector @@ -68,26 +140,30 @@ #define CFG_ENV_IS_IN_FLASH 1 #undef CFG_ENV_IS_NOWHERE -#define CFG_ENV_ADDR 0x9F01EC00 -#define CFG_ENV_SIZE 0x1000 -#define CFG_ENV_SECT_SIZE 0x10000 +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define CFG_ENV_ADDR 0x9F01EC00 + #define CFG_ENV_SIZE 0x1000 + #define CFG_ENV_SECT_SIZE 0x10000 +#endif /* * Available commands */ -#define CONFIG_COMMANDS (CFG_CMD_MEMORY | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_FLASH | \ - CFG_CMD_NET | \ - CFG_CMD_RUN | \ - CFG_CMD_DATE | \ - CFG_CMD_SNTP | \ - CFG_CMD_ECHO | \ - CFG_CMD_BOOTD | \ - CFG_CMD_ITEST | \ - CFG_CMD_ENV | \ - CFG_CMD_LOADB) +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_FLASH | \ + CFG_CMD_NET | \ + CFG_CMD_RUN | \ + CFG_CMD_DATE | \ + CFG_CMD_SNTP | \ + CFG_CMD_ECHO | \ + CFG_CMD_BOOTD | \ + CFG_CMD_ITEST | \ + CFG_CMD_ENV | \ + CFG_CMD_LOADB) +#endif // Enable NetConsole and custom NetConsole port #define CONFIG_NETCONSOLE @@ -105,21 +181,27 @@ #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE // Firmware partition offset -#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000 +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000 +#endif // U-Boot partition size #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024) // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB -#define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00" -#define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000" +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00" + #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000" +#endif // ART partition size #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024) // max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES) // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART) -#define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) +#endif // progress state info #define WEBFAILSAFE_PROGRESS_START 0 @@ -138,7 +220,26 @@ /* * Additional environment variables for simple upgrades */ -//#define CONFIG_EXTRA_ENV_SETTINGS SILENT_ENV_VARIABLE +#define CONFIG_EXTRA_ENV_SETTINGS "uboot_addr=0x9F000000\0" \ + "uboot_name=uboot.bin\0" \ + "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \ + "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \ + "uboot_upg=" \ + "if ping $serverip; then " \ + "mw.b $loadaddr 0xFF $uboot_backup_size && " \ + "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \ + "tftp $loadaddr $uboot_name && " \ + "if itest.l $filesize <= $uboot_size; then " \ + "erase $uboot_addr +$uboot_backup_size && " \ + "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \ + "echo OK!; " \ + "else " \ + "echo ERROR! Wrong file size!; " \ + "fi; " \ + "else " \ + "echo ERROR! Server not reachable!; " \ + "fi\0" \ + SILENT_ENV_VARIABLE /* * Cache lock for stack @@ -152,19 +253,45 @@ #define CONFIG_AG7240_SPEPHY #define CONFIG_NET_MULTI #define CONFIG_PCI 1 -#define WLANCAL 0x9fff1000 -#define BOARDCAL 0x9fff0000 +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define WLANCAL 0x9fff1000 + #define BOARDCAL 0x9fff0000 +#endif #define CFG_MII0_RMII 1 #define CFG_BOOTM_LEN (16 << 20) /* 16 MB */ #undef DEBUG /* MAC address, model and PIN number offsets in FLASH */ -#define OFFSET_MAC_DATA_BLOCK 0x010000 -#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 -#define OFFSET_MAC_ADDRESS 0x00FC00 -#define OFFSET_ROUTER_MODEL 0x00FD00 -#define OFFSET_PIN_NUMBER 0x00FE00 +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + #define OFFSET_MAC_DATA_BLOCK 0x010000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x00FC00 + #define OFFSET_ROUTER_MODEL 0x00FD00 + #define OFFSET_PIN_NUMBER 0x00FE00 +#endif + +/* + * PLL and clocks configurations from FLASH + */ +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) + /* + * All TP-Link routers have a lot of unused space + * in FLASH, in second 64 KiB block. + * We will store there PLL and CLOCK + * registers configuration. + */ + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 + +#endif + +#if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET) + /* Use last 32 bytes */ + #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \ + CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \ + 0x0000FFE0) +#endif #include