From: Aubrey Li <aubrey.adi@gmail.com>
Date: Mon, 12 Mar 2007 04:11:55 +0000 (+0800)
Subject: [Blackfin][PATCH] minor cleanup
X-Git-Tag: v1.3.0-rc1~132^2~6
X-Git-Url: https://git.librecmc.org/?a=commitdiff_plain;h=0d93de11449390a5984b0236c3612e50f6dbb7e8;p=oweals%2Fu-boot.git

[Blackfin][PATCH] minor cleanup
---

diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S
index 4a6c64b264..0512f3bf92 100644
--- a/cpu/bf533/flush.S
+++ b/cpu/bf533/flush.S
@@ -90,7 +90,7 @@ ENTRY(_icplb_flush)
 
 	/* Save in extraction pattern for later deposit. */
 	R3.H = R4.L << 0;
-	
+
 	/* So:
 	 * R0 = Page start
 	 * R1 = Page length (actually, offset into size/prefix tables)
@@ -264,7 +264,7 @@ ENTRY(_dcplb_flush)
 	 * (b) on whether address bit A[x] is set. x is determined
 	 * by DCBS in DMEM_CONTROL
 	 */
-	
+
 	R2 = 0;			/* Default to Bank A (Bank B would be 1)*/
 
 	P0.L = (DMEM_CONTROL & 0xFFFF);
diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
index 3a31e2f111..94556d681f 100644
--- a/cpu/bf533/start.S
+++ b/cpu/bf533/start.S
@@ -82,7 +82,7 @@ _stext:
 	SSYNC;
 
 	/* As per HW reference manual DAG registers,
-	 * DATA and Address resgister shall be zero'd 
+	 * DATA and Address resgister shall be zero'd
 	 * in initialization, after a reset state
 	 */
 	r1 = 0;	/* Data registers zero'd */
@@ -99,7 +99,7 @@ _stext:
 	p3 = 0;
 	p4 = 0;
 	p5 = 0;
-	
+
 	i0 = 0; /* DAG Registers zero'd */
 	i1 = 0;
 	i2 = 0;
@@ -150,7 +150,7 @@ no_soft_reset:
 	r1 = 0;
 	LSETUP(4,4) lc0 = p1;
 	[ p0 ++ ] = r1;
-	
+
 	p0.h = hi(SIC_IWR);
 	p0.l = lo(SIC_IWR);
 	r0.l = 0x1;
@@ -259,8 +259,8 @@ DMA:
 	/* Set Destination DMAConfig = DMA Enable,
 	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
 	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-	
-WAIT_DMA_DONE:	
+
+WAIT_DMA_DONE:
 	p0.h = hi(MDMA_D0_IRQ_STATUS);
 	p0.l = lo(MDMA_D0_IRQ_STATUS);
 	R0 = W[P0](Z);
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index cde2c245c8..79a1404a40 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -120,7 +120,7 @@
  */
 
 #define CFG_FLASH_CFI		/* The flash is CFI compatible  */
-#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
+#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver	*/
 #define	CFG_FLASH_CFI_AMD_RESET
 
 #define CFG_FLASH_BASE		0x20000000
@@ -228,7 +228,7 @@
 #endif
 
 /* configuration lookup from the BOOTP/DHCP server, */
-/* but not try to load any image using TFTP         */
+/* but not try to load any image using TFTP	    */
 
 #define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
@@ -289,7 +289,7 @@
 		"$(rootpath) console=ttyBF0,57600\0"	\
 	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
 		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
-        "ramboot=tftpboot $(loadaddr) linux; " \
+	"ramboot=tftpboot $(loadaddr) linux; " \
 		"run ramargs;run addip;bootelf\0" \
 	"nfsboot=tftpboot $(loadaddr) linux; "	\
 		"run nfsargs;run addip;bootelf\0" \